drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "intel_dsi.h"
  32
  33 struct ddi_buf_trans {
  34         u32 trans1;     /* balance leg enable, de-emph level */
  35         u32 trans2;     /* vref sel, vswing */
  36         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  37 };
  38
  39 static const u8 index_to_dp_signal_levels[] = {
  40         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  41         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  42         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  43         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  44         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  45         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  46         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  47         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  48         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  49         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  50 };
  51
  52 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  53  * them for both DP and FDI transports, allowing those ports to
  54  * automatically adapt to HDMI connections as well
  55  */
  56 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  57         { 0x00FFFFFF, 0x0006000E, 0x0 },
  58         { 0x00D75FFF, 0x0005000A, 0x0 },
  59         { 0x00C30FFF, 0x00040006, 0x0 },
  60         { 0x80AAAFFF, 0x000B0000, 0x0 },
  61         { 0x00FFFFFF, 0x0005000A, 0x0 },
  62         { 0x00D75FFF, 0x000C0004, 0x0 },
  63         { 0x80C30FFF, 0x000B0000, 0x0 },
  64         { 0x00FFFFFF, 0x00040006, 0x0 },
  65         { 0x80D75FFF, 0x000B0000, 0x0 },
  66 };
  67
  68 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  69         { 0x00FFFFFF, 0x0007000E, 0x0 },
  70         { 0x00D75FFF, 0x000F000A, 0x0 },
  71         { 0x00C30FFF, 0x00060006, 0x0 },
  72         { 0x00AAAFFF, 0x001E0000, 0x0 },
  73         { 0x00FFFFFF, 0x000F000A, 0x0 },
  74         { 0x00D75FFF, 0x00160004, 0x0 },
  75         { 0x00C30FFF, 0x001E0000, 0x0 },
  76         { 0x00FFFFFF, 0x00060006, 0x0 },
  77         { 0x00D75FFF, 0x001E0000, 0x0 },
  78 };
  79
  80 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
  81                                         /* Idx  NT mV d T mV d  db      */
  82         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
  83         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
  84         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
  85         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
  86         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
  87         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
  88         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
  89         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
  90         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
  91         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
  92         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
  93         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
  94 };
  95
  96 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
  97         { 0x00FFFFFF, 0x00000012, 0x0 },
  98         { 0x00EBAFFF, 0x00020011, 0x0 },
  99         { 0x00C71FFF, 0x0006000F, 0x0 },
 100         { 0x00AAAFFF, 0x000E000A, 0x0 },
 101         { 0x00FFFFFF, 0x00020011, 0x0 },
 102         { 0x00DB6FFF, 0x0005000F, 0x0 },
 103         { 0x00BEEFFF, 0x000A000C, 0x0 },
 104         { 0x00FFFFFF, 0x0005000F, 0x0 },
 105         { 0x00DB6FFF, 0x000A000C, 0x0 },
 106 };
 107
 108 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 109         { 0x00FFFFFF, 0x0007000E, 0x0 },
 110         { 0x00D75FFF, 0x000E000A, 0x0 },
 111         { 0x00BEFFFF, 0x00140006, 0x0 },
 112         { 0x80B2CFFF, 0x001B0002, 0x0 },
 113         { 0x00FFFFFF, 0x000E000A, 0x0 },
 114         { 0x00DB6FFF, 0x00160005, 0x0 },
 115         { 0x80C71FFF, 0x001A0002, 0x0 },
 116         { 0x00F7DFFF, 0x00180004, 0x0 },
 117         { 0x80D75FFF, 0x001B0002, 0x0 },
 118 };
 119
 120 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 121         { 0x00FFFFFF, 0x0001000E, 0x0 },
 122         { 0x00D75FFF, 0x0004000A, 0x0 },
 123         { 0x00C30FFF, 0x00070006, 0x0 },
 124         { 0x00AAAFFF, 0x000C0000, 0x0 },
 125         { 0x00FFFFFF, 0x0004000A, 0x0 },
 126         { 0x00D75FFF, 0x00090004, 0x0 },
 127         { 0x00C30FFF, 0x000C0000, 0x0 },
 128         { 0x00FFFFFF, 0x00070006, 0x0 },
 129         { 0x00D75FFF, 0x000C0000, 0x0 },
 130 };
 131
 132 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 133                                         /* Idx  NT mV d T mV df db      */
 134         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 135         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 136         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 137         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 138         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 139         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 140         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 141         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 142         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 143         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 144 };
 145
 146 /* Skylake H and S */
 147 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 148         { 0x00002016, 0x000000A0, 0x0 },
 149         { 0x00005012, 0x0000009B, 0x0 },
 150         { 0x00007011, 0x00000088, 0x0 },
 151         { 0x80009010, 0x000000C0, 0x1 },
 152         { 0x00002016, 0x0000009B, 0x0 },
 153         { 0x00005012, 0x00000088, 0x0 },
 154         { 0x80007011, 0x000000C0, 0x1 },
 155         { 0x00002016, 0x000000DF, 0x0 },
 156         { 0x80005012, 0x000000C0, 0x1 },
 157 };
 158
 159 /* Skylake U */
 160 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 161         { 0x0000201B, 0x000000A2, 0x0 },
 162         { 0x00005012, 0x00000088, 0x0 },
 163         { 0x80007011, 0x000000CD, 0x1 },
 164         { 0x80009010, 0x000000C0, 0x1 },
 165         { 0x0000201B, 0x0000009D, 0x0 },
 166         { 0x80005012, 0x000000C0, 0x1 },
 167         { 0x80007011, 0x000000C0, 0x1 },
 168         { 0x00002016, 0x00000088, 0x0 },
 169         { 0x80005012, 0x000000C0, 0x1 },
 170 };
 171
 172 /* Skylake Y */
 173 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 174         { 0x00000018, 0x000000A2, 0x0 },
 175         { 0x00005012, 0x00000088, 0x0 },
 176         { 0x80007011, 0x000000CD, 0x3 },
 177         { 0x80009010, 0x000000C0, 0x3 },
 178         { 0x00000018, 0x0000009D, 0x0 },
 179         { 0x80005012, 0x000000C0, 0x3 },
 180         { 0x80007011, 0x000000C0, 0x3 },
 181         { 0x00000018, 0x00000088, 0x0 },
 182         { 0x80005012, 0x000000C0, 0x3 },
 183 };
 184
 185 /* Kabylake H and S */
 186 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 187         { 0x00002016, 0x000000A0, 0x0 },
 188         { 0x00005012, 0x0000009B, 0x0 },
 189         { 0x00007011, 0x00000088, 0x0 },
 190         { 0x80009010, 0x000000C0, 0x1 },
 191         { 0x00002016, 0x0000009B, 0x0 },
 192         { 0x00005012, 0x00000088, 0x0 },
 193         { 0x80007011, 0x000000C0, 0x1 },
 194         { 0x00002016, 0x00000097, 0x0 },
 195         { 0x80005012, 0x000000C0, 0x1 },
 196 };
 197
 198 /* Kabylake U */
 199 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 200         { 0x0000201B, 0x000000A1, 0x0 },
 201         { 0x00005012, 0x00000088, 0x0 },
 202         { 0x80007011, 0x000000CD, 0x3 },
 203         { 0x80009010, 0x000000C0, 0x3 },
 204         { 0x0000201B, 0x0000009D, 0x0 },
 205         { 0x80005012, 0x000000C0, 0x3 },
 206         { 0x80007011, 0x000000C0, 0x3 },
 207         { 0x00002016, 0x0000004F, 0x0 },
 208         { 0x80005012, 0x000000C0, 0x3 },
 209 };
 210
 211 /* Kabylake Y */
 212 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 213         { 0x00001017, 0x000000A1, 0x0 },
 214         { 0x00005012, 0x00000088, 0x0 },
 215         { 0x80007011, 0x000000CD, 0x3 },
 216         { 0x8000800F, 0x000000C0, 0x3 },
 217         { 0x00001017, 0x0000009D, 0x0 },
 218         { 0x80005012, 0x000000C0, 0x3 },
 219         { 0x80007011, 0x000000C0, 0x3 },
 220         { 0x00001017, 0x0000004C, 0x0 },
 221         { 0x80005012, 0x000000C0, 0x3 },
 222 };
 223
 224 /*
 225  * Skylake/Kabylake H and S
 226  * eDP 1.4 low vswing translation parameters
 227  */
 228 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 229         { 0x00000018, 0x000000A8, 0x0 },
 230         { 0x00004013, 0x000000A9, 0x0 },
 231         { 0x00007011, 0x000000A2, 0x0 },
 232         { 0x00009010, 0x0000009C, 0x0 },
 233         { 0x00000018, 0x000000A9, 0x0 },
 234         { 0x00006013, 0x000000A2, 0x0 },
 235         { 0x00007011, 0x000000A6, 0x0 },
 236         { 0x00000018, 0x000000AB, 0x0 },
 237         { 0x00007013, 0x0000009F, 0x0 },
 238         { 0x00000018, 0x000000DF, 0x0 },
 239 };
 240
 241 /*
 242  * Skylake/Kabylake U
 243  * eDP 1.4 low vswing translation parameters
 244  */
 245 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 246         { 0x00000018, 0x000000A8, 0x0 },
 247         { 0x00004013, 0x000000A9, 0x0 },
 248         { 0x00007011, 0x000000A2, 0x0 },
 249         { 0x00009010, 0x0000009C, 0x0 },
 250         { 0x00000018, 0x000000A9, 0x0 },
 251         { 0x00006013, 0x000000A2, 0x0 },
 252         { 0x00007011, 0x000000A6, 0x0 },
 253         { 0x00002016, 0x000000AB, 0x0 },
 254         { 0x00005013, 0x0000009F, 0x0 },
 255         { 0x00000018, 0x000000DF, 0x0 },
 256 };
 257
 258 /*
 259  * Skylake/Kabylake Y
 260  * eDP 1.4 low vswing translation parameters
 261  */
 262 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 263         { 0x00000018, 0x000000A8, 0x0 },
 264         { 0x00004013, 0x000000AB, 0x0 },
 265         { 0x00007011, 0x000000A4, 0x0 },
 266         { 0x00009010, 0x000000DF, 0x0 },
 267         { 0x00000018, 0x000000AA, 0x0 },
 268         { 0x00006013, 0x000000A4, 0x0 },
 269         { 0x00007011, 0x0000009D, 0x0 },
 270         { 0x00000018, 0x000000A0, 0x0 },
 271         { 0x00006012, 0x000000DF, 0x0 },
 272         { 0x00000018, 0x0000008A, 0x0 },
 273 };
 274
 275 /* Skylake/Kabylake U, H and S */
 276 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 277         { 0x00000018, 0x000000AC, 0x0 },
 278         { 0x00005012, 0x0000009D, 0x0 },
 279         { 0x00007011, 0x00000088, 0x0 },
 280         { 0x00000018, 0x000000A1, 0x0 },
 281         { 0x00000018, 0x00000098, 0x0 },
 282         { 0x00004013, 0x00000088, 0x0 },
 283         { 0x80006012, 0x000000CD, 0x1 },
 284         { 0x00000018, 0x000000DF, 0x0 },
 285         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 286         { 0x80003015, 0x000000C0, 0x1 },
 287         { 0x80000018, 0x000000C0, 0x1 },
 288 };
 289
 290 /* Skylake/Kabylake Y */
 291 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 292         { 0x00000018, 0x000000A1, 0x0 },
 293         { 0x00005012, 0x000000DF, 0x0 },
 294         { 0x80007011, 0x000000CB, 0x3 },
 295         { 0x00000018, 0x000000A4, 0x0 },
 296         { 0x00000018, 0x0000009D, 0x0 },
 297         { 0x00004013, 0x00000080, 0x0 },
 298         { 0x80006013, 0x000000C0, 0x3 },
 299         { 0x00000018, 0x0000008A, 0x0 },
 300         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 301         { 0x80003015, 0x000000C0, 0x3 },
 302         { 0x80000018, 0x000000C0, 0x3 },
 303 };
 304
 305 struct bxt_ddi_buf_trans {
 306         u8 margin;      /* swing value */
 307         u8 scale;       /* scale value */
 308         u8 enable;      /* scale enable */
 309         u8 deemphasis;
 310 };
 311
 312 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 313                                         /* Idx  NT mV diff      db  */
 314         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 315         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 316         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 317         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 318         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 319         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 320         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 321         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 322         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 323         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 324 };
 325
 326 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 327                                         /* Idx  NT mV diff      db  */
 328         { 26, 0, 0, 128, },     /* 0:   200             0   */
 329         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 330         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 331         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 332         { 32, 0, 0, 128, },     /* 4:   250             0   */
 333         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 334         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 335         { 43, 0, 0, 128, },     /* 7:   300             0   */
 336         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 337         { 48, 0, 0, 128, },     /* 9:   300             0   */
 338 };
 339
 340 /* BSpec has 2 recommended values - entries 0 and 8.
 341  * Using the entry with higher vswing.
 342  */
 343 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 344                                         /* Idx  NT mV diff      db  */
 345         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 346         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 347         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 348         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 349         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 350         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 351         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 352         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 353         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 354         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 355 };
 356
 357 struct cnl_ddi_buf_trans {
 358         u8 dw2_swing_sel;
 359         u8 dw7_n_scalar;
 360         u8 dw4_cursor_coeff;
 361         u8 dw4_post_cursor_2;
 362         u8 dw4_post_cursor_1;
 363 };
 364
 365 /* Voltage Swing Programming for VccIO 0.85V for DP */
 366 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 367                                                 /* NT mV Trans mV db    */
 368         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 369         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 370         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 371         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 372         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 373         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 374         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 375         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 376         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 377         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 378 };
 379
 380 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 381 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 382                                                 /* NT mV Trans mV db    */
 383         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 384         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 385         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 386         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 387         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 388         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 389         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 390 };
 391
 392 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 393 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 394                                                 /* NT mV Trans mV db    */
 395         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 396         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 397         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 398         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 399         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 400         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 401         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 402         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 403         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 404 };
 405
 406 /* Voltage Swing Programming for VccIO 0.95V for DP */
 407 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 408                                                 /* NT mV Trans mV db    */
 409         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 410         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 411         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 412         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 413         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 414         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 415         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 416         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 417         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 418         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 419 };
 420
 421 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 422 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 423                                                 /* NT mV Trans mV db    */
 424         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 425         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 426         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 427         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 428         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 429         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 430         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 431         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 432         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 433         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 434         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 435 };
 436
 437 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 438 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 439                                                 /* NT mV Trans mV db    */
 440         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 441         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 442         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 443         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 444         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 445         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 446         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 447         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 448         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 449         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 450 };
 451
 452 /* Voltage Swing Programming for VccIO 1.05V for DP */
 453 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 454                                                 /* NT mV Trans mV db    */
 455         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 456         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 457         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 458         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 459         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 460         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 461         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 462         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 463         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 464         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 465 };
 466
 467 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 468 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 469                                                 /* NT mV Trans mV db    */
 470         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 471         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 472         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 473         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 474         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 475         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 476         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 477         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 478         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 479         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 480         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 481 };
 482
 483 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 484 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 485                                                 /* NT mV Trans mV db    */
 486         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 487         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 488         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 489         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 490         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 491         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 492         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 493         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 494         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 495 };
 496
 497 struct icl_combo_phy_ddi_buf_trans {
 498         u32 dw2_swing_select;
 499         u32 dw2_swing_scalar;
 500         u32 dw4_scaling;
 501 };
 502
 503 /* Voltage Swing Programming for VccIO 0.85V for DP */
 504 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
 505                                 /* Voltage mV  db    */
 506         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 507         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 508         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 509         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 510         { 0xB, 0x70, 0x0018 },  /* 600         0.0   */
 511         { 0xB, 0x70, 0x3015 },  /* 600         3.5   */
 512         { 0xB, 0x70, 0x6012 },  /* 600         6.0   */
 513         { 0x5, 0x00, 0x0018 },  /* 800         0.0   */
 514         { 0x5, 0x00, 0x3015 },  /* 800         3.5   */
 515         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 516 };
 517
 518 /* FIXME - After table is updated in Bspec */
 519 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 520 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
 521                                 /* Voltage mV  db    */
 522         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 523         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 524         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 525         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 526         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 527         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 528         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 529         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 530         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 531         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 532 };
 533
 534 /* Voltage Swing Programming for VccIO 0.95V for DP */
 535 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
 536                                 /* Voltage mV  db    */
 537         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 538         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 539         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 540         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 541         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 542         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 543         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 544         { 0x5, 0x76, 0x0018 },  /* 800         0.0   */
 545         { 0x5, 0x76, 0x3015 },  /* 800         3.5   */
 546         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 547 };
 548
 549 /* FIXME - After table is updated in Bspec */
 550 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 551 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
 552                                 /* Voltage mV  db    */
 553         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 554         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 555         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 556         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 557         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 558         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 559         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 560         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 561         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 562         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 563 };
 564
 565 /* Voltage Swing Programming for VccIO 1.05V for DP */
 566 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
 567                                 /* Voltage mV  db    */
 568         { 0x2, 0x98, 0x0018 },  /* 400         0.0   */
 569         { 0x2, 0x98, 0x3015 },  /* 400         3.5   */
 570         { 0x2, 0x98, 0x6012 },  /* 400         6.0   */
 571         { 0x2, 0x98, 0x900F },  /* 400         9.5   */
 572         { 0x4, 0x98, 0x0018 },  /* 600         0.0   */
 573         { 0x4, 0x98, 0x3015 },  /* 600         3.5   */
 574         { 0x4, 0x98, 0x6012 },  /* 600         6.0   */
 575         { 0x5, 0x71, 0x0018 },  /* 800         0.0   */
 576         { 0x5, 0x71, 0x3015 },  /* 800         3.5   */
 577         { 0x6, 0x98, 0x0018 },  /* 1200        0.0   */
 578 };
 579
 580 /* FIXME - After table is updated in Bspec */
 581 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 582 static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
 583                                 /* Voltage mV  db    */
 584         { 0x0, 0x00, 0x00 },    /* 200         0.0   */
 585         { 0x0, 0x00, 0x00 },    /* 200         1.5   */
 586         { 0x0, 0x00, 0x00 },    /* 200         4.0   */
 587         { 0x0, 0x00, 0x00 },    /* 200         6.0   */
 588         { 0x0, 0x00, 0x00 },    /* 250         0.0   */
 589         { 0x0, 0x00, 0x00 },    /* 250         1.5   */
 590         { 0x0, 0x00, 0x00 },    /* 250         4.0   */
 591         { 0x0, 0x00, 0x00 },    /* 300         0.0   */
 592         { 0x0, 0x00, 0x00 },    /* 300         1.5   */
 593         { 0x0, 0x00, 0x00 },    /* 350         0.0   */
 594 };
 595
 596 struct icl_mg_phy_ddi_buf_trans {
 597         u32 cri_txdeemph_override_5_0;
 598         u32 cri_txdeemph_override_11_6;
 599         u32 cri_txdeemph_override_17_12;
 600 };
 601
 602 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
 603                                 /* Voltage swing  pre-emphasis */
 604         { 0x0, 0x1B, 0x00 },    /* 0              0   */
 605         { 0x0, 0x23, 0x08 },    /* 0              1   */
 606         { 0x0, 0x2D, 0x12 },    /* 0              2   */
 607         { 0x0, 0x00, 0x00 },    /* 0              3   */
 608         { 0x0, 0x23, 0x00 },    /* 1              0   */
 609         { 0x0, 0x2B, 0x09 },    /* 1              1   */
 610         { 0x0, 0x2E, 0x11 },    /* 1              2   */
 611         { 0x0, 0x2F, 0x00 },    /* 2              0   */
 612         { 0x0, 0x33, 0x0C },    /* 2              1   */
 613         { 0x0, 0x00, 0x00 },    /* 3              0   */
 614 };
 615
 616 static const struct ddi_buf_trans *
 617 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 618 {
 619         if (dev_priv->vbt.edp.low_vswing) {
 620                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 621                 return bdw_ddi_translations_edp;
 622         } else {
 623                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 624                 return bdw_ddi_translations_dp;
 625         }
 626 }
 627
 628 static const struct ddi_buf_trans *
 629 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 630 {
 631         if (IS_SKL_ULX(dev_priv)) {
 632                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 633                 return skl_y_ddi_translations_dp;
 634         } else if (IS_SKL_ULT(dev_priv)) {
 635                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 636                 return skl_u_ddi_translations_dp;
 637         } else {
 638                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 639                 return skl_ddi_translations_dp;
 640         }
 641 }
 642
 643 static const struct ddi_buf_trans *
 644 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 645 {
 646         if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 647                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 648                 return kbl_y_ddi_translations_dp;
 649         } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
 650                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 651                 return kbl_u_ddi_translations_dp;
 652         } else {
 653                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 654                 return kbl_ddi_translations_dp;
 655         }
 656 }
 657
 658 static const struct ddi_buf_trans *
 659 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 660 {
 661         if (dev_priv->vbt.edp.low_vswing) {
 662                 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 663                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 664                         return skl_y_ddi_translations_edp;
 665                 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
 666                            IS_CFL_ULT(dev_priv)) {
 667                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 668                         return skl_u_ddi_translations_edp;
 669                 } else {
 670                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 671                         return skl_ddi_translations_edp;
 672                 }
 673         }
 674
 675         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 676                 return kbl_get_buf_trans_dp(dev_priv, n_entries);
 677         else
 678                 return skl_get_buf_trans_dp(dev_priv, n_entries);
 679 }
 680
 681 static const struct ddi_buf_trans *
 682 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 683 {
 684         if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
 685                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 686                 return skl_y_ddi_translations_hdmi;
 687         } else {
 688                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 689                 return skl_ddi_translations_hdmi;
 690         }
 691 }
 692
 693 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 694 {
 695         /* Only DDIA and DDIE can select the 10th register with DP */
 696         if (port == PORT_A || port == PORT_E)
 697                 return min(n_entries, 10);
 698         else
 699                 return min(n_entries, 9);
 700 }
 701
 702 static const struct ddi_buf_trans *
 703 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
 704                            enum port port, int *n_entries)
 705 {
 706         if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 707                 const struct ddi_buf_trans *ddi_translations =
 708                         kbl_get_buf_trans_dp(dev_priv, n_entries);
 709                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 710                 return ddi_translations;
 711         } else if (IS_SKYLAKE(dev_priv)) {
 712                 const struct ddi_buf_trans *ddi_translations =
 713                         skl_get_buf_trans_dp(dev_priv, n_entries);
 714                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 715                 return ddi_translations;
 716         } else if (IS_BROADWELL(dev_priv)) {
 717                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 718                 return  bdw_ddi_translations_dp;
 719         } else if (IS_HASWELL(dev_priv)) {
 720                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 721                 return hsw_ddi_translations_dp;
 722         }
 723
 724         *n_entries = 0;
 725         return NULL;
 726 }
 727
 728 static const struct ddi_buf_trans *
 729 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
 730                             enum port port, int *n_entries)
 731 {
 732         if (IS_GEN9_BC(dev_priv)) {
 733                 const struct ddi_buf_trans *ddi_translations =
 734                         skl_get_buf_trans_edp(dev_priv, n_entries);
 735                 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
 736                 return ddi_translations;
 737         } else if (IS_BROADWELL(dev_priv)) {
 738                 return bdw_get_buf_trans_edp(dev_priv, n_entries);
 739         } else if (IS_HASWELL(dev_priv)) {
 740                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 741                 return hsw_ddi_translations_dp;
 742         }
 743
 744         *n_entries = 0;
 745         return NULL;
 746 }
 747
 748 static const struct ddi_buf_trans *
 749 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 750                             int *n_entries)
 751 {
 752         if (IS_BROADWELL(dev_priv)) {
 753                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 754                 return bdw_ddi_translations_fdi;
 755         } else if (IS_HASWELL(dev_priv)) {
 756                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 757                 return hsw_ddi_translations_fdi;
 758         }
 759
 760         *n_entries = 0;
 761         return NULL;
 762 }
 763
 764 static const struct ddi_buf_trans *
 765 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
 766                              int *n_entries)
 767 {
 768         if (IS_GEN9_BC(dev_priv)) {
 769                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 770         } else if (IS_BROADWELL(dev_priv)) {
 771                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 772                 return bdw_ddi_translations_hdmi;
 773         } else if (IS_HASWELL(dev_priv)) {
 774                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 775                 return hsw_ddi_translations_hdmi;
 776         }
 777
 778         *n_entries = 0;
 779         return NULL;
 780 }
 781
 782 static const struct bxt_ddi_buf_trans *
 783 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 784 {
 785         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 786         return bxt_ddi_translations_dp;
 787 }
 788
 789 static const struct bxt_ddi_buf_trans *
 790 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 791 {
 792         if (dev_priv->vbt.edp.low_vswing) {
 793                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 794                 return bxt_ddi_translations_edp;
 795         }
 796
 797         return bxt_get_buf_trans_dp(dev_priv, n_entries);
 798 }
 799
 800 static const struct bxt_ddi_buf_trans *
 801 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 802 {
 803         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 804         return bxt_ddi_translations_hdmi;
 805 }
 806
 807 static const struct cnl_ddi_buf_trans *
 808 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 809 {
 810         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 811
 812         if (voltage == VOLTAGE_INFO_0_85V) {
 813                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 814                 return cnl_ddi_translations_hdmi_0_85V;
 815         } else if (voltage == VOLTAGE_INFO_0_95V) {
 816                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 817                 return cnl_ddi_translations_hdmi_0_95V;
 818         } else if (voltage == VOLTAGE_INFO_1_05V) {
 819                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 820                 return cnl_ddi_translations_hdmi_1_05V;
 821         } else {
 822                 *n_entries = 1; /* shut up gcc */
 823                 MISSING_CASE(voltage);
 824         }
 825         return NULL;
 826 }
 827
 828 static const struct cnl_ddi_buf_trans *
 829 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 830 {
 831         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 832
 833         if (voltage == VOLTAGE_INFO_0_85V) {
 834                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 835                 return cnl_ddi_translations_dp_0_85V;
 836         } else if (voltage == VOLTAGE_INFO_0_95V) {
 837                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 838                 return cnl_ddi_translations_dp_0_95V;
 839         } else if (voltage == VOLTAGE_INFO_1_05V) {
 840                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
 841                 return cnl_ddi_translations_dp_1_05V;
 842         } else {
 843                 *n_entries = 1; /* shut up gcc */
 844                 MISSING_CASE(voltage);
 845         }
 846         return NULL;
 847 }
 848
 849 static const struct cnl_ddi_buf_trans *
 850 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 851 {
 852         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 853
 854         if (dev_priv->vbt.edp.low_vswing) {
 855                 if (voltage == VOLTAGE_INFO_0_85V) {
 856                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
 857                         return cnl_ddi_translations_edp_0_85V;
 858                 } else if (voltage == VOLTAGE_INFO_0_95V) {
 859                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
 860                         return cnl_ddi_translations_edp_0_95V;
 861                 } else if (voltage == VOLTAGE_INFO_1_05V) {
 862                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
 863                         return cnl_ddi_translations_edp_1_05V;
 864                 } else {
 865                         *n_entries = 1; /* shut up gcc */
 866                         MISSING_CASE(voltage);
 867                 }
 868                 return NULL;
 869         } else {
 870                 return cnl_get_buf_trans_dp(dev_priv, n_entries);
 871         }
 872 }
 873
 874 static const struct icl_combo_phy_ddi_buf_trans *
 875 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
 876                         int type, int *n_entries)
 877 {
 878         u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
 879
 880         if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 881                 switch (voltage) {
 882                 case VOLTAGE_INFO_0_85V:
 883                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
 884                         return icl_combo_phy_ddi_translations_edp_0_85V;
 885                 case VOLTAGE_INFO_0_95V:
 886                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
 887                         return icl_combo_phy_ddi_translations_edp_0_95V;
 888                 case VOLTAGE_INFO_1_05V:
 889                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
 890                         return icl_combo_phy_ddi_translations_edp_1_05V;
 891                 default:
 892                         MISSING_CASE(voltage);
 893                         return NULL;
 894                 }
 895         } else {
 896                 switch (voltage) {
 897                 case VOLTAGE_INFO_0_85V:
 898                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
 899                         return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
 900                 case VOLTAGE_INFO_0_95V:
 901                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
 902                         return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
 903                 case VOLTAGE_INFO_1_05V:
 904                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
 905                         return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
 906                 default:
 907                         MISSING_CASE(voltage);
 908                         return NULL;
 909                 }
 910         }
 911 }
 912
 913 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 914 {
 915         int n_entries, level, default_entry;
 916
 917         level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 918
 919         if (IS_ICELAKE(dev_priv)) {
 920                 if (intel_port_is_combophy(dev_priv, port))
 921                         icl_get_combo_buf_trans(dev_priv, port,
 922                                                 INTEL_OUTPUT_HDMI, &n_entries);
 923                 else
 924                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
 925                 default_entry = n_entries - 1;
 926         } else if (IS_CANNONLAKE(dev_priv)) {
 927                 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
 928                 default_entry = n_entries - 1;
 929         } else if (IS_GEN9_LP(dev_priv)) {
 930                 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
 931                 default_entry = n_entries - 1;
 932         } else if (IS_GEN9_BC(dev_priv)) {
 933                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 934                 default_entry = 8;
 935         } else if (IS_BROADWELL(dev_priv)) {
 936                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 937                 default_entry = 7;
 938         } else if (IS_HASWELL(dev_priv)) {
 939                 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
 940                 default_entry = 6;
 941         } else {
 942                 WARN(1, "ddi translation table missing\n");
 943                 return 0;
 944         }
 945
 946         /* Choose a good default if VBT is badly populated */
 947         if (level == HDMI_LEVEL_SHIFT_UNKNOWN || level >= n_entries)
 948                 level = default_entry;
 949
 950         if (WARN_ON_ONCE(n_entries == 0))
 951                 return 0;
 952         if (WARN_ON_ONCE(level >= n_entries))
 953                 level = n_entries - 1;
 954
 955         return level;
 956 }
 957
 958 /*
 959  * Starting with Haswell, DDI port buffers must be programmed with correct
 960  * values in advance. This function programs the correct values for
 961  * DP/eDP/FDI use cases.
 962  */
 963 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 964                                          const struct intel_crtc_state *crtc_state)
 965 {
 966         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 967         u32 iboost_bit = 0;
 968         int i, n_entries;
 969         enum port port = encoder->port;
 970         const struct ddi_buf_trans *ddi_translations;
 971
 972         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
 973                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
 974                                                                &n_entries);
 975         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 976                 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
 977                                                                &n_entries);
 978         else
 979                 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
 980                                                               &n_entries);
 981
 982         /* If we're boosting the current, set bit 31 of trans1 */
 983         if (IS_GEN9_BC(dev_priv) &&
 984             dev_priv->vbt.ddi_port_info[port].dp_boost_level)
 985                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 986
 987         for (i = 0; i < n_entries; i++) {
 988                 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
 989                            ddi_translations[i].trans1 | iboost_bit);
 990                 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
 991                            ddi_translations[i].trans2);
 992         }
 993 }
 994
 995 /*
 996  * Starting with Haswell, DDI port buffers must be programmed with correct
 997  * values in advance. This function programs the correct values for
 998  * HDMI/DVI use cases.
 999  */
1000 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1001                                            int level)
1002 {
1003         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1004         u32 iboost_bit = 0;
1005         int n_entries;
1006         enum port port = encoder->port;
1007         const struct ddi_buf_trans *ddi_translations;
1008
1009         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1010
1011         if (WARN_ON_ONCE(!ddi_translations))
1012                 return;
1013         if (WARN_ON_ONCE(level >= n_entries))
1014                 level = n_entries - 1;
1015
1016         /* If we're boosting the current, set bit 31 of trans1 */
1017         if (IS_GEN9_BC(dev_priv) &&
1018             dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1019                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1020
1021         /* Entry 9 is for HDMI: */
1022         I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1023                    ddi_translations[level].trans1 | iboost_bit);
1024         I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1025                    ddi_translations[level].trans2);
1026 }
1027
1028 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1029                                     enum port port)
1030 {
1031         i915_reg_t reg = DDI_BUF_CTL(port);
1032         int i;
1033
1034         for (i = 0; i < 16; i++) {
1035                 udelay(1);
1036                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1037                         return;
1038         }
1039         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1040 }
1041
1042 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1043 {
1044         switch (pll->info->id) {
1045         case DPLL_ID_WRPLL1:
1046                 return PORT_CLK_SEL_WRPLL1;
1047         case DPLL_ID_WRPLL2:
1048                 return PORT_CLK_SEL_WRPLL2;
1049         case DPLL_ID_SPLL:
1050                 return PORT_CLK_SEL_SPLL;
1051         case DPLL_ID_LCPLL_810:
1052                 return PORT_CLK_SEL_LCPLL_810;
1053         case DPLL_ID_LCPLL_1350:
1054                 return PORT_CLK_SEL_LCPLL_1350;
1055         case DPLL_ID_LCPLL_2700:
1056                 return PORT_CLK_SEL_LCPLL_2700;
1057         default:
1058                 MISSING_CASE(pll->info->id);
1059                 return PORT_CLK_SEL_NONE;
1060         }
1061 }
1062
1063 static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
1064                                        const struct intel_crtc_state *crtc_state)
1065 {
1066         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1067         int clock = crtc_state->port_clock;
1068         const enum intel_dpll_id id = pll->info->id;
1069
1070         switch (id) {
1071         default:
1072                 MISSING_CASE(id);
1073                 /* fall through */
1074         case DPLL_ID_ICL_DPLL0:
1075         case DPLL_ID_ICL_DPLL1:
1076                 return DDI_CLK_SEL_NONE;
1077         case DPLL_ID_ICL_TBTPLL:
1078                 switch (clock) {
1079                 case 162000:
1080                         return DDI_CLK_SEL_TBT_162;
1081                 case 270000:
1082                         return DDI_CLK_SEL_TBT_270;
1083                 case 540000:
1084                         return DDI_CLK_SEL_TBT_540;
1085                 case 810000:
1086                         return DDI_CLK_SEL_TBT_810;
1087                 default:
1088                         MISSING_CASE(clock);
1089                         break;
1090                 }
1091         case DPLL_ID_ICL_MGPLL1:
1092         case DPLL_ID_ICL_MGPLL2:
1093         case DPLL_ID_ICL_MGPLL3:
1094         case DPLL_ID_ICL_MGPLL4:
1095                 return DDI_CLK_SEL_MG;
1096         }
1097 }
1098
1099 /* Starting with Haswell, different DDI ports can work in FDI mode for
1100  * connection to the PCH-located connectors. For this, it is necessary to train
1101  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1102  *
1103  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1104  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1105  * DDI A (which is used for eDP)
1106  */
1107
1108 void hsw_fdi_link_train(struct intel_crtc *crtc,
1109                         const struct intel_crtc_state *crtc_state)
1110 {
1111         struct drm_device *dev = crtc->base.dev;
1112         struct drm_i915_private *dev_priv = to_i915(dev);
1113         struct intel_encoder *encoder;
1114         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1115
1116         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1117                 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
1118                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1119         }
1120
1121         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1122          * mode set "sequence for CRT port" document:
1123          * - TP1 to TP2 time with the default value
1124          * - FDI delay to 90h
1125          *
1126          * WaFDIAutoLinkSetTimingOverrride:hsw
1127          */
1128         I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1129                                   FDI_RX_PWRDN_LANE0_VAL(2) |
1130                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1131
1132         /* Enable the PCH Receiver FDI PLL */
1133         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1134                      FDI_RX_PLL_ENABLE |
1135                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1136         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1137         POSTING_READ(FDI_RX_CTL(PIPE_A));
1138         udelay(220);
1139
1140         /* Switch from Rawclk to PCDclk */
1141         rx_ctl_val |= FDI_PCDCLK;
1142         I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1143
1144         /* Configure Port Clock Select */
1145         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1146         I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1147         WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1148
1149         /* Start the training iterating through available voltages and emphasis,
1150          * testing each value twice. */
1151         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1152                 /* Configure DP_TP_CTL with auto-training */
1153                 I915_WRITE(DP_TP_CTL(PORT_E),
1154                                         DP_TP_CTL_FDI_AUTOTRAIN |
1155                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1156                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
1157                                         DP_TP_CTL_ENABLE);
1158
1159                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1160                  * DDI E does not support port reversal, the functionality is
1161                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1162                  * port reversal bit */
1163                 I915_WRITE(DDI_BUF_CTL(PORT_E),
1164                            DDI_BUF_CTL_ENABLE |
1165                            ((crtc_state->fdi_lanes - 1) << 1) |
1166                            DDI_BUF_TRANS_SELECT(i / 2));
1167                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1168
1169                 udelay(600);
1170
1171                 /* Program PCH FDI Receiver TU */
1172                 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1173
1174                 /* Enable PCH FDI Receiver with auto-training */
1175                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1176                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1177                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1178
1179                 /* Wait for FDI receiver lane calibration */
1180                 udelay(30);
1181
1182                 /* Unset FDI_RX_MISC pwrdn lanes */
1183                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1184                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1185                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1186                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1187
1188                 /* Wait for FDI auto training time */
1189                 udelay(5);
1190
1191                 temp = I915_READ(DP_TP_STATUS(PORT_E));
1192                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1193                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1194                         break;
1195                 }
1196
1197                 /*
1198                  * Leave things enabled even if we failed to train FDI.
1199                  * Results in less fireworks from the state checker.
1200                  */
1201                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1202                         DRM_ERROR("FDI link training failed!\n");
1203                         break;
1204                 }
1205
1206                 rx_ctl_val &= ~FDI_RX_ENABLE;
1207                 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1208                 POSTING_READ(FDI_RX_CTL(PIPE_A));
1209
1210                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1211                 temp &= ~DDI_BUF_CTL_ENABLE;
1212                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1213                 POSTING_READ(DDI_BUF_CTL(PORT_E));
1214
1215                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1216                 temp = I915_READ(DP_TP_CTL(PORT_E));
1217                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1218                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1219                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1220                 POSTING_READ(DP_TP_CTL(PORT_E));
1221
1222                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1223
1224                 /* Reset FDI_RX_MISC pwrdn lanes */
1225                 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1226                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1227                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1228                 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1229                 POSTING_READ(FDI_RX_MISC(PIPE_A));
1230         }
1231
1232         /* Enable normal pixel sending for FDI */
1233         I915_WRITE(DP_TP_CTL(PORT_E),
1234                    DP_TP_CTL_FDI_AUTOTRAIN |
1235                    DP_TP_CTL_LINK_TRAIN_NORMAL |
1236                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1237                    DP_TP_CTL_ENABLE);
1238 }
1239
1240 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1241 {
1242         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1243         struct intel_digital_port *intel_dig_port =
1244                 enc_to_dig_port(&encoder->base);
1245
1246         intel_dp->DP = intel_dig_port->saved_port_bits |
1247                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1248         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1249 }
1250
1251 static struct intel_encoder *
1252 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1253 {
1254         struct drm_device *dev = crtc->base.dev;
1255         struct intel_encoder *encoder, *ret = NULL;
1256         int num_encoders = 0;
1257
1258         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1259                 ret = encoder;
1260                 num_encoders++;
1261         }
1262
1263         if (num_encoders != 1)
1264                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1265                      pipe_name(crtc->pipe));
1266
1267         BUG_ON(ret == NULL);
1268         return ret;
1269 }
1270
1271 #define LC_FREQ 2700
1272
1273 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1274                                    i915_reg_t reg)
1275 {
1276         int refclk = LC_FREQ;
1277         int n, p, r;
1278         u32 wrpll;
1279
1280         wrpll = I915_READ(reg);
1281         switch (wrpll & WRPLL_PLL_REF_MASK) {
1282         case WRPLL_PLL_SSC:
1283         case WRPLL_PLL_NON_SSC:
1284                 /*
1285                  * We could calculate spread here, but our checking
1286                  * code only cares about 5% accuracy, and spread is a max of
1287                  * 0.5% downspread.
1288                  */
1289                 refclk = 135;
1290                 break;
1291         case WRPLL_PLL_LCPLL:
1292                 refclk = LC_FREQ;
1293                 break;
1294         default:
1295                 WARN(1, "bad wrpll refclk\n");
1296                 return 0;
1297         }
1298
1299         r = wrpll & WRPLL_DIVIDER_REF_MASK;
1300         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1301         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1302
1303         /* Convert to KHz, p & r have a fixed point portion */
1304         return (refclk * n * 100) / (p * r);
1305 }
1306
1307 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1308                                enum intel_dpll_id pll_id)
1309 {
1310         i915_reg_t cfgcr1_reg, cfgcr2_reg;
1311         uint32_t cfgcr1_val, cfgcr2_val;
1312         uint32_t p0, p1, p2, dco_freq;
1313
1314         cfgcr1_reg = DPLL_CFGCR1(pll_id);
1315         cfgcr2_reg = DPLL_CFGCR2(pll_id);
1316
1317         cfgcr1_val = I915_READ(cfgcr1_reg);
1318         cfgcr2_val = I915_READ(cfgcr2_reg);
1319
1320         p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
1321         p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
1322
1323         if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
1324                 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1325         else
1326                 p1 = 1;
1327
1328
1329         switch (p0) {
1330         case DPLL_CFGCR2_PDIV_1:
1331                 p0 = 1;
1332                 break;
1333         case DPLL_CFGCR2_PDIV_2:
1334                 p0 = 2;
1335                 break;
1336         case DPLL_CFGCR2_PDIV_3:
1337                 p0 = 3;
1338                 break;
1339         case DPLL_CFGCR2_PDIV_7:
1340                 p0 = 7;
1341                 break;
1342         }
1343
1344         switch (p2) {
1345         case DPLL_CFGCR2_KDIV_5:
1346                 p2 = 5;
1347                 break;
1348         case DPLL_CFGCR2_KDIV_2:
1349                 p2 = 2;
1350                 break;
1351         case DPLL_CFGCR2_KDIV_3:
1352                 p2 = 3;
1353                 break;
1354         case DPLL_CFGCR2_KDIV_1:
1355                 p2 = 1;
1356                 break;
1357         }
1358
1359         dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1360
1361         dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1362                 1000) / 0x8000;
1363
1364         return dco_freq / (p0 * p1 * p2 * 5);
1365 }
1366
1367 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1368                         enum intel_dpll_id pll_id)
1369 {
1370         uint32_t cfgcr0, cfgcr1;
1371         uint32_t p0, p1, p2, dco_freq, ref_clock;
1372
1373         if (INTEL_GEN(dev_priv) >= 11) {
1374                 cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
1375                 cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
1376         } else {
1377                 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1378                 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
1379         }
1380
1381         p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1382         p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1383
1384         if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1385                 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1386                         DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1387         else
1388                 p1 = 1;
1389
1390
1391         switch (p0) {
1392         case DPLL_CFGCR1_PDIV_2:
1393                 p0 = 2;
1394                 break;
1395         case DPLL_CFGCR1_PDIV_3:
1396                 p0 = 3;
1397                 break;
1398         case DPLL_CFGCR1_PDIV_5:
1399                 p0 = 5;
1400                 break;
1401         case DPLL_CFGCR1_PDIV_7:
1402                 p0 = 7;
1403                 break;
1404         }
1405
1406         switch (p2) {
1407         case DPLL_CFGCR1_KDIV_1:
1408                 p2 = 1;
1409                 break;
1410         case DPLL_CFGCR1_KDIV_2:
1411                 p2 = 2;
1412                 break;
1413         case DPLL_CFGCR1_KDIV_4:
1414                 p2 = 4;
1415                 break;
1416         }
1417
1418         ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1419
1420         dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
1421
1422         dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1423                       DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1424
1425         if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1426                 return 0;
1427
1428         return dco_freq / (p0 * p1 * p2 * 5);
1429 }
1430
1431 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1432                                  enum port port)
1433 {
1434         u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1435
1436         switch (val) {
1437         case DDI_CLK_SEL_NONE:
1438                 return 0;
1439         case DDI_CLK_SEL_TBT_162:
1440                 return 162000;
1441         case DDI_CLK_SEL_TBT_270:
1442                 return 270000;
1443         case DDI_CLK_SEL_TBT_540:
1444                 return 540000;
1445         case DDI_CLK_SEL_TBT_810:
1446                 return 810000;
1447         default:
1448                 MISSING_CASE(val);
1449                 return 0;
1450         }
1451 }
1452
1453 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1454                                 enum port port)
1455 {
1456         u32 mg_pll_div0, mg_clktop_hsclkctl;
1457         u32 m1, m2_int, m2_frac, div1, div2, refclk;
1458         u64 tmp;
1459
1460         refclk = dev_priv->cdclk.hw.ref;
1461
1462         mg_pll_div0 = I915_READ(MG_PLL_DIV0(port));
1463         mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port));
1464
1465         m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK;
1466         m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1467         m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?
1468                   (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>
1469                   MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0;
1470
1471         switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1472         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1473                 div1 = 2;
1474                 break;
1475         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1476                 div1 = 3;
1477                 break;
1478         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1479                 div1 = 5;
1480                 break;
1481         case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1482                 div1 = 7;
1483                 break;
1484         default:
1485                 MISSING_CASE(mg_clktop_hsclkctl);
1486                 return 0;
1487         }
1488
1489         div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1490                 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1491         /* div2 value of 0 is same as 1 means no div */
1492         if (div2 == 0)
1493                 div2 = 1;
1494
1495         /*
1496          * Adjust the original formula to delay the division by 2^22 in order to
1497          * minimize possible rounding errors.
1498          */
1499         tmp = (u64)m1 * m2_int * refclk +
1500               (((u64)m1 * m2_frac * refclk) >> 22);
1501         tmp = div_u64(tmp, 5 * div1 * div2);
1502
1503         return tmp;
1504 }
1505
1506 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1507 {
1508         int dotclock;
1509
1510         if (pipe_config->has_pch_encoder)
1511                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1512                                                     &pipe_config->fdi_m_n);
1513         else if (intel_crtc_has_dp_encoder(pipe_config))
1514                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1515                                                     &pipe_config->dp_m_n);
1516         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1517                 dotclock = pipe_config->port_clock * 2 / 3;
1518         else
1519                 dotclock = pipe_config->port_clock;
1520
1521         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1522                 dotclock *= 2;
1523
1524         if (pipe_config->pixel_multiplier)
1525                 dotclock /= pipe_config->pixel_multiplier;
1526
1527         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1528 }
1529
1530 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1531                               struct intel_crtc_state *pipe_config)
1532 {
1533         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1534         enum port port = encoder->port;
1535         int link_clock = 0;
1536         uint32_t pll_id;
1537
1538         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1539         if (intel_port_is_combophy(dev_priv, port)) {
1540                 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
1541                         link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1542                 else
1543                         link_clock = icl_calc_dp_combo_pll_link(dev_priv,
1544                                                                 pll_id);
1545         } else {
1546                 if (pll_id == DPLL_ID_ICL_TBTPLL)
1547                         link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1548                 else
1549                         link_clock = icl_calc_mg_pll_link(dev_priv, port);
1550         }
1551
1552         pipe_config->port_clock = link_clock;
1553         ddi_dotclock_get(pipe_config);
1554 }
1555
1556 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1557                               struct intel_crtc_state *pipe_config)
1558 {
1559         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1560         int link_clock = 0;
1561         uint32_t cfgcr0;
1562         enum intel_dpll_id pll_id;
1563
1564         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1565
1566         cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
1567
1568         if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1569                 link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
1570         } else {
1571                 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1572
1573                 switch (link_clock) {
1574                 case DPLL_CFGCR0_LINK_RATE_810:
1575                         link_clock = 81000;
1576                         break;
1577                 case DPLL_CFGCR0_LINK_RATE_1080:
1578                         link_clock = 108000;
1579                         break;
1580                 case DPLL_CFGCR0_LINK_RATE_1350:
1581                         link_clock = 135000;
1582                         break;
1583                 case DPLL_CFGCR0_LINK_RATE_1620:
1584                         link_clock = 162000;
1585                         break;
1586                 case DPLL_CFGCR0_LINK_RATE_2160:
1587                         link_clock = 216000;
1588                         break;
1589                 case DPLL_CFGCR0_LINK_RATE_2700:
1590                         link_clock = 270000;
1591                         break;
1592                 case DPLL_CFGCR0_LINK_RATE_3240:
1593                         link_clock = 324000;
1594                         break;
1595                 case DPLL_CFGCR0_LINK_RATE_4050:
1596                         link_clock = 405000;
1597                         break;
1598                 default:
1599                         WARN(1, "Unsupported link rate\n");
1600                         break;
1601                 }
1602                 link_clock *= 2;
1603         }
1604
1605         pipe_config->port_clock = link_clock;
1606
1607         ddi_dotclock_get(pipe_config);
1608 }
1609
1610 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1611                                 struct intel_crtc_state *pipe_config)
1612 {
1613         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1614         int link_clock = 0;
1615         uint32_t dpll_ctl1;
1616         enum intel_dpll_id pll_id;
1617
1618         pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1619
1620         dpll_ctl1 = I915_READ(DPLL_CTRL1);
1621
1622         if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(pll_id)) {
1623                 link_clock = skl_calc_wrpll_link(dev_priv, pll_id);
1624         } else {
1625                 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(pll_id);
1626                 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(pll_id);
1627
1628                 switch (link_clock) {
1629                 case DPLL_CTRL1_LINK_RATE_810:
1630                         link_clock = 81000;
1631                         break;
1632                 case DPLL_CTRL1_LINK_RATE_1080:
1633                         link_clock = 108000;
1634                         break;
1635                 case DPLL_CTRL1_LINK_RATE_1350:
1636                         link_clock = 135000;
1637                         break;
1638                 case DPLL_CTRL1_LINK_RATE_1620:
1639                         link_clock = 162000;
1640                         break;
1641                 case DPLL_CTRL1_LINK_RATE_2160:
1642                         link_clock = 216000;
1643                         break;
1644                 case DPLL_CTRL1_LINK_RATE_2700:
1645                         link_clock = 270000;
1646                         break;
1647                 default:
1648                         WARN(1, "Unsupported link rate\n");
1649                         break;
1650                 }
1651                 link_clock *= 2;
1652         }
1653
1654         pipe_config->port_clock = link_clock;
1655
1656         ddi_dotclock_get(pipe_config);
1657 }
1658
1659 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1660                               struct intel_crtc_state *pipe_config)
1661 {
1662         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1663         int link_clock = 0;
1664         u32 val, pll;
1665
1666         val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1667         switch (val & PORT_CLK_SEL_MASK) {
1668         case PORT_CLK_SEL_LCPLL_810:
1669                 link_clock = 81000;
1670                 break;
1671         case PORT_CLK_SEL_LCPLL_1350:
1672                 link_clock = 135000;
1673                 break;
1674         case PORT_CLK_SEL_LCPLL_2700:
1675                 link_clock = 270000;
1676                 break;
1677         case PORT_CLK_SEL_WRPLL1:
1678                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1679                 break;
1680         case PORT_CLK_SEL_WRPLL2:
1681                 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1682                 break;
1683         case PORT_CLK_SEL_SPLL:
1684                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1685                 if (pll == SPLL_PLL_FREQ_810MHz)
1686                         link_clock = 81000;
1687                 else if (pll == SPLL_PLL_FREQ_1350MHz)
1688                         link_clock = 135000;
1689                 else if (pll == SPLL_PLL_FREQ_2700MHz)
1690                         link_clock = 270000;
1691                 else {
1692                         WARN(1, "bad spll freq\n");
1693                         return;
1694                 }
1695                 break;
1696         default:
1697                 WARN(1, "bad port clock sel\n");
1698                 return;
1699         }
1700
1701         pipe_config->port_clock = link_clock * 2;
1702
1703         ddi_dotclock_get(pipe_config);
1704 }
1705
1706 static int bxt_calc_pll_link(struct intel_crtc_state *crtc_state)
1707 {
1708         struct intel_dpll_hw_state *state;
1709         struct dpll clock;
1710
1711         /* For DDI ports we always use a shared PLL. */
1712         if (WARN_ON(!crtc_state->shared_dpll))
1713                 return 0;
1714
1715         state = &crtc_state->dpll_hw_state;
1716
1717         clock.m1 = 2;
1718         clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1719         if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1720                 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1721         clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1722         clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1723         clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1724
1725         return chv_calc_dpll_params(100000, &clock);
1726 }
1727
1728 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1729                               struct intel_crtc_state *pipe_config)
1730 {
1731         pipe_config->port_clock = bxt_calc_pll_link(pipe_config);
1732
1733         ddi_dotclock_get(pipe_config);
1734 }
1735
1736 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1737                                 struct intel_crtc_state *pipe_config)
1738 {
1739         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1740
1741         if (IS_ICELAKE(dev_priv))
1742                 icl_ddi_clock_get(encoder, pipe_config);
1743         else if (IS_CANNONLAKE(dev_priv))
1744                 cnl_ddi_clock_get(encoder, pipe_config);
1745         else if (IS_GEN9_LP(dev_priv))
1746                 bxt_ddi_clock_get(encoder, pipe_config);
1747         else if (IS_GEN9_BC(dev_priv))
1748                 skl_ddi_clock_get(encoder, pipe_config);
1749         else if (INTEL_GEN(dev_priv) <= 8)
1750                 hsw_ddi_clock_get(encoder, pipe_config);
1751 }
1752
1753 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1754 {
1755         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1756         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1757         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1758         u32 temp;
1759
1760         if (!intel_crtc_has_dp_encoder(crtc_state))
1761                 return;
1762
1763         WARN_ON(transcoder_is_dsi(cpu_transcoder));
1764
1765         temp = TRANS_MSA_SYNC_CLK;
1766
1767         if (crtc_state->limited_color_range)
1768                 temp |= TRANS_MSA_CEA_RANGE;
1769
1770         switch (crtc_state->pipe_bpp) {
1771         case 18:
1772                 temp |= TRANS_MSA_6_BPC;
1773                 break;
1774         case 24:
1775                 temp |= TRANS_MSA_8_BPC;
1776                 break;
1777         case 30:
1778                 temp |= TRANS_MSA_10_BPC;
1779                 break;
1780         case 36:
1781                 temp |= TRANS_MSA_12_BPC;
1782                 break;
1783         default:
1784                 MISSING_CASE(crtc_state->pipe_bpp);
1785                 break;
1786         }
1787
1788         /*
1789          * As per DP 1.2 spec section 2.3.4.3 while sending
1790          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1791          * colorspace information. The output colorspace encoding is BT601.
1792          */
1793         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1794                 temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
1795         I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1796 }
1797
1798 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1799                                     bool state)
1800 {
1801         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1802         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1803         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1804         uint32_t temp;
1805
1806         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1807         if (state == true)
1808                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1809         else
1810                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1811         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1812 }
1813
1814 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1815 {
1816         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1817         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1818         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1819         enum pipe pipe = crtc->pipe;
1820         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1821         enum port port = encoder->port;
1822         uint32_t temp;
1823
1824         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1825         temp = TRANS_DDI_FUNC_ENABLE;
1826         temp |= TRANS_DDI_SELECT_PORT(port);
1827
1828         switch (crtc_state->pipe_bpp) {
1829         case 18:
1830                 temp |= TRANS_DDI_BPC_6;
1831                 break;
1832         case 24:
1833                 temp |= TRANS_DDI_BPC_8;
1834                 break;
1835         case 30:
1836                 temp |= TRANS_DDI_BPC_10;
1837                 break;
1838         case 36:
1839                 temp |= TRANS_DDI_BPC_12;
1840                 break;
1841         default:
1842                 BUG();
1843         }
1844
1845         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1846                 temp |= TRANS_DDI_PVSYNC;
1847         if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1848                 temp |= TRANS_DDI_PHSYNC;
1849
1850         if (cpu_transcoder == TRANSCODER_EDP) {
1851                 switch (pipe) {
1852                 case PIPE_A:
1853                         /* On Haswell, can only use the always-on power well for
1854                          * eDP when not using the panel fitter, and when not
1855                          * using motion blur mitigation (which we don't
1856                          * support). */
1857                         if (IS_HASWELL(dev_priv) &&
1858                             (crtc_state->pch_pfit.enabled ||
1859                              crtc_state->pch_pfit.force_thru))
1860                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1861                         else
1862                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1863                         break;
1864                 case PIPE_B:
1865                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1866                         break;
1867                 case PIPE_C:
1868                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1869                         break;
1870                 default:
1871                         BUG();
1872                         break;
1873                 }
1874         }
1875
1876         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1877                 if (crtc_state->has_hdmi_sink)
1878                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1879                 else
1880                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1881
1882                 if (crtc_state->hdmi_scrambling)
1883                         temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
1884                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1885                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1886         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1887                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1888                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1889         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1890                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1891                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1892         } else {
1893                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1894                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1895         }
1896
1897         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1898 }
1899
1900 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1901 {
1902         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1903         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1904         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1905         i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1906         uint32_t val = I915_READ(reg);
1907
1908         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1909         val |= TRANS_DDI_PORT_NONE;
1910         I915_WRITE(reg, val);
1911
1912         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1913             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1914                 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1915                 /* Quirk time at 100ms for reliable operation */
1916                 msleep(100);
1917         }
1918 }
1919
1920 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1921                                      bool enable)
1922 {
1923         struct drm_device *dev = intel_encoder->base.dev;
1924         struct drm_i915_private *dev_priv = to_i915(dev);
1925         enum pipe pipe = 0;
1926         int ret = 0;
1927         uint32_t tmp;
1928
1929         if (WARN_ON(!intel_display_power_get_if_enabled(dev_priv,
1930                                                 intel_encoder->power_domain)))
1931                 return -ENXIO;
1932
1933         if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1934                 ret = -EIO;
1935                 goto out;
1936         }
1937
1938         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
1939         if (enable)
1940                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1941         else
1942                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1943         I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
1944 out:
1945         intel_display_power_put(dev_priv, intel_encoder->power_domain);
1946         return ret;
1947 }
1948
1949 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1950 {
1951         struct drm_device *dev = intel_connector->base.dev;
1952         struct drm_i915_private *dev_priv = to_i915(dev);
1953         struct intel_encoder *encoder = intel_connector->encoder;
1954         int type = intel_connector->base.connector_type;
1955         enum port port = encoder->port;
1956         enum pipe pipe = 0;
1957         enum transcoder cpu_transcoder;
1958         uint32_t tmp;
1959         bool ret;
1960
1961         if (!intel_display_power_get_if_enabled(dev_priv,
1962                                                 encoder->power_domain))
1963                 return false;
1964
1965         if (!encoder->get_hw_state(encoder, &pipe)) {
1966                 ret = false;
1967                 goto out;
1968         }
1969
1970         if (port == PORT_A)
1971                 cpu_transcoder = TRANSCODER_EDP;
1972         else
1973                 cpu_transcoder = (enum transcoder) pipe;
1974
1975         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1976
1977         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1978         case TRANS_DDI_MODE_SELECT_HDMI:
1979         case TRANS_DDI_MODE_SELECT_DVI:
1980                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1981                 break;
1982
1983         case TRANS_DDI_MODE_SELECT_DP_SST:
1984                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1985                       type == DRM_MODE_CONNECTOR_DisplayPort;
1986                 break;
1987
1988         case TRANS_DDI_MODE_SELECT_DP_MST:
1989                 /* if the transcoder is in MST state then
1990                  * connector isn't connected */
1991                 ret = false;
1992                 break;
1993
1994         case TRANS_DDI_MODE_SELECT_FDI:
1995                 ret = type == DRM_MODE_CONNECTOR_VGA;
1996                 break;
1997
1998         default:
1999                 ret = false;
2000                 break;
2001         }
2002
2003 out:
2004         intel_display_power_put(dev_priv, encoder->power_domain);
2005
2006         return ret;
2007 }
2008
2009 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2010                                         u8 *pipe_mask, bool *is_dp_mst)
2011 {
2012         struct drm_device *dev = encoder->base.dev;
2013         struct drm_i915_private *dev_priv = to_i915(dev);
2014         enum port port = encoder->port;
2015         enum pipe p;
2016         u32 tmp;
2017         u8 mst_pipe_mask;
2018
2019         *pipe_mask = 0;
2020         *is_dp_mst = false;
2021
2022         if (!intel_display_power_get_if_enabled(dev_priv,
2023                                                 encoder->power_domain))
2024                 return;
2025
2026         tmp = I915_READ(DDI_BUF_CTL(port));
2027         if (!(tmp & DDI_BUF_CTL_ENABLE))
2028                 goto out;
2029
2030         if (port == PORT_A) {
2031                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2032
2033                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2034                 default:
2035                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2036                         /* fallthrough */
2037                 case TRANS_DDI_EDP_INPUT_A_ON:
2038                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2039                         *pipe_mask = BIT(PIPE_A);
2040                         break;
2041                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2042                         *pipe_mask = BIT(PIPE_B);
2043                         break;
2044                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2045                         *pipe_mask = BIT(PIPE_C);
2046                         break;
2047                 }
2048
2049                 goto out;
2050         }
2051
2052         mst_pipe_mask = 0;
2053         for_each_pipe(dev_priv, p) {
2054                 enum transcoder cpu_transcoder = (enum transcoder)p;
2055
2056                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2057
2058                 if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
2059                         continue;
2060
2061                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2062                     TRANS_DDI_MODE_SELECT_DP_MST)
2063                         mst_pipe_mask |= BIT(p);
2064
2065                 *pipe_mask |= BIT(p);
2066         }
2067
2068         if (!*pipe_mask)
2069                 DRM_DEBUG_KMS("No pipe for ddi port %c found\n",
2070                               port_name(port));
2071
2072         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2073                 DRM_DEBUG_KMS("Multiple pipes for non DP-MST port %c (pipe_mask %02x)\n",
2074                               port_name(port), *pipe_mask);
2075                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2076         }
2077
2078         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2079                 DRM_DEBUG_KMS("Conflicting MST and non-MST encoders for port %c (pipe_mask %02x mst_pipe_mask %02x)\n",
2080                               port_name(port), *pipe_mask, mst_pipe_mask);
2081         else
2082                 *is_dp_mst = mst_pipe_mask;
2083
2084 out:
2085         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2086                 tmp = I915_READ(BXT_PHY_CTL(port));
2087                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2088                             BXT_PHY_LANE_POWERDOWN_ACK |
2089                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2090                         DRM_ERROR("Port %c enabled but PHY powered down? "
2091                                   "(PHY_CTL %08x)\n", port_name(port), tmp);
2092         }
2093
2094         intel_display_power_put(dev_priv, encoder->power_domain);
2095 }
2096
2097 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2098                             enum pipe *pipe)
2099 {
2100         u8 pipe_mask;
2101         bool is_mst;
2102
2103         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2104
2105         if (is_mst || !pipe_mask)
2106                 return false;
2107
2108         *pipe = ffs(pipe_mask) - 1;
2109
2110         return true;
2111 }
2112
2113 static inline enum intel_display_power_domain
2114 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2115 {
2116         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2117          * DC states enabled at the same time, while for driver initiated AUX
2118          * transfers we need the same AUX IOs to be powered but with DC states
2119          * disabled. Accordingly use the AUX power domain here which leaves DC
2120          * states enabled.
2121          * However, for non-A AUX ports the corresponding non-EDP transcoders
2122          * would have already enabled power well 2 and DC_OFF. This means we can
2123          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2124          * specific AUX_IO reference without powering up any extra wells.
2125          * Note that PSR is enabled only on Port A even though this function
2126          * returns the correct domain for other ports too.
2127          */
2128         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2129                                               intel_aux_power_domain(dig_port);
2130 }
2131
2132 static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
2133                                        struct intel_crtc_state *crtc_state)
2134 {
2135         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2136         struct intel_digital_port *dig_port;
2137         u64 domains;
2138
2139         /*
2140          * TODO: Add support for MST encoders. Atm, the following should never
2141          * happen since fake-MST encoders don't set their get_power_domains()
2142          * hook.
2143          */
2144         if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2145                 return 0;
2146
2147         dig_port = enc_to_dig_port(&encoder->base);
2148         domains = BIT_ULL(dig_port->ddi_io_power_domain);
2149
2150         /*
2151          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2152          * ports.
2153          */
2154         if (intel_crtc_has_dp_encoder(crtc_state) ||
2155             intel_port_is_tc(dev_priv, encoder->port))
2156                 domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
2157
2158         /*
2159          * VDSC power is needed when DSC is enabled
2160          */
2161         if (crtc_state->dsc_params.compression_enable)
2162                 domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));
2163
2164         return domains;
2165 }
2166
2167 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2168 {
2169         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2170         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2171         struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2172         enum port port = encoder->port;
2173         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2174
2175         if (cpu_transcoder != TRANSCODER_EDP)
2176                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2177                            TRANS_CLK_SEL_PORT(port));
2178 }
2179
2180 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2181 {
2182         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2183         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2184
2185         if (cpu_transcoder != TRANSCODER_EDP)
2186                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2187                            TRANS_CLK_SEL_DISABLED);
2188 }
2189
2190 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2191                                 enum port port, uint8_t iboost)
2192 {
2193         u32 tmp;
2194
2195         tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2196         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2197         if (iboost)
2198                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2199         else
2200                 tmp |= BALANCE_LEG_DISABLE(port);
2201         I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2202 }
2203
2204 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2205                                int level, enum intel_output_type type)
2206 {
2207         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
2208         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2209         enum port port = encoder->port;
2210         uint8_t iboost;
2211
2212         if (type == INTEL_OUTPUT_HDMI)
2213                 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2214         else
2215                 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2216
2217         if (iboost == 0) {
2218                 const struct ddi_buf_trans *ddi_translations;
2219                 int n_entries;
2220
2221                 if (type == INTEL_OUTPUT_HDMI)
2222                         ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2223                 else if (type == INTEL_OUTPUT_EDP)
2224                         ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2225                 else
2226                         ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2227
2228                 if (WARN_ON_ONCE(!ddi_translations))
2229                         return;
2230                 if (WARN_ON_ONCE(level >= n_entries))
2231                         level = n_entries - 1;
2232
2233                 iboost = ddi_translations[level].i_boost;
2234         }
2235
2236         /* Make sure that the requested I_boost is valid */
2237         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2238                 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2239                 return;
2240         }
2241
2242         _skl_ddi_set_iboost(dev_priv, port, iboost);
2243
2244         if (port == PORT_A && intel_dig_port->max_lanes == 4)
2245                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2246 }
2247
2248 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2249                                     int level, enum intel_output_type type)
2250 {
2251         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2252         const struct bxt_ddi_buf_trans *ddi_translations;
2253         enum port port = encoder->port;
2254         int n_entries;
2255
2256         if (type == INTEL_OUTPUT_HDMI)
2257                 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2258         else if (type == INTEL_OUTPUT_EDP)
2259                 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2260         else
2261                 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2262
2263         if (WARN_ON_ONCE(!ddi_translations))
2264                 return;
2265         if (WARN_ON_ONCE(level >= n_entries))
2266                 level = n_entries - 1;
2267
2268         bxt_ddi_phy_set_signal_level(dev_priv, port,
2269                                      ddi_translations[level].margin,
2270                                      ddi_translations[level].scale,
2271                                      ddi_translations[level].enable,
2272                                      ddi_translations[level].deemphasis);
2273 }
2274
2275 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2276 {
2277         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2278         enum port port = encoder->port;
2279         int n_entries;
2280
2281         if (IS_ICELAKE(dev_priv)) {
2282                 if (intel_port_is_combophy(dev_priv, port))
2283                         icl_get_combo_buf_trans(dev_priv, port, encoder->type,
2284                                                 &n_entries);
2285                 else
2286                         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2287         } else if (IS_CANNONLAKE(dev_priv)) {
2288                 if (encoder->type == INTEL_OUTPUT_EDP)
2289                         cnl_get_buf_trans_edp(dev_priv, &n_entries);
2290                 else
2291                         cnl_get_buf_trans_dp(dev_priv, &n_entries);
2292         } else if (IS_GEN9_LP(dev_priv)) {
2293                 if (encoder->type == INTEL_OUTPUT_EDP)
2294                         bxt_get_buf_trans_edp(dev_priv, &n_entries);
2295                 else
2296                         bxt_get_buf_trans_dp(dev_priv, &n_entries);
2297         } else {
2298                 if (encoder->type == INTEL_OUTPUT_EDP)
2299                         intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2300                 else
2301                         intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2302         }
2303
2304         if (WARN_ON(n_entries < 1))
2305                 n_entries = 1;
2306         if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2307                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2308
2309         return index_to_dp_signal_levels[n_entries - 1] &
2310                 DP_TRAIN_VOLTAGE_SWING_MASK;
2311 }
2312
2313 /*
2314  * We assume that the full set of pre-emphasis values can be
2315  * used on all DDI platforms. Should that change we need to
2316  * rethink this code.
2317  */
2318 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2319 {
2320         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2321         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2322                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2323         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2324                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2325         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2326                 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2327         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2328         default:
2329                 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2330         }
2331 }
2332
2333 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2334                                    int level, enum intel_output_type type)
2335 {
2336         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2337         const struct cnl_ddi_buf_trans *ddi_translations;
2338         enum port port = encoder->port;
2339         int n_entries, ln;
2340         u32 val;
2341
2342         if (type == INTEL_OUTPUT_HDMI)
2343                 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2344         else if (type == INTEL_OUTPUT_EDP)
2345                 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2346         else
2347                 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2348
2349         if (WARN_ON_ONCE(!ddi_translations))
2350                 return;
2351         if (WARN_ON_ONCE(level >= n_entries))
2352                 level = n_entries - 1;
2353
2354         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2355         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2356         val &= ~SCALING_MODE_SEL_MASK;
2357         val |= SCALING_MODE_SEL(2);
2358         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2359
2360         /* Program PORT_TX_DW2 */
2361         val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2362         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2363                  RCOMP_SCALAR_MASK);
2364         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2365         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2366         /* Rcomp scalar is fixed as 0x98 for every table entry */
2367         val |= RCOMP_SCALAR(0x98);
2368         I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2369
2370         /* Program PORT_TX_DW4 */
2371         /* We cannot write to GRP. It would overrite individual loadgen */
2372         for (ln = 0; ln < 4; ln++) {
2373                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2374                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2375                          CURSOR_COEFF_MASK);
2376                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2377                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2378                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2379                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2380         }
2381
2382         /* Program PORT_TX_DW5 */
2383         /* All DW5 values are fixed for every table entry */
2384         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2385         val &= ~RTERM_SELECT_MASK;
2386         val |= RTERM_SELECT(6);
2387         val |= TAP3_DISABLE;
2388         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2389
2390         /* Program PORT_TX_DW7 */
2391         val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2392         val &= ~N_SCALAR_MASK;
2393         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2394         I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2395 }
2396
2397 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2398                                     int level, enum intel_output_type type)
2399 {
2400         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2401         enum port port = encoder->port;
2402         int width, rate, ln;
2403         u32 val;
2404
2405         if (type == INTEL_OUTPUT_HDMI) {
2406                 width = 4;
2407                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2408         } else {
2409                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2410
2411                 width = intel_dp->lane_count;
2412                 rate = intel_dp->link_rate;
2413         }
2414
2415         /*
2416          * 1. If port type is eDP or DP,
2417          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2418          * else clear to 0b.
2419          */
2420         val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2421         if (type != INTEL_OUTPUT_HDMI)
2422                 val |= COMMON_KEEPER_EN;
2423         else
2424                 val &= ~COMMON_KEEPER_EN;
2425         I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2426
2427         /* 2. Program loadgen select */
2428         /*
2429          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2430          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2431          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2432          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2433          */
2434         for (ln = 0; ln <= 3; ln++) {
2435                 val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
2436                 val &= ~LOADGEN_SELECT;
2437
2438                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2439                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2440                         val |= LOADGEN_SELECT;
2441                 }
2442                 I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
2443         }
2444
2445         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2446         val = I915_READ(CNL_PORT_CL1CM_DW5);
2447         val |= SUS_CLOCK_CONFIG;
2448         I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2449
2450         /* 4. Clear training enable to change swing values */
2451         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2452         val &= ~TX_TRAINING_EN;
2453         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2454
2455         /* 5. Program swing and de-emphasis */
2456         cnl_ddi_vswing_program(encoder, level, type);
2457
2458         /* 6. Set training enable to trigger update */
2459         val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2460         val |= TX_TRAINING_EN;
2461         I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2462 }
2463
2464 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2465                                          u32 level, enum port port, int type)
2466 {
2467         const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
2468         u32 n_entries, val;
2469         int ln;
2470
2471         ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
2472                                                    &n_entries);
2473         if (!ddi_translations)
2474                 return;
2475
2476         if (level >= n_entries) {
2477                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2478                 level = n_entries - 1;
2479         }
2480
2481         /* Set PORT_TX_DW5 Rterm Sel to 110b. */
2482         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2483         val &= ~RTERM_SELECT_MASK;
2484         val |= RTERM_SELECT(0x6);
2485         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2486
2487         /* Program PORT_TX_DW5 */
2488         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2489         /* Set DisableTap2 and DisableTap3 if MIPI DSI
2490          * Clear DisableTap2 and DisableTap3 for all other Ports
2491          */
2492         if (type == INTEL_OUTPUT_DSI) {
2493                 val |= TAP2_DISABLE;
2494                 val |= TAP3_DISABLE;
2495         } else {
2496                 val &= ~TAP2_DISABLE;
2497                 val &= ~TAP3_DISABLE;
2498         }
2499         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2500
2501         /* Program PORT_TX_DW2 */
2502         val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
2503         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2504                  RCOMP_SCALAR_MASK);
2505         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
2506         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
2507         /* Program Rcomp scalar for every table entry */
2508         val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
2509         I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
2510
2511         /* Program PORT_TX_DW4 */
2512         /* We cannot write to GRP. It would overwrite individual loadgen. */
2513         for (ln = 0; ln <= 3; ln++) {
2514                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2515                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2516                          CURSOR_COEFF_MASK);
2517                 val |= ddi_translations[level].dw4_scaling;
2518                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2519         }
2520 }
2521
2522 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2523                                               u32 level,
2524                                               enum intel_output_type type)
2525 {
2526         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2527         enum port port = encoder->port;
2528         int width = 0;
2529         int rate = 0;
2530         u32 val;
2531         int ln = 0;
2532
2533         if (type == INTEL_OUTPUT_HDMI) {
2534                 width = 4;
2535                 /* Rate is always < than 6GHz for HDMI */
2536         } else {
2537                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2538
2539                 width = intel_dp->lane_count;
2540                 rate = intel_dp->link_rate;
2541         }
2542
2543         /*
2544          * 1. If port type is eDP or DP,
2545          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2546          * else clear to 0b.
2547          */
2548         val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
2549         if (type == INTEL_OUTPUT_HDMI)
2550                 val &= ~COMMON_KEEPER_EN;
2551         else
2552                 val |= COMMON_KEEPER_EN;
2553         I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
2554
2555         /* 2. Program loadgen select */
2556         /*
2557          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2558          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2559          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2560          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2561          */
2562         for (ln = 0; ln <= 3; ln++) {
2563                 val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
2564                 val &= ~LOADGEN_SELECT;
2565
2566                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2567                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2568                         val |= LOADGEN_SELECT;
2569                 }
2570                 I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
2571         }
2572
2573         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2574         val = I915_READ(ICL_PORT_CL_DW5(port));
2575         val |= SUS_CLOCK_CONFIG;
2576         I915_WRITE(ICL_PORT_CL_DW5(port), val);
2577
2578         /* 4. Clear training enable to change swing values */
2579         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2580         val &= ~TX_TRAINING_EN;
2581         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2582
2583         /* 5. Program swing and de-emphasis */
2584         icl_ddi_combo_vswing_program(dev_priv, level, port, type);
2585
2586         /* 6. Set training enable to trigger update */
2587         val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
2588         val |= TX_TRAINING_EN;
2589         I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
2590 }
2591
2592 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2593                                            int link_clock,
2594                                            u32 level)
2595 {
2596         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2597         enum port port = encoder->port;
2598         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2599         u32 n_entries, val;
2600         int ln;
2601
2602         n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2603         ddi_translations = icl_mg_phy_ddi_translations;
2604         /* The table does not have values for level 3 and level 9. */
2605         if (level >= n_entries || level == 3 || level == 9) {
2606                 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2607                               level, n_entries - 2);
2608                 level = n_entries - 2;
2609         }
2610
2611         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2612         for (ln = 0; ln < 2; ln++) {
2613                 val = I915_READ(MG_TX1_LINK_PARAMS(port, ln));
2614                 val &= ~CRI_USE_FS32;
2615                 I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val);
2616
2617                 val = I915_READ(MG_TX2_LINK_PARAMS(port, ln));
2618                 val &= ~CRI_USE_FS32;
2619                 I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val);
2620         }
2621
2622         /* Program MG_TX_SWINGCTRL with values from vswing table */
2623         for (ln = 0; ln < 2; ln++) {
2624                 val = I915_READ(MG_TX1_SWINGCTRL(port, ln));
2625                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2626                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2627                         ddi_translations[level].cri_txdeemph_override_17_12);
2628                 I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val);
2629
2630                 val = I915_READ(MG_TX2_SWINGCTRL(port, ln));
2631                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2632                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2633                         ddi_translations[level].cri_txdeemph_override_17_12);
2634                 I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val);
2635         }
2636
2637         /* Program MG_TX_DRVCTRL with values from vswing table */
2638         for (ln = 0; ln < 2; ln++) {
2639                 val = I915_READ(MG_TX1_DRVCTRL(port, ln));
2640                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2641                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2642                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2643                         ddi_translations[level].cri_txdeemph_override_5_0) |
2644                         CRI_TXDEEMPH_OVERRIDE_11_6(
2645                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2646                         CRI_TXDEEMPH_OVERRIDE_EN;
2647                 I915_WRITE(MG_TX1_DRVCTRL(port, ln), val);
2648
2649                 val = I915_READ(MG_TX2_DRVCTRL(port, ln));
2650                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2651                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2652                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2653                         ddi_translations[level].cri_txdeemph_override_5_0) |
2654                         CRI_TXDEEMPH_OVERRIDE_11_6(
2655                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2656                         CRI_TXDEEMPH_OVERRIDE_EN;
2657                 I915_WRITE(MG_TX2_DRVCTRL(port, ln), val);
2658
2659                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2660         }
2661
2662         /*
2663          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2664          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2665          * values from table for which TX1 and TX2 enabled.
2666          */
2667         for (ln = 0; ln < 2; ln++) {
2668                 val = I915_READ(MG_CLKHUB(port, ln));
2669                 if (link_clock < 300000)
2670                         val |= CFG_LOW_RATE_LKREN_EN;
2671                 else
2672                         val &= ~CFG_LOW_RATE_LKREN_EN;
2673                 I915_WRITE(MG_CLKHUB(port, ln), val);
2674         }
2675
2676         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2677         for (ln = 0; ln < 2; ln++) {
2678                 val = I915_READ(MG_TX1_DCC(port, ln));
2679                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2680                 if (link_clock <= 500000) {
2681                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2682                 } else {
2683                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2684                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2685                 }
2686                 I915_WRITE(MG_TX1_DCC(port, ln), val);
2687
2688                 val = I915_READ(MG_TX2_DCC(port, ln));
2689                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2690                 if (link_clock <= 500000) {
2691                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2692                 } else {
2693                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2694                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2695                 }
2696                 I915_WRITE(MG_TX2_DCC(port, ln), val);
2697         }
2698
2699         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2700         for (ln = 0; ln < 2; ln++) {
2701                 val = I915_READ(MG_TX1_PISO_READLOAD(port, ln));
2702                 val |= CRI_CALCINIT;
2703                 I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val);
2704
2705                 val = I915_READ(MG_TX2_PISO_READLOAD(port, ln));
2706                 val |= CRI_CALCINIT;
2707                 I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val);
2708         }
2709 }
2710
2711 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2712                                     int link_clock,
2713                                     u32 level,
2714                                     enum intel_output_type type)
2715 {
2716         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2717         enum port port = encoder->port;
2718
2719         if (intel_port_is_combophy(dev_priv, port))
2720                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2721         else
2722                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2723 }
2724
2725 static uint32_t translate_signal_level(int signal_levels)
2726 {
2727         int i;
2728
2729         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2730                 if (index_to_dp_signal_levels[i] == signal_levels)
2731                         return i;
2732         }
2733
2734         WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2735              signal_levels);
2736
2737         return 0;
2738 }
2739
2740 static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
2741 {
2742         uint8_t train_set = intel_dp->train_set[0];
2743         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2744                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2745
2746         return translate_signal_level(signal_levels);
2747 }
2748
2749 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2750 {
2751         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2752         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2753         struct intel_encoder *encoder = &dport->base;
2754         int level = intel_ddi_dp_level(intel_dp);
2755
2756         if (IS_ICELAKE(dev_priv))
2757                 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2758                                         level, encoder->type);
2759         else if (IS_CANNONLAKE(dev_priv))
2760                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2761         else
2762                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2763
2764         return 0;
2765 }
2766
2767 uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2768 {
2769         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2770         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2771         struct intel_encoder *encoder = &dport->base;
2772         int level = intel_ddi_dp_level(intel_dp);
2773
2774         if (IS_GEN9_BC(dev_priv))
2775                 skl_ddi_set_iboost(encoder, level, encoder->type);
2776
2777         return DDI_BUF_TRANS_SELECT(level);
2778 }
2779
2780 static inline
2781 uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2782                                    enum port port)
2783 {
2784         if (intel_port_is_combophy(dev_priv, port)) {
2785                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2786         } else if (intel_port_is_tc(dev_priv, port)) {
2787                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2788
2789                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2790         }
2791
2792         return 0;
2793 }
2794
2795 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2796                                   const struct intel_crtc_state *crtc_state)
2797 {
2798         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2799         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2800         enum port port = encoder->port;
2801         u32 val;
2802
2803         mutex_lock(&dev_priv->dpll_lock);
2804
2805         val = I915_READ(DPCLKA_CFGCR0_ICL);
2806         WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
2807
2808         if (intel_port_is_combophy(dev_priv, port)) {
2809                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2810                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2811                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2812                 POSTING_READ(DPCLKA_CFGCR0_ICL);
2813         }
2814
2815         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2816         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2817
2818         mutex_unlock(&dev_priv->dpll_lock);
2819 }
2820
2821 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2822 {
2823         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2824         enum port port = encoder->port;
2825         u32 val;
2826
2827         mutex_lock(&dev_priv->dpll_lock);
2828
2829         val = I915_READ(DPCLKA_CFGCR0_ICL);
2830         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2831         I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2832
2833         mutex_unlock(&dev_priv->dpll_lock);
2834 }
2835
2836 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2837 {
2838         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2839         u32 val;
2840         enum port port;
2841         u32 port_mask;
2842         bool ddi_clk_needed;
2843
2844         /*
2845          * In case of DP MST, we sanitize the primary encoder only, not the
2846          * virtual ones.
2847          */
2848         if (encoder->type == INTEL_OUTPUT_DP_MST)
2849                 return;
2850
2851         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2852                 u8 pipe_mask;
2853                 bool is_mst;
2854
2855                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2856                 /*
2857                  * In the unlikely case that BIOS enables DP in MST mode, just
2858                  * warn since our MST HW readout is incomplete.
2859                  */
2860                 if (WARN_ON(is_mst))
2861                         return;
2862         }
2863
2864         port_mask = BIT(encoder->port);
2865         ddi_clk_needed = encoder->base.crtc;
2866
2867         if (encoder->type == INTEL_OUTPUT_DSI) {
2868                 struct intel_encoder *other_encoder;
2869
2870                 port_mask = intel_dsi_encoder_ports(encoder);
2871                 /*
2872                  * Sanity check that we haven't incorrectly registered another
2873                  * encoder using any of the ports of this DSI encoder.
2874                  */
2875                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
2876                         if (other_encoder == encoder)
2877                                 continue;
2878
2879                         if (WARN_ON(port_mask & BIT(other_encoder->port)))
2880                                 return;
2881                 }
2882                 /*
2883                  * DSI ports should have their DDI clock ungated when disabled
2884                  * and gated when enabled.
2885                  */
2886                 ddi_clk_needed = !encoder->base.crtc;
2887         }
2888
2889         val = I915_READ(DPCLKA_CFGCR0_ICL);
2890         for_each_port_masked(port, port_mask) {
2891                 bool ddi_clk_ungated = !(val &
2892                                          icl_dpclka_cfgcr0_clk_off(dev_priv,
2893                                                                    port));
2894
2895                 if (ddi_clk_needed == ddi_clk_ungated)
2896                         continue;
2897
2898                 /*
2899                  * Punt on the case now where clock is gated, but it would
2900                  * be needed by the port. Something else is really broken then.
2901                  */
2902                 if (WARN_ON(ddi_clk_needed))
2903                         continue;
2904
2905                 DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2906                          port_name(port));
2907                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
2908                 I915_WRITE(DPCLKA_CFGCR0_ICL, val);
2909         }
2910 }
2911
2912 static void intel_ddi_clk_select(struct intel_encoder *encoder,
2913                                  const struct intel_crtc_state *crtc_state)
2914 {
2915         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2916         enum port port = encoder->port;
2917         uint32_t val;
2918         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2919
2920         if (WARN_ON(!pll))
2921                 return;
2922
2923         mutex_lock(&dev_priv->dpll_lock);
2924
2925         if (IS_ICELAKE(dev_priv)) {
2926                 if (!intel_port_is_combophy(dev_priv, port))
2927                         I915_WRITE(DDI_CLK_SEL(port),
2928                                    icl_pll_to_ddi_pll_sel(encoder, crtc_state));
2929         } else if (IS_CANNONLAKE(dev_priv)) {
2930                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
2931                 val = I915_READ(DPCLKA_CFGCR0);
2932                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
2933                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
2934                 I915_WRITE(DPCLKA_CFGCR0, val);
2935
2936                 /*
2937                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
2938                  * This step and the step before must be done with separate
2939                  * register writes.
2940                  */
2941                 val = I915_READ(DPCLKA_CFGCR0);
2942                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
2943                 I915_WRITE(DPCLKA_CFGCR0, val);
2944         } else if (IS_GEN9_BC(dev_priv)) {
2945                 /* DDI -> PLL mapping  */
2946                 val = I915_READ(DPLL_CTRL2);
2947
2948                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2949                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2950                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
2951                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2952
2953                 I915_WRITE(DPLL_CTRL2, val);
2954
2955         } else if (INTEL_GEN(dev_priv) < 9) {
2956                 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2957         }
2958
2959         mutex_unlock(&dev_priv->dpll_lock);
2960 }
2961
2962 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
2963 {
2964         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2965         enum port port = encoder->port;
2966
2967         if (IS_ICELAKE(dev_priv)) {
2968                 if (!intel_port_is_combophy(dev_priv, port))
2969                         I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2970         } else if (IS_CANNONLAKE(dev_priv)) {
2971                 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
2972                            DPCLKA_CFGCR0_DDI_CLK_OFF(port));
2973         } else if (IS_GEN9_BC(dev_priv)) {
2974                 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
2975                            DPLL_CTRL2_DDI_CLK_OFF(port));
2976         } else if (INTEL_GEN(dev_priv) < 9) {
2977                 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2978         }
2979 }
2980
2981 static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
2982 {
2983         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2984         enum port port = dig_port->base.port;
2985         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
2986         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
2987         u32 val;
2988         int i;
2989
2990         if (tc_port == PORT_TC_NONE)
2991                 return;
2992
2993         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
2994                 val = I915_READ(mg_regs[i]);
2995                 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
2996                        MG_DP_MODE_CFG_TRPWR_GATING |
2997                        MG_DP_MODE_CFG_CLNPWR_GATING |
2998                        MG_DP_MODE_CFG_DIGPWR_GATING |
2999                        MG_DP_MODE_CFG_GAONPWR_GATING;
3000                 I915_WRITE(mg_regs[i], val);
3001         }
3002
3003         val = I915_READ(MG_MISC_SUS0(tc_port));
3004         val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
3005                MG_MISC_SUS0_CFG_TR2PWR_GATING |
3006                MG_MISC_SUS0_CFG_CL2PWR_GATING |
3007                MG_MISC_SUS0_CFG_GAONPWR_GATING |
3008                MG_MISC_SUS0_CFG_TRPWR_GATING |
3009                MG_MISC_SUS0_CFG_CL1PWR_GATING |
3010                MG_MISC_SUS0_CFG_DGPWR_GATING;
3011         I915_WRITE(MG_MISC_SUS0(tc_port), val);
3012 }
3013
3014 static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
3015 {
3016         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3017         enum port port = dig_port->base.port;
3018         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3019         i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
3020         u32 val;
3021         int i;
3022
3023         if (tc_port == PORT_TC_NONE)
3024                 return;
3025
3026         for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
3027                 val = I915_READ(mg_regs[i]);
3028                 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
3029                          MG_DP_MODE_CFG_TRPWR_GATING |
3030                          MG_DP_MODE_CFG_CLNPWR_GATING |
3031                          MG_DP_MODE_CFG_DIGPWR_GATING |
3032                          MG_DP_MODE_CFG_GAONPWR_GATING);
3033                 I915_WRITE(mg_regs[i], val);
3034         }
3035
3036         val = I915_READ(MG_MISC_SUS0(tc_port));
3037         val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
3038                  MG_MISC_SUS0_CFG_TR2PWR_GATING |
3039                  MG_MISC_SUS0_CFG_CL2PWR_GATING |
3040                  MG_MISC_SUS0_CFG_GAONPWR_GATING |
3041                  MG_MISC_SUS0_CFG_TRPWR_GATING |
3042                  MG_MISC_SUS0_CFG_CL1PWR_GATING |
3043                  MG_MISC_SUS0_CFG_DGPWR_GATING);
3044         I915_WRITE(MG_MISC_SUS0(tc_port), val);
3045 }
3046
3047 static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port)
3048 {
3049         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3050         enum port port = intel_dig_port->base.port;
3051         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3052         u32 ln0, ln1, lane_info;
3053
3054         if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
3055                 return;
3056
3057         ln0 = I915_READ(MG_DP_MODE(port, 0));
3058         ln1 = I915_READ(MG_DP_MODE(port, 1));
3059
3060         switch (intel_dig_port->tc_type) {
3061         case TC_PORT_TYPEC:
3062                 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3063                 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3064
3065                 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
3066                              DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3067                             DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3068
3069                 switch (lane_info) {
3070                 case 0x1:
3071                 case 0x4:
3072                         break;
3073                 case 0x2:
3074                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3075                         break;
3076                 case 0x3:
3077                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3078                                MG_DP_MODE_CFG_DP_X2_MODE;
3079                         break;
3080                 case 0x8:
3081                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3082                         break;
3083                 case 0xC:
3084                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3085                                MG_DP_MODE_CFG_DP_X2_MODE;
3086                         break;
3087                 case 0xF:
3088                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
3089                                MG_DP_MODE_CFG_DP_X2_MODE;
3090                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
3091                                MG_DP_MODE_CFG_DP_X2_MODE;
3092                         break;
3093                 default:
3094                         MISSING_CASE(lane_info);
3095                 }
3096                 break;
3097
3098         case TC_PORT_LEGACY:
3099                 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3100                 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
3101                 break;
3102
3103         default:
3104                 MISSING_CASE(intel_dig_port->tc_type);
3105                 return;
3106         }
3107
3108         I915_WRITE(MG_DP_MODE(port, 0), ln0);
3109         I915_WRITE(MG_DP_MODE(port, 1), ln1);
3110 }
3111
3112 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3113                                         const struct intel_crtc_state *crtc_state)
3114 {
3115         if (!crtc_state->fec_enable)
3116                 return;
3117
3118         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3119                 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3120 }
3121
3122 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3123                                  const struct intel_crtc_state *crtc_state)
3124 {
3125         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3126         enum port port = encoder->port;
3127         u32 val;
3128
3129         if (!crtc_state->fec_enable)
3130                 return;
3131
3132         val = I915_READ(DP_TP_CTL(port));
3133         val |= DP_TP_CTL_FEC_ENABLE;
3134         I915_WRITE(DP_TP_CTL(port), val);
3135
3136         if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port),
3137                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3138                                     DP_TP_STATUS_FEC_ENABLE_LIVE,
3139                                     1))
3140                 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3141 }
3142
3143 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3144                                         const struct intel_crtc_state *crtc_state)
3145 {
3146         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3147         enum port port = encoder->port;
3148         u32 val;
3149
3150         if (!crtc_state->fec_enable)
3151                 return;
3152
3153         val = I915_READ(DP_TP_CTL(port));
3154         val &= ~DP_TP_CTL_FEC_ENABLE;
3155         I915_WRITE(DP_TP_CTL(port), val);
3156         POSTING_READ(DP_TP_CTL(port));
3157 }
3158
3159 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3160                                     const struct intel_crtc_state *crtc_state,
3161                                     const struct drm_connector_state *conn_state)
3162 {
3163         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3164         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3165         enum port port = encoder->port;
3166         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3167         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3168         int level = intel_ddi_dp_level(intel_dp);
3169
3170         WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3171
3172         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3173                                  crtc_state->lane_count, is_mst);
3174
3175         intel_edp_panel_on(intel_dp);
3176
3177         intel_ddi_clk_select(encoder, crtc_state);
3178
3179         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3180
3181         icl_program_mg_dp_mode(dig_port);
3182         icl_disable_phy_clock_gating(dig_port);
3183
3184         if (IS_ICELAKE(dev_priv))
3185                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3186                                         level, encoder->type);
3187         else if (IS_CANNONLAKE(dev_priv))
3188                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3189         else if (IS_GEN9_LP(dev_priv))
3190                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3191         else
3192                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3193
3194         intel_ddi_init_dp_buf_reg(encoder);
3195         if (!is_mst)
3196                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3197         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3198                                               true);
3199         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3200         intel_dp_start_link_train(intel_dp);
3201         if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
3202                 intel_dp_stop_link_train(intel_dp);
3203
3204         intel_ddi_enable_fec(encoder, crtc_state);
3205
3206         icl_enable_phy_clock_gating(dig_port);
3207
3208         if (!is_mst)
3209                 intel_ddi_enable_pipe_clock(crtc_state);
3210
3211         intel_dsc_enable(encoder, crtc_state);
3212 }
3213
3214 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3215                                       const struct intel_crtc_state *crtc_state,
3216                                       const struct drm_connector_state *conn_state)
3217 {
3218         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
3219         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3220         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3221         enum port port = encoder->port;
3222         int level = intel_ddi_hdmi_level(dev_priv, port);
3223         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3224
3225         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3226         intel_ddi_clk_select(encoder, crtc_state);
3227
3228         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3229
3230         icl_program_mg_dp_mode(dig_port);
3231         icl_disable_phy_clock_gating(dig_port);
3232
3233         if (IS_ICELAKE(dev_priv))
3234                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3235                                         level, INTEL_OUTPUT_HDMI);
3236         else if (IS_CANNONLAKE(dev_priv))
3237                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3238         else if (IS_GEN9_LP(dev_priv))
3239                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3240         else
3241                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3242
3243         icl_enable_phy_clock_gating(dig_port);
3244
3245         if (IS_GEN9_BC(dev_priv))
3246                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3247
3248         intel_ddi_enable_pipe_clock(crtc_state);
3249
3250         intel_dig_port->set_infoframes(encoder,
3251                                        crtc_state->has_infoframe,
3252                                        crtc_state, conn_state);
3253 }
3254
3255 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3256                                  const struct intel_crtc_state *crtc_state,
3257                                  const struct drm_connector_state *conn_state)
3258 {
3259         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3260         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3261         enum pipe pipe = crtc->pipe;
3262
3263         /*
3264          * When called from DP MST code:
3265          * - conn_state will be NULL
3266          * - encoder will be the main encoder (ie. mst->primary)
3267          * - the main connector associated with this port
3268          *   won't be active or linked to a crtc
3269          * - crtc_state will be the state of the first stream to
3270          *   be activated on this port, and it may not be the same
3271          *   stream that will be deactivated last, but each stream
3272          *   should have a state that is identical when it comes to
3273          *   the DP link parameteres
3274          */
3275
3276         WARN_ON(crtc_state->has_pch_encoder);
3277
3278         if (INTEL_GEN(dev_priv) >= 11)
3279                 icl_map_plls_to_ports(encoder, crtc_state);
3280
3281         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3282
3283         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3284                 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3285         } else {
3286                 struct intel_lspcon *lspcon =
3287                                 enc_to_intel_lspcon(&encoder->base);
3288
3289                 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3290                 if (lspcon->active) {
3291                         struct intel_digital_port *dig_port =
3292                                         enc_to_dig_port(&encoder->base);
3293
3294                         dig_port->set_infoframes(encoder,
3295                                                  crtc_state->has_infoframe,
3296                                                  crtc_state, conn_state);
3297                 }
3298         }
3299 }
3300
3301 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3302                                   const struct intel_crtc_state *crtc_state)
3303 {
3304         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3305         enum port port = encoder->port;
3306         bool wait = false;
3307         u32 val;
3308
3309         val = I915_READ(DDI_BUF_CTL(port));
3310         if (val & DDI_BUF_CTL_ENABLE) {
3311                 val &= ~DDI_BUF_CTL_ENABLE;
3312                 I915_WRITE(DDI_BUF_CTL(port), val);
3313                 wait = true;
3314         }
3315
3316         val = I915_READ(DP_TP_CTL(port));
3317         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3318         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3319         I915_WRITE(DP_TP_CTL(port), val);
3320
3321         /* Disable FEC in DP Sink */
3322         intel_ddi_disable_fec_state(encoder, crtc_state);
3323
3324         if (wait)
3325                 intel_wait_ddi_buf_idle(dev_priv, port);
3326 }
3327
3328 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3329                                       const struct intel_crtc_state *old_crtc_state,
3330                                       const struct drm_connector_state *old_conn_state)
3331 {
3332         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3333         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3334         struct intel_dp *intel_dp = &dig_port->dp;
3335         bool is_mst = intel_crtc_has_type(old_crtc_state,
3336                                           INTEL_OUTPUT_DP_MST);
3337
3338         if (!is_mst) {
3339                 intel_ddi_disable_pipe_clock(old_crtc_state);
3340                 /*
3341                  * Power down sink before disabling the port, otherwise we end
3342                  * up getting interrupts from the sink on detecting link loss.
3343                  */
3344                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3345         }
3346
3347         intel_disable_ddi_buf(encoder, old_crtc_state);
3348
3349         intel_edp_panel_vdd_on(intel_dp);
3350         intel_edp_panel_off(intel_dp);
3351
3352         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3353
3354         intel_ddi_clk_disable(encoder);
3355 }
3356
3357 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3358                                         const struct intel_crtc_state *old_crtc_state,
3359                                         const struct drm_connector_state *old_conn_state)
3360 {
3361         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3362         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3363         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3364
3365         dig_port->set_infoframes(encoder, false,
3366                                  old_crtc_state, old_conn_state);
3367
3368         intel_ddi_disable_pipe_clock(old_crtc_state);
3369
3370         intel_disable_ddi_buf(encoder, old_crtc_state);
3371
3372         intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
3373
3374         intel_ddi_clk_disable(encoder);
3375
3376         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3377 }
3378
3379 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3380                                    const struct intel_crtc_state *old_crtc_state,
3381                                    const struct drm_connector_state *old_conn_state)
3382 {
3383         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3384
3385         /*
3386          * When called from DP MST code:
3387          * - old_conn_state will be NULL
3388          * - encoder will be the main encoder (ie. mst->primary)
3389          * - the main connector associated with this port
3390          *   won't be active or linked to a crtc
3391          * - old_crtc_state will be the state of the last stream to
3392          *   be deactivated on this port, and it may not be the same
3393          *   stream that was activated last, but each stream
3394          *   should have a state that is identical when it comes to
3395          *   the DP link parameteres
3396          */
3397
3398         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3399                 intel_ddi_post_disable_hdmi(encoder,
3400                                             old_crtc_state, old_conn_state);
3401         else
3402                 intel_ddi_post_disable_dp(encoder,
3403                                           old_crtc_state, old_conn_state);
3404
3405         if (INTEL_GEN(dev_priv) >= 11)
3406                 icl_unmap_plls_to_ports(encoder);
3407 }
3408
3409 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3410                                 const struct intel_crtc_state *old_crtc_state,
3411                                 const struct drm_connector_state *old_conn_state)
3412 {
3413         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3414         uint32_t val;
3415
3416         /*
3417          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3418          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3419          * step 13 is the correct place for it. Step 18 is where it was
3420          * originally before the BUN.
3421          */
3422         val = I915_READ(FDI_RX_CTL(PIPE_A));
3423         val &= ~FDI_RX_ENABLE;
3424         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3425
3426         intel_disable_ddi_buf(encoder, old_crtc_state);
3427         intel_ddi_clk_disable(encoder);
3428
3429         val = I915_READ(FDI_RX_MISC(PIPE_A));
3430         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3431         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3432         I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3433
3434         val = I915_READ(FDI_RX_CTL(PIPE_A));
3435         val &= ~FDI_PCDCLK;
3436         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3437
3438         val = I915_READ(FDI_RX_CTL(PIPE_A));
3439         val &= ~FDI_RX_PLL_ENABLE;
3440         I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3441 }
3442
3443 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3444                                 const struct intel_crtc_state *crtc_state,
3445                                 const struct drm_connector_state *conn_state)
3446 {
3447         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3448         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3449         enum port port = encoder->port;
3450
3451         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3452                 intel_dp_stop_link_train(intel_dp);
3453
3454         intel_edp_backlight_on(crtc_state, conn_state);
3455         intel_psr_enable(intel_dp, crtc_state);
3456         intel_edp_drrs_enable(intel_dp, crtc_state);
3457
3458         if (crtc_state->has_audio)
3459                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3460 }
3461
3462 static i915_reg_t
3463 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3464                                enum port port)
3465 {
3466         static const i915_reg_t regs[] = {
3467                 [PORT_A] = CHICKEN_TRANS_EDP,
3468                 [PORT_B] = CHICKEN_TRANS_A,
3469                 [PORT_C] = CHICKEN_TRANS_B,
3470                 [PORT_D] = CHICKEN_TRANS_C,
3471                 [PORT_E] = CHICKEN_TRANS_A,
3472         };
3473
3474         WARN_ON(INTEL_GEN(dev_priv) < 9);
3475
3476         if (WARN_ON(port < PORT_A || port > PORT_E))
3477                 port = PORT_A;
3478
3479         return regs[port];
3480 }
3481
3482 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3483                                   const struct intel_crtc_state *crtc_state,
3484                                   const struct drm_connector_state *conn_state)
3485 {
3486         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3487         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3488         struct drm_connector *connector = conn_state->connector;
3489         enum port port = encoder->port;
3490
3491         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3492                                                crtc_state->hdmi_high_tmds_clock_ratio,
3493                                                crtc_state->hdmi_scrambling))
3494                 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3495                           connector->base.id, connector->name);
3496
3497         /* Display WA #1143: skl,kbl,cfl */
3498         if (IS_GEN9_BC(dev_priv)) {
3499                 /*
3500                  * For some reason these chicken bits have been
3501                  * stuffed into a transcoder register, event though
3502                  * the bits affect a specific DDI port rather than
3503                  * a specific transcoder.
3504                  */
3505                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3506                 u32 val;
3507
3508                 val = I915_READ(reg);
3509
3510                 if (port == PORT_E)
3511                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3512                                 DDIE_TRAINING_OVERRIDE_VALUE;
3513                 else
3514                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3515                                 DDI_TRAINING_OVERRIDE_VALUE;
3516
3517                 I915_WRITE(reg, val);
3518                 POSTING_READ(reg);
3519
3520                 udelay(1);
3521
3522                 if (port == PORT_E)
3523                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3524                                  DDIE_TRAINING_OVERRIDE_VALUE);
3525                 else
3526                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3527                                  DDI_TRAINING_OVERRIDE_VALUE);
3528
3529                 I915_WRITE(reg, val);
3530         }
3531
3532         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3533          * are ignored so nothing special needs to be done besides
3534          * enabling the port.
3535          */
3536         I915_WRITE(DDI_BUF_CTL(port),
3537                    dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3538
3539         if (crtc_state->has_audio)
3540                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3541 }
3542
3543 static void intel_enable_ddi(struct intel_encoder *encoder,
3544                              const struct intel_crtc_state *crtc_state,
3545                              const struct drm_connector_state *conn_state)
3546 {
3547         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3548                 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
3549         else
3550                 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
3551
3552         /* Enable hdcp if it's desired */
3553         if (conn_state->content_protection ==
3554             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3555                 intel_hdcp_enable(to_intel_connector(conn_state->connector));
3556 }
3557
3558 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
3559                                  const struct intel_crtc_state *old_crtc_state,
3560                                  const struct drm_connector_state *old_conn_state)
3561 {
3562         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3563
3564         intel_dp->link_trained = false;
3565
3566         if (old_crtc_state->has_audio)
3567                 intel_audio_codec_disable(encoder,
3568                                           old_crtc_state, old_conn_state);
3569
3570         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3571         intel_psr_disable(intel_dp, old_crtc_state);
3572         intel_edp_backlight_off(old_conn_state);
3573         /* Disable the decompression in DP Sink */
3574         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3575                                               false);
3576 }
3577
3578 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
3579                                    const struct intel_crtc_state *old_crtc_state,
3580                                    const struct drm_connector_state *old_conn_state)
3581 {
3582         struct drm_connector *connector = old_conn_state->connector;
3583
3584         if (old_crtc_state->has_audio)
3585                 intel_audio_codec_disable(encoder,
3586                                           old_crtc_state, old_conn_state);
3587
3588         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3589                                                false, false))
3590                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3591                               connector->base.id, connector->name);
3592 }
3593
3594 static void intel_disable_ddi(struct intel_encoder *encoder,
3595                               const struct intel_crtc_state *old_crtc_state,
3596                               const struct drm_connector_state *old_conn_state)
3597 {
3598         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3599
3600         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3601                 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
3602         else
3603                 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
3604 }
3605
3606 static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
3607                                          const struct intel_crtc_state *pipe_config,
3608                                          enum port port)
3609 {
3610         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3611         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3612         enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
3613         u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
3614         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3615
3616         val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
3617         switch (pipe_config->lane_count) {
3618         case 1:
3619                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
3620                 DFLEXDPMLE1_DPMLETC_ML0(tc_port);
3621                 break;
3622         case 2:
3623                 val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
3624                 DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
3625                 break;
3626         case 4:
3627                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3628                 break;
3629         default:
3630                 MISSING_CASE(pipe_config->lane_count);
3631         }
3632         I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3633 }
3634
3635 static void
3636 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
3637                          const struct intel_crtc_state *crtc_state,
3638                          const struct drm_connector_state *conn_state)
3639 {
3640         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3641         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3642         enum port port = encoder->port;
3643
3644         if (intel_crtc_has_dp_encoder(crtc_state) ||
3645             intel_port_is_tc(dev_priv, encoder->port))
3646                 intel_display_power_get(dev_priv,
3647                                         intel_ddi_main_link_aux_domain(dig_port));
3648
3649         if (IS_GEN9_LP(dev_priv))
3650                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3651                                                 crtc_state->lane_lat_optim_mask);
3652
3653         /*
3654          * Program the lane count for static/dynamic connections on Type-C ports.
3655          * Skip this step for TBT.
3656          */
3657         if (dig_port->tc_type == TC_PORT_UNKNOWN ||
3658             dig_port->tc_type == TC_PORT_TBT)
3659                 return;
3660
3661         intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3662 }
3663
3664 static void
3665 intel_ddi_post_pll_disable(struct intel_encoder *encoder,
3666                            const struct intel_crtc_state *crtc_state,
3667                            const struct drm_connector_state *conn_state)
3668 {
3669         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3670         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3671
3672         if (intel_crtc_has_dp_encoder(crtc_state) ||
3673             intel_port_is_tc(dev_priv, encoder->port))
3674                 intel_display_power_put(dev_priv,
3675                                         intel_ddi_main_link_aux_domain(dig_port));
3676 }
3677
3678 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
3679 {
3680         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3681         struct drm_i915_private *dev_priv =
3682                 to_i915(intel_dig_port->base.base.dev);
3683         enum port port = intel_dig_port->base.port;
3684         uint32_t val;
3685         bool wait = false;
3686
3687         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3688                 val = I915_READ(DDI_BUF_CTL(port));
3689                 if (val & DDI_BUF_CTL_ENABLE) {
3690                         val &= ~DDI_BUF_CTL_ENABLE;
3691                         I915_WRITE(DDI_BUF_CTL(port), val);
3692                         wait = true;
3693                 }
3694
3695                 val = I915_READ(DP_TP_CTL(port));
3696                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3697                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3698                 I915_WRITE(DP_TP_CTL(port), val);
3699                 POSTING_READ(DP_TP_CTL(port));
3700
3701                 if (wait)
3702                         intel_wait_ddi_buf_idle(dev_priv, port);
3703         }
3704
3705         val = DP_TP_CTL_ENABLE |
3706               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3707         if (intel_dp->link_mst)
3708                 val |= DP_TP_CTL_MODE_MST;
3709         else {
3710                 val |= DP_TP_CTL_MODE_SST;
3711                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3712                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3713         }
3714         I915_WRITE(DP_TP_CTL(port), val);
3715         POSTING_READ(DP_TP_CTL(port));
3716
3717         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3718         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3719         POSTING_READ(DDI_BUF_CTL(port));
3720
3721         udelay(600);
3722 }
3723
3724 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3725                                        enum transcoder cpu_transcoder)
3726 {
3727         if (cpu_transcoder == TRANSCODER_EDP)
3728                 return false;
3729
3730         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
3731                 return false;
3732
3733         return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
3734                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3735 }
3736
3737 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3738                                          struct intel_crtc_state *crtc_state)
3739 {
3740         if (IS_ICELAKE(dev_priv) && crtc_state->port_clock > 594000)
3741                 crtc_state->min_voltage_level = 1;
3742         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
3743                 crtc_state->min_voltage_level = 2;
3744 }
3745
3746 void intel_ddi_get_config(struct intel_encoder *encoder,
3747                           struct intel_crtc_state *pipe_config)
3748 {
3749         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3750         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3751         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3752         struct intel_digital_port *intel_dig_port;
3753         u32 temp, flags = 0;
3754
3755         /* XXX: DSI transcoder paranoia */
3756         if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
3757                 return;
3758
3759         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3760         if (temp & TRANS_DDI_PHSYNC)
3761                 flags |= DRM_MODE_FLAG_PHSYNC;
3762         else
3763                 flags |= DRM_MODE_FLAG_NHSYNC;
3764         if (temp & TRANS_DDI_PVSYNC)
3765                 flags |= DRM_MODE_FLAG_PVSYNC;
3766         else
3767                 flags |= DRM_MODE_FLAG_NVSYNC;
3768
3769         pipe_config->base.adjusted_mode.flags |= flags;
3770
3771         switch (temp & TRANS_DDI_BPC_MASK) {
3772         case TRANS_DDI_BPC_6:
3773                 pipe_config->pipe_bpp = 18;
3774                 break;
3775         case TRANS_DDI_BPC_8:
3776                 pipe_config->pipe_bpp = 24;
3777                 break;
3778         case TRANS_DDI_BPC_10:
3779                 pipe_config->pipe_bpp = 30;
3780                 break;
3781         case TRANS_DDI_BPC_12:
3782                 pipe_config->pipe_bpp = 36;
3783                 break;
3784         default:
3785                 break;
3786         }
3787
3788         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3789         case TRANS_DDI_MODE_SELECT_HDMI:
3790                 pipe_config->has_hdmi_sink = true;
3791                 intel_dig_port = enc_to_dig_port(&encoder->base);
3792
3793                 if (intel_dig_port->infoframe_enabled(encoder, pipe_config))
3794                         pipe_config->has_infoframe = true;
3795
3796                 if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
3797                         TRANS_DDI_HDMI_SCRAMBLING_MASK)
3798                         pipe_config->hdmi_scrambling = true;
3799                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3800                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3801                 /* fall through */
3802         case TRANS_DDI_MODE_SELECT_DVI:
3803                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3804                 pipe_config->lane_count = 4;
3805                 break;
3806         case TRANS_DDI_MODE_SELECT_FDI:
3807                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3808                 break;
3809         case TRANS_DDI_MODE_SELECT_DP_SST:
3810                 if (encoder->type == INTEL_OUTPUT_EDP)
3811                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3812                 else
3813                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3814                 pipe_config->lane_count =
3815                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3816                 intel_dp_get_m_n(intel_crtc, pipe_config);
3817                 break;
3818         case TRANS_DDI_MODE_SELECT_DP_MST:
3819                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3820                 pipe_config->lane_count =
3821                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3822                 intel_dp_get_m_n(intel_crtc, pipe_config);
3823                 break;
3824         default:
3825                 break;
3826         }
3827
3828         pipe_config->has_audio =
3829                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3830
3831         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
3832             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3833                 /*
3834                  * This is a big fat ugly hack.
3835                  *
3836                  * Some machines in UEFI boot mode provide us a VBT that has 18
3837                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3838                  * unknown we fail to light up. Yet the same BIOS boots up with
3839                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3840                  * max, not what it tells us to use.
3841                  *
3842                  * Note: This will still be broken if the eDP panel is not lit
3843                  * up by the BIOS, and thus we can't get the mode at module
3844                  * load.
3845                  */
3846                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3847                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3848                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3849         }
3850
3851         intel_ddi_clock_get(encoder, pipe_config);
3852
3853         if (IS_GEN9_LP(dev_priv))
3854                 pipe_config->lane_lat_optim_mask =
3855                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3856
3857         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3858 }
3859
3860 static enum intel_output_type
3861 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3862                               struct intel_crtc_state *crtc_state,
3863                               struct drm_connector_state *conn_state)
3864 {
3865         switch (conn_state->connector->connector_type) {
3866         case DRM_MODE_CONNECTOR_HDMIA:
3867                 return INTEL_OUTPUT_HDMI;
3868         case DRM_MODE_CONNECTOR_eDP:
3869                 return INTEL_OUTPUT_EDP;
3870         case DRM_MODE_CONNECTOR_DisplayPort:
3871                 return INTEL_OUTPUT_DP;
3872         default:
3873                 MISSING_CASE(conn_state->connector->connector_type);
3874                 return INTEL_OUTPUT_UNUSED;
3875         }
3876 }
3877
3878 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3879                                      struct intel_crtc_state *pipe_config,
3880                                      struct drm_connector_state *conn_state)
3881 {
3882         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3883         enum port port = encoder->port;
3884         int ret;
3885
3886         if (port == PORT_A)
3887                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3888
3889         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
3890                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3891         else
3892                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3893
3894         if (IS_GEN9_LP(dev_priv) && ret)
3895                 pipe_config->lane_lat_optim_mask =
3896                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3897
3898         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3899
3900         return ret;
3901
3902 }
3903
3904 static const struct drm_encoder_funcs intel_ddi_funcs = {
3905         .reset = intel_dp_encoder_reset,
3906         .destroy = intel_dp_encoder_destroy,
3907 };
3908
3909 static struct intel_connector *
3910 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3911 {
3912         struct intel_connector *connector;
3913         enum port port = intel_dig_port->base.port;
3914
3915         connector = intel_connector_alloc();
3916         if (!connector)
3917                 return NULL;
3918
3919         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3920         if (!intel_dp_init_connector(intel_dig_port, connector)) {
3921                 kfree(connector);
3922                 return NULL;
3923         }
3924
3925         return connector;
3926 }
3927
3928 static int modeset_pipe(struct drm_crtc *crtc,
3929                         struct drm_modeset_acquire_ctx *ctx)
3930 {
3931         struct drm_atomic_state *state;
3932         struct drm_crtc_state *crtc_state;
3933         int ret;
3934
3935         state = drm_atomic_state_alloc(crtc->dev);
3936         if (!state)
3937                 return -ENOMEM;
3938
3939         state->acquire_ctx = ctx;
3940
3941         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3942         if (IS_ERR(crtc_state)) {
3943                 ret = PTR_ERR(crtc_state);
3944                 goto out;
3945         }
3946
3947         crtc_state->mode_changed = true;
3948
3949         ret = drm_atomic_add_affected_connectors(state, crtc);
3950         if (ret)
3951                 goto out;
3952
3953         ret = drm_atomic_add_affected_planes(state, crtc);
3954         if (ret)
3955                 goto out;
3956
3957         ret = drm_atomic_commit(state);
3958         if (ret)
3959                 goto out;
3960
3961         return 0;
3962
3963  out:
3964         drm_atomic_state_put(state);
3965
3966         return ret;
3967 }
3968
3969 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3970                                  struct drm_modeset_acquire_ctx *ctx)
3971 {
3972         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3973         struct intel_hdmi *hdmi = enc_to_intel_hdmi(&encoder->base);
3974         struct intel_connector *connector = hdmi->attached_connector;
3975         struct i2c_adapter *adapter =
3976                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3977         struct drm_connector_state *conn_state;
3978         struct intel_crtc_state *crtc_state;
3979         struct intel_crtc *crtc;
3980         u8 config;
3981         int ret;
3982
3983         if (!connector || connector->base.status != connector_status_connected)
3984                 return 0;
3985
3986         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3987                                ctx);
3988         if (ret)
3989                 return ret;
3990
3991         conn_state = connector->base.state;
3992
3993         crtc = to_intel_crtc(conn_state->crtc);
3994         if (!crtc)
3995                 return 0;
3996
3997         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3998         if (ret)
3999                 return ret;
4000
4001         crtc_state = to_intel_crtc_state(crtc->base.state);
4002
4003         WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4004
4005         if (!crtc_state->base.active)
4006                 return 0;
4007
4008         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4009             !crtc_state->hdmi_scrambling)
4010                 return 0;
4011
4012         if (conn_state->commit &&
4013             !try_wait_for_completion(&conn_state->commit->hw_done))
4014                 return 0;
4015
4016         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4017         if (ret < 0) {
4018                 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4019                 return 0;
4020         }
4021
4022         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4023             crtc_state->hdmi_high_tmds_clock_ratio &&
4024             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4025             crtc_state->hdmi_scrambling)
4026                 return 0;
4027
4028         /*
4029          * HDMI 2.0 says that one should not send scrambled data
4030          * prior to configuring the sink scrambling, and that
4031          * TMDS clock/data transmission should be suspended when
4032          * changing the TMDS clock rate in the sink. So let's
4033          * just do a full modeset here, even though some sinks
4034          * would be perfectly happy if were to just reconfigure
4035          * the SCDC settings on the fly.
4036          */
4037         return modeset_pipe(&crtc->base, ctx);
4038 }
4039
4040 static bool intel_ddi_hotplug(struct intel_encoder *encoder,
4041                               struct intel_connector *connector)
4042 {
4043         struct drm_modeset_acquire_ctx ctx;
4044         bool changed;
4045         int ret;
4046
4047         changed = intel_encoder_hotplug(encoder, connector);
4048
4049         drm_modeset_acquire_init(&ctx, 0);
4050
4051         for (;;) {
4052                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4053                         ret = intel_hdmi_reset_link(encoder, &ctx);
4054                 else
4055                         ret = intel_dp_retrain_link(encoder, &ctx);
4056
4057                 if (ret == -EDEADLK) {
4058                         drm_modeset_backoff(&ctx);
4059                         continue;
4060                 }
4061
4062                 break;
4063         }
4064
4065         drm_modeset_drop_locks(&ctx);
4066         drm_modeset_acquire_fini(&ctx);
4067         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4068
4069         return changed;
4070 }
4071
4072 static struct intel_connector *
4073 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4074 {
4075         struct intel_connector *connector;
4076         enum port port = intel_dig_port->base.port;
4077
4078         connector = intel_connector_alloc();
4079         if (!connector)
4080                 return NULL;
4081
4082         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4083         intel_hdmi_init_connector(intel_dig_port, connector);
4084
4085         return connector;
4086 }
4087
4088 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4089 {
4090         struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4091
4092         if (dport->base.port != PORT_A)
4093                 return false;
4094
4095         if (dport->saved_port_bits & DDI_A_4_LANES)
4096                 return false;
4097
4098         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4099          *                     supported configuration
4100          */
4101         if (IS_GEN9_LP(dev_priv))
4102                 return true;
4103
4104         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4105          *             one who does also have a full A/E split called
4106          *             DDI_F what makes DDI_E useless. However for this
4107          *             case let's trust VBT info.
4108          */
4109         if (IS_CANNONLAKE(dev_priv) &&
4110             !intel_bios_is_port_present(dev_priv, PORT_E))
4111                 return true;
4112
4113         return false;
4114 }
4115
4116 static int
4117 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4118 {
4119         struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4120         enum port port = intel_dport->base.port;
4121         int max_lanes = 4;
4122
4123         if (INTEL_GEN(dev_priv) >= 11)
4124                 return max_lanes;
4125
4126         if (port == PORT_A || port == PORT_E) {
4127                 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4128                         max_lanes = port == PORT_A ? 4 : 0;
4129                 else
4130                         /* Both A and E share 2 lanes */
4131                         max_lanes = 2;
4132         }
4133
4134         /*
4135          * Some BIOS might fail to set this bit on port A if eDP
4136          * wasn't lit up at boot.  Force this bit set when needed
4137          * so we use the proper lane count for our calculations.
4138          */
4139         if (intel_ddi_a_force_4_lanes(intel_dport)) {
4140                 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4141                 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4142                 max_lanes = 4;
4143         }
4144
4145         return max_lanes;
4146 }
4147
4148 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4149 {
4150         struct intel_digital_port *intel_dig_port;
4151         struct intel_encoder *intel_encoder;
4152         struct drm_encoder *encoder;
4153         bool init_hdmi, init_dp, init_lspcon = false;
4154         enum pipe pipe;
4155
4156
4157         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
4158                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
4159         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
4160
4161         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4162                 /*
4163                  * Lspcon device needs to be driven with DP connector
4164                  * with special detection sequence. So make sure DP
4165                  * is initialized before lspcon.
4166                  */
4167                 init_dp = true;
4168                 init_lspcon = true;
4169                 init_hdmi = false;
4170                 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4171         }
4172
4173         if (!init_dp && !init_hdmi) {
4174                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4175                               port_name(port));
4176                 return;
4177         }
4178
4179         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4180         if (!intel_dig_port)
4181                 return;
4182
4183         intel_encoder = &intel_dig_port->base;
4184         encoder = &intel_encoder->base;
4185
4186         drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
4187                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4188
4189         intel_encoder->hotplug = intel_ddi_hotplug;
4190         intel_encoder->compute_output_type = intel_ddi_compute_output_type;
4191         intel_encoder->compute_config = intel_ddi_compute_config;
4192         intel_encoder->enable = intel_enable_ddi;
4193         intel_encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4194         intel_encoder->post_pll_disable = intel_ddi_post_pll_disable;
4195         intel_encoder->pre_enable = intel_ddi_pre_enable;
4196         intel_encoder->disable = intel_disable_ddi;
4197         intel_encoder->post_disable = intel_ddi_post_disable;
4198         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4199         intel_encoder->get_config = intel_ddi_get_config;
4200         intel_encoder->suspend = intel_dp_encoder_suspend;
4201         intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4202         intel_encoder->type = INTEL_OUTPUT_DDI;
4203         intel_encoder->power_domain = intel_port_to_power_domain(port);
4204         intel_encoder->port = port;
4205         intel_encoder->cloneable = 0;
4206         for_each_pipe(dev_priv, pipe)
4207                 intel_encoder->crtc_mask |= BIT(pipe);
4208
4209         if (INTEL_GEN(dev_priv) >= 11)
4210                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4211                         DDI_BUF_PORT_REVERSAL;
4212         else
4213                 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4214                         (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4215         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4216         intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4217         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4218
4219         switch (port) {
4220         case PORT_A:
4221                 intel_dig_port->ddi_io_power_domain =
4222                         POWER_DOMAIN_PORT_DDI_A_IO;
4223                 break;
4224         case PORT_B:
4225                 intel_dig_port->ddi_io_power_domain =
4226                         POWER_DOMAIN_PORT_DDI_B_IO;
4227                 break;
4228         case PORT_C:
4229                 intel_dig_port->ddi_io_power_domain =
4230                         POWER_DOMAIN_PORT_DDI_C_IO;
4231                 break;
4232         case PORT_D:
4233                 intel_dig_port->ddi_io_power_domain =
4234                         POWER_DOMAIN_PORT_DDI_D_IO;
4235                 break;
4236         case PORT_E:
4237                 intel_dig_port->ddi_io_power_domain =
4238                         POWER_DOMAIN_PORT_DDI_E_IO;
4239                 break;
4240         case PORT_F:
4241                 intel_dig_port->ddi_io_power_domain =
4242                         POWER_DOMAIN_PORT_DDI_F_IO;
4243                 break;
4244         default:
4245                 MISSING_CASE(port);
4246         }
4247
4248         if (init_dp) {
4249                 if (!intel_ddi_init_dp_connector(intel_dig_port))
4250                         goto err;
4251
4252                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4253         }
4254
4255         /* In theory we don't need the encoder->type check, but leave it just in
4256          * case we have some really bad VBTs... */
4257         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4258                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4259                         goto err;
4260         }
4261
4262         if (init_lspcon) {
4263                 if (lspcon_init(intel_dig_port))
4264                         /* TODO: handle hdmi info frame part */
4265                         DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4266                                 port_name(port));
4267                 else
4268                         /*
4269                          * LSPCON init faied, but DP init was success, so
4270                          * lets try to drive as DP++ port.
4271                          */
4272                         DRM_ERROR("LSPCON init failed on port %c\n",
4273                                 port_name(port));
4274         }
4275
4276         intel_infoframe_init(intel_dig_port);
4277         return;
4278
4279 err:
4280         drm_encoder_cleanup(encoder);
4281         kfree(intel_dig_port);
4282 }