drivers/crypto/caam/ctrl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* * CAAM control-plane driver backend
   3  * Controller-level driver, kernel property detection, initialization
   4  *
   5  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/device.h>
   9 #include <linux/of_address.h>
  10 #include <linux/of_irq.h>
  11 #include <linux/sys_soc.h>
  12
  13 #include "compat.h"
  14 #include "regs.h"
  15 #include "intern.h"
  16 #include "jr.h"
  17 #include "desc_constr.h"
  18 #include "ctrl.h"
  19
  20 bool caam_little_end;
  21 EXPORT_SYMBOL(caam_little_end);
  22 bool caam_dpaa2;
  23 EXPORT_SYMBOL(caam_dpaa2);
  24 bool caam_imx;
  25 EXPORT_SYMBOL(caam_imx);
  26
  27 #ifdef CONFIG_CAAM_QI
  28 #include "qi.h"
  29 #endif
  30
  31 /*
  32  * i.MX targets tend to have clock control subsystems that can
  33  * enable/disable clocking to our device.
  34  */
  35 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  36                                                 char *clk_name)
  37 {
  38         return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
  39 }
  40
  41 /*
  42  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  43  * load the JDKEK, TDKEK and TDSK registers
  44  */
  45 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
  46 {
  47         u32 *jump_cmd, op_flags;
  48
  49         init_job_desc(desc, 0);
  50
  51         op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  52                         (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
  53
  54         /* INIT RNG in non-test mode */
  55         append_operation(desc, op_flags);
  56
  57         if (!handle && do_sk) {
  58                 /*
  59                  * For SH0, Secure Keys must be generated as well
  60                  */
  61
  62                 /* wait for done */
  63                 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
  64                 set_jump_tgt_here(desc, jump_cmd);
  65
  66                 /*
  67                  * load 1 to clear written reg:
  68                  * resets the done interrrupt and returns the RNG to idle.
  69                  */
  70                 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
  71
  72                 /* Initialize State Handle  */
  73                 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  74                                  OP_ALG_AAI_RNG4_SK);
  75         }
  76
  77         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  78 }
  79
  80 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
  81 static void build_deinstantiation_desc(u32 *desc, int handle)
  82 {
  83         init_job_desc(desc, 0);
  84
  85         /* Uninstantiate State Handle 0 */
  86         append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  87                          (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
  88
  89         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  90 }
  91
  92 /*
  93  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
  94  *                        the software (no JR/QI used).
  95  * @ctrldev - pointer to device
  96  * @status - descriptor status, after being run
  97  *
  98  * Return: - 0 if no error occurred
  99  *         - -ENODEV if the DECO couldn't be acquired
 100  *         - -EAGAIN if an error occurred while executing the descriptor
 101  */
 102 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
 103                                         u32 *status)
 104 {
 105         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 106         struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
 107         struct caam_deco __iomem *deco = ctrlpriv->deco;
 108         unsigned int timeout = 100000;
 109         u32 deco_dbg_reg, flags;
 110         int i;
 111
 112
 113         if (ctrlpriv->virt_en == 1) {
 114                 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 115
 116                 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
 117                        --timeout)
 118                         cpu_relax();
 119
 120                 timeout = 100000;
 121         }
 122
 123         clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 124
 125         while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
 126                                                                  --timeout)
 127                 cpu_relax();
 128
 129         if (!timeout) {
 130                 dev_err(ctrldev, "failed to acquire DECO 0\n");
 131                 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 132                 return -ENODEV;
 133         }
 134
 135         for (i = 0; i < desc_len(desc); i++)
 136                 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 137
 138         flags = DECO_JQCR_WHL;
 139         /*
 140          * If the descriptor length is longer than 4 words, then the
 141          * FOUR bit in JRCTRL register must be set.
 142          */
 143         if (desc_len(desc) >= 4)
 144                 flags |= DECO_JQCR_FOUR;
 145
 146         /* Instruct the DECO to execute it */
 147         clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 148
 149         timeout = 10000000;
 150         do {
 151                 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
 152                 /*
 153                  * If an error occured in the descriptor, then
 154                  * the DECO status field will be set to 0x0D
 155                  */
 156                 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
 157                     DESC_DBG_DECO_STAT_HOST_ERR)
 158                         break;
 159                 cpu_relax();
 160         } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
 161
 162         *status = rd_reg32(&deco->op_status_hi) &
 163                   DECO_OP_STATUS_HI_ERR_MASK;
 164
 165         if (ctrlpriv->virt_en == 1)
 166                 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 167
 168         /* Mark the DECO as free */
 169         clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 170
 171         if (!timeout)
 172                 return -EAGAIN;
 173
 174         return 0;
 175 }
 176
 177 /*
 178  * instantiate_rng - builds and executes a descriptor on DECO0,
 179  *                   which initializes the RNG block.
 180  * @ctrldev - pointer to device
 181  * @state_handle_mask - bitmask containing the instantiation status
 182  *                      for the RNG4 state handles which exist in
 183  *                      the RNG4 block: 1 if it's been instantiated
 184  *                      by an external entry, 0 otherwise.
 185  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
 186  *            Caution: this can be done only once; if the keys need to be
 187  *            regenerated, a POR is required
 188  *
 189  * Return: - 0 if no error occurred
 190  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 191  *         - -ENODEV if DECO0 couldn't be acquired
 192  *         - -EAGAIN if an error occurred when executing the descriptor
 193  *            f.i. there was a RNG hardware error due to not "good enough"
 194  *            entropy being aquired.
 195  */
 196 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
 197                            int gen_sk)
 198 {
 199         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 200         struct caam_ctrl __iomem *ctrl;
 201         u32 *desc, status = 0, rdsta_val;
 202         int ret = 0, sh_idx;
 203
 204         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 205         desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
 206         if (!desc)
 207                 return -ENOMEM;
 208
 209         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 210                 /*
 211                  * If the corresponding bit is set, this state handle
 212                  * was initialized by somebody else, so it's left alone.
 213                  */
 214                 if ((1 << sh_idx) & state_handle_mask)
 215                         continue;
 216
 217                 /* Create the descriptor for instantiating RNG State Handle */
 218                 build_instantiation_desc(desc, sh_idx, gen_sk);
 219
 220                 /* Try to run it through DECO0 */
 221                 ret = run_descriptor_deco0(ctrldev, desc, &status);
 222
 223                 /*
 224                  * If ret is not 0, or descriptor status is not 0, then
 225                  * something went wrong. No need to try the next state
 226                  * handle (if available), bail out here.
 227                  * Also, if for some reason, the State Handle didn't get
 228                  * instantiated although the descriptor has finished
 229                  * without any error (HW optimizations for later
 230                  * CAAM eras), then try again.
 231                  */
 232                 if (ret)
 233                         break;
 234
 235                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 236                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 237                     !(rdsta_val & (1 << sh_idx))) {
 238                         ret = -EAGAIN;
 239                         break;
 240                 }
 241
 242                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 243                 /* Clear the contents before recreating the descriptor */
 244                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
 245         }
 246
 247         kfree(desc);
 248
 249         return ret;
 250 }
 251
 252 /*
 253  * deinstantiate_rng - builds and executes a descriptor on DECO0,
 254  *                     which deinitializes the RNG block.
 255  * @ctrldev - pointer to device
 256  * @state_handle_mask - bitmask containing the instantiation status
 257  *                      for the RNG4 state handles which exist in
 258  *                      the RNG4 block: 1 if it's been instantiated
 259  *
 260  * Return: - 0 if no error occurred
 261  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 262  *         - -ENODEV if DECO0 couldn't be acquired
 263  *         - -EAGAIN if an error occurred when executing the descriptor
 264  */
 265 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
 266 {
 267         u32 *desc, status;
 268         int sh_idx, ret = 0;
 269
 270         desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
 271         if (!desc)
 272                 return -ENOMEM;
 273
 274         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 275                 /*
 276                  * If the corresponding bit is set, then it means the state
 277                  * handle was initialized by us, and thus it needs to be
 278                  * deinitialized as well
 279                  */
 280                 if ((1 << sh_idx) & state_handle_mask) {
 281                         /*
 282                          * Create the descriptor for deinstantating this state
 283                          * handle
 284                          */
 285                         build_deinstantiation_desc(desc, sh_idx);
 286
 287                         /* Try to run it through DECO0 */
 288                         ret = run_descriptor_deco0(ctrldev, desc, &status);
 289
 290                         if (ret ||
 291                             (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
 292                                 dev_err(ctrldev,
 293                                         "Failed to deinstantiate RNG4 SH%d\n",
 294                                         sh_idx);
 295                                 break;
 296                         }
 297                         dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
 298                 }
 299         }
 300
 301         kfree(desc);
 302
 303         return ret;
 304 }
 305
 306 static int caam_remove(struct platform_device *pdev)
 307 {
 308         struct device *ctrldev;
 309         struct caam_drv_private *ctrlpriv;
 310         struct caam_ctrl __iomem *ctrl;
 311
 312         ctrldev = &pdev->dev;
 313         ctrlpriv = dev_get_drvdata(ctrldev);
 314         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 315
 316         /* Remove platform devices under the crypto node */
 317         of_platform_depopulate(ctrldev);
 318
 319 #ifdef CONFIG_CAAM_QI
 320         if (ctrlpriv->qidev)
 321                 caam_qi_shutdown(ctrlpriv->qidev);
 322 #endif
 323
 324         /*
 325          * De-initialize RNG state handles initialized by this driver.
 326          * In case of SoCs with Management Complex, RNG is managed by MC f/w.
 327          */
 328         if (!ctrlpriv->mc_en && ctrlpriv->rng4_sh_init)
 329                 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
 330
 331         /* Shut down debug views */
 332 #ifdef CONFIG_DEBUG_FS
 333         debugfs_remove_recursive(ctrlpriv->dfs_root);
 334 #endif
 335
 336         /* Unmap controller region */
 337         iounmap(ctrl);
 338
 339         /* shut clocks off before finalizing shutdown */
 340         clk_disable_unprepare(ctrlpriv->caam_ipg);
 341         if (ctrlpriv->caam_mem)
 342                 clk_disable_unprepare(ctrlpriv->caam_mem);
 343         clk_disable_unprepare(ctrlpriv->caam_aclk);
 344         if (ctrlpriv->caam_emi_slow)
 345                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 346         return 0;
 347 }
 348
 349 /*
 350  * kick_trng - sets the various parameters for enabling the initialization
 351  *             of the RNG4 block in CAAM
 352  * @pdev - pointer to the platform device
 353  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
 354  */
 355 static void kick_trng(struct platform_device *pdev, int ent_delay)
 356 {
 357         struct device *ctrldev = &pdev->dev;
 358         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 359         struct caam_ctrl __iomem *ctrl;
 360         struct rng4tst __iomem *r4tst;
 361         u32 val;
 362
 363         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 364         r4tst = &ctrl->r4tst[0];
 365
 366         /* put RNG4 into program mode */
 367         clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 368
 369         /*
 370          * Performance-wise, it does not make sense to
 371          * set the delay to a value that is lower
 372          * than the last one that worked (i.e. the state handles
 373          * were instantiated properly. Thus, instead of wasting
 374          * time trying to set the values controlling the sample
 375          * frequency, the function simply returns.
 376          */
 377         val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 378               >> RTSDCTL_ENT_DLY_SHIFT;
 379         if (ent_delay <= val)
 380                 goto start_rng;
 381
 382         val = rd_reg32(&r4tst->rtsdctl);
 383         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 384               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 385         wr_reg32(&r4tst->rtsdctl, val);
 386         /* min. freq. count, equal to 1/4 of the entropy sample length */
 387         wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 388         /* disable maximum frequency count */
 389         wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 390         /* read the control register */
 391         val = rd_reg32(&r4tst->rtmctl);
 392 start_rng:
 393         /*
 394          * select raw sampling in both entropy shifter
 395          * and statistical checker; ; put RNG4 into run mode
 396          */
 397         clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 398 }
 399
 400 static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
 401 {
 402         static const struct {
 403                 u16 ip_id;
 404                 u8 maj_rev;
 405                 u8 era;
 406         } id[] = {
 407                 {0x0A10, 1, 1},
 408                 {0x0A10, 2, 2},
 409                 {0x0A12, 1, 3},
 410                 {0x0A14, 1, 3},
 411                 {0x0A14, 2, 4},
 412                 {0x0A16, 1, 4},
 413                 {0x0A10, 3, 4},
 414                 {0x0A11, 1, 4},
 415                 {0x0A18, 1, 4},
 416                 {0x0A11, 2, 5},
 417                 {0x0A12, 2, 5},
 418                 {0x0A13, 1, 5},
 419                 {0x0A1C, 1, 5}
 420         };
 421         u32 ccbvid, id_ms;
 422         u8 maj_rev, era;
 423         u16 ip_id;
 424         int i;
 425
 426         ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
 427         era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
 428         if (era)        /* This is '0' prior to CAAM ERA-6 */
 429                 return era;
 430
 431         id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
 432         ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
 433         maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
 434
 435         for (i = 0; i < ARRAY_SIZE(id); i++)
 436                 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
 437                         return id[i].era;
 438
 439         return -ENOTSUPP;
 440 }
 441
 442 /**
 443  * caam_get_era() - Return the ERA of the SEC on SoC, based
 444  * on "sec-era" optional property in the DTS. This property is updated
 445  * by u-boot.
 446  * In case this property is not passed an attempt to retrieve the CAAM
 447  * era via register reads will be made.
 448  **/
 449 static int caam_get_era(struct caam_ctrl __iomem *ctrl)
 450 {
 451         struct device_node *caam_node;
 452         int ret;
 453         u32 prop;
 454
 455         caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 456         ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 457         of_node_put(caam_node);
 458
 459         if (!ret)
 460                 return prop;
 461         else
 462                 return caam_get_era_from_hw(ctrl);
 463 }
 464
 465 static const struct of_device_id caam_match[] = {
 466         {
 467                 .compatible = "fsl,sec-v4.0",
 468         },
 469         {
 470                 .compatible = "fsl,sec4.0",
 471         },
 472         {},
 473 };
 474 MODULE_DEVICE_TABLE(of, caam_match);
 475
 476 /* Probe routine for CAAM top (controller) level */
 477 static int caam_probe(struct platform_device *pdev)
 478 {
 479         int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 480         u64 caam_id;
 481         static const struct soc_device_attribute imx_soc[] = {
 482                 {.family = "Freescale i.MX"},
 483                 {},
 484         };
 485         struct device *dev;
 486         struct device_node *nprop, *np;
 487         struct caam_ctrl __iomem *ctrl;
 488         struct caam_drv_private *ctrlpriv;
 489         struct clk *clk;
 490 #ifdef CONFIG_DEBUG_FS
 491         struct caam_perfmon *perfmon;
 492 #endif
 493         u32 scfgr, comp_params;
 494         u32 cha_vid_ls;
 495         int pg_size;
 496         int BLOCK_OFFSET = 0;
 497
 498         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
 499         if (!ctrlpriv)
 500                 return -ENOMEM;
 501
 502         dev = &pdev->dev;
 503         dev_set_drvdata(dev, ctrlpriv);
 504         nprop = pdev->dev.of_node;
 505
 506         caam_imx = (bool)soc_device_match(imx_soc);
 507
 508         /* Enable clocking */
 509         clk = caam_drv_identify_clk(&pdev->dev, "ipg");
 510         if (IS_ERR(clk)) {
 511                 ret = PTR_ERR(clk);
 512                 dev_err(&pdev->dev,
 513                         "can't identify CAAM ipg clk: %d\n", ret);
 514                 return ret;
 515         }
 516         ctrlpriv->caam_ipg = clk;
 517
 518         if (!of_machine_is_compatible("fsl,imx7d") &&
 519             !of_machine_is_compatible("fsl,imx7s")) {
 520                 clk = caam_drv_identify_clk(&pdev->dev, "mem");
 521                 if (IS_ERR(clk)) {
 522                         ret = PTR_ERR(clk);
 523                         dev_err(&pdev->dev,
 524                                 "can't identify CAAM mem clk: %d\n", ret);
 525                         return ret;
 526                 }
 527                 ctrlpriv->caam_mem = clk;
 528         }
 529
 530         clk = caam_drv_identify_clk(&pdev->dev, "aclk");
 531         if (IS_ERR(clk)) {
 532                 ret = PTR_ERR(clk);
 533                 dev_err(&pdev->dev,
 534                         "can't identify CAAM aclk clk: %d\n", ret);
 535                 return ret;
 536         }
 537         ctrlpriv->caam_aclk = clk;
 538
 539         if (!of_machine_is_compatible("fsl,imx6ul") &&
 540             !of_machine_is_compatible("fsl,imx7d") &&
 541             !of_machine_is_compatible("fsl,imx7s")) {
 542                 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
 543                 if (IS_ERR(clk)) {
 544                         ret = PTR_ERR(clk);
 545                         dev_err(&pdev->dev,
 546                                 "can't identify CAAM emi_slow clk: %d\n", ret);
 547                         return ret;
 548                 }
 549                 ctrlpriv->caam_emi_slow = clk;
 550         }
 551
 552         ret = clk_prepare_enable(ctrlpriv->caam_ipg);
 553         if (ret < 0) {
 554                 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
 555                 return ret;
 556         }
 557
 558         if (ctrlpriv->caam_mem) {
 559                 ret = clk_prepare_enable(ctrlpriv->caam_mem);
 560                 if (ret < 0) {
 561                         dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
 562                                 ret);
 563                         goto disable_caam_ipg;
 564                 }
 565         }
 566
 567         ret = clk_prepare_enable(ctrlpriv->caam_aclk);
 568         if (ret < 0) {
 569                 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
 570                 goto disable_caam_mem;
 571         }
 572
 573         if (ctrlpriv->caam_emi_slow) {
 574                 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
 575                 if (ret < 0) {
 576                         dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
 577                                 ret);
 578                         goto disable_caam_aclk;
 579                 }
 580         }
 581
 582         /* Get configuration properties from device tree */
 583         /* First, get register page */
 584         ctrl = of_iomap(nprop, 0);
 585         if (ctrl == NULL) {
 586                 dev_err(dev, "caam: of_iomap() failed\n");
 587                 ret = -ENOMEM;
 588                 goto disable_caam_emi_slow;
 589         }
 590
 591         caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
 592                                   (CSTA_PLEND | CSTA_ALT_PLEND));
 593
 594         /* Finding the page size for using the CTPR_MS register */
 595         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 596         pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 597
 598         /* Allocating the BLOCK_OFFSET based on the supported page size on
 599          * the platform
 600          */
 601         if (pg_size == 0)
 602                 BLOCK_OFFSET = PG_SIZE_4K;
 603         else
 604                 BLOCK_OFFSET = PG_SIZE_64K;
 605
 606         ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
 607         ctrlpriv->assure = (struct caam_assurance __iomem __force *)
 608                            ((__force uint8_t *)ctrl +
 609                             BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
 610                            );
 611         ctrlpriv->deco = (struct caam_deco __iomem __force *)
 612                          ((__force uint8_t *)ctrl +
 613                          BLOCK_OFFSET * DECO_BLOCK_NUMBER
 614                          );
 615
 616         /* Get the IRQ of the controller (for security violations only) */
 617         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
 618
 619         /*
 620          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 621          * long pointers in master configuration register.
 622          * In case of SoCs with Management Complex, MC f/w performs
 623          * the configuration.
 624          */
 625         caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
 626         np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
 627         ctrlpriv->mc_en = !!np;
 628         of_node_put(np);
 629
 630         if (!ctrlpriv->mc_en)
 631                 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
 632                               MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
 633                               MCFGR_WDENABLE | MCFGR_LARGE_BURST |
 634                               (sizeof(dma_addr_t) == sizeof(u64) ?
 635                                MCFGR_LONG_PTR : 0));
 636
 637         /*
 638          *  Read the Compile Time paramters and SCFGR to determine
 639          * if Virtualization is enabled for this platform
 640          */
 641         scfgr = rd_reg32(&ctrl->scfgr);
 642
 643         ctrlpriv->virt_en = 0;
 644         if (comp_params & CTPR_MS_VIRT_EN_INCL) {
 645                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
 646                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
 647                  */
 648                 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
 649                     (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
 650                        (scfgr & SCFGR_VIRT_EN)))
 651                                 ctrlpriv->virt_en = 1;
 652         } else {
 653                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 654                 if (comp_params & CTPR_MS_VIRT_EN_POR)
 655                                 ctrlpriv->virt_en = 1;
 656         }
 657
 658         if (ctrlpriv->virt_en == 1)
 659                 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
 660                               JRSTART_JR1_START | JRSTART_JR2_START |
 661                               JRSTART_JR3_START);
 662
 663         if (sizeof(dma_addr_t) == sizeof(u64)) {
 664                 if (caam_dpaa2)
 665                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
 666                 else if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
 667                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 668                 else
 669                         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
 670         } else {
 671                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 672         }
 673         if (ret) {
 674                 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
 675                 goto iounmap_ctrl;
 676         }
 677
 678         ctrlpriv->era = caam_get_era(ctrl);
 679
 680         ret = of_platform_populate(nprop, caam_match, NULL, dev);
 681         if (ret) {
 682                 dev_err(dev, "JR platform devices creation error\n");
 683                 goto iounmap_ctrl;
 684         }
 685
 686 #ifdef CONFIG_DEBUG_FS
 687         /*
 688          * FIXME: needs better naming distinction, as some amalgamation of
 689          * "caam" and nprop->full_name. The OF name isn't distinctive,
 690          * but does separate instances
 691          */
 692         perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
 693
 694         ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
 695         ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
 696 #endif
 697
 698         ring = 0;
 699         for_each_available_child_of_node(nprop, np)
 700                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 701                     of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 702                         ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
 703                                              ((__force uint8_t *)ctrl +
 704                                              (ring + JR_BLOCK_NUMBER) *
 705                                               BLOCK_OFFSET
 706                                              );
 707                         ctrlpriv->total_jobrs++;
 708                         ring++;
 709                 }
 710
 711         /* Check to see if (DPAA 1.x) QI present. If so, enable */
 712         ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
 713         if (ctrlpriv->qi_present && !caam_dpaa2) {
 714                 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
 715                                ((__force uint8_t *)ctrl +
 716                                  BLOCK_OFFSET * QI_BLOCK_NUMBER
 717                                );
 718                 /* This is all that's required to physically enable QI */
 719                 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 720
 721                 /* If QMAN driver is present, init CAAM-QI backend */
 722 #ifdef CONFIG_CAAM_QI
 723                 ret = caam_qi_init(pdev);
 724                 if (ret)
 725                         dev_err(dev, "caam qi i/f init failed: %d\n", ret);
 726 #endif
 727         }
 728
 729         /* If no QI and no rings specified, quit and go home */
 730         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
 731                 dev_err(dev, "no queues configured, terminating\n");
 732                 ret = -ENOMEM;
 733                 goto caam_remove;
 734         }
 735
 736         cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
 737
 738         /*
 739          * If SEC has RNG version >= 4 and RNG state handle has not been
 740          * already instantiated, do RNG instantiation
 741          * In case of SoCs with Management Complex, RNG is managed by MC f/w.
 742          */
 743         if (!ctrlpriv->mc_en &&
 744             (cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
 745                 ctrlpriv->rng4_sh_init =
 746                         rd_reg32(&ctrl->r4tst[0].rdsta);
 747                 /*
 748                  * If the secure keys (TDKEK, JDKEK, TDSK), were already
 749                  * generated, signal this to the function that is instantiating
 750                  * the state handles. An error would occur if RNG4 attempts
 751                  * to regenerate these keys before the next POR.
 752                  */
 753                 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
 754                 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 755                 do {
 756                         int inst_handles =
 757                                 rd_reg32(&ctrl->r4tst[0].rdsta) &
 758                                                                 RDSTA_IFMASK;
 759                         /*
 760                          * If either SH were instantiated by somebody else
 761                          * (e.g. u-boot) then it is assumed that the entropy
 762                          * parameters are properly set and thus the function
 763                          * setting these (kick_trng(...)) is skipped.
 764                          * Also, if a handle was instantiated, do not change
 765                          * the TRNG parameters.
 766                          */
 767                         if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
 768                                 dev_info(dev,
 769                                          "Entropy delay = %u\n",
 770                                          ent_delay);
 771                                 kick_trng(pdev, ent_delay);
 772                                 ent_delay += 400;
 773                         }
 774                         /*
 775                          * if instantiate_rng(...) fails, the loop will rerun
 776                          * and the kick_trng(...) function will modfiy the
 777                          * upper and lower limits of the entropy sampling
 778                          * interval, leading to a sucessful initialization of
 779                          * the RNG.
 780                          */
 781                         ret = instantiate_rng(dev, inst_handles,
 782                                               gen_sk);
 783                         if (ret == -EAGAIN)
 784                                 /*
 785                                  * if here, the loop will rerun,
 786                                  * so don't hog the CPU
 787                                  */
 788                                 cpu_relax();
 789                 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 790                 if (ret) {
 791                         dev_err(dev, "failed to instantiate RNG");
 792                         goto caam_remove;
 793                 }
 794                 /*
 795                  * Set handles init'ed by this module as the complement of the
 796                  * already initialized ones
 797                  */
 798                 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 799
 800                 /* Enable RDB bit so that RNG works faster */
 801                 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 802         }
 803
 804         /* NOTE: RTIC detection ought to go here, around Si time */
 805
 806         caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
 807                   (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 808
 809         /* Report "alive" for developer to see */
 810         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
 811                  ctrlpriv->era);
 812         dev_info(dev, "job rings = %d, qi = %d\n",
 813                  ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 814
 815 #ifdef CONFIG_DEBUG_FS
 816         debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,
 817                             ctrlpriv->ctl, &perfmon->req_dequeued,
 818                             &caam_fops_u64_ro);
 819         debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
 820                             ctrlpriv->ctl, &perfmon->ob_enc_req,
 821                             &caam_fops_u64_ro);
 822         debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
 823                             ctrlpriv->ctl, &perfmon->ib_dec_req,
 824                             &caam_fops_u64_ro);
 825         debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
 826                             ctrlpriv->ctl, &perfmon->ob_enc_bytes,
 827                             &caam_fops_u64_ro);
 828         debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH,
 829                             ctrlpriv->ctl, &perfmon->ob_prot_bytes,
 830                             &caam_fops_u64_ro);
 831         debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
 832                             ctrlpriv->ctl, &perfmon->ib_dec_bytes,
 833                             &caam_fops_u64_ro);
 834         debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH,
 835                             ctrlpriv->ctl, &perfmon->ib_valid_bytes,
 836                             &caam_fops_u64_ro);
 837
 838         /* Controller level - global status values */
 839         debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH,
 840                             ctrlpriv->ctl, &perfmon->faultaddr,
 841                             &caam_fops_u32_ro);
 842         debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH,
 843                             ctrlpriv->ctl, &perfmon->faultdetail,
 844                             &caam_fops_u32_ro);
 845         debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH,
 846                             ctrlpriv->ctl, &perfmon->status,
 847                             &caam_fops_u32_ro);
 848
 849         /* Internal covering keys (useful in non-secure mode only) */
 850         ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
 851         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 852         ctrlpriv->ctl_kek = debugfs_create_blob("kek",
 853                                                 S_IRUSR |
 854                                                 S_IRGRP | S_IROTH,
 855                                                 ctrlpriv->ctl,
 856                                                 &ctrlpriv->ctl_kek_wrap);
 857
 858         ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
 859         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 860         ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
 861                                                  S_IRUSR |
 862                                                  S_IRGRP | S_IROTH,
 863                                                  ctrlpriv->ctl,
 864                                                  &ctrlpriv->ctl_tkek_wrap);
 865
 866         ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
 867         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 868         ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
 869                                                  S_IRUSR |
 870                                                  S_IRGRP | S_IROTH,
 871                                                  ctrlpriv->ctl,
 872                                                  &ctrlpriv->ctl_tdsk_wrap);
 873 #endif
 874         return 0;
 875
 876 caam_remove:
 877         caam_remove(pdev);
 878         return ret;
 879
 880 iounmap_ctrl:
 881         iounmap(ctrl);
 882 disable_caam_emi_slow:
 883         if (ctrlpriv->caam_emi_slow)
 884                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 885 disable_caam_aclk:
 886         clk_disable_unprepare(ctrlpriv->caam_aclk);
 887 disable_caam_mem:
 888         if (ctrlpriv->caam_mem)
 889                 clk_disable_unprepare(ctrlpriv->caam_mem);
 890 disable_caam_ipg:
 891         clk_disable_unprepare(ctrlpriv->caam_ipg);
 892         return ret;
 893 }
 894
 895 static struct platform_driver caam_driver = {
 896         .driver = {
 897                 .name = "caam",
 898                 .of_match_table = caam_match,
 899         },
 900         .probe       = caam_probe,
 901         .remove      = caam_remove,
 902 };
 903
 904 module_platform_driver(caam_driver);
 905
 906 MODULE_LICENSE("GPL");
 907 MODULE_DESCRIPTION("FSL CAAM request backend");
 908 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");