drivers/scsi/ufs/ufs-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/acpi.h>
   7 #include <linux/time.h>
   8 #include <linux/of.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/phy/phy.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/reset-controller.h>
  13 #include <linux/devfreq.h>
  14
  15 #include "ufshcd.h"
  16 #include "ufshcd-pltfrm.h"
  17 #include "unipro.h"
  18 #include "ufs-qcom.h"
  19 #include "ufshci.h"
  20 #include "ufs_quirks.h"
  21 #define UFS_QCOM_DEFAULT_DBG_PRINT_EN   \
  22         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
  23
  24 enum {
  25         TSTBUS_UAWM,
  26         TSTBUS_UARM,
  27         TSTBUS_TXUC,
  28         TSTBUS_RXUC,
  29         TSTBUS_DFC,
  30         TSTBUS_TRLUT,
  31         TSTBUS_TMRLUT,
  32         TSTBUS_OCSC,
  33         TSTBUS_UTP_HCI,
  34         TSTBUS_COMBINED,
  35         TSTBUS_WRAPPER,
  36         TSTBUS_UNIPRO,
  37         TSTBUS_MAX,
  38 };
  39
  40 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
  41
  42 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
  43 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
  44                                                        u32 clk_cycles);
  45
  46 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
  47 {
  48         return container_of(rcd, struct ufs_qcom_host, rcdev);
  49 }
  50
  51 static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
  52                                        const char *prefix, void *priv)
  53 {
  54         ufshcd_dump_regs(hba, offset, len * 4, prefix);
  55 }
  56
  57 static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
  58 {
  59         int err = 0;
  60
  61         err = ufshcd_dme_get(hba,
  62                         UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), tx_lanes);
  63         if (err)
  64                 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n",
  65                                 __func__, err);
  66
  67         return err;
  68 }
  69
  70 static int ufs_qcom_host_clk_get(struct device *dev,
  71                 const char *name, struct clk **clk_out, bool optional)
  72 {
  73         struct clk *clk;
  74         int err = 0;
  75
  76         clk = devm_clk_get(dev, name);
  77         if (!IS_ERR(clk)) {
  78                 *clk_out = clk;
  79                 return 0;
  80         }
  81
  82         err = PTR_ERR(clk);
  83
  84         if (optional && err == -ENOENT) {
  85                 *clk_out = NULL;
  86                 return 0;
  87         }
  88
  89         if (err != -EPROBE_DEFER)
  90                 dev_err(dev, "failed to get %s err %d\n", name, err);
  91
  92         return err;
  93 }
  94
  95 static int ufs_qcom_host_clk_enable(struct device *dev,
  96                 const char *name, struct clk *clk)
  97 {
  98         int err = 0;
  99
 100         err = clk_prepare_enable(clk);
 101         if (err)
 102                 dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err);
 103
 104         return err;
 105 }
 106
 107 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
 108 {
 109         if (!host->is_lane_clks_enabled)
 110                 return;
 111
 112         clk_disable_unprepare(host->tx_l1_sync_clk);
 113         clk_disable_unprepare(host->tx_l0_sync_clk);
 114         clk_disable_unprepare(host->rx_l1_sync_clk);
 115         clk_disable_unprepare(host->rx_l0_sync_clk);
 116
 117         host->is_lane_clks_enabled = false;
 118 }
 119
 120 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
 121 {
 122         int err = 0;
 123         struct device *dev = host->hba->dev;
 124
 125         if (host->is_lane_clks_enabled)
 126                 return 0;
 127
 128         err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
 129                 host->rx_l0_sync_clk);
 130         if (err)
 131                 goto out;
 132
 133         err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
 134                 host->tx_l0_sync_clk);
 135         if (err)
 136                 goto disable_rx_l0;
 137
 138         err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
 139                         host->rx_l1_sync_clk);
 140         if (err)
 141                 goto disable_tx_l0;
 142
 143         err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
 144                         host->tx_l1_sync_clk);
 145         if (err)
 146                 goto disable_rx_l1;
 147
 148         host->is_lane_clks_enabled = true;
 149         goto out;
 150
 151 disable_rx_l1:
 152         clk_disable_unprepare(host->rx_l1_sync_clk);
 153 disable_tx_l0:
 154         clk_disable_unprepare(host->tx_l0_sync_clk);
 155 disable_rx_l0:
 156         clk_disable_unprepare(host->rx_l0_sync_clk);
 157 out:
 158         return err;
 159 }
 160
 161 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
 162 {
 163         int err = 0;
 164         struct device *dev = host->hba->dev;
 165
 166         if (has_acpi_companion(dev))
 167                 return 0;
 168
 169         err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
 170                                         &host->rx_l0_sync_clk, false);
 171         if (err)
 172                 goto out;
 173
 174         err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
 175                                         &host->tx_l0_sync_clk, false);
 176         if (err)
 177                 goto out;
 178
 179         /* In case of single lane per direction, don't read lane1 clocks */
 180         if (host->hba->lanes_per_direction > 1) {
 181                 err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
 182                         &host->rx_l1_sync_clk, false);
 183                 if (err)
 184                         goto out;
 185
 186                 err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
 187                         &host->tx_l1_sync_clk, true);
 188         }
 189 out:
 190         return err;
 191 }
 192
 193 static int ufs_qcom_link_startup_post_change(struct ufs_hba *hba)
 194 {
 195         u32 tx_lanes;
 196
 197         return ufs_qcom_get_connected_tx_lanes(hba, &tx_lanes);
 198 }
 199
 200 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
 201 {
 202         int err;
 203         u32 tx_fsm_val = 0;
 204         unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
 205
 206         do {
 207                 err = ufshcd_dme_get(hba,
 208                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 209                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 210                                 &tx_fsm_val);
 211                 if (err || tx_fsm_val == TX_FSM_HIBERN8)
 212                         break;
 213
 214                 /* sleep for max. 200us */
 215                 usleep_range(100, 200);
 216         } while (time_before(jiffies, timeout));
 217
 218         /*
 219          * we might have scheduled out for long during polling so
 220          * check the state again.
 221          */
 222         if (time_after(jiffies, timeout))
 223                 err = ufshcd_dme_get(hba,
 224                                 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
 225                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
 226                                 &tx_fsm_val);
 227
 228         if (err) {
 229                 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
 230                                 __func__, err);
 231         } else if (tx_fsm_val != TX_FSM_HIBERN8) {
 232                 err = tx_fsm_val;
 233                 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
 234                                 __func__, err);
 235         }
 236
 237         return err;
 238 }
 239
 240 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
 241 {
 242         ufshcd_rmwl(host->hba, QUNIPRO_SEL,
 243                    ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0,
 244                    REG_UFS_CFG1);
 245         /* make sure above configuration is applied before we return */
 246         mb();
 247 }
 248
 249 /*
 250  * ufs_qcom_host_reset - reset host controller and PHY
 251  */
 252 static int ufs_qcom_host_reset(struct ufs_hba *hba)
 253 {
 254         int ret = 0;
 255         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 256         bool reenable_intr = false;
 257
 258         if (!host->core_reset) {
 259                 dev_warn(hba->dev, "%s: reset control not set\n", __func__);
 260                 goto out;
 261         }
 262
 263         reenable_intr = hba->is_irq_enabled;
 264         disable_irq(hba->irq);
 265         hba->is_irq_enabled = false;
 266
 267         ret = reset_control_assert(host->core_reset);
 268         if (ret) {
 269                 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
 270                                  __func__, ret);
 271                 goto out;
 272         }
 273
 274         /*
 275          * The hardware requirement for delay between assert/deassert
 276          * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
 277          * ~125us (4/32768). To be on the safe side add 200us delay.
 278          */
 279         usleep_range(200, 210);
 280
 281         ret = reset_control_deassert(host->core_reset);
 282         if (ret)
 283                 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
 284                                  __func__, ret);
 285
 286         usleep_range(1000, 1100);
 287
 288         if (reenable_intr) {
 289                 enable_irq(hba->irq);
 290                 hba->is_irq_enabled = true;
 291         }
 292
 293 out:
 294         return ret;
 295 }
 296
 297 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
 298 {
 299         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 300         struct phy *phy = host->generic_phy;
 301         int ret = 0;
 302         bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)
 303                                                         ? true : false;
 304
 305         /* Reset UFS Host Controller and PHY */
 306         ret = ufs_qcom_host_reset(hba);
 307         if (ret)
 308                 dev_warn(hba->dev, "%s: host reset returned %d\n",
 309                                   __func__, ret);
 310
 311         if (is_rate_B)
 312                 phy_set_mode(phy, PHY_MODE_UFS_HS_B);
 313
 314         /* phy initialization - calibrate the phy */
 315         ret = phy_init(phy);
 316         if (ret) {
 317                 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
 318                         __func__, ret);
 319                 goto out;
 320         }
 321
 322         /* power on phy - start serdes and phy's power and clocks */
 323         ret = phy_power_on(phy);
 324         if (ret) {
 325                 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
 326                         __func__, ret);
 327                 goto out_disable_phy;
 328         }
 329
 330         ufs_qcom_select_unipro_mode(host);
 331
 332         return 0;
 333
 334 out_disable_phy:
 335         phy_exit(phy);
 336 out:
 337         return ret;
 338 }
 339
 340 /*
 341  * The UTP controller has a number of internal clock gating cells (CGCs).
 342  * Internal hardware sub-modules within the UTP controller control the CGCs.
 343  * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
 344  * in a specific operation, UTP controller CGCs are by default disabled and
 345  * this function enables them (after every UFS link startup) to save some power
 346  * leakage.
 347  */
 348 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 349 {
 350         ufshcd_writel(hba,
 351                 ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
 352                 REG_UFS_CFG2);
 353
 354         /* Ensure that HW clock gating is enabled before next operations */
 355         mb();
 356 }
 357
 358 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
 359                                       enum ufs_notify_change_status status)
 360 {
 361         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 362         int err = 0;
 363
 364         switch (status) {
 365         case PRE_CHANGE:
 366                 ufs_qcom_power_up_sequence(hba);
 367                 /*
 368                  * The PHY PLL output is the source of tx/rx lane symbol
 369                  * clocks, hence, enable the lane clocks only after PHY
 370                  * is initialized.
 371                  */
 372                 err = ufs_qcom_enable_lane_clks(host);
 373                 break;
 374         case POST_CHANGE:
 375                 /* check if UFS PHY moved from DISABLED to HIBERN8 */
 376                 err = ufs_qcom_check_hibern8(hba);
 377                 ufs_qcom_enable_hw_clk_gating(hba);
 378                 ufs_qcom_ice_enable(host);
 379                 break;
 380         default:
 381                 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
 382                 err = -EINVAL;
 383                 break;
 384         }
 385         return err;
 386 }
 387
 388 /*
 389  * Returns zero for success and non-zero in case of a failure
 390  */
 391 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
 392                                u32 hs, u32 rate, bool update_link_startup_timer)
 393 {
 394         int ret = 0;
 395         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 396         struct ufs_clk_info *clki;
 397         u32 core_clk_period_in_ns;
 398         u32 tx_clk_cycles_per_us = 0;
 399         unsigned long core_clk_rate = 0;
 400         u32 core_clk_cycles_per_us = 0;
 401
 402         static u32 pwm_fr_table[][2] = {
 403                 {UFS_PWM_G1, 0x1},
 404                 {UFS_PWM_G2, 0x1},
 405                 {UFS_PWM_G3, 0x1},
 406                 {UFS_PWM_G4, 0x1},
 407         };
 408
 409         static u32 hs_fr_table_rA[][2] = {
 410                 {UFS_HS_G1, 0x1F},
 411                 {UFS_HS_G2, 0x3e},
 412                 {UFS_HS_G3, 0x7D},
 413         };
 414
 415         static u32 hs_fr_table_rB[][2] = {
 416                 {UFS_HS_G1, 0x24},
 417                 {UFS_HS_G2, 0x49},
 418                 {UFS_HS_G3, 0x92},
 419         };
 420
 421         /*
 422          * The Qunipro controller does not use following registers:
 423          * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
 424          * UFS_REG_PA_LINK_STARTUP_TIMER
 425          * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
 426          * Aggregation logic.
 427         */
 428         if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
 429                 goto out;
 430
 431         if (gear == 0) {
 432                 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
 433                 goto out_error;
 434         }
 435
 436         list_for_each_entry(clki, &hba->clk_list_head, list) {
 437                 if (!strcmp(clki->name, "core_clk"))
 438                         core_clk_rate = clk_get_rate(clki->clk);
 439         }
 440
 441         /* If frequency is smaller than 1MHz, set to 1MHz */
 442         if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
 443                 core_clk_rate = DEFAULT_CLK_RATE_HZ;
 444
 445         core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
 446         if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
 447                 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
 448                 /*
 449                  * make sure above write gets applied before we return from
 450                  * this function.
 451                  */
 452                 mb();
 453         }
 454
 455         if (ufs_qcom_cap_qunipro(host))
 456                 goto out;
 457
 458         core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
 459         core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
 460         core_clk_period_in_ns &= MASK_CLK_NS_REG;
 461
 462         switch (hs) {
 463         case FASTAUTO_MODE:
 464         case FAST_MODE:
 465                 if (rate == PA_HS_MODE_A) {
 466                         if (gear > ARRAY_SIZE(hs_fr_table_rA)) {
 467                                 dev_err(hba->dev,
 468                                         "%s: index %d exceeds table size %zu\n",
 469                                         __func__, gear,
 470                                         ARRAY_SIZE(hs_fr_table_rA));
 471                                 goto out_error;
 472                         }
 473                         tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
 474                 } else if (rate == PA_HS_MODE_B) {
 475                         if (gear > ARRAY_SIZE(hs_fr_table_rB)) {
 476                                 dev_err(hba->dev,
 477                                         "%s: index %d exceeds table size %zu\n",
 478                                         __func__, gear,
 479                                         ARRAY_SIZE(hs_fr_table_rB));
 480                                 goto out_error;
 481                         }
 482                         tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
 483                 } else {
 484                         dev_err(hba->dev, "%s: invalid rate = %d\n",
 485                                 __func__, rate);
 486                         goto out_error;
 487                 }
 488                 break;
 489         case SLOWAUTO_MODE:
 490         case SLOW_MODE:
 491                 if (gear > ARRAY_SIZE(pwm_fr_table)) {
 492                         dev_err(hba->dev,
 493                                         "%s: index %d exceeds table size %zu\n",
 494                                         __func__, gear,
 495                                         ARRAY_SIZE(pwm_fr_table));
 496                         goto out_error;
 497                 }
 498                 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
 499                 break;
 500         case UNCHANGED:
 501         default:
 502                 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
 503                 goto out_error;
 504         }
 505
 506         if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
 507             (core_clk_period_in_ns | tx_clk_cycles_per_us)) {
 508                 /* this register 2 fields shall be written at once */
 509                 ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us,
 510                               REG_UFS_TX_SYMBOL_CLK_NS_US);
 511                 /*
 512                  * make sure above write gets applied before we return from
 513                  * this function.
 514                  */
 515                 mb();
 516         }
 517
 518         if (update_link_startup_timer) {
 519                 ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100),
 520                               REG_UFS_PA_LINK_STARTUP_TIMER);
 521                 /*
 522                  * make sure that this configuration is applied before
 523                  * we return
 524                  */
 525                 mb();
 526         }
 527         goto out;
 528
 529 out_error:
 530         ret = -EINVAL;
 531 out:
 532         return ret;
 533 }
 534
 535 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
 536                                         enum ufs_notify_change_status status)
 537 {
 538         int err = 0;
 539         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 540
 541         switch (status) {
 542         case PRE_CHANGE:
 543                 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
 544                                         0, true)) {
 545                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 546                                 __func__);
 547                         err = -EINVAL;
 548                         goto out;
 549                 }
 550
 551                 if (ufs_qcom_cap_qunipro(host))
 552                         /*
 553                          * set unipro core clock cycles to 150 & clear clock
 554                          * divider
 555                          */
 556                         err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
 557                                                                           150);
 558
 559                 /*
 560                  * Some UFS devices (and may be host) have issues if LCC is
 561                  * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
 562                  * before link startup which will make sure that both host
 563                  * and device TX LCC are disabled once link startup is
 564                  * completed.
 565                  */
 566                 if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41)
 567                         err = ufshcd_disable_host_tx_lcc(hba);
 568
 569                 break;
 570         case POST_CHANGE:
 571                 ufs_qcom_link_startup_post_change(hba);
 572                 break;
 573         default:
 574                 break;
 575         }
 576
 577 out:
 578         return err;
 579 }
 580
 581 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
 582 {
 583         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 584
 585         /* reset gpio is optional */
 586         if (!host->device_reset)
 587                 return;
 588
 589         gpiod_set_value_cansleep(host->device_reset, asserted);
 590 }
 591
 592 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
 593         enum ufs_notify_change_status status)
 594 {
 595         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 596         struct phy *phy = host->generic_phy;
 597
 598         if (status == PRE_CHANGE)
 599                 return 0;
 600
 601         if (ufs_qcom_is_link_off(hba)) {
 602                 /*
 603                  * Disable the tx/rx lane symbol clocks before PHY is
 604                  * powered down as the PLL source should be disabled
 605                  * after downstream clocks are disabled.
 606                  */
 607                 ufs_qcom_disable_lane_clks(host);
 608                 phy_power_off(phy);
 609
 610                 /* reset the connected UFS device during power down */
 611                 ufs_qcom_device_reset_ctrl(hba, true);
 612
 613         } else if (!ufs_qcom_is_link_active(hba)) {
 614                 ufs_qcom_disable_lane_clks(host);
 615         }
 616
 617         return 0;
 618 }
 619
 620 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 621 {
 622         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 623         struct phy *phy = host->generic_phy;
 624         int err;
 625
 626         if (ufs_qcom_is_link_off(hba)) {
 627                 err = phy_power_on(phy);
 628                 if (err) {
 629                         dev_err(hba->dev, "%s: failed PHY power on: %d\n",
 630                                 __func__, err);
 631                         return err;
 632                 }
 633
 634                 err = ufs_qcom_enable_lane_clks(host);
 635                 if (err)
 636                         return err;
 637
 638         } else if (!ufs_qcom_is_link_active(hba)) {
 639                 err = ufs_qcom_enable_lane_clks(host);
 640                 if (err)
 641                         return err;
 642         }
 643
 644         err = ufs_qcom_ice_resume(host);
 645         if (err)
 646                 return err;
 647
 648         hba->is_sys_suspended = false;
 649         return 0;
 650 }
 651
 652 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 653 {
 654         if (host->dev_ref_clk_ctrl_mmio &&
 655             (enable ^ host->is_dev_ref_clk_enabled)) {
 656                 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
 657
 658                 if (enable)
 659                         temp |= host->dev_ref_clk_en_mask;
 660                 else
 661                         temp &= ~host->dev_ref_clk_en_mask;
 662
 663                 /*
 664                  * If we are here to disable this clock it might be immediately
 665                  * after entering into hibern8 in which case we need to make
 666                  * sure that device ref_clk is active for specific time after
 667                  * hibern8 enter.
 668                  */
 669                 if (!enable) {
 670                         unsigned long gating_wait;
 671
 672                         gating_wait = host->hba->dev_info.clk_gating_wait_us;
 673                         if (!gating_wait) {
 674                                 udelay(1);
 675                         } else {
 676                                 /*
 677                                  * bRefClkGatingWaitTime defines the minimum
 678                                  * time for which the reference clock is
 679                                  * required by device during transition from
 680                                  * HS-MODE to LS-MODE or HIBERN8 state. Give it
 681                                  * more delay to be on the safe side.
 682                                  */
 683                                 gating_wait += 10;
 684                                 usleep_range(gating_wait, gating_wait + 10);
 685                         }
 686                 }
 687
 688                 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
 689
 690                 /* ensure that ref_clk is enabled/disabled before we return */
 691                 wmb();
 692
 693                 /*
 694                  * If we call hibern8 exit after this, we need to make sure that
 695                  * device ref_clk is stable for at least 1us before the hibern8
 696                  * exit command.
 697                  */
 698                 if (enable)
 699                         udelay(1);
 700
 701                 host->is_dev_ref_clk_enabled = enable;
 702         }
 703 }
 704
 705 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 706                                 enum ufs_notify_change_status status,
 707                                 struct ufs_pa_layer_attr *dev_max_params,
 708                                 struct ufs_pa_layer_attr *dev_req_params)
 709 {
 710         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 711         struct ufs_dev_params ufs_qcom_cap;
 712         int ret = 0;
 713
 714         if (!dev_req_params) {
 715                 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
 716                 ret = -EINVAL;
 717                 goto out;
 718         }
 719
 720         switch (status) {
 721         case PRE_CHANGE:
 722                 ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
 723                 ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
 724
 725                 if (host->hw_ver.major == 0x1) {
 726                         /*
 727                          * HS-G3 operations may not reliably work on legacy QCOM
 728                          * UFS host controller hardware even though capability
 729                          * exchange during link startup phase may end up
 730                          * negotiating maximum supported gear as G3.
 731                          * Hence downgrade the maximum supported gear to HS-G2.
 732                          */
 733                         if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
 734                                 ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
 735                         if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
 736                                 ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
 737                 }
 738
 739                 ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
 740                                                dev_max_params,
 741                                                dev_req_params);
 742                 if (ret) {
 743                         pr_err("%s: failed to determine capabilities\n",
 744                                         __func__);
 745                         goto out;
 746                 }
 747
 748                 /* enable the device ref clock before changing to HS mode */
 749                 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
 750                         ufshcd_is_hs_mode(dev_req_params))
 751                         ufs_qcom_dev_ref_clk_ctrl(host, true);
 752
 753                 if (host->hw_ver.major >= 0x4) {
 754                         ufshcd_dme_configure_adapt(hba,
 755                                                 dev_req_params->gear_tx,
 756                                                 PA_INITIAL_ADAPT);
 757                 }
 758                 break;
 759         case POST_CHANGE:
 760                 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
 761                                         dev_req_params->pwr_rx,
 762                                         dev_req_params->hs_rate, false)) {
 763                         dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
 764                                 __func__);
 765                         /*
 766                          * we return error code at the end of the routine,
 767                          * but continue to configure UFS_PHY_TX_LANE_ENABLE
 768                          * and bus voting as usual
 769                          */
 770                         ret = -EINVAL;
 771                 }
 772
 773                 /* cache the power mode parameters to use internally */
 774                 memcpy(&host->dev_req_params,
 775                                 dev_req_params, sizeof(*dev_req_params));
 776
 777                 /* disable the device ref clock if entered PWM mode */
 778                 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
 779                         !ufshcd_is_hs_mode(dev_req_params))
 780                         ufs_qcom_dev_ref_clk_ctrl(host, false);
 781                 break;
 782         default:
 783                 ret = -EINVAL;
 784                 break;
 785         }
 786 out:
 787         return ret;
 788 }
 789
 790 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
 791 {
 792         int err;
 793         u32 pa_vs_config_reg1;
 794
 795         err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
 796                              &pa_vs_config_reg1);
 797         if (err)
 798                 goto out;
 799
 800         /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
 801         err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
 802                             (pa_vs_config_reg1 | (1 << 12)));
 803
 804 out:
 805         return err;
 806 }
 807
 808 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
 809 {
 810         int err = 0;
 811
 812         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
 813                 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
 814
 815         if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC)
 816                 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE;
 817
 818         return err;
 819 }
 820
 821 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
 822 {
 823         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 824
 825         if (host->hw_ver.major == 0x1)
 826                 return ufshci_version(1, 1);
 827         else
 828                 return ufshci_version(2, 0);
 829 }
 830
 831 /**
 832  * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
 833  * @hba: host controller instance
 834  *
 835  * QCOM UFS host controller might have some non standard behaviours (quirks)
 836  * than what is specified by UFSHCI specification. Advertise all such
 837  * quirks to standard UFS host controller driver so standard takes them into
 838  * account.
 839  */
 840 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
 841 {
 842         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 843
 844         if (host->hw_ver.major == 0x01) {
 845                 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
 846                             | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
 847                             | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE;
 848
 849                 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001)
 850                         hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR;
 851
 852                 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
 853         }
 854
 855         if (host->hw_ver.major == 0x2) {
 856                 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
 857
 858                 if (!ufs_qcom_cap_qunipro(host))
 859                         /* Legacy UniPro mode still need following quirks */
 860                         hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
 861                                 | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
 862                                 | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
 863         }
 864 }
 865
 866 static void ufs_qcom_set_caps(struct ufs_hba *hba)
 867 {
 868         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 869
 870         hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
 871         hba->caps |= UFSHCD_CAP_CLK_SCALING;
 872         hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
 873         hba->caps |= UFSHCD_CAP_WB_EN;
 874         hba->caps |= UFSHCD_CAP_CRYPTO;
 875         hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
 876
 877         if (host->hw_ver.major >= 0x2) {
 878                 host->caps = UFS_QCOM_CAP_QUNIPRO |
 879                              UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE;
 880         }
 881 }
 882
 883 /**
 884  * ufs_qcom_setup_clocks - enables/disable clocks
 885  * @hba: host controller instance
 886  * @on: If true, enable clocks else disable them.
 887  * @status: PRE_CHANGE or POST_CHANGE notify
 888  *
 889  * Returns 0 on success, non-zero on failure.
 890  */
 891 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
 892                                  enum ufs_notify_change_status status)
 893 {
 894         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
 895
 896         /*
 897          * In case ufs_qcom_init() is not yet done, simply ignore.
 898          * This ufs_qcom_setup_clocks() shall be called from
 899          * ufs_qcom_init() after init is done.
 900          */
 901         if (!host)
 902                 return 0;
 903
 904         switch (status) {
 905         case PRE_CHANGE:
 906                 if (!on) {
 907                         if (!ufs_qcom_is_link_active(hba)) {
 908                                 /* disable device ref_clk */
 909                                 ufs_qcom_dev_ref_clk_ctrl(host, false);
 910                         }
 911                 }
 912                 break;
 913         case POST_CHANGE:
 914                 if (on) {
 915                         /* enable the device ref clock for HS mode*/
 916                         if (ufshcd_is_hs_mode(&hba->pwr_info))
 917                                 ufs_qcom_dev_ref_clk_ctrl(host, true);
 918                 }
 919                 break;
 920         }
 921
 922         return 0;
 923 }
 924
 925 static int
 926 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
 927 {
 928         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
 929
 930         /* Currently this code only knows about a single reset. */
 931         WARN_ON(id);
 932         ufs_qcom_assert_reset(host->hba);
 933         /* provide 1ms delay to let the reset pulse propagate. */
 934         usleep_range(1000, 1100);
 935         return 0;
 936 }
 937
 938 static int
 939 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
 940 {
 941         struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
 942
 943         /* Currently this code only knows about a single reset. */
 944         WARN_ON(id);
 945         ufs_qcom_deassert_reset(host->hba);
 946
 947         /*
 948          * after reset deassertion, phy will need all ref clocks,
 949          * voltage, current to settle down before starting serdes.
 950          */
 951         usleep_range(1000, 1100);
 952         return 0;
 953 }
 954
 955 static const struct reset_control_ops ufs_qcom_reset_ops = {
 956         .assert = ufs_qcom_reset_assert,
 957         .deassert = ufs_qcom_reset_deassert,
 958 };
 959
 960 #define ANDROID_BOOT_DEV_MAX    30
 961 static char android_boot_dev[ANDROID_BOOT_DEV_MAX];
 962
 963 #ifndef MODULE
 964 static int __init get_android_boot_dev(char *str)
 965 {
 966         strlcpy(android_boot_dev, str, ANDROID_BOOT_DEV_MAX);
 967         return 1;
 968 }
 969 __setup("androidboot.bootdevice=", get_android_boot_dev);
 970 #endif
 971
 972 /**
 973  * ufs_qcom_init - bind phy with controller
 974  * @hba: host controller instance
 975  *
 976  * Binds PHY with controller and powers up PHY enabling clocks
 977  * and regulators.
 978  *
 979  * Returns -EPROBE_DEFER if binding fails, returns negative error
 980  * on phy power up failure and returns zero on success.
 981  */
 982 static int ufs_qcom_init(struct ufs_hba *hba)
 983 {
 984         int err;
 985         struct device *dev = hba->dev;
 986         struct platform_device *pdev = to_platform_device(dev);
 987         struct ufs_qcom_host *host;
 988         struct resource *res;
 989         struct ufs_clk_info *clki;
 990
 991         if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
 992                 return -ENODEV;
 993
 994         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
 995         if (!host) {
 996                 err = -ENOMEM;
 997                 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
 998                 goto out;
 999         }
1000
1001         /* Make a two way bind between the qcom host and the hba */
1002         host->hba = hba;
1003         ufshcd_set_variant(hba, host);
1004
1005         /* Setup the reset control of HCI */
1006         host->core_reset = devm_reset_control_get(hba->dev, "rst");
1007         if (IS_ERR(host->core_reset)) {
1008                 err = PTR_ERR(host->core_reset);
1009                 dev_warn(dev, "Failed to get reset control %d\n", err);
1010                 host->core_reset = NULL;
1011                 err = 0;
1012         }
1013
1014         /* Fire up the reset controller. Failure here is non-fatal. */
1015         host->rcdev.of_node = dev->of_node;
1016         host->rcdev.ops = &ufs_qcom_reset_ops;
1017         host->rcdev.owner = dev->driver->owner;
1018         host->rcdev.nr_resets = 1;
1019         err = devm_reset_controller_register(dev, &host->rcdev);
1020         if (err) {
1021                 dev_warn(dev, "Failed to register reset controller\n");
1022                 err = 0;
1023         }
1024
1025         /*
1026          * voting/devoting device ref_clk source is time consuming hence
1027          * skip devoting it during aggressive clock gating. This clock
1028          * will still be gated off during runtime suspend.
1029          */
1030         host->generic_phy = devm_phy_get(dev, "ufsphy");
1031
1032         if (host->generic_phy == ERR_PTR(-EPROBE_DEFER)) {
1033                 /*
1034                  * UFS driver might be probed before the phy driver does.
1035                  * In that case we would like to return EPROBE_DEFER code.
1036                  */
1037                 err = -EPROBE_DEFER;
1038                 dev_warn(dev, "%s: required phy device. hasn't probed yet. err = %d\n",
1039                         __func__, err);
1040                 goto out_variant_clear;
1041         } else if (IS_ERR(host->generic_phy)) {
1042                 if (has_acpi_companion(dev)) {
1043                         host->generic_phy = NULL;
1044                 } else {
1045                         err = PTR_ERR(host->generic_phy);
1046                         dev_err(dev, "%s: PHY get failed %d\n", __func__, err);
1047                         goto out_variant_clear;
1048                 }
1049         }
1050
1051         host->device_reset = devm_gpiod_get_optional(dev, "reset",
1052                                                      GPIOD_OUT_HIGH);
1053         if (IS_ERR(host->device_reset)) {
1054                 err = PTR_ERR(host->device_reset);
1055                 if (err != -EPROBE_DEFER)
1056                         dev_err(dev, "failed to acquire reset gpio: %d\n", err);
1057                 goto out_variant_clear;
1058         }
1059
1060         ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1061                 &host->hw_ver.minor, &host->hw_ver.step);
1062
1063         /*
1064          * for newer controllers, device reference clock control bit has
1065          * moved inside UFS controller register address space itself.
1066          */
1067         if (host->hw_ver.major >= 0x02) {
1068                 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1069                 host->dev_ref_clk_en_mask = BIT(26);
1070         } else {
1071                 /* "dev_ref_clk_ctrl_mem" is optional resource */
1072                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1073                                                    "dev_ref_clk_ctrl_mem");
1074                 if (res) {
1075                         host->dev_ref_clk_ctrl_mmio =
1076                                         devm_ioremap_resource(dev, res);
1077                         if (IS_ERR(host->dev_ref_clk_ctrl_mmio))
1078                                 host->dev_ref_clk_ctrl_mmio = NULL;
1079                         host->dev_ref_clk_en_mask = BIT(5);
1080                 }
1081         }
1082
1083         list_for_each_entry(clki, &hba->clk_list_head, list) {
1084                 if (!strcmp(clki->name, "core_clk_unipro"))
1085                         clki->keep_link_active = true;
1086         }
1087
1088         err = ufs_qcom_init_lane_clks(host);
1089         if (err)
1090                 goto out_variant_clear;
1091
1092         ufs_qcom_set_caps(hba);
1093         ufs_qcom_advertise_quirks(hba);
1094
1095         err = ufs_qcom_ice_init(host);
1096         if (err)
1097                 goto out_variant_clear;
1098
1099         ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1100
1101         if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
1102                 ufs_qcom_hosts[hba->dev->id] = host;
1103
1104         host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
1105         ufs_qcom_get_default_testbus_cfg(host);
1106         err = ufs_qcom_testbus_config(host);
1107         if (err) {
1108                 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1109                                 __func__, err);
1110                 err = 0;
1111         }
1112
1113         goto out;
1114
1115 out_variant_clear:
1116         ufshcd_set_variant(hba, NULL);
1117 out:
1118         return err;
1119 }
1120
1121 static void ufs_qcom_exit(struct ufs_hba *hba)
1122 {
1123         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1124
1125         ufs_qcom_disable_lane_clks(host);
1126         phy_power_off(host->generic_phy);
1127         phy_exit(host->generic_phy);
1128 }
1129
1130 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
1131                                                        u32 clk_cycles)
1132 {
1133         int err;
1134         u32 core_clk_ctrl_reg;
1135
1136         if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
1137                 return -EINVAL;
1138
1139         err = ufshcd_dme_get(hba,
1140                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1141                             &core_clk_ctrl_reg);
1142         if (err)
1143                 goto out;
1144
1145         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
1146         core_clk_ctrl_reg |= clk_cycles;
1147
1148         /* Clear CORE_CLK_DIV_EN */
1149         core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1150
1151         err = ufshcd_dme_set(hba,
1152                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1153                             core_clk_ctrl_reg);
1154 out:
1155         return err;
1156 }
1157
1158 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1159 {
1160         /* nothing to do as of now */
1161         return 0;
1162 }
1163
1164 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1165 {
1166         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1167
1168         if (!ufs_qcom_cap_qunipro(host))
1169                 return 0;
1170
1171         /* set unipro core clock cycles to 150 and clear clock divider */
1172         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150);
1173 }
1174
1175 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1176 {
1177         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1178         int err;
1179         u32 core_clk_ctrl_reg;
1180
1181         if (!ufs_qcom_cap_qunipro(host))
1182                 return 0;
1183
1184         err = ufshcd_dme_get(hba,
1185                             UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1186                             &core_clk_ctrl_reg);
1187
1188         /* make sure CORE_CLK_DIV_EN is cleared */
1189         if (!err &&
1190             (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1191                 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1192                 err = ufshcd_dme_set(hba,
1193                                     UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1194                                     core_clk_ctrl_reg);
1195         }
1196
1197         return err;
1198 }
1199
1200 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1201 {
1202         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1203
1204         if (!ufs_qcom_cap_qunipro(host))
1205                 return 0;
1206
1207         /* set unipro core clock cycles to 75 and clear clock divider */
1208         return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75);
1209 }
1210
1211 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1212                 bool scale_up, enum ufs_notify_change_status status)
1213 {
1214         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1215         struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params;
1216         int err = 0;
1217
1218         if (status == PRE_CHANGE) {
1219                 err = ufshcd_uic_hibern8_enter(hba);
1220                 if (err)
1221                         return err;
1222                 if (scale_up)
1223                         err = ufs_qcom_clk_scale_up_pre_change(hba);
1224                 else
1225                         err = ufs_qcom_clk_scale_down_pre_change(hba);
1226                 if (err)
1227                         ufshcd_uic_hibern8_exit(hba);
1228
1229         } else {
1230                 if (scale_up)
1231                         err = ufs_qcom_clk_scale_up_post_change(hba);
1232                 else
1233                         err = ufs_qcom_clk_scale_down_post_change(hba);
1234
1235
1236                 if (err || !dev_req_params) {
1237                         ufshcd_uic_hibern8_exit(hba);
1238                         goto out;
1239                 }
1240
1241                 ufs_qcom_cfg_timers(hba,
1242                                     dev_req_params->gear_rx,
1243                                     dev_req_params->pwr_rx,
1244                                     dev_req_params->hs_rate,
1245                                     false);
1246                 ufshcd_uic_hibern8_exit(hba);
1247         }
1248
1249 out:
1250         return err;
1251 }
1252
1253 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
1254                 void *priv, void (*print_fn)(struct ufs_hba *hba,
1255                 int offset, int num_regs, const char *str, void *priv))
1256 {
1257         u32 reg;
1258         struct ufs_qcom_host *host;
1259
1260         if (unlikely(!hba)) {
1261                 pr_err("%s: hba is NULL\n", __func__);
1262                 return;
1263         }
1264         if (unlikely(!print_fn)) {
1265                 dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
1266                 return;
1267         }
1268
1269         host = ufshcd_get_variant(hba);
1270         if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
1271                 return;
1272
1273         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1274         print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
1275
1276         reg = ufshcd_readl(hba, REG_UFS_CFG1);
1277         reg |= UTP_DBG_RAMS_EN;
1278         ufshcd_writel(hba, reg, REG_UFS_CFG1);
1279
1280         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1281         print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
1282
1283         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1284         print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
1285
1286         reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1287         print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
1288
1289         /* clear bit 17 - UTP_DBG_RAMS_EN */
1290         ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1291
1292         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1293         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
1294
1295         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1296         print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
1297
1298         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1299         print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
1300
1301         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1302         print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
1303
1304         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1305         print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
1306
1307         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1308         print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
1309
1310         reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1311         print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
1312 }
1313
1314 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1315 {
1316         if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {
1317                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1318                                 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1319                 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1320         } else {
1321                 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);
1322                 ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
1323         }
1324 }
1325
1326 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1327 {
1328         /* provide a legal default configuration */
1329         host->testbus.select_major = TSTBUS_UNIPRO;
1330         host->testbus.select_minor = 37;
1331 }
1332
1333 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1334 {
1335         if (host->testbus.select_major >= TSTBUS_MAX) {
1336                 dev_err(host->hba->dev,
1337                         "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1338                         __func__, host->testbus.select_major);
1339                 return false;
1340         }
1341
1342         return true;
1343 }
1344
1345 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1346 {
1347         int reg;
1348         int offset;
1349         u32 mask = TEST_BUS_SUB_SEL_MASK;
1350
1351         if (!host)
1352                 return -EINVAL;
1353
1354         if (!ufs_qcom_testbus_cfg_is_ok(host))
1355                 return -EPERM;
1356
1357         switch (host->testbus.select_major) {
1358         case TSTBUS_UAWM:
1359                 reg = UFS_TEST_BUS_CTRL_0;
1360                 offset = 24;
1361                 break;
1362         case TSTBUS_UARM:
1363                 reg = UFS_TEST_BUS_CTRL_0;
1364                 offset = 16;
1365                 break;
1366         case TSTBUS_TXUC:
1367                 reg = UFS_TEST_BUS_CTRL_0;
1368                 offset = 8;
1369                 break;
1370         case TSTBUS_RXUC:
1371                 reg = UFS_TEST_BUS_CTRL_0;
1372                 offset = 0;
1373                 break;
1374         case TSTBUS_DFC:
1375                 reg = UFS_TEST_BUS_CTRL_1;
1376                 offset = 24;
1377                 break;
1378         case TSTBUS_TRLUT:
1379                 reg = UFS_TEST_BUS_CTRL_1;
1380                 offset = 16;
1381                 break;
1382         case TSTBUS_TMRLUT:
1383                 reg = UFS_TEST_BUS_CTRL_1;
1384                 offset = 8;
1385                 break;
1386         case TSTBUS_OCSC:
1387                 reg = UFS_TEST_BUS_CTRL_1;
1388                 offset = 0;
1389                 break;
1390         case TSTBUS_WRAPPER:
1391                 reg = UFS_TEST_BUS_CTRL_2;
1392                 offset = 16;
1393                 break;
1394         case TSTBUS_COMBINED:
1395                 reg = UFS_TEST_BUS_CTRL_2;
1396                 offset = 8;
1397                 break;
1398         case TSTBUS_UTP_HCI:
1399                 reg = UFS_TEST_BUS_CTRL_2;
1400                 offset = 0;
1401                 break;
1402         case TSTBUS_UNIPRO:
1403                 reg = UFS_UNIPRO_CFG;
1404                 offset = 20;
1405                 mask = 0xFFF;
1406                 break;
1407         /*
1408          * No need for a default case, since
1409          * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1410          * is legal
1411          */
1412         }
1413         mask <<= offset;
1414         ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1415                     (u32)host->testbus.select_major << 19,
1416                     REG_UFS_CFG1);
1417         ufshcd_rmwl(host->hba, mask,
1418                     (u32)host->testbus.select_minor << offset,
1419                     reg);
1420         ufs_qcom_enable_test_bus(host);
1421         /*
1422          * Make sure the test bus configuration is
1423          * committed before returning.
1424          */
1425         mb();
1426
1427         return 0;
1428 }
1429
1430 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1431 {
1432         ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1433                          "HCI Vendor Specific Registers ");
1434
1435         ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
1436 }
1437
1438 /**
1439  * ufs_qcom_device_reset() - toggle the (optional) device reset line
1440  * @hba: per-adapter instance
1441  *
1442  * Toggles the (optional) reset line to reset the attached device.
1443  */
1444 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1445 {
1446         struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1447
1448         /* reset gpio is optional */
1449         if (!host->device_reset)
1450                 return -EOPNOTSUPP;
1451
1452         /*
1453          * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1454          * be on the safe side.
1455          */
1456         ufs_qcom_device_reset_ctrl(hba, true);
1457         usleep_range(10, 15);
1458
1459         ufs_qcom_device_reset_ctrl(hba, false);
1460         usleep_range(10, 15);
1461
1462         return 0;
1463 }
1464
1465 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
1466 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1467                                           struct devfreq_dev_profile *p,
1468                                           void *data)
1469 {
1470         static struct devfreq_simple_ondemand_data *d;
1471
1472         if (!data)
1473                 return;
1474
1475         d = (struct devfreq_simple_ondemand_data *)data;
1476         p->polling_ms = 60;
1477         d->upthreshold = 70;
1478         d->downdifferential = 5;
1479 }
1480 #else
1481 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1482                                           struct devfreq_dev_profile *p,
1483                                           void *data)
1484 {
1485 }
1486 #endif
1487
1488 /*
1489  * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1490  *
1491  * The variant operations configure the necessary controller and PHY
1492  * handshake during initialization.
1493  */
1494 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1495         .name                   = "qcom",
1496         .init                   = ufs_qcom_init,
1497         .exit                   = ufs_qcom_exit,
1498         .get_ufs_hci_version    = ufs_qcom_get_ufs_hci_version,
1499         .clk_scale_notify       = ufs_qcom_clk_scale_notify,
1500         .setup_clocks           = ufs_qcom_setup_clocks,
1501         .hce_enable_notify      = ufs_qcom_hce_enable_notify,
1502         .link_startup_notify    = ufs_qcom_link_startup_notify,
1503         .pwr_change_notify      = ufs_qcom_pwr_change_notify,
1504         .apply_dev_quirks       = ufs_qcom_apply_dev_quirks,
1505         .suspend                = ufs_qcom_suspend,
1506         .resume                 = ufs_qcom_resume,
1507         .dbg_register_dump      = ufs_qcom_dump_dbg_regs,
1508         .device_reset           = ufs_qcom_device_reset,
1509         .config_scaling_param = ufs_qcom_config_scaling_param,
1510         .program_key            = ufs_qcom_ice_program_key,
1511 };
1512
1513 /**
1514  * ufs_qcom_probe - probe routine of the driver
1515  * @pdev: pointer to Platform device handle
1516  *
1517  * Return zero for success and non-zero for failure
1518  */
1519 static int ufs_qcom_probe(struct platform_device *pdev)
1520 {
1521         int err;
1522         struct device *dev = &pdev->dev;
1523
1524         /* Perform generic probe */
1525         err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1526         if (err)
1527                 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1528
1529         return err;
1530 }
1531
1532 /**
1533  * ufs_qcom_remove - set driver_data of the device to NULL
1534  * @pdev: pointer to platform device handle
1535  *
1536  * Always returns 0
1537  */
1538 static int ufs_qcom_remove(struct platform_device *pdev)
1539 {
1540         struct ufs_hba *hba =  platform_get_drvdata(pdev);
1541
1542         pm_runtime_get_sync(&(pdev)->dev);
1543         ufshcd_remove(hba);
1544         return 0;
1545 }
1546
1547 static const struct of_device_id ufs_qcom_of_match[] = {
1548         { .compatible = "qcom,ufshc"},
1549         {},
1550 };
1551 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1552
1553 #ifdef CONFIG_ACPI
1554 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1555         { "QCOM24A5" },
1556         { },
1557 };
1558 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1559 #endif
1560
1561 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1562         SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
1563         SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1564         .prepare         = ufshcd_suspend_prepare,
1565         .complete        = ufshcd_resume_complete,
1566 };
1567
1568 static struct platform_driver ufs_qcom_pltform = {
1569         .probe  = ufs_qcom_probe,
1570         .remove = ufs_qcom_remove,
1571         .shutdown = ufshcd_pltfrm_shutdown,
1572         .driver = {
1573                 .name   = "ufshcd-qcom",
1574                 .pm     = &ufs_qcom_pm_ops,
1575                 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1576                 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1577         },
1578 };
1579 module_platform_driver(ufs_qcom_pltform);
1580
1581 MODULE_LICENSE("GPL v2");