drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_11_0_0_offset.h"
  30 #include "gc/gc_11_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v11_structs.h"
  33 #include "mes_v11_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes_2.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes_2.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
  41 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
  42 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes_2.bin");
  43 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
  44 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
  45 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes_2.bin");
  46 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
  47 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes.bin");
  48 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes_2.bin");
  49 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mes1.bin");
  50 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes_2.bin");
  51 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mes1.bin");
  52
  53
  54 static int mes_v11_0_hw_fini(void *handle);
  55 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
  56 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
  57
  58 #define MES_EOP_SIZE   2048
  59
  60 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
  61 {
  62         struct amdgpu_device *adev = ring->adev;
  63
  64         if (ring->use_doorbell) {
  65                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  66                              ring->wptr);
  67                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  68         } else {
  69                 BUG();
  70         }
  71 }
  72
  73 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
  74 {
  75         return *ring->rptr_cpu_addr;
  76 }
  77
  78 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
  79 {
  80         u64 wptr;
  81
  82         if (ring->use_doorbell)
  83                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  84         else
  85                 BUG();
  86         return wptr;
  87 }
  88
  89 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
  90         .type = AMDGPU_RING_TYPE_MES,
  91         .align_mask = 1,
  92         .nop = 0,
  93         .support_64bit_ptrs = true,
  94         .get_rptr = mes_v11_0_ring_get_rptr,
  95         .get_wptr = mes_v11_0_ring_get_wptr,
  96         .set_wptr = mes_v11_0_ring_set_wptr,
  97         .insert_nop = amdgpu_ring_insert_nop,
  98 };
  99
 100 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
 101                                                     void *pkt, int size,
 102                                                     int api_status_off)
 103 {
 104         int ndw = size / 4;
 105         signed long r;
 106         union MESAPI__ADD_QUEUE *x_pkt = pkt;
 107         struct MES_API_STATUS *api_status;
 108         struct amdgpu_device *adev = mes->adev;
 109         struct amdgpu_ring *ring = &mes->ring;
 110         unsigned long flags;
 111         signed long timeout = adev->usec_timeout;
 112
 113         if (amdgpu_emu_mode) {
 114                 timeout *= 100;
 115         } else if (amdgpu_sriov_vf(adev)) {
 116                 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
 117                 timeout = 15 * 600 * 1000;
 118         }
 119         BUG_ON(size % 4 != 0);
 120
 121         spin_lock_irqsave(&mes->ring_lock, flags);
 122         if (amdgpu_ring_alloc(ring, ndw)) {
 123                 spin_unlock_irqrestore(&mes->ring_lock, flags);
 124                 return -ENOMEM;
 125         }
 126
 127         api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
 128         api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr;
 129         api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq;
 130
 131         amdgpu_ring_write_multiple(ring, pkt, ndw);
 132         amdgpu_ring_commit(ring);
 133         spin_unlock_irqrestore(&mes->ring_lock, flags);
 134
 135         DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
 136
 137         r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
 138                       timeout);
 139         if (r < 1) {
 140                 DRM_ERROR("MES failed to response msg=%d\n",
 141                           x_pkt->header.opcode);
 142
 143                 while (halt_if_hws_hang)
 144                         schedule();
 145
 146                 return -ETIMEDOUT;
 147         }
 148
 149         return 0;
 150 }
 151
 152 static int convert_to_mes_queue_type(int queue_type)
 153 {
 154         if (queue_type == AMDGPU_RING_TYPE_GFX)
 155                 return MES_QUEUE_TYPE_GFX;
 156         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 157                 return MES_QUEUE_TYPE_COMPUTE;
 158         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 159                 return MES_QUEUE_TYPE_SDMA;
 160         else
 161                 BUG();
 162         return -1;
 163 }
 164
 165 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 166                                   struct mes_add_queue_input *input)
 167 {
 168         struct amdgpu_device *adev = mes->adev;
 169         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 170         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
 171         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 172
 173         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 174
 175         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 176         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 177         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 178
 179         mes_add_queue_pkt.process_id = input->process_id;
 180         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 181         mes_add_queue_pkt.process_va_start = input->process_va_start;
 182         mes_add_queue_pkt.process_va_end = input->process_va_end;
 183         mes_add_queue_pkt.process_quantum = input->process_quantum;
 184         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 185         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 186         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 187         mes_add_queue_pkt.inprocess_gang_priority =
 188                 input->inprocess_gang_priority;
 189         mes_add_queue_pkt.gang_global_priority_level =
 190                 input->gang_global_priority_level;
 191         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 192         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 193
 194         if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
 195                         AMDGPU_MES_API_VERSION_SHIFT) >= 2)
 196                 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
 197         else
 198                 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 199
 200         mes_add_queue_pkt.queue_type =
 201                 convert_to_mes_queue_type(input->queue_type);
 202         mes_add_queue_pkt.paging = input->paging;
 203         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 204         mes_add_queue_pkt.gws_base = input->gws_base;
 205         mes_add_queue_pkt.gws_size = input->gws_size;
 206         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 207         mes_add_queue_pkt.tma_addr = input->tma_addr;
 208         mes_add_queue_pkt.trap_en = input->trap_en;
 209         mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
 210         mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 211
 212         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 213         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 214         mes_add_queue_pkt.gds_size = input->queue_size;
 215
 216         mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled;
 217
 218         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 219                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 220                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 221 }
 222
 223 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
 224                                      struct mes_remove_queue_input *input)
 225 {
 226         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 227
 228         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 229
 230         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 231         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 232         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 233
 234         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 235         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 236
 237         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 238                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 239                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 240 }
 241
 242 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 243                         struct mes_unmap_legacy_queue_input *input)
 244 {
 245         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 246
 247         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 248
 249         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 250         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 251         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 252
 253         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 254         mes_remove_queue_pkt.gang_context_addr = 0;
 255
 256         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 257         mes_remove_queue_pkt.queue_id = input->queue_id;
 258
 259         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 260                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 261                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 262                 mes_remove_queue_pkt.tf_data =
 263                         lower_32_bits(input->trail_fence_data);
 264         } else {
 265                 mes_remove_queue_pkt.unmap_legacy_queue = 1;
 266                 mes_remove_queue_pkt.queue_type =
 267                         convert_to_mes_queue_type(input->queue_type);
 268         }
 269
 270         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 271                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 272                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 273 }
 274
 275 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
 276                                   struct mes_suspend_gang_input *input)
 277 {
 278         return 0;
 279 }
 280
 281 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
 282                                  struct mes_resume_gang_input *input)
 283 {
 284         return 0;
 285 }
 286
 287 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
 288 {
 289         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 290
 291         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 292
 293         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 294         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 295         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 296
 297         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 298                         &mes_status_pkt, sizeof(mes_status_pkt),
 299                         offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
 300 }
 301
 302 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
 303                              struct mes_misc_op_input *input)
 304 {
 305         union MESAPI__MISC misc_pkt;
 306
 307         memset(&misc_pkt, 0, sizeof(misc_pkt));
 308
 309         misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
 310         misc_pkt.header.opcode = MES_SCH_API_MISC;
 311         misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 312
 313         switch (input->op) {
 314         case MES_MISC_OP_READ_REG:
 315                 misc_pkt.opcode = MESAPI_MISC__READ_REG;
 316                 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
 317                 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
 318                 break;
 319         case MES_MISC_OP_WRITE_REG:
 320                 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
 321                 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
 322                 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
 323                 break;
 324         case MES_MISC_OP_WRM_REG_WAIT:
 325                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 326                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
 327                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 328                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 329                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 330                 misc_pkt.wait_reg_mem.reg_offset2 = 0;
 331                 break;
 332         case MES_MISC_OP_WRM_REG_WR_WAIT:
 333                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 334                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
 335                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 336                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 337                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 338                 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
 339                 break;
 340         case MES_MISC_OP_SET_SHADER_DEBUGGER:
 341                 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
 342                 misc_pkt.set_shader_debugger.process_context_addr =
 343                                 input->set_shader_debugger.process_context_addr;
 344                 misc_pkt.set_shader_debugger.flags.u32all =
 345                                 input->set_shader_debugger.flags.u32all;
 346                 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
 347                                 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
 348                 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
 349                                 input->set_shader_debugger.tcp_watch_cntl,
 350                                 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
 351                 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
 352                 break;
 353         default:
 354                 DRM_ERROR("unsupported misc op (%d) \n", input->op);
 355                 return -EINVAL;
 356         }
 357
 358         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 359                         &misc_pkt, sizeof(misc_pkt),
 360                         offsetof(union MESAPI__MISC, api_status));
 361 }
 362
 363 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 364 {
 365         int i;
 366         struct amdgpu_device *adev = mes->adev;
 367         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 368
 369         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 370
 371         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 372         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 373         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 374
 375         mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 376         mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 377         mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 378         mes_set_hw_res_pkt.paging_vmid = 0;
 379         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
 380         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 381                 mes->query_status_fence_gpu_addr;
 382
 383         for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 384                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
 385                         mes->compute_hqd_mask[i];
 386
 387         for (i = 0; i < MAX_GFX_PIPES; i++)
 388                 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
 389
 390         for (i = 0; i < MAX_SDMA_PIPES; i++)
 391                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
 392
 393         for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 394                 mes_set_hw_res_pkt.aggregated_doorbells[i] =
 395                         mes->aggregated_doorbells[i];
 396
 397         for (i = 0; i < 5; i++) {
 398                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 399                 mes_set_hw_res_pkt.mmhub_base[i] =
 400                                 adev->reg_offset[MMHUB_HWIP][0][i];
 401                 mes_set_hw_res_pkt.osssys_base[i] =
 402                 adev->reg_offset[OSSSYS_HWIP][0][i];
 403         }
 404
 405         mes_set_hw_res_pkt.disable_reset = 1;
 406         mes_set_hw_res_pkt.disable_mes_log = 1;
 407         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 408         mes_set_hw_res_pkt.enable_reg_active_poll = 1;
 409         mes_set_hw_res_pkt.enable_level_process_quantum_check = 1;
 410         mes_set_hw_res_pkt.oversubscription_timer = 50;
 411
 412         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 413                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 414                         offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
 415 }
 416
 417 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
 418         .add_hw_queue = mes_v11_0_add_hw_queue,
 419         .remove_hw_queue = mes_v11_0_remove_hw_queue,
 420         .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
 421         .suspend_gang = mes_v11_0_suspend_gang,
 422         .resume_gang = mes_v11_0_resume_gang,
 423         .misc_op = mes_v11_0_misc_op,
 424 };
 425
 426 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 427                                            enum admgpu_mes_pipe pipe)
 428 {
 429         int r;
 430         const struct mes_firmware_header_v1_0 *mes_hdr;
 431         const __le32 *fw_data;
 432         unsigned fw_size;
 433
 434         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 435                 adev->mes.fw[pipe]->data;
 436
 437         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 438                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 439         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 440
 441         r = amdgpu_bo_create_reserved(adev, fw_size,
 442                                       PAGE_SIZE,
 443                                       AMDGPU_GEM_DOMAIN_VRAM |
 444                                       AMDGPU_GEM_DOMAIN_GTT,
 445                                       &adev->mes.ucode_fw_obj[pipe],
 446                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 447                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 448         if (r) {
 449                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 450                 return r;
 451         }
 452
 453         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 454
 455         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 456         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 457
 458         return 0;
 459 }
 460
 461 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 462                                                 enum admgpu_mes_pipe pipe)
 463 {
 464         int r;
 465         const struct mes_firmware_header_v1_0 *mes_hdr;
 466         const __le32 *fw_data;
 467         unsigned fw_size;
 468
 469         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 470                 adev->mes.fw[pipe]->data;
 471
 472         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 473                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 474         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 475
 476         r = amdgpu_bo_create_reserved(adev, fw_size,
 477                                       64 * 1024,
 478                                       AMDGPU_GEM_DOMAIN_VRAM |
 479                                       AMDGPU_GEM_DOMAIN_GTT,
 480                                       &adev->mes.data_fw_obj[pipe],
 481                                       &adev->mes.data_fw_gpu_addr[pipe],
 482                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 483         if (r) {
 484                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 485                 return r;
 486         }
 487
 488         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 489
 490         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 491         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 492
 493         return 0;
 494 }
 495
 496 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
 497                                          enum admgpu_mes_pipe pipe)
 498 {
 499         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 500                               &adev->mes.data_fw_gpu_addr[pipe],
 501                               (void **)&adev->mes.data_fw_ptr[pipe]);
 502
 503         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 504                               &adev->mes.ucode_fw_gpu_addr[pipe],
 505                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 506 }
 507
 508 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 509 {
 510         uint64_t ucode_addr;
 511         uint32_t pipe, data = 0;
 512
 513         if (enable) {
 514                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 515                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 516                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 517                              MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
 518                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 519
 520                 mutex_lock(&adev->srbm_mutex);
 521                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 522                         if (!adev->enable_mes_kiq &&
 523                             pipe == AMDGPU_MES_KIQ_PIPE)
 524                                 continue;
 525
 526                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 527
 528                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 529                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 530                                      lower_32_bits(ucode_addr));
 531                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 532                                      upper_32_bits(ucode_addr));
 533                 }
 534                 soc21_grbm_select(adev, 0, 0, 0, 0);
 535                 mutex_unlock(&adev->srbm_mutex);
 536
 537                 /* unhalt MES and activate pipe0 */
 538                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 539                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 540                                      adev->enable_mes_kiq ? 1 : 0);
 541                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 542
 543                 if (amdgpu_emu_mode)
 544                         msleep(100);
 545                 else
 546                         udelay(50);
 547         } else {
 548                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 549                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 550                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 551                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 552                                      MES_INVALIDATE_ICACHE, 1);
 553                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 554                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 555                                      adev->enable_mes_kiq ? 1 : 0);
 556                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 557                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 558         }
 559 }
 560
 561 /* This function is for backdoor MES firmware */
 562 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
 563                                     enum admgpu_mes_pipe pipe, bool prime_icache)
 564 {
 565         int r;
 566         uint32_t data;
 567         uint64_t ucode_addr;
 568
 569         mes_v11_0_enable(adev, false);
 570
 571         if (!adev->mes.fw[pipe])
 572                 return -EINVAL;
 573
 574         r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
 575         if (r)
 576                 return r;
 577
 578         r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
 579         if (r) {
 580                 mes_v11_0_free_ucode_buffers(adev, pipe);
 581                 return r;
 582         }
 583
 584         mutex_lock(&adev->srbm_mutex);
 585         /* me=3, pipe=0, queue=0 */
 586         soc21_grbm_select(adev, 3, pipe, 0, 0);
 587
 588         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 589
 590         /* set ucode start address */
 591         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 592         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 593                      lower_32_bits(ucode_addr));
 594         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 595                      upper_32_bits(ucode_addr));
 596
 597         /* set ucode fimrware address */
 598         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 599                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 600         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 601                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 602
 603         /* set ucode instruction cache boundary to 2M-1 */
 604         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 605
 606         /* set ucode data firmware address */
 607         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 608                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 609         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 610                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 611
 612         /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
 613         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
 614
 615         if (prime_icache) {
 616                 /* invalidate ICACHE */
 617                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 618                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 619                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 620                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 621
 622                 /* prime the ICACHE. */
 623                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 624                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 625                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 626         }
 627
 628         soc21_grbm_select(adev, 0, 0, 0, 0);
 629         mutex_unlock(&adev->srbm_mutex);
 630
 631         return 0;
 632 }
 633
 634 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
 635                                       enum admgpu_mes_pipe pipe)
 636 {
 637         int r;
 638         u32 *eop;
 639
 640         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 641                               AMDGPU_GEM_DOMAIN_GTT,
 642                               &adev->mes.eop_gpu_obj[pipe],
 643                               &adev->mes.eop_gpu_addr[pipe],
 644                               (void **)&eop);
 645         if (r) {
 646                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 647                 return r;
 648         }
 649
 650         memset(eop, 0,
 651                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 652
 653         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 654         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 655
 656         return 0;
 657 }
 658
 659 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
 660 {
 661         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 662         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 663         uint32_t tmp;
 664
 665         memset(mqd, 0, sizeof(*mqd));
 666
 667         mqd->header = 0xC0310800;
 668         mqd->compute_pipelinestat_enable = 0x00000001;
 669         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 670         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 671         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 672         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 673         mqd->compute_misc_reserved = 0x00000007;
 674
 675         eop_base_addr = ring->eop_gpu_addr >> 8;
 676
 677         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 678         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 679         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 680                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 681
 682         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 683         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 684         mqd->cp_hqd_eop_control = tmp;
 685
 686         /* disable the queue if it's active */
 687         ring->wptr = 0;
 688         mqd->cp_hqd_pq_rptr = 0;
 689         mqd->cp_hqd_pq_wptr_lo = 0;
 690         mqd->cp_hqd_pq_wptr_hi = 0;
 691
 692         /* set the pointer to the MQD */
 693         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 694         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 695
 696         /* set MQD vmid to 0 */
 697         tmp = regCP_MQD_CONTROL_DEFAULT;
 698         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 699         mqd->cp_mqd_control = tmp;
 700
 701         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 702         hqd_gpu_addr = ring->gpu_addr >> 8;
 703         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 704         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 705
 706         /* set the wb address whether it's enabled or not */
 707         wb_gpu_addr = ring->rptr_gpu_addr;
 708         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 709         mqd->cp_hqd_pq_rptr_report_addr_hi =
 710                 upper_32_bits(wb_gpu_addr) & 0xffff;
 711
 712         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 713         wb_gpu_addr = ring->wptr_gpu_addr;
 714         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 715         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 716
 717         /* set up the HQD, this is similar to CP_RB0_CNTL */
 718         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 719         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 720                             (order_base_2(ring->ring_size / 4) - 1));
 721         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 722                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 723         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 724         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 725         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 726         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 727         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 728         mqd->cp_hqd_pq_control = tmp;
 729
 730         /* enable doorbell */
 731         tmp = 0;
 732         if (ring->use_doorbell) {
 733                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 734                                     DOORBELL_OFFSET, ring->doorbell_index);
 735                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 736                                     DOORBELL_EN, 1);
 737                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 738                                     DOORBELL_SOURCE, 0);
 739                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 740                                     DOORBELL_HIT, 0);
 741         } else
 742                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 743                                     DOORBELL_EN, 0);
 744         mqd->cp_hqd_pq_doorbell_control = tmp;
 745
 746         mqd->cp_hqd_vmid = 0;
 747         /* activate the queue */
 748         mqd->cp_hqd_active = 1;
 749
 750         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
 751         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
 752                             PRELOAD_SIZE, 0x55);
 753         mqd->cp_hqd_persistent_state = tmp;
 754
 755         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
 756         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
 757         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
 758
 759         amdgpu_device_flush_hdp(ring->adev, NULL);
 760         return 0;
 761 }
 762
 763 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
 764 {
 765         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 766         struct amdgpu_device *adev = ring->adev;
 767         uint32_t data = 0;
 768
 769         mutex_lock(&adev->srbm_mutex);
 770         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 771
 772         /* set CP_HQD_VMID.VMID = 0. */
 773         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
 774         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
 775         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
 776
 777         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
 778         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
 779         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
 780                              DOORBELL_EN, 0);
 781         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
 782
 783         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
 784         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
 785         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
 786
 787         /* set CP_MQD_CONTROL.VMID=0 */
 788         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
 789         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
 790         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
 791
 792         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
 793         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
 794         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
 795
 796         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
 797         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
 798                      mqd->cp_hqd_pq_rptr_report_addr_lo);
 799         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 800                      mqd->cp_hqd_pq_rptr_report_addr_hi);
 801
 802         /* set CP_HQD_PQ_CONTROL */
 803         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
 804
 805         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
 806         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
 807                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
 808         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 809                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
 810
 811         /* set CP_HQD_PQ_DOORBELL_CONTROL */
 812         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
 813                      mqd->cp_hqd_pq_doorbell_control);
 814
 815         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
 816         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
 817
 818         /* set CP_HQD_ACTIVE.ACTIVE=1 */
 819         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
 820
 821         soc21_grbm_select(adev, 0, 0, 0, 0);
 822         mutex_unlock(&adev->srbm_mutex);
 823 }
 824
 825 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
 826 {
 827         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 828         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
 829         int r;
 830
 831         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 832                 return -EINVAL;
 833
 834         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
 835         if (r) {
 836                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 837                 return r;
 838         }
 839
 840         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
 841
 842         return amdgpu_ring_test_helper(kiq_ring);
 843 }
 844
 845 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
 846                                 enum admgpu_mes_pipe pipe)
 847 {
 848         struct amdgpu_ring *ring;
 849         int r;
 850
 851         if (pipe == AMDGPU_MES_KIQ_PIPE)
 852                 ring = &adev->gfx.kiq[0].ring;
 853         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 854                 ring = &adev->mes.ring;
 855         else
 856                 BUG();
 857
 858         if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
 859             (amdgpu_in_reset(adev) || adev->in_suspend)) {
 860                 *(ring->wptr_cpu_addr) = 0;
 861                 *(ring->rptr_cpu_addr) = 0;
 862                 amdgpu_ring_clear_ring(ring);
 863         }
 864
 865         r = mes_v11_0_mqd_init(ring);
 866         if (r)
 867                 return r;
 868
 869         if (pipe == AMDGPU_MES_SCHED_PIPE) {
 870                 r = mes_v11_0_kiq_enable_queue(adev);
 871                 if (r)
 872                         return r;
 873         } else {
 874                 mes_v11_0_queue_init_register(ring);
 875         }
 876
 877         /* get MES scheduler/KIQ versions */
 878         mutex_lock(&adev->srbm_mutex);
 879         soc21_grbm_select(adev, 3, pipe, 0, 0);
 880
 881         if (pipe == AMDGPU_MES_SCHED_PIPE)
 882                 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
 883         else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
 884                 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
 885
 886         soc21_grbm_select(adev, 0, 0, 0, 0);
 887         mutex_unlock(&adev->srbm_mutex);
 888
 889         return 0;
 890 }
 891
 892 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
 893 {
 894         struct amdgpu_ring *ring;
 895
 896         ring = &adev->mes.ring;
 897
 898         ring->funcs = &mes_v11_0_ring_funcs;
 899
 900         ring->me = 3;
 901         ring->pipe = 0;
 902         ring->queue = 0;
 903
 904         ring->ring_obj = NULL;
 905         ring->use_doorbell = true;
 906         ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
 907         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
 908         ring->no_scheduler = true;
 909         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 910
 911         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
 912                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
 913 }
 914
 915 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
 916 {
 917         struct amdgpu_ring *ring;
 918
 919         spin_lock_init(&adev->gfx.kiq[0].ring_lock);
 920
 921         ring = &adev->gfx.kiq[0].ring;
 922
 923         ring->me = 3;
 924         ring->pipe = 1;
 925         ring->queue = 0;
 926
 927         ring->adev = NULL;
 928         ring->ring_obj = NULL;
 929         ring->use_doorbell = true;
 930         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
 931         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
 932         ring->no_scheduler = true;
 933         sprintf(ring->name, "mes_kiq_%d.%d.%d",
 934                 ring->me, ring->pipe, ring->queue);
 935
 936         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
 937                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
 938 }
 939
 940 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
 941                                  enum admgpu_mes_pipe pipe)
 942 {
 943         int r, mqd_size = sizeof(struct v11_compute_mqd);
 944         struct amdgpu_ring *ring;
 945
 946         if (pipe == AMDGPU_MES_KIQ_PIPE)
 947                 ring = &adev->gfx.kiq[0].ring;
 948         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 949                 ring = &adev->mes.ring;
 950         else
 951                 BUG();
 952
 953         if (ring->mqd_obj)
 954                 return 0;
 955
 956         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 957                                     AMDGPU_GEM_DOMAIN_VRAM |
 958                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
 959                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 960         if (r) {
 961                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 962                 return r;
 963         }
 964
 965         memset(ring->mqd_ptr, 0, mqd_size);
 966
 967         /* prepare MQD backup */
 968         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
 969         if (!adev->mes.mqd_backup[pipe]) {
 970                 dev_warn(adev->dev,
 971                          "no memory to create MQD backup for ring %s\n",
 972                          ring->name);
 973                 return -ENOMEM;
 974         }
 975
 976         return 0;
 977 }
 978
 979 static int mes_v11_0_sw_init(void *handle)
 980 {
 981         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 982         int pipe, r;
 983
 984         adev->mes.funcs = &mes_v11_0_funcs;
 985         adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
 986         adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
 987
 988         r = amdgpu_mes_init(adev);
 989         if (r)
 990                 return r;
 991
 992         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 993                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
 994                         continue;
 995
 996                 r = mes_v11_0_allocate_eop_buf(adev, pipe);
 997                 if (r)
 998                         return r;
 999
1000                 r = mes_v11_0_mqd_sw_init(adev, pipe);
1001                 if (r)
1002                         return r;
1003         }
1004
1005         if (adev->enable_mes_kiq) {
1006                 r = mes_v11_0_kiq_ring_init(adev);
1007                 if (r)
1008                         return r;
1009         }
1010
1011         r = mes_v11_0_ring_init(adev);
1012         if (r)
1013                 return r;
1014
1015         return 0;
1016 }
1017
1018 static int mes_v11_0_sw_fini(void *handle)
1019 {
1020         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1021         int pipe;
1022
1023         amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1024         amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1025
1026         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1027                 kfree(adev->mes.mqd_backup[pipe]);
1028
1029                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1030                                       &adev->mes.eop_gpu_addr[pipe],
1031                                       NULL);
1032                 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1033         }
1034
1035         amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1036                               &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1037                               &adev->gfx.kiq[0].ring.mqd_ptr);
1038
1039         amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1040                               &adev->mes.ring.mqd_gpu_addr,
1041                               &adev->mes.ring.mqd_ptr);
1042
1043         amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1044         amdgpu_ring_fini(&adev->mes.ring);
1045
1046         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1047                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1048                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1049         }
1050
1051         amdgpu_mes_fini(adev);
1052         return 0;
1053 }
1054
1055 static void mes_v11_0_kiq_dequeue(struct amdgpu_ring *ring)
1056 {
1057         uint32_t data;
1058         int i;
1059         struct amdgpu_device *adev = ring->adev;
1060
1061         mutex_lock(&adev->srbm_mutex);
1062         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
1063
1064         /* disable the queue if it's active */
1065         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1066                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1067                 for (i = 0; i < adev->usec_timeout; i++) {
1068                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1069                                 break;
1070                         udelay(1);
1071                 }
1072         }
1073         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1074         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1075                                 DOORBELL_EN, 0);
1076         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1077                                 DOORBELL_HIT, 1);
1078         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1079
1080         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1081
1082         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1083         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1084         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1085
1086         soc21_grbm_select(adev, 0, 0, 0, 0);
1087         mutex_unlock(&adev->srbm_mutex);
1088 }
1089
1090 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1091 {
1092         uint32_t tmp;
1093         struct amdgpu_device *adev = ring->adev;
1094
1095         /* tell RLC which is KIQ queue */
1096         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1097         tmp &= 0xffffff00;
1098         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1099         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1100         tmp |= 0x80;
1101         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1102 }
1103
1104 static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
1105 {
1106         uint32_t tmp;
1107
1108         /* tell RLC which is KIQ dequeue */
1109         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1110         tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
1111         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1112 }
1113
1114 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1115 {
1116         int r = 0;
1117
1118         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1119
1120                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1121                 if (r) {
1122                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1123                         return r;
1124                 }
1125
1126                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1127                 if (r) {
1128                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1129                         return r;
1130                 }
1131
1132         }
1133
1134         mes_v11_0_enable(adev, true);
1135
1136         mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
1137
1138         r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1139         if (r)
1140                 goto failure;
1141
1142         return r;
1143
1144 failure:
1145         mes_v11_0_hw_fini(adev);
1146         return r;
1147 }
1148
1149 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1150 {
1151         if (adev->mes.ring.sched.ready) {
1152                 mes_v11_0_kiq_dequeue(&adev->mes.ring);
1153                 adev->mes.ring.sched.ready = false;
1154         }
1155
1156         if (amdgpu_sriov_vf(adev)) {
1157                 mes_v11_0_kiq_dequeue(&adev->gfx.kiq[0].ring);
1158                 mes_v11_0_kiq_clear(adev);
1159         }
1160
1161         mes_v11_0_enable(adev, false);
1162
1163         return 0;
1164 }
1165
1166 static int mes_v11_0_hw_init(void *handle)
1167 {
1168         int r;
1169         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1170
1171         if (!adev->enable_mes_kiq) {
1172                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1173                         r = mes_v11_0_load_microcode(adev,
1174                                              AMDGPU_MES_SCHED_PIPE, true);
1175                         if (r) {
1176                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1177                                 return r;
1178                         }
1179                 }
1180
1181                 mes_v11_0_enable(adev, true);
1182         }
1183
1184         r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1185         if (r)
1186                 goto failure;
1187
1188         r = mes_v11_0_set_hw_resources(&adev->mes);
1189         if (r)
1190                 goto failure;
1191
1192         r = mes_v11_0_query_sched_status(&adev->mes);
1193         if (r) {
1194                 DRM_ERROR("MES is busy\n");
1195                 goto failure;
1196         }
1197
1198         /*
1199          * Disable KIQ ring usage from the driver once MES is enabled.
1200          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1201          * with MES enabled.
1202          */
1203         adev->gfx.kiq[0].ring.sched.ready = false;
1204         adev->mes.ring.sched.ready = true;
1205
1206         return 0;
1207
1208 failure:
1209         mes_v11_0_hw_fini(adev);
1210         return r;
1211 }
1212
1213 static int mes_v11_0_hw_fini(void *handle)
1214 {
1215         return 0;
1216 }
1217
1218 static int mes_v11_0_suspend(void *handle)
1219 {
1220         int r;
1221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223         r = amdgpu_mes_suspend(adev);
1224         if (r)
1225                 return r;
1226
1227         return mes_v11_0_hw_fini(adev);
1228 }
1229
1230 static int mes_v11_0_resume(void *handle)
1231 {
1232         int r;
1233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234
1235         r = mes_v11_0_hw_init(adev);
1236         if (r)
1237                 return r;
1238
1239         return amdgpu_mes_resume(adev);
1240 }
1241
1242 static int mes_v11_0_early_init(void *handle)
1243 {
1244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1245         int pipe, r;
1246
1247         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1248                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1249                         continue;
1250                 r = amdgpu_mes_init_microcode(adev, pipe);
1251                 if (r)
1252                         return r;
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int mes_v11_0_late_init(void *handle)
1259 {
1260         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1261
1262         /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1263         if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend &&
1264             (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(11, 0, 3)))
1265                 amdgpu_mes_self_test(adev);
1266
1267         return 0;
1268 }
1269
1270 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1271         .name = "mes_v11_0",
1272         .early_init = mes_v11_0_early_init,
1273         .late_init = mes_v11_0_late_init,
1274         .sw_init = mes_v11_0_sw_init,
1275         .sw_fini = mes_v11_0_sw_fini,
1276         .hw_init = mes_v11_0_hw_init,
1277         .hw_fini = mes_v11_0_hw_fini,
1278         .suspend = mes_v11_0_suspend,
1279         .resume = mes_v11_0_resume,
1280 };
1281
1282 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1283         .type = AMD_IP_BLOCK_TYPE_MES,
1284         .major = 11,
1285         .minor = 0,
1286         .rev = 0,
1287         .funcs = &mes_v11_0_ip_funcs,
1288 };