drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <drm/drm_drv.h>
  40 #include "amdgpu.h"
  41 #include "amdgpu_trace.h"
  42 #include "amdgpu_reset.h"
  43
  44 /*
  45  * Fences mark an event in the GPUs pipeline and are used
  46  * for GPU/CPU synchronization.  When the fence is written,
  47  * it is expected that all buffers associated with that fence
  48  * are no longer in use by the associated ring on the GPU and
  49  * that the relevant GPU caches have been flushed.
  50  */
  51
  52 struct amdgpu_fence {
  53         struct dma_fence base;
  54
  55         /* RB, DMA, etc. */
  56         struct amdgpu_ring              *ring;
  57         ktime_t                         start_timestamp;
  58 };
  59
  60 static struct kmem_cache *amdgpu_fence_slab;
  61
  62 int amdgpu_fence_slab_init(void)
  63 {
  64         amdgpu_fence_slab = kmem_cache_create(
  65                 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
  66                 SLAB_HWCACHE_ALIGN, NULL);
  67         if (!amdgpu_fence_slab)
  68                 return -ENOMEM;
  69         return 0;
  70 }
  71
  72 void amdgpu_fence_slab_fini(void)
  73 {
  74         rcu_barrier();
  75         kmem_cache_destroy(amdgpu_fence_slab);
  76 }
  77 /*
  78  * Cast helper
  79  */
  80 static const struct dma_fence_ops amdgpu_fence_ops;
  81 static const struct dma_fence_ops amdgpu_job_fence_ops;
  82 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
  83 {
  84         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  85
  86         if (__f->base.ops == &amdgpu_fence_ops ||
  87             __f->base.ops == &amdgpu_job_fence_ops)
  88                 return __f;
  89
  90         return NULL;
  91 }
  92
  93 /**
  94  * amdgpu_fence_write - write a fence value
  95  *
  96  * @ring: ring the fence is associated with
  97  * @seq: sequence number to write
  98  *
  99  * Writes a fence value to memory (all asics).
 100  */
 101 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
 102 {
 103         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 104
 105         if (drv->cpu_addr)
 106                 *drv->cpu_addr = cpu_to_le32(seq);
 107 }
 108
 109 /**
 110  * amdgpu_fence_read - read a fence value
 111  *
 112  * @ring: ring the fence is associated with
 113  *
 114  * Reads a fence value from memory (all asics).
 115  * Returns the value of the fence read from memory.
 116  */
 117 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
 118 {
 119         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 120         u32 seq = 0;
 121
 122         if (drv->cpu_addr)
 123                 seq = le32_to_cpu(*drv->cpu_addr);
 124         else
 125                 seq = atomic_read(&drv->last_seq);
 126
 127         return seq;
 128 }
 129
 130 /**
 131  * amdgpu_fence_emit - emit a fence on the requested ring
 132  *
 133  * @ring: ring the fence is associated with
 134  * @f: resulting fence object
 135  * @job: job the fence is embedded in
 136  * @flags: flags to pass into the subordinate .emit_fence() call
 137  *
 138  * Emits a fence command on the requested ring (all asics).
 139  * Returns 0 on success, -ENOMEM on failure.
 140  */
 141 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amdgpu_job *job,
 142                       unsigned int flags)
 143 {
 144         struct amdgpu_device *adev = ring->adev;
 145         struct dma_fence *fence;
 146         struct amdgpu_fence *am_fence;
 147         struct dma_fence __rcu **ptr;
 148         uint32_t seq;
 149         int r;
 150
 151         if (job == NULL) {
 152                 /* create a sperate hw fence */
 153                 am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);
 154                 if (am_fence == NULL)
 155                         return -ENOMEM;
 156                 fence = &am_fence->base;
 157                 am_fence->ring = ring;
 158         } else {
 159                 /* take use of job-embedded fence */
 160                 fence = &job->hw_fence;
 161         }
 162
 163         seq = ++ring->fence_drv.sync_seq;
 164         if (job && job->job_run_counter) {
 165                 /* reinit seq for resubmitted jobs */
 166                 fence->seqno = seq;
 167                 /* TO be inline with external fence creation and other drivers */
 168                 dma_fence_get(fence);
 169         } else {
 170                 if (job) {
 171                         dma_fence_init(fence, &amdgpu_job_fence_ops,
 172                                        &ring->fence_drv.lock,
 173                                        adev->fence_context + ring->idx, seq);
 174                         /* Against remove in amdgpu_job_{free, free_cb} */
 175                         dma_fence_get(fence);
 176                 } else {
 177                         dma_fence_init(fence, &amdgpu_fence_ops,
 178                                        &ring->fence_drv.lock,
 179                                        adev->fence_context + ring->idx, seq);
 180                 }
 181         }
 182
 183         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 184                                seq, flags | AMDGPU_FENCE_FLAG_INT);
 185         pm_runtime_get_noresume(adev_to_drm(adev)->dev);
 186         trace_amdgpu_runpm_reference_dumps(1, __func__);
 187         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 188         if (unlikely(rcu_dereference_protected(*ptr, 1))) {
 189                 struct dma_fence *old;
 190
 191                 rcu_read_lock();
 192                 old = dma_fence_get_rcu_safe(ptr);
 193                 rcu_read_unlock();
 194
 195                 if (old) {
 196                         r = dma_fence_wait(old, false);
 197                         dma_fence_put(old);
 198                         if (r)
 199                                 return r;
 200                 }
 201         }
 202
 203         to_amdgpu_fence(fence)->start_timestamp = ktime_get();
 204
 205         /* This function can't be called concurrently anyway, otherwise
 206          * emitting the fence would mess up the hardware ring buffer.
 207          */
 208         rcu_assign_pointer(*ptr, dma_fence_get(fence));
 209
 210         *f = fence;
 211
 212         return 0;
 213 }
 214
 215 /**
 216  * amdgpu_fence_emit_polling - emit a fence on the requeste ring
 217  *
 218  * @ring: ring the fence is associated with
 219  * @s: resulting sequence number
 220  * @timeout: the timeout for waiting in usecs
 221  *
 222  * Emits a fence command on the requested ring (all asics).
 223  * Used For polling fence.
 224  * Returns 0 on success, -ENOMEM on failure.
 225  */
 226 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
 227                               uint32_t timeout)
 228 {
 229         uint32_t seq;
 230         signed long r;
 231
 232         if (!s)
 233                 return -EINVAL;
 234
 235         seq = ++ring->fence_drv.sync_seq;
 236         r = amdgpu_fence_wait_polling(ring,
 237                                       seq - ring->fence_drv.num_fences_mask,
 238                                       timeout);
 239         if (r < 1)
 240                 return -ETIMEDOUT;
 241
 242         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 243                                seq, 0);
 244
 245         *s = seq;
 246
 247         return 0;
 248 }
 249
 250 /**
 251  * amdgpu_fence_schedule_fallback - schedule fallback check
 252  *
 253  * @ring: pointer to struct amdgpu_ring
 254  *
 255  * Start a timer as fallback to our interrupts.
 256  */
 257 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 258 {
 259         mod_timer(&ring->fence_drv.fallback_timer,
 260                   jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
 261 }
 262
 263 /**
 264  * amdgpu_fence_process - check for fence activity
 265  *
 266  * @ring: pointer to struct amdgpu_ring
 267  *
 268  * Checks the current fence value and calculates the last
 269  * signalled fence value. Wakes the fence queue if the
 270  * sequence number has increased.
 271  *
 272  * Returns true if fence was processed
 273  */
 274 bool amdgpu_fence_process(struct amdgpu_ring *ring)
 275 {
 276         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 277         struct amdgpu_device *adev = ring->adev;
 278         uint32_t seq, last_seq;
 279
 280         do {
 281                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 282                 seq = amdgpu_fence_read(ring);
 283
 284         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 285
 286         if (del_timer(&ring->fence_drv.fallback_timer) &&
 287             seq != ring->fence_drv.sync_seq)
 288                 amdgpu_fence_schedule_fallback(ring);
 289
 290         if (unlikely(seq == last_seq))
 291                 return false;
 292
 293         last_seq &= drv->num_fences_mask;
 294         seq &= drv->num_fences_mask;
 295
 296         do {
 297                 struct dma_fence *fence, **ptr;
 298
 299                 ++last_seq;
 300                 last_seq &= drv->num_fences_mask;
 301                 ptr = &drv->fences[last_seq];
 302
 303                 /* There is always exactly one thread signaling this fence slot */
 304                 fence = rcu_dereference_protected(*ptr, 1);
 305                 RCU_INIT_POINTER(*ptr, NULL);
 306
 307                 if (!fence)
 308                         continue;
 309
 310                 dma_fence_signal(fence);
 311                 dma_fence_put(fence);
 312                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 313                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 314                 trace_amdgpu_runpm_reference_dumps(0, __func__);
 315         } while (last_seq != seq);
 316
 317         return true;
 318 }
 319
 320 /**
 321  * amdgpu_fence_fallback - fallback for hardware interrupts
 322  *
 323  * @t: timer context used to obtain the pointer to ring structure
 324  *
 325  * Checks for fence activity.
 326  */
 327 static void amdgpu_fence_fallback(struct timer_list *t)
 328 {
 329         struct amdgpu_ring *ring = from_timer(ring, t,
 330                                               fence_drv.fallback_timer);
 331
 332         if (amdgpu_fence_process(ring))
 333                 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
 334 }
 335
 336 /**
 337  * amdgpu_fence_wait_empty - wait for all fences to signal
 338  *
 339  * @ring: ring index the fence is associated with
 340  *
 341  * Wait for all fences on the requested ring to signal (all asics).
 342  * Returns 0 if the fences have passed, error for all other cases.
 343  */
 344 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 345 {
 346         uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
 347         struct dma_fence *fence, **ptr;
 348         int r;
 349
 350         if (!seq)
 351                 return 0;
 352
 353         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 354         rcu_read_lock();
 355         fence = rcu_dereference(*ptr);
 356         if (!fence || !dma_fence_get_rcu(fence)) {
 357                 rcu_read_unlock();
 358                 return 0;
 359         }
 360         rcu_read_unlock();
 361
 362         r = dma_fence_wait(fence, false);
 363         dma_fence_put(fence);
 364         return r;
 365 }
 366
 367 /**
 368  * amdgpu_fence_wait_polling - busy wait for givn sequence number
 369  *
 370  * @ring: ring index the fence is associated with
 371  * @wait_seq: sequence number to wait
 372  * @timeout: the timeout for waiting in usecs
 373  *
 374  * Wait for all fences on the requested ring to signal (all asics).
 375  * Returns left time if no timeout, 0 or minus if timeout.
 376  */
 377 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 378                                       uint32_t wait_seq,
 379                                       signed long timeout)
 380 {
 381
 382         while ((int32_t)(wait_seq - amdgpu_fence_read(ring)) > 0 && timeout > 0) {
 383                 udelay(2);
 384                 timeout -= 2;
 385         }
 386         return timeout > 0 ? timeout : 0;
 387 }
 388 /**
 389  * amdgpu_fence_count_emitted - get the count of emitted fences
 390  *
 391  * @ring: ring the fence is associated with
 392  *
 393  * Get the number of fences emitted on the requested ring (all asics).
 394  * Returns the number of emitted fences on the ring.  Used by the
 395  * dynpm code to ring track activity.
 396  */
 397 unsigned int amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 398 {
 399         uint64_t emitted;
 400
 401         /* We are not protected by ring lock when reading the last sequence
 402          * but it's ok to report slightly wrong fence count here.
 403          */
 404         emitted = 0x100000000ull;
 405         emitted -= atomic_read(&ring->fence_drv.last_seq);
 406         emitted += READ_ONCE(ring->fence_drv.sync_seq);
 407         return lower_32_bits(emitted);
 408 }
 409
 410 /**
 411  * amdgpu_fence_last_unsignaled_time_us - the time fence emitted until now
 412  * @ring: ring the fence is associated with
 413  *
 414  * Find the earliest fence unsignaled until now, calculate the time delta
 415  * between the time fence emitted and now.
 416  */
 417 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring)
 418 {
 419         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 420         struct dma_fence *fence;
 421         uint32_t last_seq, sync_seq;
 422
 423         last_seq = atomic_read(&ring->fence_drv.last_seq);
 424         sync_seq = READ_ONCE(ring->fence_drv.sync_seq);
 425         if (last_seq == sync_seq)
 426                 return 0;
 427
 428         ++last_seq;
 429         last_seq &= drv->num_fences_mask;
 430         fence = drv->fences[last_seq];
 431         if (!fence)
 432                 return 0;
 433
 434         return ktime_us_delta(ktime_get(),
 435                 to_amdgpu_fence(fence)->start_timestamp);
 436 }
 437
 438 /**
 439  * amdgpu_fence_update_start_timestamp - update the timestamp of the fence
 440  * @ring: ring the fence is associated with
 441  * @seq: the fence seq number to update.
 442  * @timestamp: the start timestamp to update.
 443  *
 444  * The function called at the time the fence and related ib is about to
 445  * resubmit to gpu in MCBP scenario. Thus we do not consider race condition
 446  * with amdgpu_fence_process to modify the same fence.
 447  */
 448 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, ktime_t timestamp)
 449 {
 450         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 451         struct dma_fence *fence;
 452
 453         seq &= drv->num_fences_mask;
 454         fence = drv->fences[seq];
 455         if (!fence)
 456                 return;
 457
 458         to_amdgpu_fence(fence)->start_timestamp = timestamp;
 459 }
 460
 461 /**
 462  * amdgpu_fence_driver_start_ring - make the fence driver
 463  * ready for use on the requested ring.
 464  *
 465  * @ring: ring to start the fence driver on
 466  * @irq_src: interrupt source to use for this ring
 467  * @irq_type: interrupt type to use for this ring
 468  *
 469  * Make the fence driver ready for processing (all asics).
 470  * Not all asics have all rings, so each asic will only
 471  * start the fence driver on the rings it has.
 472  * Returns 0 for success, errors for failure.
 473  */
 474 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 475                                    struct amdgpu_irq_src *irq_src,
 476                                    unsigned int irq_type)
 477 {
 478         struct amdgpu_device *adev = ring->adev;
 479         uint64_t index;
 480
 481         if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
 482                 ring->fence_drv.cpu_addr = ring->fence_cpu_addr;
 483                 ring->fence_drv.gpu_addr = ring->fence_gpu_addr;
 484         } else {
 485                 /* put fence directly behind firmware */
 486                 index = ALIGN(adev->uvd.fw->size, 8);
 487                 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
 488                 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
 489         }
 490         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 491
 492         ring->fence_drv.irq_src = irq_src;
 493         ring->fence_drv.irq_type = irq_type;
 494         ring->fence_drv.initialized = true;
 495
 496         DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",
 497                       ring->name, ring->fence_drv.gpu_addr);
 498         return 0;
 499 }
 500
 501 /**
 502  * amdgpu_fence_driver_init_ring - init the fence driver
 503  * for the requested ring.
 504  *
 505  * @ring: ring to init the fence driver on
 506  *
 507  * Init the fence driver for the requested ring (all asics).
 508  * Helper function for amdgpu_fence_driver_init().
 509  */
 510 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
 511 {
 512         struct amdgpu_device *adev = ring->adev;
 513
 514         if (!adev)
 515                 return -EINVAL;
 516
 517         if (!is_power_of_2(ring->num_hw_submission))
 518                 return -EINVAL;
 519
 520         ring->fence_drv.cpu_addr = NULL;
 521         ring->fence_drv.gpu_addr = 0;
 522         ring->fence_drv.sync_seq = 0;
 523         atomic_set(&ring->fence_drv.last_seq, 0);
 524         ring->fence_drv.initialized = false;
 525
 526         timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
 527
 528         ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1;
 529         spin_lock_init(&ring->fence_drv.lock);
 530         ring->fence_drv.fences = kcalloc(ring->num_hw_submission * 2, sizeof(void *),
 531                                          GFP_KERNEL);
 532
 533         if (!ring->fence_drv.fences)
 534                 return -ENOMEM;
 535
 536         return 0;
 537 }
 538
 539 /**
 540  * amdgpu_fence_driver_sw_init - init the fence driver
 541  * for all possible rings.
 542  *
 543  * @adev: amdgpu device pointer
 544  *
 545  * Init the fence driver for all possible rings (all asics).
 546  * Not all asics have all rings, so each asic will only
 547  * start the fence driver on the rings it has using
 548  * amdgpu_fence_driver_start_ring().
 549  * Returns 0 for success.
 550  */
 551 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
 552 {
 553         return 0;
 554 }
 555
 556 /**
 557  * amdgpu_fence_need_ring_interrupt_restore - helper function to check whether
 558  * fence driver interrupts need to be restored.
 559  *
 560  * @ring: ring that to be checked
 561  *
 562  * Interrupts for rings that belong to GFX IP don't need to be restored
 563  * when the target power state is s0ix.
 564  *
 565  * Return true if need to restore interrupts, false otherwise.
 566  */
 567 static bool amdgpu_fence_need_ring_interrupt_restore(struct amdgpu_ring *ring)
 568 {
 569         struct amdgpu_device *adev = ring->adev;
 570         bool is_gfx_power_domain = false;
 571
 572         switch (ring->funcs->type) {
 573         case AMDGPU_RING_TYPE_SDMA:
 574         /* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
 575                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >=
 576                     IP_VERSION(5, 0, 0))
 577                         is_gfx_power_domain = true;
 578                 break;
 579         case AMDGPU_RING_TYPE_GFX:
 580         case AMDGPU_RING_TYPE_COMPUTE:
 581         case AMDGPU_RING_TYPE_KIQ:
 582         case AMDGPU_RING_TYPE_MES:
 583                 is_gfx_power_domain = true;
 584                 break;
 585         default:
 586                 break;
 587         }
 588
 589         return !(adev->in_s0ix && is_gfx_power_domain);
 590 }
 591
 592 /**
 593  * amdgpu_fence_driver_hw_fini - tear down the fence driver
 594  * for all possible rings.
 595  *
 596  * @adev: amdgpu device pointer
 597  *
 598  * Tear down the fence driver for all possible rings (all asics).
 599  */
 600 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
 601 {
 602         int i, r;
 603
 604         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 605                 struct amdgpu_ring *ring = adev->rings[i];
 606
 607                 if (!ring || !ring->fence_drv.initialized)
 608                         continue;
 609
 610                 /* You can't wait for HW to signal if it's gone */
 611                 if (!drm_dev_is_unplugged(adev_to_drm(adev)))
 612                         r = amdgpu_fence_wait_empty(ring);
 613                 else
 614                         r = -ENODEV;
 615                 /* no need to trigger GPU reset as we are unloading */
 616                 if (r)
 617                         amdgpu_fence_driver_force_completion(ring);
 618
 619                 if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
 620                     ring->fence_drv.irq_src &&
 621                     amdgpu_fence_need_ring_interrupt_restore(ring))
 622                         amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 623                                        ring->fence_drv.irq_type);
 624
 625                 del_timer_sync(&ring->fence_drv.fallback_timer);
 626         }
 627 }
 628
 629 /* Will either stop and flush handlers for amdgpu interrupt or reanble it */
 630 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop)
 631 {
 632         int i;
 633
 634         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 635                 struct amdgpu_ring *ring = adev->rings[i];
 636
 637                 if (!ring || !ring->fence_drv.initialized || !ring->fence_drv.irq_src)
 638                         continue;
 639
 640                 if (stop)
 641                         disable_irq(adev->irq.irq);
 642                 else
 643                         enable_irq(adev->irq.irq);
 644         }
 645 }
 646
 647 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
 648 {
 649         unsigned int i, j;
 650
 651         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 652                 struct amdgpu_ring *ring = adev->rings[i];
 653
 654                 if (!ring || !ring->fence_drv.initialized)
 655                         continue;
 656
 657                 /*
 658                  * Notice we check for sched.ops since there's some
 659                  * override on the meaning of sched.ready by amdgpu.
 660                  * The natural check would be sched.ready, which is
 661                  * set as drm_sched_init() finishes...
 662                  */
 663                 if (ring->sched.ops)
 664                         drm_sched_fini(&ring->sched);
 665
 666                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 667                         dma_fence_put(ring->fence_drv.fences[j]);
 668                 kfree(ring->fence_drv.fences);
 669                 ring->fence_drv.fences = NULL;
 670                 ring->fence_drv.initialized = false;
 671         }
 672 }
 673
 674 /**
 675  * amdgpu_fence_driver_hw_init - enable the fence driver
 676  * for all possible rings.
 677  *
 678  * @adev: amdgpu device pointer
 679  *
 680  * Enable the fence driver for all possible rings (all asics).
 681  * Not all asics have all rings, so each asic will only
 682  * start the fence driver on the rings it has using
 683  * amdgpu_fence_driver_start_ring().
 684  * Returns 0 for success.
 685  */
 686 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
 687 {
 688         int i;
 689
 690         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 691                 struct amdgpu_ring *ring = adev->rings[i];
 692
 693                 if (!ring || !ring->fence_drv.initialized)
 694                         continue;
 695
 696                 /* enable the interrupt */
 697                 if (ring->fence_drv.irq_src &&
 698                     amdgpu_fence_need_ring_interrupt_restore(ring))
 699                         amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 700                                        ring->fence_drv.irq_type);
 701         }
 702 }
 703
 704 /**
 705  * amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring
 706  *
 707  * @ring: fence of the ring to be cleared
 708  *
 709  */
 710 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
 711 {
 712         int i;
 713         struct dma_fence *old, **ptr;
 714
 715         for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
 716                 ptr = &ring->fence_drv.fences[i];
 717                 old = rcu_dereference_protected(*ptr, 1);
 718                 if (old && old->ops == &amdgpu_job_fence_ops) {
 719                         struct amdgpu_job *job;
 720
 721                         /* For non-scheduler bad job, i.e. failed ib test, we need to signal
 722                          * it right here or we won't be able to track them in fence_drv
 723                          * and they will remain unsignaled during sa_bo free.
 724                          */
 725                         job = container_of(old, struct amdgpu_job, hw_fence);
 726                         if (!job->base.s_fence && !dma_fence_is_signaled(old))
 727                                 dma_fence_signal(old);
 728                         RCU_INIT_POINTER(*ptr, NULL);
 729                         dma_fence_put(old);
 730                 }
 731         }
 732 }
 733
 734 /**
 735  * amdgpu_fence_driver_set_error - set error code on fences
 736  * @ring: the ring which contains the fences
 737  * @error: the error code to set
 738  *
 739  * Set an error code to all the fences pending on the ring.
 740  */
 741 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error)
 742 {
 743         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 744         unsigned long flags;
 745
 746         spin_lock_irqsave(&drv->lock, flags);
 747         for (unsigned int i = 0; i <= drv->num_fences_mask; ++i) {
 748                 struct dma_fence *fence;
 749
 750                 fence = rcu_dereference_protected(drv->fences[i],
 751                                                   lockdep_is_held(&drv->lock));
 752                 if (fence && !dma_fence_is_signaled_locked(fence))
 753                         dma_fence_set_error(fence, error);
 754         }
 755         spin_unlock_irqrestore(&drv->lock, flags);
 756 }
 757
 758 /**
 759  * amdgpu_fence_driver_force_completion - force signal latest fence of ring
 760  *
 761  * @ring: fence of the ring to signal
 762  *
 763  */
 764 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
 765 {
 766         amdgpu_fence_driver_set_error(ring, -ECANCELED);
 767         amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 768         amdgpu_fence_process(ring);
 769 }
 770
 771 /*
 772  * Common fence implementation
 773  */
 774
 775 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
 776 {
 777         return "amdgpu";
 778 }
 779
 780 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 781 {
 782         return (const char *)to_amdgpu_fence(f)->ring->name;
 783 }
 784
 785 static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
 786 {
 787         struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
 788
 789         return (const char *)to_amdgpu_ring(job->base.sched)->name;
 790 }
 791
 792 /**
 793  * amdgpu_fence_enable_signaling - enable signalling on fence
 794  * @f: fence
 795  *
 796  * This function is called with fence_queue lock held, and adds a callback
 797  * to fence_queue that checks if this fence is signaled, and if so it
 798  * signals the fence and removes itself.
 799  */
 800 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
 801 {
 802         if (!timer_pending(&to_amdgpu_fence(f)->ring->fence_drv.fallback_timer))
 803                 amdgpu_fence_schedule_fallback(to_amdgpu_fence(f)->ring);
 804
 805         return true;
 806 }
 807
 808 /**
 809  * amdgpu_job_fence_enable_signaling - enable signalling on job fence
 810  * @f: fence
 811  *
 812  * This is the simliar function with amdgpu_fence_enable_signaling above, it
 813  * only handles the job embedded fence.
 814  */
 815 static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
 816 {
 817         struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
 818
 819         if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
 820                 amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
 821
 822         return true;
 823 }
 824
 825 /**
 826  * amdgpu_fence_free - free up the fence memory
 827  *
 828  * @rcu: RCU callback head
 829  *
 830  * Free up the fence memory after the RCU grace period.
 831  */
 832 static void amdgpu_fence_free(struct rcu_head *rcu)
 833 {
 834         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 835
 836         /* free fence_slab if it's separated fence*/
 837         kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));
 838 }
 839
 840 /**
 841  * amdgpu_job_fence_free - free up the job with embedded fence
 842  *
 843  * @rcu: RCU callback head
 844  *
 845  * Free up the job with embedded fence after the RCU grace period.
 846  */
 847 static void amdgpu_job_fence_free(struct rcu_head *rcu)
 848 {
 849         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 850
 851         /* free job if fence has a parent job */
 852         kfree(container_of(f, struct amdgpu_job, hw_fence));
 853 }
 854
 855 /**
 856  * amdgpu_fence_release - callback that fence can be freed
 857  *
 858  * @f: fence
 859  *
 860  * This function is called when the reference count becomes zero.
 861  * It just RCU schedules freeing up the fence.
 862  */
 863 static void amdgpu_fence_release(struct dma_fence *f)
 864 {
 865         call_rcu(&f->rcu, amdgpu_fence_free);
 866 }
 867
 868 /**
 869  * amdgpu_job_fence_release - callback that job embedded fence can be freed
 870  *
 871  * @f: fence
 872  *
 873  * This is the simliar function with amdgpu_fence_release above, it
 874  * only handles the job embedded fence.
 875  */
 876 static void amdgpu_job_fence_release(struct dma_fence *f)
 877 {
 878         call_rcu(&f->rcu, amdgpu_job_fence_free);
 879 }
 880
 881 static const struct dma_fence_ops amdgpu_fence_ops = {
 882         .get_driver_name = amdgpu_fence_get_driver_name,
 883         .get_timeline_name = amdgpu_fence_get_timeline_name,
 884         .enable_signaling = amdgpu_fence_enable_signaling,
 885         .release = amdgpu_fence_release,
 886 };
 887
 888 static const struct dma_fence_ops amdgpu_job_fence_ops = {
 889         .get_driver_name = amdgpu_fence_get_driver_name,
 890         .get_timeline_name = amdgpu_job_fence_get_timeline_name,
 891         .enable_signaling = amdgpu_job_fence_enable_signaling,
 892         .release = amdgpu_job_fence_release,
 893 };
 894
 895 /*
 896  * Fence debugfs
 897  */
 898 #if defined(CONFIG_DEBUG_FS)
 899 static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused)
 900 {
 901         struct amdgpu_device *adev = m->private;
 902         int i;
 903
 904         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 905                 struct amdgpu_ring *ring = adev->rings[i];
 906
 907                 if (!ring || !ring->fence_drv.initialized)
 908                         continue;
 909
 910                 amdgpu_fence_process(ring);
 911
 912                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 913                 seq_printf(m, "Last signaled fence          0x%08x\n",
 914                            atomic_read(&ring->fence_drv.last_seq));
 915                 seq_printf(m, "Last emitted                 0x%08x\n",
 916                            ring->fence_drv.sync_seq);
 917
 918                 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
 919                     ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
 920                         seq_printf(m, "Last signaled trailing fence 0x%08x\n",
 921                                    le32_to_cpu(*ring->trail_fence_cpu_addr));
 922                         seq_printf(m, "Last emitted                 0x%08x\n",
 923                                    ring->trail_seq);
 924                 }
 925
 926                 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
 927                         continue;
 928
 929                 /* set in CP_VMID_PREEMPT and preemption occurred */
 930                 seq_printf(m, "Last preempted               0x%08x\n",
 931                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
 932                 /* set in CP_VMID_RESET and reset occurred */
 933                 seq_printf(m, "Last reset                   0x%08x\n",
 934                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
 935                 /* Both preemption and reset occurred */
 936                 seq_printf(m, "Last both                    0x%08x\n",
 937                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
 938         }
 939         return 0;
 940 }
 941
 942 /*
 943  * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
 944  *
 945  * Manually trigger a gpu reset at the next fence wait.
 946  */
 947 static int gpu_recover_get(void *data, u64 *val)
 948 {
 949         struct amdgpu_device *adev = (struct amdgpu_device *)data;
 950         struct drm_device *dev = adev_to_drm(adev);
 951         int r;
 952
 953         r = pm_runtime_get_sync(dev->dev);
 954         if (r < 0) {
 955                 pm_runtime_put_autosuspend(dev->dev);
 956                 return 0;
 957         }
 958
 959         if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work))
 960                 flush_work(&adev->reset_work);
 961
 962         *val = atomic_read(&adev->reset_domain->reset_res);
 963
 964         pm_runtime_mark_last_busy(dev->dev);
 965         pm_runtime_put_autosuspend(dev->dev);
 966
 967         return 0;
 968 }
 969
 970 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
 971 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
 972                          "%lld\n");
 973
 974 static void amdgpu_debugfs_reset_work(struct work_struct *work)
 975 {
 976         struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
 977                                                   reset_work);
 978
 979         struct amdgpu_reset_context reset_context;
 980
 981         memset(&reset_context, 0, sizeof(reset_context));
 982
 983         reset_context.method = AMD_RESET_METHOD_NONE;
 984         reset_context.reset_req_dev = adev;
 985         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
 986
 987         amdgpu_device_gpu_recover(adev, NULL, &reset_context);
 988 }
 989
 990 #endif
 991
 992 void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 993 {
 994 #if defined(CONFIG_DEBUG_FS)
 995         struct drm_minor *minor = adev_to_drm(adev)->primary;
 996         struct dentry *root = minor->debugfs_root;
 997
 998         debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
 999                             &amdgpu_debugfs_fence_info_fops);
1000
1001         if (!amdgpu_sriov_vf(adev)) {
1002
1003                 INIT_WORK(&adev->reset_work, amdgpu_debugfs_reset_work);
1004                 debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
1005                                     &amdgpu_debugfs_gpu_recover_fops);
1006         }
1007 #endif
1008 }
1009