drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31
  32 /* delay 0.1 second to enable gfx off feature */
  33 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  34
  35 #define GFX_OFF_NO_DELAY 0
  36
  37 /*
  38  * GPU GFX IP block helpers function.
  39  */
  40
  41 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  42                                 int pipe, int queue)
  43 {
  44         int bit = 0;
  45
  46         bit += mec * adev->gfx.mec.num_pipe_per_mec
  47                 * adev->gfx.mec.num_queue_per_pipe;
  48         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  49         bit += queue;
  50
  51         return bit;
  52 }
  53
  54 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  55                                  int *mec, int *pipe, int *queue)
  56 {
  57         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  58         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  59                 % adev->gfx.mec.num_pipe_per_mec;
  60         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  61                / adev->gfx.mec.num_pipe_per_mec;
  62
  63 }
  64
  65 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  66                                      int xcc_id, int mec, int pipe, int queue)
  67 {
  68         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  69                         adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
  70 }
  71
  72 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  73                                int me, int pipe, int queue)
  74 {
  75         int bit = 0;
  76
  77         bit += me * adev->gfx.me.num_pipe_per_me
  78                 * adev->gfx.me.num_queue_per_pipe;
  79         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  80         bit += queue;
  81
  82         return bit;
  83 }
  84
  85 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  86                                 int *me, int *pipe, int *queue)
  87 {
  88         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  89         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  90                 % adev->gfx.me.num_pipe_per_me;
  91         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  92                 / adev->gfx.me.num_pipe_per_me;
  93 }
  94
  95 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  96                                     int me, int pipe, int queue)
  97 {
  98         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
  99                         adev->gfx.me.queue_bitmap);
 100 }
 101
 102 /**
 103  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 104  *
 105  * @mask: array in which the per-shader array disable masks will be stored
 106  * @max_se: number of SEs
 107  * @max_sh: number of SHs
 108  *
 109  * The bitmask of CUs to be disabled in the shader array determined by se and
 110  * sh is stored in mask[se * max_sh + sh].
 111  */
 112 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 113 {
 114         unsigned se, sh, cu;
 115         const char *p;
 116
 117         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 118
 119         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 120                 return;
 121
 122         p = amdgpu_disable_cu;
 123         for (;;) {
 124                 char *next;
 125                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 126                 if (ret < 3) {
 127                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 128                         return;
 129                 }
 130
 131                 if (se < max_se && sh < max_sh && cu < 16) {
 132                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 133                         mask[se * max_sh + sh] |= 1u << cu;
 134                 } else {
 135                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 136                                   se, sh, cu);
 137                 }
 138
 139                 next = strchr(p, ',');
 140                 if (!next)
 141                         break;
 142                 p = next + 1;
 143         }
 144 }
 145
 146 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 147 {
 148         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 149 }
 150
 151 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 152 {
 153         if (amdgpu_compute_multipipe != -1) {
 154                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 155                          amdgpu_compute_multipipe);
 156                 return amdgpu_compute_multipipe == 1;
 157         }
 158
 159         if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
 160                 return true;
 161
 162         /* FIXME: spreading the queues across pipes causes perf regressions
 163          * on POLARIS11 compute workloads */
 164         if (adev->asic_type == CHIP_POLARIS11)
 165                 return false;
 166
 167         return adev->gfx.mec.num_mec > 1;
 168 }
 169
 170 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 171                                                 struct amdgpu_ring *ring)
 172 {
 173         int queue = ring->queue;
 174         int pipe = ring->pipe;
 175
 176         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 177          * have more than one gfx pipe.
 178          */
 179         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 180             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 181                 int me = ring->me;
 182                 int bit;
 183
 184                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 185                 if (ring == &adev->gfx.gfx_ring[bit])
 186                         return true;
 187         }
 188
 189         return false;
 190 }
 191
 192 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 193                                                struct amdgpu_ring *ring)
 194 {
 195         /* Policy: use 1st queue as high priority compute queue if we
 196          * have more than one compute queue.
 197          */
 198         if (adev->gfx.num_compute_rings > 1 &&
 199             ring == &adev->gfx.compute_ring[0])
 200                 return true;
 201
 202         return false;
 203 }
 204
 205 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 206 {
 207         int i, j, queue, pipe;
 208         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 209         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 210                                      adev->gfx.mec.num_queue_per_pipe,
 211                                      adev->gfx.num_compute_rings);
 212         int num_xcd = (adev->gfx.num_xcd > 1) ? adev->gfx.num_xcd : 1;
 213
 214         if (multipipe_policy) {
 215                 /* policy: make queues evenly cross all pipes on MEC1 only
 216                  * for multiple xcc, just use the original policy for simplicity */
 217                 for (j = 0; j < num_xcd; j++) {
 218                         for (i = 0; i < max_queues_per_mec; i++) {
 219                                 pipe = i % adev->gfx.mec.num_pipe_per_mec;
 220                                 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 221                                          adev->gfx.mec.num_queue_per_pipe;
 222
 223                                 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 224                                         adev->gfx.mec_bitmap[j].queue_bitmap);
 225                         }
 226                 }
 227         } else {
 228                 /* policy: amdgpu owns all queues in the given pipe */
 229                 for (j = 0; j < num_xcd; j++) {
 230                         for (i = 0; i < max_queues_per_mec; ++i)
 231                                 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
 232                 }
 233         }
 234
 235         for (j = 0; j < num_xcd; j++) {
 236                 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
 237                         bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 238         }
 239 }
 240
 241 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 242 {
 243         int i, queue, pipe;
 244         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 245         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 246                                         adev->gfx.me.num_queue_per_pipe;
 247
 248         if (multipipe_policy) {
 249                 /* policy: amdgpu owns the first queue per pipe at this stage
 250                  * will extend to mulitple queues per pipe later */
 251                 for (i = 0; i < max_queues_per_me; i++) {
 252                         pipe = i % adev->gfx.me.num_pipe_per_me;
 253                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 254                                 adev->gfx.me.num_queue_per_pipe;
 255
 256                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 257                                 adev->gfx.me.queue_bitmap);
 258                 }
 259         } else {
 260                 for (i = 0; i < max_queues_per_me; ++i)
 261                         set_bit(i, adev->gfx.me.queue_bitmap);
 262         }
 263
 264         /* update the number of active graphics rings */
 265         adev->gfx.num_gfx_rings =
 266                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 267 }
 268
 269 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 270                                   struct amdgpu_ring *ring, int xcc_id)
 271 {
 272         int queue_bit;
 273         int mec, pipe, queue;
 274
 275         queue_bit = adev->gfx.mec.num_mec
 276                     * adev->gfx.mec.num_pipe_per_mec
 277                     * adev->gfx.mec.num_queue_per_pipe;
 278
 279         while (--queue_bit >= 0) {
 280                 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 281                         continue;
 282
 283                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 284
 285                 /*
 286                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 287                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 288                  * only can be issued on queue 0.
 289                  */
 290                 if ((mec == 1 && pipe > 1) || queue != 0)
 291                         continue;
 292
 293                 ring->me = mec + 1;
 294                 ring->pipe = pipe;
 295                 ring->queue = queue;
 296
 297                 return 0;
 298         }
 299
 300         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 301         return -EINVAL;
 302 }
 303
 304 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 305                              struct amdgpu_ring *ring,
 306                              struct amdgpu_irq_src *irq, int xcc_id)
 307 {
 308         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 309         int r = 0;
 310
 311         spin_lock_init(&kiq->ring_lock);
 312
 313         ring->adev = NULL;
 314         ring->ring_obj = NULL;
 315         ring->use_doorbell = true;
 316         ring->doorbell_index = adev->doorbell_index.kiq;
 317         ring->xcc_id = xcc_id;
 318         ring->vm_hub = AMDGPU_GFXHUB_0;
 319         if (xcc_id >= 1)
 320                 ring->doorbell_index = adev->doorbell_index.xcc1_kiq_start +
 321                                         xcc_id - 1;
 322         else
 323                 ring->doorbell_index = adev->doorbell_index.kiq;
 324
 325         r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id);
 326         if (r)
 327                 return r;
 328
 329         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 330         ring->no_scheduler = true;
 331         sprintf(ring->name, "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue);
 332         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 333                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 334         if (r)
 335                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 336
 337         return r;
 338 }
 339
 340 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 341 {
 342         amdgpu_ring_fini(ring);
 343 }
 344
 345 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id)
 346 {
 347         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 348
 349         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 350 }
 351
 352 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 353                         unsigned hpd_size, int xcc_id)
 354 {
 355         int r;
 356         u32 *hpd;
 357         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 358
 359         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 360                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 361                                     &kiq->eop_gpu_addr, (void **)&hpd);
 362         if (r) {
 363                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 364                 return r;
 365         }
 366
 367         memset(hpd, 0, hpd_size);
 368
 369         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 370         if (unlikely(r != 0))
 371                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 372         amdgpu_bo_kunmap(kiq->eop_obj);
 373         amdgpu_bo_unreserve(kiq->eop_obj);
 374
 375         return 0;
 376 }
 377
 378 /* create MQD for each compute/gfx queue */
 379 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 380                            unsigned mqd_size, int xcc_id)
 381 {
 382         int r, i, j;
 383         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 384         struct amdgpu_ring *ring = &kiq->ring;
 385         u32 domain = AMDGPU_GEM_DOMAIN_GTT;
 386
 387         /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
 388         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
 389                 domain |= AMDGPU_GEM_DOMAIN_VRAM;
 390
 391         /* create MQD for KIQ */
 392         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 393                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 394                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 395                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 396                  * KIQ MQD no matter SRIOV or Bare-metal
 397                  */
 398                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 399                                             AMDGPU_GEM_DOMAIN_VRAM |
 400                                             AMDGPU_GEM_DOMAIN_GTT,
 401                                             &ring->mqd_obj,
 402                                             &ring->mqd_gpu_addr,
 403                                             &ring->mqd_ptr);
 404                 if (r) {
 405                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 406                         return r;
 407                 }
 408
 409                 /* prepare MQD backup */
 410                 kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
 411                 if (!kiq->mqd_backup)
 412                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 413         }
 414
 415         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 416                 /* create MQD for each KGQ */
 417                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 418                         ring = &adev->gfx.gfx_ring[i];
 419                         if (!ring->mqd_obj) {
 420                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 421                                                             domain, &ring->mqd_obj,
 422                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 423                                 if (r) {
 424                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 425                                         return r;
 426                                 }
 427
 428                                 ring->mqd_size = mqd_size;
 429                                 /* prepare MQD backup */
 430                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 431                                 if (!adev->gfx.me.mqd_backup[i])
 432                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 433                         }
 434                 }
 435         }
 436
 437         /* create MQD for each KCQ */
 438         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 439                 j = i + xcc_id * adev->gfx.num_compute_rings;
 440                 ring = &adev->gfx.compute_ring[j];
 441                 if (!ring->mqd_obj) {
 442                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 443                                                     domain, &ring->mqd_obj,
 444                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 445                         if (r) {
 446                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 447                                 return r;
 448                         }
 449
 450                         ring->mqd_size = mqd_size;
 451                         /* prepare MQD backup */
 452                         adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL);
 453                         if (!adev->gfx.mec.mqd_backup[j])
 454                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 455                 }
 456         }
 457
 458         return 0;
 459 }
 460
 461 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id)
 462 {
 463         struct amdgpu_ring *ring = NULL;
 464         int i, j;
 465         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 466
 467         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 468                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 469                         ring = &adev->gfx.gfx_ring[i];
 470                         kfree(adev->gfx.me.mqd_backup[i]);
 471                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 472                                               &ring->mqd_gpu_addr,
 473                                               &ring->mqd_ptr);
 474                 }
 475         }
 476
 477         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 478                 j = i + xcc_id * adev->gfx.num_compute_rings;
 479                 ring = &adev->gfx.compute_ring[j];
 480                 kfree(adev->gfx.mec.mqd_backup[j]);
 481                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 482                                       &ring->mqd_gpu_addr,
 483                                       &ring->mqd_ptr);
 484         }
 485
 486         ring = &kiq->ring;
 487         kfree(kiq->mqd_backup);
 488         kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
 489         amdgpu_bo_free_kernel(&ring->mqd_obj,
 490                               &ring->mqd_gpu_addr,
 491                               &ring->mqd_ptr);
 492 }
 493
 494 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
 495 {
 496         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 497         struct amdgpu_ring *kiq_ring = &kiq->ring;
 498         int i, r = 0;
 499         int j;
 500
 501         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 502                 return -EINVAL;
 503
 504         spin_lock(&kiq->ring_lock);
 505         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 506                 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 507                                                 adev->gfx.num_compute_rings)) {
 508                         spin_unlock(&kiq->ring_lock);
 509                         return -ENOMEM;
 510                 }
 511
 512                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 513                         j = i + xcc_id * adev->gfx.num_compute_rings;
 514                         kiq->pmf->kiq_unmap_queues(kiq_ring,
 515                                                    &adev->gfx.compute_ring[i],
 516                                                    RESET_QUEUES, 0, 0);
 517                 }
 518         }
 519
 520         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 521                 r = amdgpu_ring_test_helper(kiq_ring);
 522         spin_unlock(&kiq->ring_lock);
 523
 524         return r;
 525 }
 526
 527 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
 528 {
 529         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 530         struct amdgpu_ring *kiq_ring = &kiq->ring;
 531         int i, r = 0;
 532         int j;
 533
 534         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 535                 return -EINVAL;
 536
 537         spin_lock(&kiq->ring_lock);
 538         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 539                 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 540                                                 adev->gfx.num_gfx_rings)) {
 541                         spin_unlock(&kiq->ring_lock);
 542                         return -ENOMEM;
 543                 }
 544
 545                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 546                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 547                         kiq->pmf->kiq_unmap_queues(kiq_ring,
 548                                                    &adev->gfx.gfx_ring[i],
 549                                                    PREEMPT_QUEUES, 0, 0);
 550                 }
 551         }
 552
 553         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 554                 r = amdgpu_ring_test_helper(kiq_ring);
 555         spin_unlock(&kiq->ring_lock);
 556
 557         return r;
 558 }
 559
 560 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 561                                         int queue_bit)
 562 {
 563         int mec, pipe, queue;
 564         int set_resource_bit = 0;
 565
 566         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 567
 568         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 569
 570         return set_resource_bit;
 571 }
 572
 573 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 574 {
 575         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 576         struct amdgpu_ring *kiq_ring = &kiq->ring;
 577         uint64_t queue_mask = 0;
 578         int r, i, j;
 579
 580         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 581                 return -EINVAL;
 582
 583         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 584                 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 585                         continue;
 586
 587                 /* This situation may be hit in the future if a new HW
 588                  * generation exposes more than 64 queues. If so, the
 589                  * definition of queue_mask needs updating */
 590                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 591                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 592                         break;
 593                 }
 594
 595                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 596         }
 597
 598         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 599                                                         kiq_ring->queue);
 600         spin_lock(&kiq->ring_lock);
 601         /* No need to map kcq on the slave */
 602         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 603                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 604                                                 adev->gfx.num_compute_rings +
 605                                                 kiq->pmf->set_resources_size);
 606                 if (r) {
 607                         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 608                         spin_unlock(&kiq->ring_lock);
 609                         return r;
 610                 }
 611
 612                 if (adev->enable_mes)
 613                         queue_mask = ~0ULL;
 614
 615                 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 616                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 617                         j = i + xcc_id * adev->gfx.num_compute_rings;
 618                         kiq->pmf->kiq_map_queues(kiq_ring,
 619                                                  &adev->gfx.compute_ring[i]);
 620                 }
 621         }
 622
 623         r = amdgpu_ring_test_helper(kiq_ring);
 624         spin_unlock(&kiq->ring_lock);
 625         if (r)
 626                 DRM_ERROR("KCQ enable failed\n");
 627
 628         return r;
 629 }
 630
 631 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
 632 {
 633         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 634         struct amdgpu_ring *kiq_ring = &kiq->ring;
 635         int r, i, j;
 636
 637         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 638                 return -EINVAL;
 639
 640         spin_lock(&kiq->ring_lock);
 641         /* No need to map kcq on the slave */
 642         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 643                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 644                                                 adev->gfx.num_gfx_rings);
 645                 if (r) {
 646                         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 647                         spin_unlock(&adev->gfx.kiq[0].ring_lock);
 648                         return r;
 649                 }
 650
 651                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 652                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 653                         kiq->pmf->kiq_map_queues(kiq_ring,
 654                                                  &adev->gfx.gfx_ring[i]);
 655                 }
 656         }
 657
 658         r = amdgpu_ring_test_helper(kiq_ring);
 659         spin_unlock(&kiq->ring_lock);
 660         if (r)
 661                 DRM_ERROR("KCQ enable failed\n");
 662
 663         return r;
 664 }
 665
 666 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 667  *
 668  * @adev: amdgpu_device pointer
 669  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 670  *
 671  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 672  * 2. other client can send request to disable gfx off feature, the request should be honored.
 673  * 3. other client can cancel their request of disable gfx off feature
 674  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 675  */
 676
 677 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 678 {
 679         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 680
 681         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 682                 return;
 683
 684         mutex_lock(&adev->gfx.gfx_off_mutex);
 685
 686         if (enable) {
 687                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 688                  * Note that the bug may be in a different caller than the one which triggers the
 689                  * WARN_ON_ONCE.
 690                  */
 691                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 692                         goto unlock;
 693
 694                 adev->gfx.gfx_off_req_count--;
 695
 696                 if (adev->gfx.gfx_off_req_count == 0 &&
 697                     !adev->gfx.gfx_off_state) {
 698                         /* If going to s2idle, no need to wait */
 699                         if (adev->in_s0ix) {
 700                                 if (!amdgpu_dpm_set_powergating_by_smu(adev,
 701                                                 AMD_IP_BLOCK_TYPE_GFX, true))
 702                                         adev->gfx.gfx_off_state = true;
 703                         } else {
 704                                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 705                                               delay);
 706                         }
 707                 }
 708         } else {
 709                 if (adev->gfx.gfx_off_req_count == 0) {
 710                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 711
 712                         if (adev->gfx.gfx_off_state &&
 713                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 714                                 adev->gfx.gfx_off_state = false;
 715
 716                                 if (adev->gfx.funcs->init_spm_golden) {
 717                                         dev_dbg(adev->dev,
 718                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 719                                         amdgpu_gfx_init_spm_golden(adev);
 720                                 }
 721                         }
 722                 }
 723
 724                 adev->gfx.gfx_off_req_count++;
 725         }
 726
 727 unlock:
 728         mutex_unlock(&adev->gfx.gfx_off_mutex);
 729 }
 730
 731 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 732 {
 733         int r = 0;
 734
 735         mutex_lock(&adev->gfx.gfx_off_mutex);
 736
 737         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 738
 739         mutex_unlock(&adev->gfx.gfx_off_mutex);
 740
 741         return r;
 742 }
 743
 744 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 745 {
 746         int r = 0;
 747
 748         mutex_lock(&adev->gfx.gfx_off_mutex);
 749
 750         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 751
 752         mutex_unlock(&adev->gfx.gfx_off_mutex);
 753
 754         return r;
 755 }
 756
 757 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 758 {
 759         int r = 0;
 760
 761         mutex_lock(&adev->gfx.gfx_off_mutex);
 762
 763         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 764
 765         mutex_unlock(&adev->gfx.gfx_off_mutex);
 766
 767         return r;
 768 }
 769
 770 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 771 {
 772
 773         int r = 0;
 774
 775         mutex_lock(&adev->gfx.gfx_off_mutex);
 776
 777         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 778
 779         mutex_unlock(&adev->gfx.gfx_off_mutex);
 780
 781         return r;
 782 }
 783
 784 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 785 {
 786         int r;
 787
 788         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 789                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 790                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 791
 792                 r = amdgpu_ras_block_late_init(adev, ras_block);
 793                 if (r)
 794                         return r;
 795
 796                 if (adev->gfx.cp_ecc_error_irq.funcs) {
 797                         r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 798                         if (r)
 799                                 goto late_fini;
 800                 }
 801         } else {
 802                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 803         }
 804
 805         return 0;
 806 late_fini:
 807         amdgpu_ras_block_late_fini(adev, ras_block);
 808         return r;
 809 }
 810
 811 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 812 {
 813         int err = 0;
 814         struct amdgpu_gfx_ras *ras = NULL;
 815
 816         /* adev->gfx.ras is NULL, which means gfx does not
 817          * support ras function, then do nothing here.
 818          */
 819         if (!adev->gfx.ras)
 820                 return 0;
 821
 822         ras = adev->gfx.ras;
 823
 824         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 825         if (err) {
 826                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 827                 return err;
 828         }
 829
 830         strcpy(ras->ras_block.ras_comm.name, "gfx");
 831         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 832         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 833         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 834
 835         /* If not define special ras_late_init function, use gfx default ras_late_init */
 836         if (!ras->ras_block.ras_late_init)
 837                 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
 838
 839         /* If not defined special ras_cb function, use default ras_cb */
 840         if (!ras->ras_block.ras_cb)
 841                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 842
 843         return 0;
 844 }
 845
 846 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 847                                                 struct amdgpu_iv_entry *entry)
 848 {
 849         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 850                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 851
 852         return 0;
 853 }
 854
 855 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 856                 void *err_data,
 857                 struct amdgpu_iv_entry *entry)
 858 {
 859         /* TODO ue will trigger an interrupt.
 860          *
 861          * When “Full RAS” is enabled, the per-IP interrupt sources should
 862          * be disabled and the driver should only look for the aggregated
 863          * interrupt via sync flood
 864          */
 865         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 866                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 867                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 868                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 869                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 870                 amdgpu_ras_reset_gpu(adev);
 871         }
 872         return AMDGPU_RAS_SUCCESS;
 873 }
 874
 875 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 876                                   struct amdgpu_irq_src *source,
 877                                   struct amdgpu_iv_entry *entry)
 878 {
 879         struct ras_common_if *ras_if = adev->gfx.ras_if;
 880         struct ras_dispatch_if ih_data = {
 881                 .entry = entry,
 882         };
 883
 884         if (!ras_if)
 885                 return 0;
 886
 887         ih_data.head = *ras_if;
 888
 889         DRM_ERROR("CP ECC ERROR IRQ\n");
 890         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 891         return 0;
 892 }
 893
 894 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 895 {
 896         signed long r, cnt = 0;
 897         unsigned long flags;
 898         uint32_t seq, reg_val_offs = 0, value = 0;
 899         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 900         struct amdgpu_ring *ring = &kiq->ring;
 901
 902         if (amdgpu_device_skip_hw_access(adev))
 903                 return 0;
 904
 905         if (adev->mes.ring.sched.ready)
 906                 return amdgpu_mes_rreg(adev, reg);
 907
 908         BUG_ON(!ring->funcs->emit_rreg);
 909
 910         spin_lock_irqsave(&kiq->ring_lock, flags);
 911         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 912                 pr_err("critical bug! too many kiq readers\n");
 913                 goto failed_unlock;
 914         }
 915         amdgpu_ring_alloc(ring, 32);
 916         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 917         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 918         if (r)
 919                 goto failed_undo;
 920
 921         amdgpu_ring_commit(ring);
 922         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 923
 924         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 925
 926         /* don't wait anymore for gpu reset case because this way may
 927          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 928          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 929          * never return if we keep waiting in virt_kiq_rreg, which cause
 930          * gpu_recover() hang there.
 931          *
 932          * also don't wait anymore for IRQ context
 933          * */
 934         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 935                 goto failed_kiq_read;
 936
 937         might_sleep();
 938         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 939                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 940                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 941         }
 942
 943         if (cnt > MAX_KIQ_REG_TRY)
 944                 goto failed_kiq_read;
 945
 946         mb();
 947         value = adev->wb.wb[reg_val_offs];
 948         amdgpu_device_wb_free(adev, reg_val_offs);
 949         return value;
 950
 951 failed_undo:
 952         amdgpu_ring_undo(ring);
 953 failed_unlock:
 954         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 955 failed_kiq_read:
 956         if (reg_val_offs)
 957                 amdgpu_device_wb_free(adev, reg_val_offs);
 958         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 959         return ~0;
 960 }
 961
 962 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 963 {
 964         signed long r, cnt = 0;
 965         unsigned long flags;
 966         uint32_t seq;
 967         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 968         struct amdgpu_ring *ring = &kiq->ring;
 969
 970         BUG_ON(!ring->funcs->emit_wreg);
 971
 972         if (amdgpu_device_skip_hw_access(adev))
 973                 return;
 974
 975         if (adev->mes.ring.sched.ready) {
 976                 amdgpu_mes_wreg(adev, reg, v);
 977                 return;
 978         }
 979
 980         spin_lock_irqsave(&kiq->ring_lock, flags);
 981         amdgpu_ring_alloc(ring, 32);
 982         amdgpu_ring_emit_wreg(ring, reg, v);
 983         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 984         if (r)
 985                 goto failed_undo;
 986
 987         amdgpu_ring_commit(ring);
 988         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 989
 990         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 991
 992         /* don't wait anymore for gpu reset case because this way may
 993          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 994          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 995          * never return if we keep waiting in virt_kiq_rreg, which cause
 996          * gpu_recover() hang there.
 997          *
 998          * also don't wait anymore for IRQ context
 999          * */
1000         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
1001                 goto failed_kiq_write;
1002
1003         might_sleep();
1004         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
1005
1006                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
1007                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1008         }
1009
1010         if (cnt > MAX_KIQ_REG_TRY)
1011                 goto failed_kiq_write;
1012
1013         return;
1014
1015 failed_undo:
1016         amdgpu_ring_undo(ring);
1017         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1018 failed_kiq_write:
1019         dev_err(adev->dev, "failed to write reg:%x\n", reg);
1020 }
1021
1022 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
1023 {
1024         if (amdgpu_num_kcq == -1) {
1025                 return 8;
1026         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
1027                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
1028                 return 8;
1029         }
1030         return amdgpu_num_kcq;
1031 }
1032
1033 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
1034                                   uint32_t ucode_id)
1035 {
1036         const struct gfx_firmware_header_v1_0 *cp_hdr;
1037         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
1038         struct amdgpu_firmware_info *info = NULL;
1039         const struct firmware *ucode_fw;
1040         unsigned int fw_size;
1041
1042         switch (ucode_id) {
1043         case AMDGPU_UCODE_ID_CP_PFP:
1044                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1045                         adev->gfx.pfp_fw->data;
1046                 adev->gfx.pfp_fw_version =
1047                         le32_to_cpu(cp_hdr->header.ucode_version);
1048                 adev->gfx.pfp_feature_version =
1049                         le32_to_cpu(cp_hdr->ucode_feature_version);
1050                 ucode_fw = adev->gfx.pfp_fw;
1051                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1052                 break;
1053         case AMDGPU_UCODE_ID_CP_RS64_PFP:
1054                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1055                         adev->gfx.pfp_fw->data;
1056                 adev->gfx.pfp_fw_version =
1057                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1058                 adev->gfx.pfp_feature_version =
1059                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1060                 ucode_fw = adev->gfx.pfp_fw;
1061                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1062                 break;
1063         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
1064         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
1065                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1066                         adev->gfx.pfp_fw->data;
1067                 ucode_fw = adev->gfx.pfp_fw;
1068                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1069                 break;
1070         case AMDGPU_UCODE_ID_CP_ME:
1071                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1072                         adev->gfx.me_fw->data;
1073                 adev->gfx.me_fw_version =
1074                         le32_to_cpu(cp_hdr->header.ucode_version);
1075                 adev->gfx.me_feature_version =
1076                         le32_to_cpu(cp_hdr->ucode_feature_version);
1077                 ucode_fw = adev->gfx.me_fw;
1078                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1079                 break;
1080         case AMDGPU_UCODE_ID_CP_RS64_ME:
1081                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1082                         adev->gfx.me_fw->data;
1083                 adev->gfx.me_fw_version =
1084                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1085                 adev->gfx.me_feature_version =
1086                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1087                 ucode_fw = adev->gfx.me_fw;
1088                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1089                 break;
1090         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
1091         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
1092                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1093                         adev->gfx.me_fw->data;
1094                 ucode_fw = adev->gfx.me_fw;
1095                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1096                 break;
1097         case AMDGPU_UCODE_ID_CP_CE:
1098                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1099                         adev->gfx.ce_fw->data;
1100                 adev->gfx.ce_fw_version =
1101                         le32_to_cpu(cp_hdr->header.ucode_version);
1102                 adev->gfx.ce_feature_version =
1103                         le32_to_cpu(cp_hdr->ucode_feature_version);
1104                 ucode_fw = adev->gfx.ce_fw;
1105                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1106                 break;
1107         case AMDGPU_UCODE_ID_CP_MEC1:
1108                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1109                         adev->gfx.mec_fw->data;
1110                 adev->gfx.mec_fw_version =
1111                         le32_to_cpu(cp_hdr->header.ucode_version);
1112                 adev->gfx.mec_feature_version =
1113                         le32_to_cpu(cp_hdr->ucode_feature_version);
1114                 ucode_fw = adev->gfx.mec_fw;
1115                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1116                           le32_to_cpu(cp_hdr->jt_size) * 4;
1117                 break;
1118         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1119                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1120                         adev->gfx.mec_fw->data;
1121                 ucode_fw = adev->gfx.mec_fw;
1122                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1123                 break;
1124         case AMDGPU_UCODE_ID_CP_MEC2:
1125                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1126                         adev->gfx.mec2_fw->data;
1127                 adev->gfx.mec2_fw_version =
1128                         le32_to_cpu(cp_hdr->header.ucode_version);
1129                 adev->gfx.mec2_feature_version =
1130                         le32_to_cpu(cp_hdr->ucode_feature_version);
1131                 ucode_fw = adev->gfx.mec2_fw;
1132                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1133                           le32_to_cpu(cp_hdr->jt_size) * 4;
1134                 break;
1135         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1136                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1137                         adev->gfx.mec2_fw->data;
1138                 ucode_fw = adev->gfx.mec2_fw;
1139                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1140                 break;
1141         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1142                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1143                         adev->gfx.mec_fw->data;
1144                 adev->gfx.mec_fw_version =
1145                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1146                 adev->gfx.mec_feature_version =
1147                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1148                 ucode_fw = adev->gfx.mec_fw;
1149                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1150                 break;
1151         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1152         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1153         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1154         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1155                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1156                         adev->gfx.mec_fw->data;
1157                 ucode_fw = adev->gfx.mec_fw;
1158                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1159                 break;
1160         default:
1161                 break;
1162         }
1163
1164         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1165                 info = &adev->firmware.ucode[ucode_id];
1166                 info->ucode_id = ucode_id;
1167                 info->fw = ucode_fw;
1168                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1169         }
1170 }
1171
1172 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
1173 {
1174         return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
1175                         adev->gfx.num_xcc_per_xcp : 1));
1176 }