drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/mlx5/eswitch.h>
  56 #include <linux/list.h>
  57 #include <rdma/ib_smi.h>
  58 #include <rdma/ib_umem.h>
  59 #include <linux/in.h>
  60 #include <linux/etherdevice.h>
  61 #include "mlx5_ib.h"
  62 #include "ib_rep.h"
  63 #include "cmd.h"
  64 #include "srq.h"
  65 #include <linux/mlx5/fs_helpers.h>
  66 #include <linux/mlx5/accel.h>
  67 #include <rdma/uverbs_std_types.h>
  68 #include <rdma/mlx5_user_ioctl_verbs.h>
  69 #include <rdma/mlx5_user_ioctl_cmds.h>
  70
  71 #define UVERBS_MODULE_NAME mlx5_ib
  72 #include <rdma/uverbs_named_ioctl.h>
  73
  74 #define DRIVER_NAME "mlx5_ib"
  75 #define DRIVER_VERSION "5.0-0"
  76
  77 MODULE_AUTHOR("Eli Cohen <[email protected]>");
  78 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  79 MODULE_LICENSE("Dual BSD/GPL");
  80
  81 static char mlx5_version[] =
  82         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  83         DRIVER_VERSION "\n";
  84
  85 struct mlx5_ib_event_work {
  86         struct work_struct      work;
  87         union {
  88                 struct mlx5_ib_dev            *dev;
  89                 struct mlx5_ib_multiport_info *mpi;
  90         };
  91         bool                    is_slave;
  92         unsigned int            event;
  93         void                    *param;
  94 };
  95
  96 enum {
  97         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  98 };
  99
 100 static struct workqueue_struct *mlx5_ib_event_wq;
 101 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
 102 static LIST_HEAD(mlx5_ib_dev_list);
 103 /*
 104  * This mutex should be held when accessing either of the above lists
 105  */
 106 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 107
 108 /* We can't use an array for xlt_emergency_page because dma_map_single
 109  * doesn't work on kernel modules memory
 110  */
 111 static unsigned long xlt_emergency_page;
 112 static struct mutex xlt_emergency_page_mutex;
 113
 114 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 115 {
 116         struct mlx5_ib_dev *dev;
 117
 118         mutex_lock(&mlx5_ib_multiport_mutex);
 119         dev = mpi->ibdev;
 120         mutex_unlock(&mlx5_ib_multiport_mutex);
 121         return dev;
 122 }
 123
 124 static enum rdma_link_layer
 125 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 126 {
 127         switch (port_type_cap) {
 128         case MLX5_CAP_PORT_TYPE_IB:
 129                 return IB_LINK_LAYER_INFINIBAND;
 130         case MLX5_CAP_PORT_TYPE_ETH:
 131                 return IB_LINK_LAYER_ETHERNET;
 132         default:
 133                 return IB_LINK_LAYER_UNSPECIFIED;
 134         }
 135 }
 136
 137 static enum rdma_link_layer
 138 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 139 {
 140         struct mlx5_ib_dev *dev = to_mdev(device);
 141         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 142
 143         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 144 }
 145
 146 static int get_port_state(struct ib_device *ibdev,
 147                           u8 port_num,
 148                           enum ib_port_state *state)
 149 {
 150         struct ib_port_attr attr;
 151         int ret;
 152
 153         memset(&attr, 0, sizeof(attr));
 154         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 155         if (!ret)
 156                 *state = attr.state;
 157         return ret;
 158 }
 159
 160 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 161                                            struct net_device *ndev,
 162                                            u8 *port_num)
 163 {
 164         struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
 165         struct net_device *rep_ndev;
 166         struct mlx5_ib_port *port;
 167         int i;
 168
 169         for (i = 0; i < dev->num_ports; i++) {
 170                 port  = &dev->port[i];
 171                 if (!port->rep)
 172                         continue;
 173
 174                 read_lock(&port->roce.netdev_lock);
 175                 rep_ndev = mlx5_ib_get_rep_netdev(esw,
 176                                                   port->rep->vport);
 177                 if (rep_ndev == ndev) {
 178                         read_unlock(&port->roce.netdev_lock);
 179                         *port_num = i + 1;
 180                         return &port->roce;
 181                 }
 182                 read_unlock(&port->roce.netdev_lock);
 183         }
 184
 185         return NULL;
 186 }
 187
 188 static int mlx5_netdev_event(struct notifier_block *this,
 189                              unsigned long event, void *ptr)
 190 {
 191         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 192         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 193         u8 port_num = roce->native_port_num;
 194         struct mlx5_core_dev *mdev;
 195         struct mlx5_ib_dev *ibdev;
 196
 197         ibdev = roce->dev;
 198         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 199         if (!mdev)
 200                 return NOTIFY_DONE;
 201
 202         switch (event) {
 203         case NETDEV_REGISTER:
 204                 /* Should already be registered during the load */
 205                 if (ibdev->is_rep)
 206                         break;
 207                 write_lock(&roce->netdev_lock);
 208                 if (ndev->dev.parent == mdev->device)
 209                         roce->netdev = ndev;
 210                 write_unlock(&roce->netdev_lock);
 211                 break;
 212
 213         case NETDEV_UNREGISTER:
 214                 /* In case of reps, ib device goes away before the netdevs */
 215                 write_lock(&roce->netdev_lock);
 216                 if (roce->netdev == ndev)
 217                         roce->netdev = NULL;
 218                 write_unlock(&roce->netdev_lock);
 219                 break;
 220
 221         case NETDEV_CHANGE:
 222         case NETDEV_UP:
 223         case NETDEV_DOWN: {
 224                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 225                 struct net_device *upper = NULL;
 226
 227                 if (lag_ndev) {
 228                         upper = netdev_master_upper_dev_get(lag_ndev);
 229                         dev_put(lag_ndev);
 230                 }
 231
 232                 if (ibdev->is_rep)
 233                         roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
 234                 if (!roce)
 235                         return NOTIFY_DONE;
 236                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 237                     && ibdev->ib_active) {
 238                         struct ib_event ibev = { };
 239                         enum ib_port_state port_state;
 240
 241                         if (get_port_state(&ibdev->ib_dev, port_num,
 242                                            &port_state))
 243                                 goto done;
 244
 245                         if (roce->last_port_state == port_state)
 246                                 goto done;
 247
 248                         roce->last_port_state = port_state;
 249                         ibev.device = &ibdev->ib_dev;
 250                         if (port_state == IB_PORT_DOWN)
 251                                 ibev.event = IB_EVENT_PORT_ERR;
 252                         else if (port_state == IB_PORT_ACTIVE)
 253                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 254                         else
 255                                 goto done;
 256
 257                         ibev.element.port_num = port_num;
 258                         ib_dispatch_event(&ibev);
 259                 }
 260                 break;
 261         }
 262
 263         default:
 264                 break;
 265         }
 266 done:
 267         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 268         return NOTIFY_DONE;
 269 }
 270
 271 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 272                                              u8 port_num)
 273 {
 274         struct mlx5_ib_dev *ibdev = to_mdev(device);
 275         struct net_device *ndev;
 276         struct mlx5_core_dev *mdev;
 277
 278         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 279         if (!mdev)
 280                 return NULL;
 281
 282         ndev = mlx5_lag_get_roce_netdev(mdev);
 283         if (ndev)
 284                 goto out;
 285
 286         /* Ensure ndev does not disappear before we invoke dev_hold()
 287          */
 288         read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
 289         ndev = ibdev->port[port_num - 1].roce.netdev;
 290         if (ndev)
 291                 dev_hold(ndev);
 292         read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
 293
 294 out:
 295         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 296         return ndev;
 297 }
 298
 299 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 300                                                    u8 ib_port_num,
 301                                                    u8 *native_port_num)
 302 {
 303         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 304                                                           ib_port_num);
 305         struct mlx5_core_dev *mdev = NULL;
 306         struct mlx5_ib_multiport_info *mpi;
 307         struct mlx5_ib_port *port;
 308
 309         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 310             ll != IB_LINK_LAYER_ETHERNET) {
 311                 if (native_port_num)
 312                         *native_port_num = ib_port_num;
 313                 return ibdev->mdev;
 314         }
 315
 316         if (native_port_num)
 317                 *native_port_num = 1;
 318
 319         port = &ibdev->port[ib_port_num - 1];
 320         if (!port)
 321                 return NULL;
 322
 323         spin_lock(&port->mp.mpi_lock);
 324         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 325         if (mpi && !mpi->unaffiliate) {
 326                 mdev = mpi->mdev;
 327                 /* If it's the master no need to refcount, it'll exist
 328                  * as long as the ib_dev exists.
 329                  */
 330                 if (!mpi->is_master)
 331                         mpi->mdev_refcnt++;
 332         }
 333         spin_unlock(&port->mp.mpi_lock);
 334
 335         return mdev;
 336 }
 337
 338 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 339 {
 340         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 341                                                           port_num);
 342         struct mlx5_ib_multiport_info *mpi;
 343         struct mlx5_ib_port *port;
 344
 345         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 346                 return;
 347
 348         port = &ibdev->port[port_num - 1];
 349
 350         spin_lock(&port->mp.mpi_lock);
 351         mpi = ibdev->port[port_num - 1].mp.mpi;
 352         if (mpi->is_master)
 353                 goto out;
 354
 355         mpi->mdev_refcnt--;
 356         if (mpi->unaffiliate)
 357                 complete(&mpi->unref_comp);
 358 out:
 359         spin_unlock(&port->mp.mpi_lock);
 360 }
 361
 362 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 363                                            u8 *active_width)
 364 {
 365         switch (eth_proto_oper) {
 366         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 367         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 368         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 369         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 370                 *active_width = IB_WIDTH_1X;
 371                 *active_speed = IB_SPEED_SDR;
 372                 break;
 373         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 374         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 375         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 376         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 377         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 378         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 379         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 380                 *active_width = IB_WIDTH_1X;
 381                 *active_speed = IB_SPEED_QDR;
 382                 break;
 383         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 384         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 385         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 386                 *active_width = IB_WIDTH_1X;
 387                 *active_speed = IB_SPEED_EDR;
 388                 break;
 389         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 390         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 391         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 392         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 393                 *active_width = IB_WIDTH_4X;
 394                 *active_speed = IB_SPEED_QDR;
 395                 break;
 396         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 397         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 398         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 399                 *active_width = IB_WIDTH_1X;
 400                 *active_speed = IB_SPEED_HDR;
 401                 break;
 402         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 403                 *active_width = IB_WIDTH_4X;
 404                 *active_speed = IB_SPEED_FDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 407         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 408         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 409         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 410                 *active_width = IB_WIDTH_4X;
 411                 *active_speed = IB_SPEED_EDR;
 412                 break;
 413         default:
 414                 return -EINVAL;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 421                                         u8 *active_width)
 422 {
 423         switch (eth_proto_oper) {
 424         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 425         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 426                 *active_width = IB_WIDTH_1X;
 427                 *active_speed = IB_SPEED_SDR;
 428                 break;
 429         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 430                 *active_width = IB_WIDTH_1X;
 431                 *active_speed = IB_SPEED_DDR;
 432                 break;
 433         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 434                 *active_width = IB_WIDTH_1X;
 435                 *active_speed = IB_SPEED_QDR;
 436                 break;
 437         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 438                 *active_width = IB_WIDTH_4X;
 439                 *active_speed = IB_SPEED_QDR;
 440                 break;
 441         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 442                 *active_width = IB_WIDTH_1X;
 443                 *active_speed = IB_SPEED_EDR;
 444                 break;
 445         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 446                 *active_width = IB_WIDTH_2X;
 447                 *active_speed = IB_SPEED_EDR;
 448                 break;
 449         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 450                 *active_width = IB_WIDTH_1X;
 451                 *active_speed = IB_SPEED_HDR;
 452                 break;
 453         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 454                 *active_width = IB_WIDTH_4X;
 455                 *active_speed = IB_SPEED_EDR;
 456                 break;
 457         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 458                 *active_width = IB_WIDTH_2X;
 459                 *active_speed = IB_SPEED_HDR;
 460                 break;
 461         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 462                 *active_width = IB_WIDTH_4X;
 463                 *active_speed = IB_SPEED_HDR;
 464                 break;
 465         default:
 466                 return -EINVAL;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 473                                     u8 *active_width, bool ext)
 474 {
 475         return ext ?
 476                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 477                                              active_width) :
 478                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 479                                                 active_width);
 480 }
 481
 482 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 483                                 struct ib_port_attr *props)
 484 {
 485         struct mlx5_ib_dev *dev = to_mdev(device);
 486         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 487         struct mlx5_core_dev *mdev;
 488         struct net_device *ndev, *upper;
 489         enum ib_mtu ndev_ib_mtu;
 490         bool put_mdev = true;
 491         u16 qkey_viol_cntr;
 492         u32 eth_prot_oper;
 493         u8 mdev_port_num;
 494         bool ext;
 495         int err;
 496
 497         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 498         if (!mdev) {
 499                 /* This means the port isn't affiliated yet. Get the
 500                  * info for the master port instead.
 501                  */
 502                 put_mdev = false;
 503                 mdev = dev->mdev;
 504                 mdev_port_num = 1;
 505                 port_num = 1;
 506         }
 507
 508         /* Possible bad flows are checked before filling out props so in case
 509          * of an error it will still be zeroed out.
 510          * Use native port in case of reps
 511          */
 512         if (dev->is_rep)
 513                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 514                                            1);
 515         else
 516                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 517                                            mdev_port_num);
 518         if (err)
 519                 goto out;
 520         ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
 521         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 522
 523         props->active_width     = IB_WIDTH_4X;
 524         props->active_speed     = IB_SPEED_QDR;
 525
 526         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 527                                  &props->active_width, ext);
 528
 529         props->port_cap_flags |= IB_PORT_CM_SUP;
 530         props->ip_gids = true;
 531
 532         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 533                                                 roce_address_table_size);
 534         props->max_mtu          = IB_MTU_4096;
 535         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 536         props->pkey_tbl_len     = 1;
 537         props->state            = IB_PORT_DOWN;
 538         props->phys_state       = 3;
 539
 540         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 541         props->qkey_viol_cntr = qkey_viol_cntr;
 542
 543         /* If this is a stub query for an unaffiliated port stop here */
 544         if (!put_mdev)
 545                 goto out;
 546
 547         ndev = mlx5_ib_get_netdev(device, port_num);
 548         if (!ndev)
 549                 goto out;
 550
 551         if (dev->lag_active) {
 552                 rcu_read_lock();
 553                 upper = netdev_master_upper_dev_get_rcu(ndev);
 554                 if (upper) {
 555                         dev_put(ndev);
 556                         ndev = upper;
 557                         dev_hold(ndev);
 558                 }
 559                 rcu_read_unlock();
 560         }
 561
 562         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 563                 props->state      = IB_PORT_ACTIVE;
 564                 props->phys_state = 5;
 565         }
 566
 567         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 568
 569         dev_put(ndev);
 570
 571         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 572 out:
 573         if (put_mdev)
 574                 mlx5_ib_put_native_port_mdev(dev, port_num);
 575         return err;
 576 }
 577
 578 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 579                          unsigned int index, const union ib_gid *gid,
 580                          const struct ib_gid_attr *attr)
 581 {
 582         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 583         u16 vlan_id = 0xffff;
 584         u8 roce_version = 0;
 585         u8 roce_l3_type = 0;
 586         u8 mac[ETH_ALEN];
 587         int ret;
 588
 589         if (gid) {
 590                 gid_type = attr->gid_type;
 591                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 592                 if (ret)
 593                         return ret;
 594         }
 595
 596         switch (gid_type) {
 597         case IB_GID_TYPE_IB:
 598                 roce_version = MLX5_ROCE_VERSION_1;
 599                 break;
 600         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 601                 roce_version = MLX5_ROCE_VERSION_2;
 602                 if (ipv6_addr_v4mapped((void *)gid))
 603                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 604                 else
 605                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 606                 break;
 607
 608         default:
 609                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 610         }
 611
 612         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 613                                       roce_l3_type, gid->raw, mac,
 614                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 615                                       port_num);
 616 }
 617
 618 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 619                            __always_unused void **context)
 620 {
 621         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 622                              attr->index, &attr->gid, attr);
 623 }
 624
 625 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 626                            __always_unused void **context)
 627 {
 628         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 629                              attr->index, NULL, NULL);
 630 }
 631
 632 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
 633                                const struct ib_gid_attr *attr)
 634 {
 635         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 636                 return 0;
 637
 638         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 639 }
 640
 641 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 642 {
 643         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 644                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 645         return 0;
 646 }
 647
 648 enum {
 649         MLX5_VPORT_ACCESS_METHOD_MAD,
 650         MLX5_VPORT_ACCESS_METHOD_HCA,
 651         MLX5_VPORT_ACCESS_METHOD_NIC,
 652 };
 653
 654 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 655 {
 656         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 657                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 658
 659         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 660             IB_LINK_LAYER_ETHERNET)
 661                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 662
 663         return MLX5_VPORT_ACCESS_METHOD_HCA;
 664 }
 665
 666 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 667                             u8 atomic_size_qp,
 668                             struct ib_device_attr *props)
 669 {
 670         u8 tmp;
 671         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 672         u8 atomic_req_8B_endianness_mode =
 673                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 674
 675         /* Check if HW supports 8 bytes standard atomic operations and capable
 676          * of host endianness respond
 677          */
 678         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 679         if (((atomic_operations & tmp) == tmp) &&
 680             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 681             (atomic_req_8B_endianness_mode)) {
 682                 props->atomic_cap = IB_ATOMIC_HCA;
 683         } else {
 684                 props->atomic_cap = IB_ATOMIC_NONE;
 685         }
 686 }
 687
 688 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 689                                struct ib_device_attr *props)
 690 {
 691         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 692
 693         get_atomic_caps(dev, atomic_size_qp, props);
 694 }
 695
 696 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 697                                struct ib_device_attr *props)
 698 {
 699         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 700
 701         get_atomic_caps(dev, atomic_size_qp, props);
 702 }
 703
 704 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 705 {
 706         struct ib_device_attr props = {};
 707
 708         get_atomic_caps_dc(dev, &props);
 709         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 710 }
 711 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 712                                         __be64 *sys_image_guid)
 713 {
 714         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 715         struct mlx5_core_dev *mdev = dev->mdev;
 716         u64 tmp;
 717         int err;
 718
 719         switch (mlx5_get_vport_access_method(ibdev)) {
 720         case MLX5_VPORT_ACCESS_METHOD_MAD:
 721                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 722                                                             sys_image_guid);
 723
 724         case MLX5_VPORT_ACCESS_METHOD_HCA:
 725                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 726                 break;
 727
 728         case MLX5_VPORT_ACCESS_METHOD_NIC:
 729                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 730                 break;
 731
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         if (!err)
 737                 *sys_image_guid = cpu_to_be64(tmp);
 738
 739         return err;
 740
 741 }
 742
 743 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 744                                 u16 *max_pkeys)
 745 {
 746         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 747         struct mlx5_core_dev *mdev = dev->mdev;
 748
 749         switch (mlx5_get_vport_access_method(ibdev)) {
 750         case MLX5_VPORT_ACCESS_METHOD_MAD:
 751                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 752
 753         case MLX5_VPORT_ACCESS_METHOD_HCA:
 754         case MLX5_VPORT_ACCESS_METHOD_NIC:
 755                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 756                                                 pkey_table_size));
 757                 return 0;
 758
 759         default:
 760                 return -EINVAL;
 761         }
 762 }
 763
 764 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 765                                 u32 *vendor_id)
 766 {
 767         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 768
 769         switch (mlx5_get_vport_access_method(ibdev)) {
 770         case MLX5_VPORT_ACCESS_METHOD_MAD:
 771                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 772
 773         case MLX5_VPORT_ACCESS_METHOD_HCA:
 774         case MLX5_VPORT_ACCESS_METHOD_NIC:
 775                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 776
 777         default:
 778                 return -EINVAL;
 779         }
 780 }
 781
 782 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 783                                 __be64 *node_guid)
 784 {
 785         u64 tmp;
 786         int err;
 787
 788         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 789         case MLX5_VPORT_ACCESS_METHOD_MAD:
 790                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 791
 792         case MLX5_VPORT_ACCESS_METHOD_HCA:
 793                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 794                 break;
 795
 796         case MLX5_VPORT_ACCESS_METHOD_NIC:
 797                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 798                 break;
 799
 800         default:
 801                 return -EINVAL;
 802         }
 803
 804         if (!err)
 805                 *node_guid = cpu_to_be64(tmp);
 806
 807         return err;
 808 }
 809
 810 struct mlx5_reg_node_desc {
 811         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 812 };
 813
 814 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 815 {
 816         struct mlx5_reg_node_desc in;
 817
 818         if (mlx5_use_mad_ifc(dev))
 819                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 820
 821         memset(&in, 0, sizeof(in));
 822
 823         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 824                                     sizeof(struct mlx5_reg_node_desc),
 825                                     MLX5_REG_NODE_DESC, 0, 0);
 826 }
 827
 828 static int mlx5_ib_query_device(struct ib_device *ibdev,
 829                                 struct ib_device_attr *props,
 830                                 struct ib_udata *uhw)
 831 {
 832         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 833         struct mlx5_core_dev *mdev = dev->mdev;
 834         int err = -ENOMEM;
 835         int max_sq_desc;
 836         int max_rq_sg;
 837         int max_sq_sg;
 838         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 839         bool raw_support = !mlx5_core_mp_enabled(mdev);
 840         struct mlx5_ib_query_device_resp resp = {};
 841         size_t resp_len;
 842         u64 max_tso;
 843
 844         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 845         if (uhw->outlen && uhw->outlen < resp_len)
 846                 return -EINVAL;
 847         else
 848                 resp.response_length = resp_len;
 849
 850         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 851                 return -EINVAL;
 852
 853         memset(props, 0, sizeof(*props));
 854         err = mlx5_query_system_image_guid(ibdev,
 855                                            &props->sys_image_guid);
 856         if (err)
 857                 return err;
 858
 859         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 860         if (err)
 861                 return err;
 862
 863         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 864         if (err)
 865                 return err;
 866
 867         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 868                 (fw_rev_min(dev->mdev) << 16) |
 869                 fw_rev_sub(dev->mdev);
 870         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 871                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 872                 IB_DEVICE_SYS_IMAGE_GUID                |
 873                 IB_DEVICE_RC_RNR_NAK_GEN;
 874
 875         if (MLX5_CAP_GEN(mdev, pkv))
 876                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 877         if (MLX5_CAP_GEN(mdev, qkv))
 878                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 879         if (MLX5_CAP_GEN(mdev, apm))
 880                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 881         if (MLX5_CAP_GEN(mdev, xrc))
 882                 props->device_cap_flags |= IB_DEVICE_XRC;
 883         if (MLX5_CAP_GEN(mdev, imaicl)) {
 884                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 885                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 886                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 887                 /* We support 'Gappy' memory registration too */
 888                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 889         }
 890         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 891         if (MLX5_CAP_GEN(mdev, sho)) {
 892                 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
 893                 /* At this stage no support for signature handover */
 894                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 895                                       IB_PROT_T10DIF_TYPE_2 |
 896                                       IB_PROT_T10DIF_TYPE_3;
 897                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 898                                        IB_GUARD_T10DIF_CSUM;
 899         }
 900         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 901                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 902
 903         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 904                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 905                         /* Legacy bit to support old userspace libraries */
 906                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 907                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 908                 }
 909
 910                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 911                         props->raw_packet_caps |=
 912                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 913
 914                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 915                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 916                         if (max_tso) {
 917                                 resp.tso_caps.max_tso = 1 << max_tso;
 918                                 resp.tso_caps.supported_qpts |=
 919                                         1 << IB_QPT_RAW_PACKET;
 920                                 resp.response_length += sizeof(resp.tso_caps);
 921                         }
 922                 }
 923
 924                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 925                         resp.rss_caps.rx_hash_function =
 926                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 927                         resp.rss_caps.rx_hash_fields_mask =
 928                                                 MLX5_RX_HASH_SRC_IPV4 |
 929                                                 MLX5_RX_HASH_DST_IPV4 |
 930                                                 MLX5_RX_HASH_SRC_IPV6 |
 931                                                 MLX5_RX_HASH_DST_IPV6 |
 932                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 933                                                 MLX5_RX_HASH_DST_PORT_TCP |
 934                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 935                                                 MLX5_RX_HASH_DST_PORT_UDP |
 936                                                 MLX5_RX_HASH_INNER;
 937                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 938                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 939                                 resp.rss_caps.rx_hash_fields_mask |=
 940                                         MLX5_RX_HASH_IPSEC_SPI;
 941                         resp.response_length += sizeof(resp.rss_caps);
 942                 }
 943         } else {
 944                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 945                         resp.response_length += sizeof(resp.tso_caps);
 946                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 947                         resp.response_length += sizeof(resp.rss_caps);
 948         }
 949
 950         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 951                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 952                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 953         }
 954
 955         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 956             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 957             raw_support)
 958                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 959
 960         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 961             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 962                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 963
 964         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 965             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 966             raw_support) {
 967                 /* Legacy bit to support old userspace libraries */
 968                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 969                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 970         }
 971
 972         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 973                 props->max_dm_size =
 974                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 975         }
 976
 977         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 978                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 979
 980         if (MLX5_CAP_GEN(mdev, end_pad))
 981                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 982
 983         props->vendor_part_id      = mdev->pdev->device;
 984         props->hw_ver              = mdev->pdev->revision;
 985
 986         props->max_mr_size         = ~0ull;
 987         props->page_size_cap       = ~(min_page_size - 1);
 988         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 989         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 990         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 991                      sizeof(struct mlx5_wqe_data_seg);
 992         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 993         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 994                      sizeof(struct mlx5_wqe_raddr_seg)) /
 995                 sizeof(struct mlx5_wqe_data_seg);
 996         props->max_send_sge = max_sq_sg;
 997         props->max_recv_sge = max_rq_sg;
 998         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 999         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
1000         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
1001         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
1008         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
1009         props->max_srq_sge         = max_rq_sg - 1;
1010         props->max_fast_reg_page_list_len =
1011                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
1012         props->max_pi_fast_reg_page_list_len =
1013                 props->max_fast_reg_page_list_len / 2;
1014         get_atomic_caps_qp(dev, props);
1015         props->masked_atomic_cap   = IB_ATOMIC_NONE;
1016         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1017         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1018         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1019                                            props->max_mcast_grp;
1020         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
1021         props->max_ah = INT_MAX;
1022         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1023         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1024
1025         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1026                 if (MLX5_CAP_GEN(mdev, pg))
1027                         props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1028                 props->odp_caps = dev->odp_caps;
1029         }
1030
1031         if (MLX5_CAP_GEN(mdev, cd))
1032                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1033
1034         if (!mlx5_core_is_pf(mdev))
1035                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1036
1037         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1038             IB_LINK_LAYER_ETHERNET && raw_support) {
1039                 props->rss_caps.max_rwq_indirection_tables =
1040                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1041                 props->rss_caps.max_rwq_indirection_table_size =
1042                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1043                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1044                 props->max_wq_type_rq =
1045                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1046         }
1047
1048         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1049                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1050                 props->tm_caps.max_num_tags =
1051                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1052                 props->tm_caps.flags = IB_TM_CAP_RC;
1053                 props->tm_caps.max_ops =
1054                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1055                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1056         }
1057
1058         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1059                 props->cq_caps.max_cq_moderation_count =
1060                                                 MLX5_MAX_CQ_COUNT;
1061                 props->cq_caps.max_cq_moderation_period =
1062                                                 MLX5_MAX_CQ_PERIOD;
1063         }
1064
1065         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
1066                 resp.response_length += sizeof(resp.cqe_comp_caps);
1067
1068                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1069                         resp.cqe_comp_caps.max_num =
1070                                 MLX5_CAP_GEN(dev->mdev,
1071                                              cqe_compression_max_num);
1072
1073                         resp.cqe_comp_caps.supported_format =
1074                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1075                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1076
1077                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1078                                 resp.cqe_comp_caps.supported_format |=
1079                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1080                 }
1081         }
1082
1083         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1084             raw_support) {
1085                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1086                     MLX5_CAP_GEN(mdev, qos)) {
1087                         resp.packet_pacing_caps.qp_rate_limit_max =
1088                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1089                         resp.packet_pacing_caps.qp_rate_limit_min =
1090                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1091                         resp.packet_pacing_caps.supported_qpts |=
1092                                 1 << IB_QPT_RAW_PACKET;
1093                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1094                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1095                                 resp.packet_pacing_caps.cap_flags |=
1096                                         MLX5_IB_PP_SUPPORT_BURST;
1097                 }
1098                 resp.response_length += sizeof(resp.packet_pacing_caps);
1099         }
1100
1101         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1102                         uhw->outlen)) {
1103                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1104                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1105                                 MLX5_IB_ALLOW_MPW;
1106
1107                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1108                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1109                                 MLX5_IB_SUPPORT_EMPW;
1110
1111                 resp.response_length +=
1112                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1113         }
1114
1115         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1116                 resp.response_length += sizeof(resp.flags);
1117
1118                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1119                         resp.flags |=
1120                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1121
1122                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1123                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1124                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1125                         resp.flags |=
1126                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1127
1128                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1129         }
1130
1131         if (field_avail(typeof(resp), sw_parsing_caps,
1132                         uhw->outlen)) {
1133                 resp.response_length += sizeof(resp.sw_parsing_caps);
1134                 if (MLX5_CAP_ETH(mdev, swp)) {
1135                         resp.sw_parsing_caps.sw_parsing_offloads |=
1136                                 MLX5_IB_SW_PARSING;
1137
1138                         if (MLX5_CAP_ETH(mdev, swp_csum))
1139                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1140                                         MLX5_IB_SW_PARSING_CSUM;
1141
1142                         if (MLX5_CAP_ETH(mdev, swp_lso))
1143                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1144                                         MLX5_IB_SW_PARSING_LSO;
1145
1146                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1147                                 resp.sw_parsing_caps.supported_qpts =
1148                                         BIT(IB_QPT_RAW_PACKET);
1149                 }
1150         }
1151
1152         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1153             raw_support) {
1154                 resp.response_length += sizeof(resp.striding_rq_caps);
1155                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1156                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1157                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1158                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1159                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1160                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1161                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1162                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1163                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1164                         resp.striding_rq_caps.supported_qpts =
1165                                 BIT(IB_QPT_RAW_PACKET);
1166                 }
1167         }
1168
1169         if (field_avail(typeof(resp), tunnel_offloads_caps,
1170                         uhw->outlen)) {
1171                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1172                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1173                         resp.tunnel_offloads_caps |=
1174                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1175                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1176                         resp.tunnel_offloads_caps |=
1177                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1178                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1179                         resp.tunnel_offloads_caps |=
1180                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1181                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1182                     MLX5_FLEX_PROTO_CW_MPLS_GRE)
1183                         resp.tunnel_offloads_caps |=
1184                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1185                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1186                     MLX5_FLEX_PROTO_CW_MPLS_UDP)
1187                         resp.tunnel_offloads_caps |=
1188                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1189         }
1190
1191         if (uhw->outlen) {
1192                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1193
1194                 if (err)
1195                         return err;
1196         }
1197
1198         return 0;
1199 }
1200
1201 enum mlx5_ib_width {
1202         MLX5_IB_WIDTH_1X        = 1 << 0,
1203         MLX5_IB_WIDTH_2X        = 1 << 1,
1204         MLX5_IB_WIDTH_4X        = 1 << 2,
1205         MLX5_IB_WIDTH_8X        = 1 << 3,
1206         MLX5_IB_WIDTH_12X       = 1 << 4
1207 };
1208
1209 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1210                                   u8 *ib_width)
1211 {
1212         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1213
1214         if (active_width & MLX5_IB_WIDTH_1X)
1215                 *ib_width = IB_WIDTH_1X;
1216         else if (active_width & MLX5_IB_WIDTH_2X)
1217                 *ib_width = IB_WIDTH_2X;
1218         else if (active_width & MLX5_IB_WIDTH_4X)
1219                 *ib_width = IB_WIDTH_4X;
1220         else if (active_width & MLX5_IB_WIDTH_8X)
1221                 *ib_width = IB_WIDTH_8X;
1222         else if (active_width & MLX5_IB_WIDTH_12X)
1223                 *ib_width = IB_WIDTH_12X;
1224         else {
1225                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1226                             (int)active_width);
1227                 *ib_width = IB_WIDTH_4X;
1228         }
1229
1230         return;
1231 }
1232
1233 static int mlx5_mtu_to_ib_mtu(int mtu)
1234 {
1235         switch (mtu) {
1236         case 256: return 1;
1237         case 512: return 2;
1238         case 1024: return 3;
1239         case 2048: return 4;
1240         case 4096: return 5;
1241         default:
1242                 pr_warn("invalid mtu\n");
1243                 return -1;
1244         }
1245 }
1246
1247 enum ib_max_vl_num {
1248         __IB_MAX_VL_0           = 1,
1249         __IB_MAX_VL_0_1         = 2,
1250         __IB_MAX_VL_0_3         = 3,
1251         __IB_MAX_VL_0_7         = 4,
1252         __IB_MAX_VL_0_14        = 5,
1253 };
1254
1255 enum mlx5_vl_hw_cap {
1256         MLX5_VL_HW_0    = 1,
1257         MLX5_VL_HW_0_1  = 2,
1258         MLX5_VL_HW_0_2  = 3,
1259         MLX5_VL_HW_0_3  = 4,
1260         MLX5_VL_HW_0_4  = 5,
1261         MLX5_VL_HW_0_5  = 6,
1262         MLX5_VL_HW_0_6  = 7,
1263         MLX5_VL_HW_0_7  = 8,
1264         MLX5_VL_HW_0_14 = 15
1265 };
1266
1267 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1268                                 u8 *max_vl_num)
1269 {
1270         switch (vl_hw_cap) {
1271         case MLX5_VL_HW_0:
1272                 *max_vl_num = __IB_MAX_VL_0;
1273                 break;
1274         case MLX5_VL_HW_0_1:
1275                 *max_vl_num = __IB_MAX_VL_0_1;
1276                 break;
1277         case MLX5_VL_HW_0_3:
1278                 *max_vl_num = __IB_MAX_VL_0_3;
1279                 break;
1280         case MLX5_VL_HW_0_7:
1281                 *max_vl_num = __IB_MAX_VL_0_7;
1282                 break;
1283         case MLX5_VL_HW_0_14:
1284                 *max_vl_num = __IB_MAX_VL_0_14;
1285                 break;
1286
1287         default:
1288                 return -EINVAL;
1289         }
1290
1291         return 0;
1292 }
1293
1294 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1295                                struct ib_port_attr *props)
1296 {
1297         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1298         struct mlx5_core_dev *mdev = dev->mdev;
1299         struct mlx5_hca_vport_context *rep;
1300         u16 max_mtu;
1301         u16 oper_mtu;
1302         int err;
1303         u8 ib_link_width_oper;
1304         u8 vl_hw_cap;
1305
1306         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1307         if (!rep) {
1308                 err = -ENOMEM;
1309                 goto out;
1310         }
1311
1312         /* props being zeroed by the caller, avoid zeroing it here */
1313
1314         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1315         if (err)
1316                 goto out;
1317
1318         props->lid              = rep->lid;
1319         props->lmc              = rep->lmc;
1320         props->sm_lid           = rep->sm_lid;
1321         props->sm_sl            = rep->sm_sl;
1322         props->state            = rep->vport_state;
1323         props->phys_state       = rep->port_physical_state;
1324         props->port_cap_flags   = rep->cap_mask1;
1325         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1326         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1327         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1328         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1329         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1330         props->subnet_timeout   = rep->subnet_timeout;
1331         props->init_type_reply  = rep->init_type_reply;
1332
1333         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1334                 props->port_cap_flags2 = rep->cap_mask2;
1335
1336         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1337         if (err)
1338                 goto out;
1339
1340         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1341
1342         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1343         if (err)
1344                 goto out;
1345
1346         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1347
1348         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1349
1350         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1351
1352         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1353
1354         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1355         if (err)
1356                 goto out;
1357
1358         err = translate_max_vl_num(ibdev, vl_hw_cap,
1359                                    &props->max_vl_num);
1360 out:
1361         kfree(rep);
1362         return err;
1363 }
1364
1365 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1366                        struct ib_port_attr *props)
1367 {
1368         unsigned int count;
1369         int ret;
1370
1371         switch (mlx5_get_vport_access_method(ibdev)) {
1372         case MLX5_VPORT_ACCESS_METHOD_MAD:
1373                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1374                 break;
1375
1376         case MLX5_VPORT_ACCESS_METHOD_HCA:
1377                 ret = mlx5_query_hca_port(ibdev, port, props);
1378                 break;
1379
1380         case MLX5_VPORT_ACCESS_METHOD_NIC:
1381                 ret = mlx5_query_port_roce(ibdev, port, props);
1382                 break;
1383
1384         default:
1385                 ret = -EINVAL;
1386         }
1387
1388         if (!ret && props) {
1389                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1390                 struct mlx5_core_dev *mdev;
1391                 bool put_mdev = true;
1392
1393                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1394                 if (!mdev) {
1395                         /* If the port isn't affiliated yet query the master.
1396                          * The master and slave will have the same values.
1397                          */
1398                         mdev = dev->mdev;
1399                         port = 1;
1400                         put_mdev = false;
1401                 }
1402                 count = mlx5_core_reserved_gids_count(mdev);
1403                 if (put_mdev)
1404                         mlx5_ib_put_native_port_mdev(dev, port);
1405                 props->gid_tbl_len -= count;
1406         }
1407         return ret;
1408 }
1409
1410 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1411                                   struct ib_port_attr *props)
1412 {
1413         int ret;
1414
1415         /* Only link layer == ethernet is valid for representors
1416          * and we always use port 1
1417          */
1418         ret = mlx5_query_port_roce(ibdev, port, props);
1419         if (ret || !props)
1420                 return ret;
1421
1422         /* We don't support GIDS */
1423         props->gid_tbl_len = 0;
1424
1425         return ret;
1426 }
1427
1428 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1429                              union ib_gid *gid)
1430 {
1431         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1432         struct mlx5_core_dev *mdev = dev->mdev;
1433
1434         switch (mlx5_get_vport_access_method(ibdev)) {
1435         case MLX5_VPORT_ACCESS_METHOD_MAD:
1436                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1437
1438         case MLX5_VPORT_ACCESS_METHOD_HCA:
1439                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1440
1441         default:
1442                 return -EINVAL;
1443         }
1444
1445 }
1446
1447 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1448                                    u16 index, u16 *pkey)
1449 {
1450         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1451         struct mlx5_core_dev *mdev;
1452         bool put_mdev = true;
1453         u8 mdev_port_num;
1454         int err;
1455
1456         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1457         if (!mdev) {
1458                 /* The port isn't affiliated yet, get the PKey from the master
1459                  * port. For RoCE the PKey tables will be the same.
1460                  */
1461                 put_mdev = false;
1462                 mdev = dev->mdev;
1463                 mdev_port_num = 1;
1464         }
1465
1466         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1467                                         index, pkey);
1468         if (put_mdev)
1469                 mlx5_ib_put_native_port_mdev(dev, port);
1470
1471         return err;
1472 }
1473
1474 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1475                               u16 *pkey)
1476 {
1477         switch (mlx5_get_vport_access_method(ibdev)) {
1478         case MLX5_VPORT_ACCESS_METHOD_MAD:
1479                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1480
1481         case MLX5_VPORT_ACCESS_METHOD_HCA:
1482         case MLX5_VPORT_ACCESS_METHOD_NIC:
1483                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1484         default:
1485                 return -EINVAL;
1486         }
1487 }
1488
1489 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1490                                  struct ib_device_modify *props)
1491 {
1492         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1493         struct mlx5_reg_node_desc in;
1494         struct mlx5_reg_node_desc out;
1495         int err;
1496
1497         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1498                 return -EOPNOTSUPP;
1499
1500         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1501                 return 0;
1502
1503         /*
1504          * If possible, pass node desc to FW, so it can generate
1505          * a 144 trap.  If cmd fails, just ignore.
1506          */
1507         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1508         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1509                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1510         if (err)
1511                 return err;
1512
1513         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1514
1515         return err;
1516 }
1517
1518 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1519                                 u32 value)
1520 {
1521         struct mlx5_hca_vport_context ctx = {};
1522         struct mlx5_core_dev *mdev;
1523         u8 mdev_port_num;
1524         int err;
1525
1526         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1527         if (!mdev)
1528                 return -ENODEV;
1529
1530         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1531         if (err)
1532                 goto out;
1533
1534         if (~ctx.cap_mask1_perm & mask) {
1535                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1536                              mask, ctx.cap_mask1_perm);
1537                 err = -EINVAL;
1538                 goto out;
1539         }
1540
1541         ctx.cap_mask1 = value;
1542         ctx.cap_mask1_perm = mask;
1543         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1544                                                  0, &ctx);
1545
1546 out:
1547         mlx5_ib_put_native_port_mdev(dev, port_num);
1548
1549         return err;
1550 }
1551
1552 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1553                                struct ib_port_modify *props)
1554 {
1555         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1556         struct ib_port_attr attr;
1557         u32 tmp;
1558         int err;
1559         u32 change_mask;
1560         u32 value;
1561         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1562                       IB_LINK_LAYER_INFINIBAND);
1563
1564         /* CM layer calls ib_modify_port() regardless of the link layer. For
1565          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1566          */
1567         if (!is_ib)
1568                 return 0;
1569
1570         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1571                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1572                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1573                 return set_port_caps_atomic(dev, port, change_mask, value);
1574         }
1575
1576         mutex_lock(&dev->cap_mask_mutex);
1577
1578         err = ib_query_port(ibdev, port, &attr);
1579         if (err)
1580                 goto out;
1581
1582         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1583                 ~props->clr_port_cap_mask;
1584
1585         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1586
1587 out:
1588         mutex_unlock(&dev->cap_mask_mutex);
1589         return err;
1590 }
1591
1592 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1593 {
1594         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1595                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1596 }
1597
1598 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1599 {
1600         /* Large page with non 4k uar support might limit the dynamic size */
1601         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1602                 return MLX5_MIN_DYN_BFREGS;
1603
1604         return MLX5_MAX_DYN_BFREGS;
1605 }
1606
1607 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1608                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1609                              struct mlx5_bfreg_info *bfregi)
1610 {
1611         int uars_per_sys_page;
1612         int bfregs_per_sys_page;
1613         int ref_bfregs = req->total_num_bfregs;
1614
1615         if (req->total_num_bfregs == 0)
1616                 return -EINVAL;
1617
1618         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1619         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1620
1621         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1622                 return -ENOMEM;
1623
1624         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1625         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1626         /* This holds the required static allocation asked by the user */
1627         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1628         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1629                 return -EINVAL;
1630
1631         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1632         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1633         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1634         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1635
1636         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1637                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1638                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1639                     req->total_num_bfregs, bfregi->total_num_bfregs,
1640                     bfregi->num_sys_pages);
1641
1642         return 0;
1643 }
1644
1645 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1646 {
1647         struct mlx5_bfreg_info *bfregi;
1648         int err;
1649         int i;
1650
1651         bfregi = &context->bfregi;
1652         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1653                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1654                 if (err)
1655                         goto error;
1656
1657                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1658         }
1659
1660         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1661                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1662
1663         return 0;
1664
1665 error:
1666         for (--i; i >= 0; i--)
1667                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1668                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1669
1670         return err;
1671 }
1672
1673 static void deallocate_uars(struct mlx5_ib_dev *dev,
1674                             struct mlx5_ib_ucontext *context)
1675 {
1676         struct mlx5_bfreg_info *bfregi;
1677         int i;
1678
1679         bfregi = &context->bfregi;
1680         for (i = 0; i < bfregi->num_sys_pages; i++)
1681                 if (i < bfregi->num_static_sys_pages ||
1682                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1683                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1684 }
1685
1686 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1687 {
1688         int err = 0;
1689
1690         mutex_lock(&dev->lb.mutex);
1691         if (td)
1692                 dev->lb.user_td++;
1693         if (qp)
1694                 dev->lb.qps++;
1695
1696         if (dev->lb.user_td == 2 ||
1697             dev->lb.qps == 1) {
1698                 if (!dev->lb.enabled) {
1699                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1700                         dev->lb.enabled = true;
1701                 }
1702         }
1703
1704         mutex_unlock(&dev->lb.mutex);
1705
1706         return err;
1707 }
1708
1709 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1710 {
1711         mutex_lock(&dev->lb.mutex);
1712         if (td)
1713                 dev->lb.user_td--;
1714         if (qp)
1715                 dev->lb.qps--;
1716
1717         if (dev->lb.user_td == 1 &&
1718             dev->lb.qps == 0) {
1719                 if (dev->lb.enabled) {
1720                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1721                         dev->lb.enabled = false;
1722                 }
1723         }
1724
1725         mutex_unlock(&dev->lb.mutex);
1726 }
1727
1728 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1729                                           u16 uid)
1730 {
1731         int err;
1732
1733         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1734                 return 0;
1735
1736         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1737         if (err)
1738                 return err;
1739
1740         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1741             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1742              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1743                 return err;
1744
1745         return mlx5_ib_enable_lb(dev, true, false);
1746 }
1747
1748 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1749                                              u16 uid)
1750 {
1751         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1752                 return;
1753
1754         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1755
1756         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1757             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1758              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1759                 return;
1760
1761         mlx5_ib_disable_lb(dev, true, false);
1762 }
1763
1764 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1765                                   struct ib_udata *udata)
1766 {
1767         struct ib_device *ibdev = uctx->device;
1768         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1769         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1770         struct mlx5_ib_alloc_ucontext_resp resp = {};
1771         struct mlx5_core_dev *mdev = dev->mdev;
1772         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1773         struct mlx5_bfreg_info *bfregi;
1774         int ver;
1775         int err;
1776         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1777                                      max_cqe_version);
1778         u32 dump_fill_mkey;
1779         bool lib_uar_4k;
1780
1781         if (!dev->ib_active)
1782                 return -EAGAIN;
1783
1784         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1785                 ver = 0;
1786         else if (udata->inlen >= min_req_v2)
1787                 ver = 2;
1788         else
1789                 return -EINVAL;
1790
1791         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1792         if (err)
1793                 return err;
1794
1795         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1796                 return -EOPNOTSUPP;
1797
1798         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1799                 return -EOPNOTSUPP;
1800
1801         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1802                                     MLX5_NON_FP_BFREGS_PER_UAR);
1803         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1804                 return -EINVAL;
1805
1806         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1807         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1808                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1809         resp.cache_line_size = cache_line_size();
1810         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1811         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1812         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1813         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1814         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1815         resp.cqe_version = min_t(__u8,
1816                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1817                                  req.max_cqe_version);
1818         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1819                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1820         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1821                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1822         resp.response_length = min(offsetof(typeof(resp), response_length) +
1823                                    sizeof(resp.response_length), udata->outlen);
1824
1825         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1826                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1827                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1828                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1829                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1830                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1831                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1832                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1833                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1834                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1835         }
1836
1837         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1838         bfregi = &context->bfregi;
1839
1840         /* updates req->total_num_bfregs */
1841         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1842         if (err)
1843                 goto out_ctx;
1844
1845         mutex_init(&bfregi->lock);
1846         bfregi->lib_uar_4k = lib_uar_4k;
1847         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1848                                 GFP_KERNEL);
1849         if (!bfregi->count) {
1850                 err = -ENOMEM;
1851                 goto out_ctx;
1852         }
1853
1854         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1855                                     sizeof(*bfregi->sys_pages),
1856                                     GFP_KERNEL);
1857         if (!bfregi->sys_pages) {
1858                 err = -ENOMEM;
1859                 goto out_count;
1860         }
1861
1862         err = allocate_uars(dev, context);
1863         if (err)
1864                 goto out_sys_pages;
1865
1866         if (ibdev->attrs.device_cap_flags & IB_DEVICE_ON_DEMAND_PAGING)
1867                 context->ibucontext.invalidate_range =
1868                         &mlx5_ib_invalidate_range;
1869
1870         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1871                 err = mlx5_ib_devx_create(dev, true);
1872                 if (err < 0)
1873                         goto out_uars;
1874                 context->devx_uid = err;
1875         }
1876
1877         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1878                                              context->devx_uid);
1879         if (err)
1880                 goto out_devx;
1881
1882         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1883                 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1884                 if (err)
1885                         goto out_mdev;
1886         }
1887
1888         INIT_LIST_HEAD(&context->db_page_list);
1889         mutex_init(&context->db_page_mutex);
1890
1891         resp.tot_bfregs = req.total_num_bfregs;
1892         resp.num_ports = dev->num_ports;
1893
1894         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1895                 resp.response_length += sizeof(resp.cqe_version);
1896
1897         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1898                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1899                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1900                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1901         }
1902
1903         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1904                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1905                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1906                         resp.eth_min_inline++;
1907                 }
1908                 resp.response_length += sizeof(resp.eth_min_inline);
1909         }
1910
1911         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1912                 if (mdev->clock_info)
1913                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1914                 resp.response_length += sizeof(resp.clock_info_versions);
1915         }
1916
1917         /*
1918          * We don't want to expose information from the PCI bar that is located
1919          * after 4096 bytes, so if the arch only supports larger pages, let's
1920          * pretend we don't support reading the HCA's core clock. This is also
1921          * forced by mmap function.
1922          */
1923         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1924                 if (PAGE_SIZE <= 4096) {
1925                         resp.comp_mask |=
1926                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1927                         resp.hca_core_clock_offset =
1928                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1929                 }
1930                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1931         }
1932
1933         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1934                 resp.response_length += sizeof(resp.log_uar_size);
1935
1936         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1937                 resp.response_length += sizeof(resp.num_uars_per_page);
1938
1939         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1940                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1941                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1942         }
1943
1944         if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1945                 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1946                         resp.dump_fill_mkey = dump_fill_mkey;
1947                         resp.comp_mask |=
1948                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1949                 }
1950                 resp.response_length += sizeof(resp.dump_fill_mkey);
1951         }
1952
1953         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1954         if (err)
1955                 goto out_mdev;
1956
1957         bfregi->ver = ver;
1958         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1959         context->cqe_version = resp.cqe_version;
1960         context->lib_caps = req.lib_caps;
1961         print_lib_caps(dev, context->lib_caps);
1962
1963         if (dev->lag_active) {
1964                 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1965
1966                 atomic_set(&context->tx_port_affinity,
1967                            atomic_add_return(
1968                                    1, &dev->port[port].roce.tx_port_affinity));
1969         }
1970
1971         return 0;
1972
1973 out_mdev:
1974         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1975 out_devx:
1976         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1977                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1978
1979 out_uars:
1980         deallocate_uars(dev, context);
1981
1982 out_sys_pages:
1983         kfree(bfregi->sys_pages);
1984
1985 out_count:
1986         kfree(bfregi->count);
1987
1988 out_ctx:
1989         return err;
1990 }
1991
1992 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1993 {
1994         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1995         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1996         struct mlx5_bfreg_info *bfregi;
1997
1998         /* All umem's must be destroyed before destroying the ucontext. */
1999         mutex_lock(&ibcontext->per_mm_list_lock);
2000         WARN_ON(!list_empty(&ibcontext->per_mm_list));
2001         mutex_unlock(&ibcontext->per_mm_list_lock);
2002
2003         bfregi = &context->bfregi;
2004         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2005
2006         if (context->devx_uid)
2007                 mlx5_ib_devx_destroy(dev, context->devx_uid);
2008
2009         deallocate_uars(dev, context);
2010         kfree(bfregi->sys_pages);
2011         kfree(bfregi->count);
2012 }
2013
2014 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2015                                  int uar_idx)
2016 {
2017         int fw_uars_per_page;
2018
2019         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2020
2021         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2022 }
2023
2024 static int get_command(unsigned long offset)
2025 {
2026         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2027 }
2028
2029 static int get_arg(unsigned long offset)
2030 {
2031         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2032 }
2033
2034 static int get_index(unsigned long offset)
2035 {
2036         return get_arg(offset);
2037 }
2038
2039 /* Index resides in an extra byte to enable larger values than 255 */
2040 static int get_extended_index(unsigned long offset)
2041 {
2042         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2043 }
2044
2045
2046 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2047 {
2048 }
2049
2050 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2051 {
2052         switch (cmd) {
2053         case MLX5_IB_MMAP_WC_PAGE:
2054                 return "WC";
2055         case MLX5_IB_MMAP_REGULAR_PAGE:
2056                 return "best effort WC";
2057         case MLX5_IB_MMAP_NC_PAGE:
2058                 return "NC";
2059         case MLX5_IB_MMAP_DEVICE_MEM:
2060                 return "Device Memory";
2061         default:
2062                 return NULL;
2063         }
2064 }
2065
2066 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2067                                         struct vm_area_struct *vma,
2068                                         struct mlx5_ib_ucontext *context)
2069 {
2070         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2071             !(vma->vm_flags & VM_SHARED))
2072                 return -EINVAL;
2073
2074         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2075                 return -EOPNOTSUPP;
2076
2077         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2078                 return -EPERM;
2079         vma->vm_flags &= ~VM_MAYWRITE;
2080
2081         if (!dev->mdev->clock_info)
2082                 return -EOPNOTSUPP;
2083
2084         return vm_insert_page(vma, vma->vm_start,
2085                               virt_to_page(dev->mdev->clock_info));
2086 }
2087
2088 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2089                     struct vm_area_struct *vma,
2090                     struct mlx5_ib_ucontext *context)
2091 {
2092         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2093         int err;
2094         unsigned long idx;
2095         phys_addr_t pfn;
2096         pgprot_t prot;
2097         u32 bfreg_dyn_idx = 0;
2098         u32 uar_index;
2099         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2100         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2101                                 bfregi->num_static_sys_pages;
2102
2103         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2104                 return -EINVAL;
2105
2106         if (dyn_uar)
2107                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2108         else
2109                 idx = get_index(vma->vm_pgoff);
2110
2111         if (idx >= max_valid_idx) {
2112                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2113                              idx, max_valid_idx);
2114                 return -EINVAL;
2115         }
2116
2117         switch (cmd) {
2118         case MLX5_IB_MMAP_WC_PAGE:
2119         case MLX5_IB_MMAP_ALLOC_WC:
2120 /* Some architectures don't support WC memory */
2121 #if defined(CONFIG_X86)
2122                 if (!pat_enabled())
2123                         return -EPERM;
2124 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2125                         return -EPERM;
2126 #endif
2127         /* fall through */
2128         case MLX5_IB_MMAP_REGULAR_PAGE:
2129                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2130                 prot = pgprot_writecombine(vma->vm_page_prot);
2131                 break;
2132         case MLX5_IB_MMAP_NC_PAGE:
2133                 prot = pgprot_noncached(vma->vm_page_prot);
2134                 break;
2135         default:
2136                 return -EINVAL;
2137         }
2138
2139         if (dyn_uar) {
2140                 int uars_per_page;
2141
2142                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2143                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2144                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2145                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2146                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2147                         return -EINVAL;
2148                 }
2149
2150                 mutex_lock(&bfregi->lock);
2151                 /* Fail if uar already allocated, first bfreg index of each
2152                  * page holds its count.
2153                  */
2154                 if (bfregi->count[bfreg_dyn_idx]) {
2155                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2156                         mutex_unlock(&bfregi->lock);
2157                         return -EINVAL;
2158                 }
2159
2160                 bfregi->count[bfreg_dyn_idx]++;
2161                 mutex_unlock(&bfregi->lock);
2162
2163                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2164                 if (err) {
2165                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2166                         goto free_bfreg;
2167                 }
2168         } else {
2169                 uar_index = bfregi->sys_pages[idx];
2170         }
2171
2172         pfn = uar_index2pfn(dev, uar_index);
2173         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2174
2175         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2176                                 prot);
2177         if (err) {
2178                 mlx5_ib_err(dev,
2179                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2180                             err, mmap_cmd2str(cmd));
2181                 goto err;
2182         }
2183
2184         if (dyn_uar)
2185                 bfregi->sys_pages[idx] = uar_index;
2186         return 0;
2187
2188 err:
2189         if (!dyn_uar)
2190                 return err;
2191
2192         mlx5_cmd_free_uar(dev->mdev, idx);
2193
2194 free_bfreg:
2195         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2196
2197         return err;
2198 }
2199
2200 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2201 {
2202         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2203         struct mlx5_ib_dev *dev = to_mdev(context->device);
2204         u16 page_idx = get_extended_index(vma->vm_pgoff);
2205         size_t map_size = vma->vm_end - vma->vm_start;
2206         u32 npages = map_size >> PAGE_SHIFT;
2207         phys_addr_t pfn;
2208
2209         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2210             page_idx + npages)
2211                 return -EINVAL;
2212
2213         pfn = ((dev->mdev->bar_addr +
2214               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2215               PAGE_SHIFT) +
2216               page_idx;
2217         return rdma_user_mmap_io(context, vma, pfn, map_size,
2218                                  pgprot_writecombine(vma->vm_page_prot));
2219 }
2220
2221 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2222 {
2223         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2224         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2225         unsigned long command;
2226         phys_addr_t pfn;
2227
2228         command = get_command(vma->vm_pgoff);
2229         switch (command) {
2230         case MLX5_IB_MMAP_WC_PAGE:
2231         case MLX5_IB_MMAP_NC_PAGE:
2232         case MLX5_IB_MMAP_REGULAR_PAGE:
2233         case MLX5_IB_MMAP_ALLOC_WC:
2234                 return uar_mmap(dev, command, vma, context);
2235
2236         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2237                 return -ENOSYS;
2238
2239         case MLX5_IB_MMAP_CORE_CLOCK:
2240                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2241                         return -EINVAL;
2242
2243                 if (vma->vm_flags & VM_WRITE)
2244                         return -EPERM;
2245                 vma->vm_flags &= ~VM_MAYWRITE;
2246
2247                 /* Don't expose to user-space information it shouldn't have */
2248                 if (PAGE_SIZE > 4096)
2249                         return -EOPNOTSUPP;
2250
2251                 pfn = (dev->mdev->iseg_base +
2252                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2253                         PAGE_SHIFT;
2254                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2255                                          PAGE_SIZE,
2256                                          pgprot_noncached(vma->vm_page_prot));
2257         case MLX5_IB_MMAP_CLOCK_INFO:
2258                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2259
2260         case MLX5_IB_MMAP_DEVICE_MEM:
2261                 return dm_mmap(ibcontext, vma);
2262
2263         default:
2264                 return -EINVAL;
2265         }
2266
2267         return 0;
2268 }
2269
2270 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2271                                         u32 type)
2272 {
2273         switch (type) {
2274         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2275                 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2276                         return -EOPNOTSUPP;
2277                 break;
2278         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2279                 if (!capable(CAP_SYS_RAWIO) ||
2280                     !capable(CAP_NET_RAW))
2281                         return -EPERM;
2282
2283                 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2284                       MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2285                         return -EOPNOTSUPP;
2286                 break;
2287         }
2288
2289         return 0;
2290 }
2291
2292 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2293                                  struct mlx5_ib_dm *dm,
2294                                  struct ib_dm_alloc_attr *attr,
2295                                  struct uverbs_attr_bundle *attrs)
2296 {
2297         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2298         u64 start_offset;
2299         u32 page_idx;
2300         int err;
2301
2302         dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2303
2304         err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2305                                    dm->size, attr->alignment);
2306         if (err)
2307                 return err;
2308
2309         page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2310                     MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
2311                     PAGE_SHIFT;
2312
2313         err = uverbs_copy_to(attrs,
2314                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2315                              &page_idx, sizeof(page_idx));
2316         if (err)
2317                 goto err_dealloc;
2318
2319         start_offset = dm->dev_addr & ~PAGE_MASK;
2320         err = uverbs_copy_to(attrs,
2321                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2322                              &start_offset, sizeof(start_offset));
2323         if (err)
2324                 goto err_dealloc;
2325
2326         bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2327                    DIV_ROUND_UP(dm->size, PAGE_SIZE));
2328
2329         return 0;
2330
2331 err_dealloc:
2332         mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2333
2334         return err;
2335 }
2336
2337 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2338                                   struct mlx5_ib_dm *dm,
2339                                   struct ib_dm_alloc_attr *attr,
2340                                   struct uverbs_attr_bundle *attrs,
2341                                   int type)
2342 {
2343         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2344         u64 act_size;
2345         int err;
2346
2347         /* Allocation size must a multiple of the basic block size
2348          * and a power of 2.
2349          */
2350         act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dm_db->dev));
2351         act_size = roundup_pow_of_two(act_size);
2352
2353         dm->size = act_size;
2354         err = mlx5_cmd_alloc_sw_icm(dm_db, type, act_size,
2355                                     to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2356                                     &dm->icm_dm.obj_id);
2357         if (err)
2358                 return err;
2359
2360         err = uverbs_copy_to(attrs,
2361                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2362                              &dm->dev_addr, sizeof(dm->dev_addr));
2363         if (err)
2364                 mlx5_cmd_dealloc_sw_icm(dm_db, type, dm->size,
2365                                         to_mucontext(ctx)->devx_uid,
2366                                         dm->dev_addr, dm->icm_dm.obj_id);
2367
2368         return err;
2369 }
2370
2371 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2372                                struct ib_ucontext *context,
2373                                struct ib_dm_alloc_attr *attr,
2374                                struct uverbs_attr_bundle *attrs)
2375 {
2376         struct mlx5_ib_dm *dm;
2377         enum mlx5_ib_uapi_dm_type type;
2378         int err;
2379
2380         err = uverbs_get_const_default(&type, attrs,
2381                                        MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2382                                        MLX5_IB_UAPI_DM_TYPE_MEMIC);
2383         if (err)
2384                 return ERR_PTR(err);
2385
2386         mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2387                     type, attr->length, attr->alignment);
2388
2389         err = check_dm_type_support(to_mdev(ibdev), type);
2390         if (err)
2391                 return ERR_PTR(err);
2392
2393         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2394         if (!dm)
2395                 return ERR_PTR(-ENOMEM);
2396
2397         dm->type = type;
2398
2399         switch (type) {
2400         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2401                 err = handle_alloc_dm_memic(context, dm,
2402                                             attr,
2403                                             attrs);
2404                 break;
2405         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2406         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2407                 err = handle_alloc_dm_sw_icm(context, dm, attr, attrs, type);
2408                 break;
2409         default:
2410                 err = -EOPNOTSUPP;
2411         }
2412
2413         if (err)
2414                 goto err_free;
2415
2416         return &dm->ibdm;
2417
2418 err_free:
2419         kfree(dm);
2420         return ERR_PTR(err);
2421 }
2422
2423 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2424 {
2425         struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2426                 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2427         struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
2428         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2429         u32 page_idx;
2430         int ret;
2431
2432         switch (dm->type) {
2433         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2434                 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2435                 if (ret)
2436                         return ret;
2437
2438                 page_idx = (dm->dev_addr -
2439                             pci_resource_start(dm_db->dev->pdev, 0) -
2440                             MLX5_CAP64_DEV_MEM(dm_db->dev,
2441                                                memic_bar_start_addr)) >>
2442                            PAGE_SHIFT;
2443                 bitmap_clear(ctx->dm_pages, page_idx,
2444                              DIV_ROUND_UP(dm->size, PAGE_SIZE));
2445                 break;
2446         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2447         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2448                 ret = mlx5_cmd_dealloc_sw_icm(dm_db, dm->type, dm->size,
2449                                               ctx->devx_uid, dm->dev_addr,
2450                                               dm->icm_dm.obj_id);
2451                 if (ret)
2452                         return ret;
2453                 break;
2454         default:
2455                 return -EOPNOTSUPP;
2456         }
2457
2458         kfree(dm);
2459
2460         return 0;
2461 }
2462
2463 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2464 {
2465         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2466         struct ib_device *ibdev = ibpd->device;
2467         struct mlx5_ib_alloc_pd_resp resp;
2468         int err;
2469         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2470         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)]   = {};
2471         u16 uid = 0;
2472         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2473                 udata, struct mlx5_ib_ucontext, ibucontext);
2474
2475         uid = context ? context->devx_uid : 0;
2476         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2477         MLX5_SET(alloc_pd_in, in, uid, uid);
2478         err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2479                             out, sizeof(out));
2480         if (err)
2481                 return err;
2482
2483         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2484         pd->uid = uid;
2485         if (udata) {
2486                 resp.pdn = pd->pdn;
2487                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2488                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2489                         return -EFAULT;
2490                 }
2491         }
2492
2493         return 0;
2494 }
2495
2496 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2497 {
2498         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2499         struct mlx5_ib_pd *mpd = to_mpd(pd);
2500
2501         mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2502 }
2503
2504 enum {
2505         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2506         MATCH_CRITERIA_ENABLE_MISC_BIT,
2507         MATCH_CRITERIA_ENABLE_INNER_BIT,
2508         MATCH_CRITERIA_ENABLE_MISC2_BIT
2509 };
2510
2511 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2512         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2513                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2514
2515 static u8 get_match_criteria_enable(u32 *match_criteria)
2516 {
2517         u8 match_criteria_enable;
2518
2519         match_criteria_enable =
2520                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2521                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2522         match_criteria_enable |=
2523                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2524                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2525         match_criteria_enable |=
2526                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2527                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2528         match_criteria_enable |=
2529                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2530                 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2531
2532         return match_criteria_enable;
2533 }
2534
2535 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2536 {
2537         u8 entry_mask;
2538         u8 entry_val;
2539         int err = 0;
2540
2541         if (!mask)
2542                 goto out;
2543
2544         entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2545                               ip_protocol);
2546         entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2547                              ip_protocol);
2548         if (!entry_mask) {
2549                 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2550                 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2551                 goto out;
2552         }
2553         /* Don't override existing ip protocol */
2554         if (mask != entry_mask || val != entry_val)
2555                 err = -EINVAL;
2556 out:
2557         return err;
2558 }
2559
2560 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2561                            bool inner)
2562 {
2563         if (inner) {
2564                 MLX5_SET(fte_match_set_misc,
2565                          misc_c, inner_ipv6_flow_label, mask);
2566                 MLX5_SET(fte_match_set_misc,
2567                          misc_v, inner_ipv6_flow_label, val);
2568         } else {
2569                 MLX5_SET(fte_match_set_misc,
2570                          misc_c, outer_ipv6_flow_label, mask);
2571                 MLX5_SET(fte_match_set_misc,
2572                          misc_v, outer_ipv6_flow_label, val);
2573         }
2574 }
2575
2576 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2577 {
2578         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2579         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2580         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2581         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2582 }
2583
2584 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2585 {
2586         if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2587             !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2588                 return -EOPNOTSUPP;
2589
2590         if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2591             !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2592                 return -EOPNOTSUPP;
2593
2594         if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2595             !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2596                 return -EOPNOTSUPP;
2597
2598         if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2599             !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2600                 return -EOPNOTSUPP;
2601
2602         return 0;
2603 }
2604
2605 #define LAST_ETH_FIELD vlan_tag
2606 #define LAST_IB_FIELD sl
2607 #define LAST_IPV4_FIELD tos
2608 #define LAST_IPV6_FIELD traffic_class
2609 #define LAST_TCP_UDP_FIELD src_port
2610 #define LAST_TUNNEL_FIELD tunnel_id
2611 #define LAST_FLOW_TAG_FIELD tag_id
2612 #define LAST_DROP_FIELD size
2613 #define LAST_COUNTERS_FIELD counters
2614
2615 /* Field is the last supported field */
2616 #define FIELDS_NOT_SUPPORTED(filter, field)\
2617         memchr_inv((void *)&filter.field  +\
2618                    sizeof(filter.field), 0,\
2619                    sizeof(filter) -\
2620                    offsetof(typeof(filter), field) -\
2621                    sizeof(filter.field))
2622
2623 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2624                            bool is_egress,
2625                            struct mlx5_flow_act *action)
2626 {
2627
2628         switch (maction->ib_action.type) {
2629         case IB_FLOW_ACTION_ESP:
2630                 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2631                                       MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2632                         return -EINVAL;
2633                 /* Currently only AES_GCM keymat is supported by the driver */
2634                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2635                 action->action |= is_egress ?
2636                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2637                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2638                 return 0;
2639         case IB_FLOW_ACTION_UNSPECIFIED:
2640                 if (maction->flow_action_raw.sub_type ==
2641                     MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2642                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2643                                 return -EINVAL;
2644                         action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2645                         action->modify_id = maction->flow_action_raw.action_id;
2646                         return 0;
2647                 }
2648                 if (maction->flow_action_raw.sub_type ==
2649                     MLX5_IB_FLOW_ACTION_DECAP) {
2650                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2651                                 return -EINVAL;
2652                         action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2653                         return 0;
2654                 }
2655                 if (maction->flow_action_raw.sub_type ==
2656                     MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2657                         if (action->action &
2658                             MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2659                                 return -EINVAL;
2660                         action->action |=
2661                                 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2662                         action->reformat_id =
2663                                 maction->flow_action_raw.action_id;
2664                         return 0;
2665                 }
2666                 /* fall through */
2667         default:
2668                 return -EOPNOTSUPP;
2669         }
2670 }
2671
2672 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2673                            u32 *match_v, const union ib_flow_spec *ib_spec,
2674                            const struct ib_flow_attr *flow_attr,
2675                            struct mlx5_flow_act *action, u32 prev_type)
2676 {
2677         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2678                                            misc_parameters);
2679         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2680                                            misc_parameters);
2681         void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2682                                             misc_parameters_2);
2683         void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2684                                             misc_parameters_2);
2685         void *headers_c;
2686         void *headers_v;
2687         int match_ipv;
2688         int ret;
2689
2690         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2691                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2692                                          inner_headers);
2693                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2694                                          inner_headers);
2695                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2696                                         ft_field_support.inner_ip_version);
2697         } else {
2698                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2699                                          outer_headers);
2700                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2701                                          outer_headers);
2702                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2703                                         ft_field_support.outer_ip_version);
2704         }
2705
2706         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2707         case IB_FLOW_SPEC_ETH:
2708                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2709                         return -EOPNOTSUPP;
2710
2711                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2712                                              dmac_47_16),
2713                                 ib_spec->eth.mask.dst_mac);
2714                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2715                                              dmac_47_16),
2716                                 ib_spec->eth.val.dst_mac);
2717
2718                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2719                                              smac_47_16),
2720                                 ib_spec->eth.mask.src_mac);
2721                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2722                                              smac_47_16),
2723                                 ib_spec->eth.val.src_mac);
2724
2725                 if (ib_spec->eth.mask.vlan_tag) {
2726                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2727                                  cvlan_tag, 1);
2728                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2729                                  cvlan_tag, 1);
2730
2731                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2732                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2733                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2734                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2735
2736                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2737                                  first_cfi,
2738                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2739                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2740                                  first_cfi,
2741                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2742
2743                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2744                                  first_prio,
2745                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2746                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2747                                  first_prio,
2748                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2749                 }
2750                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2751                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2752                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2753                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2754                 break;
2755         case IB_FLOW_SPEC_IPV4:
2756                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2757                         return -EOPNOTSUPP;
2758
2759                 if (match_ipv) {
2760                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2761                                  ip_version, 0xf);
2762                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2763                                  ip_version, MLX5_FS_IPV4_VERSION);
2764                 } else {
2765                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2766                                  ethertype, 0xffff);
2767                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2768                                  ethertype, ETH_P_IP);
2769                 }
2770
2771                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2772                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2773                        &ib_spec->ipv4.mask.src_ip,
2774                        sizeof(ib_spec->ipv4.mask.src_ip));
2775                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2776                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2777                        &ib_spec->ipv4.val.src_ip,
2778                        sizeof(ib_spec->ipv4.val.src_ip));
2779                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2780                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2781                        &ib_spec->ipv4.mask.dst_ip,
2782                        sizeof(ib_spec->ipv4.mask.dst_ip));
2783                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2784                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2785                        &ib_spec->ipv4.val.dst_ip,
2786                        sizeof(ib_spec->ipv4.val.dst_ip));
2787
2788                 set_tos(headers_c, headers_v,
2789                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2790
2791                 if (set_proto(headers_c, headers_v,
2792                               ib_spec->ipv4.mask.proto,
2793                               ib_spec->ipv4.val.proto))
2794                         return -EINVAL;
2795                 break;
2796         case IB_FLOW_SPEC_IPV6:
2797                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2798                         return -EOPNOTSUPP;
2799
2800                 if (match_ipv) {
2801                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2802                                  ip_version, 0xf);
2803                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2804                                  ip_version, MLX5_FS_IPV6_VERSION);
2805                 } else {
2806                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2807                                  ethertype, 0xffff);
2808                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2809                                  ethertype, ETH_P_IPV6);
2810                 }
2811
2812                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2813                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2814                        &ib_spec->ipv6.mask.src_ip,
2815                        sizeof(ib_spec->ipv6.mask.src_ip));
2816                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2817                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2818                        &ib_spec->ipv6.val.src_ip,
2819                        sizeof(ib_spec->ipv6.val.src_ip));
2820                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2821                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2822                        &ib_spec->ipv6.mask.dst_ip,
2823                        sizeof(ib_spec->ipv6.mask.dst_ip));
2824                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2825                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2826                        &ib_spec->ipv6.val.dst_ip,
2827                        sizeof(ib_spec->ipv6.val.dst_ip));
2828
2829                 set_tos(headers_c, headers_v,
2830                         ib_spec->ipv6.mask.traffic_class,
2831                         ib_spec->ipv6.val.traffic_class);
2832
2833                 if (set_proto(headers_c, headers_v,
2834                               ib_spec->ipv6.mask.next_hdr,
2835                               ib_spec->ipv6.val.next_hdr))
2836                         return -EINVAL;
2837
2838                 set_flow_label(misc_params_c, misc_params_v,
2839                                ntohl(ib_spec->ipv6.mask.flow_label),
2840                                ntohl(ib_spec->ipv6.val.flow_label),
2841                                ib_spec->type & IB_FLOW_SPEC_INNER);
2842                 break;
2843         case IB_FLOW_SPEC_ESP:
2844                 if (ib_spec->esp.mask.seq)
2845                         return -EOPNOTSUPP;
2846
2847                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2848                          ntohl(ib_spec->esp.mask.spi));
2849                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2850                          ntohl(ib_spec->esp.val.spi));
2851                 break;
2852         case IB_FLOW_SPEC_TCP:
2853                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2854                                          LAST_TCP_UDP_FIELD))
2855                         return -EOPNOTSUPP;
2856
2857                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2858                         return -EINVAL;
2859
2860                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2861                          ntohs(ib_spec->tcp_udp.mask.src_port));
2862                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2863                          ntohs(ib_spec->tcp_udp.val.src_port));
2864
2865                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2866                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2867                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2868                          ntohs(ib_spec->tcp_udp.val.dst_port));
2869                 break;
2870         case IB_FLOW_SPEC_UDP:
2871                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2872                                          LAST_TCP_UDP_FIELD))
2873                         return -EOPNOTSUPP;
2874
2875                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2876                         return -EINVAL;
2877
2878                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2879                          ntohs(ib_spec->tcp_udp.mask.src_port));
2880                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2881                          ntohs(ib_spec->tcp_udp.val.src_port));
2882
2883                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2884                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2885                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2886                          ntohs(ib_spec->tcp_udp.val.dst_port));
2887                 break;
2888         case IB_FLOW_SPEC_GRE:
2889                 if (ib_spec->gre.mask.c_ks_res0_ver)
2890                         return -EOPNOTSUPP;
2891
2892                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2893                         return -EINVAL;
2894
2895                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2896                          0xff);
2897                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2898                          IPPROTO_GRE);
2899
2900                 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2901                          ntohs(ib_spec->gre.mask.protocol));
2902                 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2903                          ntohs(ib_spec->gre.val.protocol));
2904
2905                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2906                                     gre_key.nvgre.hi),
2907                        &ib_spec->gre.mask.key,
2908                        sizeof(ib_spec->gre.mask.key));
2909                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2910                                     gre_key.nvgre.hi),
2911                        &ib_spec->gre.val.key,
2912                        sizeof(ib_spec->gre.val.key));
2913                 break;
2914         case IB_FLOW_SPEC_MPLS:
2915                 switch (prev_type) {
2916                 case IB_FLOW_SPEC_UDP:
2917                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2918                                                    ft_field_support.outer_first_mpls_over_udp),
2919                                                    &ib_spec->mpls.mask.tag))
2920                                 return -EOPNOTSUPP;
2921
2922                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2923                                             outer_first_mpls_over_udp),
2924                                &ib_spec->mpls.val.tag,
2925                                sizeof(ib_spec->mpls.val.tag));
2926                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2927                                             outer_first_mpls_over_udp),
2928                                &ib_spec->mpls.mask.tag,
2929                                sizeof(ib_spec->mpls.mask.tag));
2930                         break;
2931                 case IB_FLOW_SPEC_GRE:
2932                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2933                                                    ft_field_support.outer_first_mpls_over_gre),
2934                                                    &ib_spec->mpls.mask.tag))
2935                                 return -EOPNOTSUPP;
2936
2937                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2938                                             outer_first_mpls_over_gre),
2939                                &ib_spec->mpls.val.tag,
2940                                sizeof(ib_spec->mpls.val.tag));
2941                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2942                                             outer_first_mpls_over_gre),
2943                                &ib_spec->mpls.mask.tag,
2944                                sizeof(ib_spec->mpls.mask.tag));
2945                         break;
2946                 default:
2947                         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2948                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2949                                                            ft_field_support.inner_first_mpls),
2950                                                            &ib_spec->mpls.mask.tag))
2951                                         return -EOPNOTSUPP;
2952
2953                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2954                                                     inner_first_mpls),
2955                                        &ib_spec->mpls.val.tag,
2956                                        sizeof(ib_spec->mpls.val.tag));
2957                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2958                                                     inner_first_mpls),
2959                                        &ib_spec->mpls.mask.tag,
2960                                        sizeof(ib_spec->mpls.mask.tag));
2961                         } else {
2962                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2963                                                            ft_field_support.outer_first_mpls),
2964                                                            &ib_spec->mpls.mask.tag))
2965                                         return -EOPNOTSUPP;
2966
2967                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2968                                                     outer_first_mpls),
2969                                        &ib_spec->mpls.val.tag,
2970                                        sizeof(ib_spec->mpls.val.tag));
2971                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2972                                                     outer_first_mpls),
2973                                        &ib_spec->mpls.mask.tag,
2974                                        sizeof(ib_spec->mpls.mask.tag));
2975                         }
2976                 }
2977                 break;
2978         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2979                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2980                                          LAST_TUNNEL_FIELD))
2981                         return -EOPNOTSUPP;
2982
2983                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2984                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2985                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2986                          ntohl(ib_spec->tunnel.val.tunnel_id));
2987                 break;
2988         case IB_FLOW_SPEC_ACTION_TAG:
2989                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2990                                          LAST_FLOW_TAG_FIELD))
2991                         return -EOPNOTSUPP;
2992                 if (ib_spec->flow_tag.tag_id >= BIT(24))
2993                         return -EINVAL;
2994
2995                 action->flow_tag = ib_spec->flow_tag.tag_id;
2996                 action->flags |= FLOW_ACT_HAS_TAG;
2997                 break;
2998         case IB_FLOW_SPEC_ACTION_DROP:
2999                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3000                                          LAST_DROP_FIELD))
3001                         return -EOPNOTSUPP;
3002                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3003                 break;
3004         case IB_FLOW_SPEC_ACTION_HANDLE:
3005                 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3006                         flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
3007                 if (ret)
3008                         return ret;
3009                 break;
3010         case IB_FLOW_SPEC_ACTION_COUNT:
3011                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3012                                          LAST_COUNTERS_FIELD))
3013                         return -EOPNOTSUPP;
3014
3015                 /* for now support only one counters spec per flow */
3016                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3017                         return -EINVAL;
3018
3019                 action->counters = ib_spec->flow_count.counters;
3020                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3021                 break;
3022         default:
3023                 return -EINVAL;
3024         }
3025
3026         return 0;
3027 }
3028
3029 /* If a flow could catch both multicast and unicast packets,
3030  * it won't fall into the multicast flow steering table and this rule
3031  * could steal other multicast packets.
3032  */
3033 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
3034 {
3035         union ib_flow_spec *flow_spec;
3036
3037         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
3038             ib_attr->num_of_specs < 1)
3039                 return false;
3040
3041         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3042         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3043                 struct ib_flow_spec_ipv4 *ipv4_spec;
3044
3045                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3046                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3047                         return true;
3048
3049                 return false;
3050         }
3051
3052         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3053                 struct ib_flow_spec_eth *eth_spec;
3054
3055                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3056                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3057                        is_multicast_ether_addr(eth_spec->val.dst_mac);
3058         }
3059
3060         return false;
3061 }
3062
3063 enum valid_spec {
3064         VALID_SPEC_INVALID,
3065         VALID_SPEC_VALID,
3066         VALID_SPEC_NA,
3067 };
3068
3069 static enum valid_spec
3070 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3071                      const struct mlx5_flow_spec *spec,
3072                      const struct mlx5_flow_act *flow_act,
3073                      bool egress)
3074 {
3075         const u32 *match_c = spec->match_criteria;
3076         bool is_crypto =
3077                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3078                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3079         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3080         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3081
3082         /*
3083          * Currently only crypto is supported in egress, when regular egress
3084          * rules would be supported, always return VALID_SPEC_NA.
3085          */
3086         if (!is_crypto)
3087                 return VALID_SPEC_NA;
3088
3089         return is_crypto && is_ipsec &&
3090                 (!egress || (!is_drop && !(flow_act->flags & FLOW_ACT_HAS_TAG))) ?
3091                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3092 }
3093
3094 static bool is_valid_spec(struct mlx5_core_dev *mdev,
3095                           const struct mlx5_flow_spec *spec,
3096                           const struct mlx5_flow_act *flow_act,
3097                           bool egress)
3098 {
3099         /* We curretly only support ipsec egress flow */
3100         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3101 }
3102
3103 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3104                                const struct ib_flow_attr *flow_attr,
3105                                bool check_inner)
3106 {
3107         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
3108         int match_ipv = check_inner ?
3109                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3110                                         ft_field_support.inner_ip_version) :
3111                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3112                                         ft_field_support.outer_ip_version);
3113         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3114         bool ipv4_spec_valid, ipv6_spec_valid;
3115         unsigned int ip_spec_type = 0;
3116         bool has_ethertype = false;
3117         unsigned int spec_index;
3118         bool mask_valid = true;
3119         u16 eth_type = 0;
3120         bool type_valid;
3121
3122         /* Validate that ethertype is correct */
3123         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3124                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
3125                     ib_spec->eth.mask.ether_type) {
3126                         mask_valid = (ib_spec->eth.mask.ether_type ==
3127                                       htons(0xffff));
3128                         has_ethertype = true;
3129                         eth_type = ntohs(ib_spec->eth.val.ether_type);
3130                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3131                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3132                         ip_spec_type = ib_spec->type;
3133                 }
3134                 ib_spec = (void *)ib_spec + ib_spec->size;
3135         }
3136
3137         type_valid = (!has_ethertype) || (!ip_spec_type);
3138         if (!type_valid && mask_valid) {
3139                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3140                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3141                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3142                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
3143
3144                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3145                              (((eth_type == ETH_P_MPLS_UC) ||
3146                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
3147         }
3148
3149         return type_valid;
3150 }
3151
3152 static bool is_valid_attr(struct mlx5_core_dev *mdev,
3153                           const struct ib_flow_attr *flow_attr)
3154 {
3155         return is_valid_ethertype(mdev, flow_attr, false) &&
3156                is_valid_ethertype(mdev, flow_attr, true);
3157 }
3158
3159 static void put_flow_table(struct mlx5_ib_dev *dev,
3160                            struct mlx5_ib_flow_prio *prio, bool ft_added)
3161 {
3162         prio->refcount -= !!ft_added;
3163         if (!prio->refcount) {
3164                 mlx5_destroy_flow_table(prio->flow_table);
3165                 prio->flow_table = NULL;
3166         }
3167 }
3168
3169 static void counters_clear_description(struct ib_counters *counters)
3170 {
3171         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3172
3173         mutex_lock(&mcounters->mcntrs_mutex);
3174         kfree(mcounters->counters_data);
3175         mcounters->counters_data = NULL;
3176         mcounters->cntrs_max_index = 0;
3177         mutex_unlock(&mcounters->mcntrs_mutex);
3178 }
3179
3180 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3181 {
3182         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3183                                                           struct mlx5_ib_flow_handler,
3184                                                           ibflow);
3185         struct mlx5_ib_flow_handler *iter, *tmp;
3186         struct mlx5_ib_dev *dev = handler->dev;
3187
3188         mutex_lock(&dev->flow_db->lock);
3189
3190         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3191                 mlx5_del_flow_rules(iter->rule);
3192                 put_flow_table(dev, iter->prio, true);
3193                 list_del(&iter->list);
3194                 kfree(iter);
3195         }
3196
3197         mlx5_del_flow_rules(handler->rule);
3198         put_flow_table(dev, handler->prio, true);
3199         if (handler->ibcounters &&
3200             atomic_read(&handler->ibcounters->usecnt) == 1)
3201                 counters_clear_description(handler->ibcounters);
3202
3203         mutex_unlock(&dev->flow_db->lock);
3204         if (handler->flow_matcher)
3205                 atomic_dec(&handler->flow_matcher->usecnt);
3206         kfree(handler);
3207
3208         return 0;
3209 }
3210
3211 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3212 {
3213         priority *= 2;
3214         if (!dont_trap)
3215                 priority++;
3216         return priority;
3217 }
3218
3219 enum flow_table_type {
3220         MLX5_IB_FT_RX,
3221         MLX5_IB_FT_TX
3222 };
3223
3224 #define MLX5_FS_MAX_TYPES        6
3225 #define MLX5_FS_MAX_ENTRIES      BIT(16)
3226
3227 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3228                                            struct mlx5_ib_flow_prio *prio,
3229                                            int priority,
3230                                            int num_entries, int num_groups,
3231                                            u32 flags)
3232 {
3233         struct mlx5_flow_table *ft;
3234
3235         ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3236                                                  num_entries,
3237                                                  num_groups,
3238                                                  0, flags);
3239         if (IS_ERR(ft))
3240                 return ERR_CAST(ft);
3241
3242         prio->flow_table = ft;
3243         prio->refcount = 0;
3244         return prio;
3245 }
3246
3247 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3248                                                 struct ib_flow_attr *flow_attr,
3249                                                 enum flow_table_type ft_type)
3250 {
3251         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3252         struct mlx5_flow_namespace *ns = NULL;
3253         struct mlx5_ib_flow_prio *prio;
3254         struct mlx5_flow_table *ft;
3255         int max_table_size;
3256         int num_entries;
3257         int num_groups;
3258         bool esw_encap;
3259         u32 flags = 0;
3260         int priority;
3261
3262         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3263                                                        log_max_ft_size));
3264         esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3265                 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3266         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3267                 enum mlx5_flow_namespace_type fn_type;
3268
3269                 if (flow_is_multicast_only(flow_attr) &&
3270                     !dont_trap)
3271                         priority = MLX5_IB_FLOW_MCAST_PRIO;
3272                 else
3273                         priority = ib_prio_to_core_prio(flow_attr->priority,
3274                                                         dont_trap);
3275                 if (ft_type == MLX5_IB_FT_RX) {
3276                         fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3277                         prio = &dev->flow_db->prios[priority];
3278                         if (!dev->is_rep && !esw_encap &&
3279                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3280                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3281                         if (!dev->is_rep && !esw_encap &&
3282                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3283                                         reformat_l3_tunnel_to_l2))
3284                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3285                 } else {
3286                         max_table_size =
3287                                 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3288                                                               log_max_ft_size));
3289                         fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3290                         prio = &dev->flow_db->egress_prios[priority];
3291                         if (!dev->is_rep && !esw_encap &&
3292                             MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3293                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3294                 }
3295                 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3296                 num_entries = MLX5_FS_MAX_ENTRIES;
3297                 num_groups = MLX5_FS_MAX_TYPES;
3298         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3299                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3300                 ns = mlx5_get_flow_namespace(dev->mdev,
3301                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
3302                 build_leftovers_ft_param(&priority,
3303                                          &num_entries,
3304                                          &num_groups);
3305                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3306         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3307                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3308                                         allow_sniffer_and_nic_rx_shared_tir))
3309                         return ERR_PTR(-ENOTSUPP);
3310
3311                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3312                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3313                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3314
3315                 prio = &dev->flow_db->sniffer[ft_type];
3316                 priority = 0;
3317                 num_entries = 1;
3318                 num_groups = 1;
3319         }
3320
3321         if (!ns)
3322                 return ERR_PTR(-ENOTSUPP);
3323
3324         max_table_size = min_t(int, num_entries, max_table_size);
3325
3326         ft = prio->flow_table;
3327         if (!ft)
3328                 return _get_prio(ns, prio, priority, max_table_size, num_groups,
3329                                  flags);
3330
3331         return prio;
3332 }
3333
3334 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3335                             struct mlx5_flow_spec *spec,
3336                             u32 underlay_qpn)
3337 {
3338         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3339                                            spec->match_criteria,
3340                                            misc_parameters);
3341         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3342                                            misc_parameters);
3343
3344         if (underlay_qpn &&
3345             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3346                                       ft_field_support.bth_dst_qp)) {
3347                 MLX5_SET(fte_match_set_misc,
3348                          misc_params_v, bth_dst_qp, underlay_qpn);
3349                 MLX5_SET(fte_match_set_misc,
3350                          misc_params_c, bth_dst_qp, 0xffffff);
3351         }
3352 }
3353
3354 static int read_flow_counters(struct ib_device *ibdev,
3355                               struct mlx5_read_counters_attr *read_attr)
3356 {
3357         struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3358         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3359
3360         return mlx5_fc_query(dev->mdev, fc,
3361                              &read_attr->out[IB_COUNTER_PACKETS],
3362                              &read_attr->out[IB_COUNTER_BYTES]);
3363 }
3364
3365 /* flow counters currently expose two counters packets and bytes */
3366 #define FLOW_COUNTERS_NUM 2
3367 static int counters_set_description(struct ib_counters *counters,
3368                                     enum mlx5_ib_counters_type counters_type,
3369                                     struct mlx5_ib_flow_counters_desc *desc_data,
3370                                     u32 ncounters)
3371 {
3372         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3373         u32 cntrs_max_index = 0;
3374         int i;
3375
3376         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3377                 return -EINVAL;
3378
3379         /* init the fields for the object */
3380         mcounters->type = counters_type;
3381         mcounters->read_counters = read_flow_counters;
3382         mcounters->counters_num = FLOW_COUNTERS_NUM;
3383         mcounters->ncounters = ncounters;
3384         /* each counter entry have both description and index pair */
3385         for (i = 0; i < ncounters; i++) {
3386                 if (desc_data[i].description > IB_COUNTER_BYTES)
3387                         return -EINVAL;
3388
3389                 if (cntrs_max_index <= desc_data[i].index)
3390                         cntrs_max_index = desc_data[i].index + 1;
3391         }
3392
3393         mutex_lock(&mcounters->mcntrs_mutex);
3394         mcounters->counters_data = desc_data;
3395         mcounters->cntrs_max_index = cntrs_max_index;
3396         mutex_unlock(&mcounters->mcntrs_mutex);
3397
3398         return 0;
3399 }
3400
3401 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3402 static int flow_counters_set_data(struct ib_counters *ibcounters,
3403                                   struct mlx5_ib_create_flow *ucmd)
3404 {
3405         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3406         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3407         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3408         bool hw_hndl = false;
3409         int ret = 0;
3410
3411         if (ucmd && ucmd->ncounters_data != 0) {
3412                 cntrs_data = ucmd->data;
3413                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3414                         return -EINVAL;
3415
3416                 desc_data = kcalloc(cntrs_data->ncounters,
3417                                     sizeof(*desc_data),
3418                                     GFP_KERNEL);
3419                 if (!desc_data)
3420                         return  -ENOMEM;
3421
3422                 if (copy_from_user(desc_data,
3423                                    u64_to_user_ptr(cntrs_data->counters_data),
3424                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3425                         ret = -EFAULT;
3426                         goto free;
3427                 }
3428         }
3429
3430         if (!mcounters->hw_cntrs_hndl) {
3431                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3432                         to_mdev(ibcounters->device)->mdev, false);
3433                 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3434                         ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3435                         goto free;
3436                 }
3437                 hw_hndl = true;
3438         }
3439
3440         if (desc_data) {
3441                 /* counters already bound to at least one flow */
3442                 if (mcounters->cntrs_max_index) {
3443                         ret = -EINVAL;
3444                         goto free_hndl;
3445                 }
3446
3447                 ret = counters_set_description(ibcounters,
3448                                                MLX5_IB_COUNTERS_FLOW,
3449                                                desc_data,
3450                                                cntrs_data->ncounters);
3451                 if (ret)
3452                         goto free_hndl;
3453
3454         } else if (!mcounters->cntrs_max_index) {
3455                 /* counters not bound yet, must have udata passed */
3456                 ret = -EINVAL;
3457                 goto free_hndl;
3458         }
3459
3460         return 0;
3461
3462 free_hndl:
3463         if (hw_hndl) {
3464                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3465                                 mcounters->hw_cntrs_hndl);
3466                 mcounters->hw_cntrs_hndl = NULL;
3467         }
3468 free:
3469         kfree(desc_data);
3470         return ret;
3471 }
3472
3473 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3474                                                       struct mlx5_ib_flow_prio *ft_prio,
3475                                                       const struct ib_flow_attr *flow_attr,
3476                                                       struct mlx5_flow_destination *dst,
3477                                                       u32 underlay_qpn,
3478                                                       struct mlx5_ib_create_flow *ucmd)
3479 {
3480         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3481         struct mlx5_ib_flow_handler *handler;
3482         struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3483         struct mlx5_flow_spec *spec;
3484         struct mlx5_flow_destination dest_arr[2] = {};
3485         struct mlx5_flow_destination *rule_dst = dest_arr;
3486         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3487         unsigned int spec_index;
3488         u32 prev_type = 0;
3489         int err = 0;
3490         int dest_num = 0;
3491         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3492
3493         if (!is_valid_attr(dev->mdev, flow_attr))
3494                 return ERR_PTR(-EINVAL);
3495
3496         if (dev->is_rep && is_egress)
3497                 return ERR_PTR(-EINVAL);
3498
3499         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3500         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3501         if (!handler || !spec) {
3502                 err = -ENOMEM;
3503                 goto free;
3504         }
3505
3506         INIT_LIST_HEAD(&handler->list);
3507         if (dst) {
3508                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3509                 dest_num++;
3510         }
3511
3512         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3513                 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3514                                       spec->match_value,
3515                                       ib_flow, flow_attr, &flow_act,
3516                                       prev_type);
3517                 if (err < 0)
3518                         goto free;
3519
3520                 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3521                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3522         }
3523
3524         if (!flow_is_multicast_only(flow_attr))
3525                 set_underlay_qp(dev, spec, underlay_qpn);
3526
3527         if (dev->is_rep) {
3528                 void *misc;
3529
3530                 if (!dev->port[flow_attr->port - 1].rep) {
3531                         err = -EINVAL;
3532                         goto free;
3533                 }
3534                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3535                                     misc_parameters);
3536                 MLX5_SET(fte_match_set_misc, misc, source_port,
3537                          dev->port[flow_attr->port - 1].rep->vport);
3538                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3539                                     misc_parameters);
3540                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3541         }
3542
3543         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3544
3545         if (is_egress &&
3546             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3547                 err = -EINVAL;
3548                 goto free;
3549         }
3550
3551         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3552                 struct mlx5_ib_mcounters *mcounters;
3553
3554                 err = flow_counters_set_data(flow_act.counters, ucmd);
3555                 if (err)
3556                         goto free;
3557
3558                 mcounters = to_mcounters(flow_act.counters);
3559                 handler->ibcounters = flow_act.counters;
3560                 dest_arr[dest_num].type =
3561                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3562                 dest_arr[dest_num].counter_id =
3563                         mlx5_fc_id(mcounters->hw_cntrs_hndl);
3564                 dest_num++;
3565         }
3566
3567         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3568                 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3569                         rule_dst = NULL;
3570                         dest_num = 0;
3571                 }
3572         } else {
3573                 if (is_egress)
3574                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3575                 else
3576                         flow_act.action |=
3577                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3578                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3579         }
3580
3581         if ((flow_act.flags & FLOW_ACT_HAS_TAG)  &&
3582             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3583              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3584                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3585                              flow_act.flow_tag, flow_attr->type);
3586                 err = -EINVAL;
3587                 goto free;
3588         }
3589         handler->rule = mlx5_add_flow_rules(ft, spec,
3590                                             &flow_act,
3591                                             rule_dst, dest_num);
3592
3593         if (IS_ERR(handler->rule)) {
3594                 err = PTR_ERR(handler->rule);
3595                 goto free;
3596         }
3597
3598         ft_prio->refcount++;
3599         handler->prio = ft_prio;
3600         handler->dev = dev;
3601
3602         ft_prio->flow_table = ft;
3603 free:
3604         if (err && handler) {
3605                 if (handler->ibcounters &&
3606                     atomic_read(&handler->ibcounters->usecnt) == 1)
3607                         counters_clear_description(handler->ibcounters);
3608                 kfree(handler);
3609         }
3610         kvfree(spec);
3611         return err ? ERR_PTR(err) : handler;
3612 }
3613
3614 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3615                                                      struct mlx5_ib_flow_prio *ft_prio,
3616                                                      const struct ib_flow_attr *flow_attr,
3617                                                      struct mlx5_flow_destination *dst)
3618 {
3619         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3620 }
3621
3622 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3623                                                           struct mlx5_ib_flow_prio *ft_prio,
3624                                                           struct ib_flow_attr *flow_attr,
3625                                                           struct mlx5_flow_destination *dst)
3626 {
3627         struct mlx5_ib_flow_handler *handler_dst = NULL;
3628         struct mlx5_ib_flow_handler *handler = NULL;
3629
3630         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3631         if (!IS_ERR(handler)) {
3632                 handler_dst = create_flow_rule(dev, ft_prio,
3633                                                flow_attr, dst);
3634                 if (IS_ERR(handler_dst)) {
3635                         mlx5_del_flow_rules(handler->rule);
3636                         ft_prio->refcount--;
3637                         kfree(handler);
3638                         handler = handler_dst;
3639                 } else {
3640                         list_add(&handler_dst->list, &handler->list);
3641                 }
3642         }
3643
3644         return handler;
3645 }
3646 enum {
3647         LEFTOVERS_MC,
3648         LEFTOVERS_UC,
3649 };
3650
3651 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3652                                                           struct mlx5_ib_flow_prio *ft_prio,
3653                                                           struct ib_flow_attr *flow_attr,
3654                                                           struct mlx5_flow_destination *dst)
3655 {
3656         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3657         struct mlx5_ib_flow_handler *handler = NULL;
3658
3659         static struct {
3660                 struct ib_flow_attr     flow_attr;
3661                 struct ib_flow_spec_eth eth_flow;
3662         } leftovers_specs[] = {
3663                 [LEFTOVERS_MC] = {
3664                         .flow_attr = {
3665                                 .num_of_specs = 1,
3666                                 .size = sizeof(leftovers_specs[0])
3667                         },
3668                         .eth_flow = {
3669                                 .type = IB_FLOW_SPEC_ETH,
3670                                 .size = sizeof(struct ib_flow_spec_eth),
3671                                 .mask = {.dst_mac = {0x1} },
3672                                 .val =  {.dst_mac = {0x1} }
3673                         }
3674                 },
3675                 [LEFTOVERS_UC] = {
3676                         .flow_attr = {
3677                                 .num_of_specs = 1,
3678                                 .size = sizeof(leftovers_specs[0])
3679                         },
3680                         .eth_flow = {
3681                                 .type = IB_FLOW_SPEC_ETH,
3682                                 .size = sizeof(struct ib_flow_spec_eth),
3683                                 .mask = {.dst_mac = {0x1} },
3684                                 .val = {.dst_mac = {} }
3685                         }
3686                 }
3687         };
3688
3689         handler = create_flow_rule(dev, ft_prio,
3690                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3691                                    dst);
3692         if (!IS_ERR(handler) &&
3693             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3694                 handler_ucast = create_flow_rule(dev, ft_prio,
3695                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3696                                                  dst);
3697                 if (IS_ERR(handler_ucast)) {
3698                         mlx5_del_flow_rules(handler->rule);
3699                         ft_prio->refcount--;
3700                         kfree(handler);
3701                         handler = handler_ucast;
3702                 } else {
3703                         list_add(&handler_ucast->list, &handler->list);
3704                 }
3705         }
3706
3707         return handler;
3708 }
3709
3710 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3711                                                         struct mlx5_ib_flow_prio *ft_rx,
3712                                                         struct mlx5_ib_flow_prio *ft_tx,
3713                                                         struct mlx5_flow_destination *dst)
3714 {
3715         struct mlx5_ib_flow_handler *handler_rx;
3716         struct mlx5_ib_flow_handler *handler_tx;
3717         int err;
3718         static const struct ib_flow_attr flow_attr  = {
3719                 .num_of_specs = 0,
3720                 .size = sizeof(flow_attr)
3721         };
3722
3723         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3724         if (IS_ERR(handler_rx)) {
3725                 err = PTR_ERR(handler_rx);
3726                 goto err;
3727         }
3728
3729         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3730         if (IS_ERR(handler_tx)) {
3731                 err = PTR_ERR(handler_tx);
3732                 goto err_tx;
3733         }
3734
3735         list_add(&handler_tx->list, &handler_rx->list);
3736
3737         return handler_rx;
3738
3739 err_tx:
3740         mlx5_del_flow_rules(handler_rx->rule);
3741         ft_rx->refcount--;
3742         kfree(handler_rx);
3743 err:
3744         return ERR_PTR(err);
3745 }
3746
3747 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3748                                            struct ib_flow_attr *flow_attr,
3749                                            int domain,
3750                                            struct ib_udata *udata)
3751 {
3752         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3753         struct mlx5_ib_qp *mqp = to_mqp(qp);
3754         struct mlx5_ib_flow_handler *handler = NULL;
3755         struct mlx5_flow_destination *dst = NULL;
3756         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3757         struct mlx5_ib_flow_prio *ft_prio;
3758         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3759         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3760         size_t min_ucmd_sz, required_ucmd_sz;
3761         int err;
3762         int underlay_qpn;
3763
3764         if (udata && udata->inlen) {
3765                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3766                                 sizeof(ucmd_hdr.reserved);
3767                 if (udata->inlen < min_ucmd_sz)
3768                         return ERR_PTR(-EOPNOTSUPP);
3769
3770                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3771                 if (err)
3772                         return ERR_PTR(err);
3773
3774                 /* currently supports only one counters data */
3775                 if (ucmd_hdr.ncounters_data > 1)
3776                         return ERR_PTR(-EINVAL);
3777
3778                 required_ucmd_sz = min_ucmd_sz +
3779                         sizeof(struct mlx5_ib_flow_counters_data) *
3780                         ucmd_hdr.ncounters_data;
3781                 if (udata->inlen > required_ucmd_sz &&
3782                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3783                                          udata->inlen - required_ucmd_sz))
3784                         return ERR_PTR(-EOPNOTSUPP);
3785
3786                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3787                 if (!ucmd)
3788                         return ERR_PTR(-ENOMEM);
3789
3790                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3791                 if (err)
3792                         goto free_ucmd;
3793         }
3794
3795         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3796                 err = -ENOMEM;
3797                 goto free_ucmd;
3798         }
3799
3800         if (domain != IB_FLOW_DOMAIN_USER ||
3801             flow_attr->port > dev->num_ports ||
3802             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3803                                   IB_FLOW_ATTR_FLAGS_EGRESS))) {
3804                 err = -EINVAL;
3805                 goto free_ucmd;
3806         }
3807
3808         if (is_egress &&
3809             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3810              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3811                 err = -EINVAL;
3812                 goto free_ucmd;
3813         }
3814
3815         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3816         if (!dst) {
3817                 err = -ENOMEM;
3818                 goto free_ucmd;
3819         }
3820
3821         mutex_lock(&dev->flow_db->lock);
3822
3823         ft_prio = get_flow_table(dev, flow_attr,
3824                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3825         if (IS_ERR(ft_prio)) {
3826                 err = PTR_ERR(ft_prio);
3827                 goto unlock;
3828         }
3829         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3830                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3831                 if (IS_ERR(ft_prio_tx)) {
3832                         err = PTR_ERR(ft_prio_tx);
3833                         ft_prio_tx = NULL;
3834                         goto destroy_ft;
3835                 }
3836         }
3837
3838         if (is_egress) {
3839                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3840         } else {
3841                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3842                 if (mqp->flags & MLX5_IB_QP_RSS)
3843                         dst->tir_num = mqp->rss_qp.tirn;
3844                 else
3845                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3846         }
3847
3848         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3849                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3850                         handler = create_dont_trap_rule(dev, ft_prio,
3851                                                         flow_attr, dst);
3852                 } else {
3853                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3854                                         mqp->underlay_qpn : 0;
3855                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3856                                                     dst, underlay_qpn, ucmd);
3857                 }
3858         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3859                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3860                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3861                                                 dst);
3862         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3863                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3864         } else {
3865                 err = -EINVAL;
3866                 goto destroy_ft;
3867         }
3868
3869         if (IS_ERR(handler)) {
3870                 err = PTR_ERR(handler);
3871                 handler = NULL;
3872                 goto destroy_ft;
3873         }
3874
3875         mutex_unlock(&dev->flow_db->lock);
3876         kfree(dst);
3877         kfree(ucmd);
3878
3879         return &handler->ibflow;
3880
3881 destroy_ft:
3882         put_flow_table(dev, ft_prio, false);
3883         if (ft_prio_tx)
3884                 put_flow_table(dev, ft_prio_tx, false);
3885 unlock:
3886         mutex_unlock(&dev->flow_db->lock);
3887         kfree(dst);
3888 free_ucmd:
3889         kfree(ucmd);
3890         return ERR_PTR(err);
3891 }
3892
3893 static struct mlx5_ib_flow_prio *
3894 _get_flow_table(struct mlx5_ib_dev *dev,
3895                 struct mlx5_ib_flow_matcher *fs_matcher,
3896                 bool mcast)
3897 {
3898         struct mlx5_flow_namespace *ns = NULL;
3899         struct mlx5_ib_flow_prio *prio = NULL;
3900         int max_table_size = 0;
3901         bool esw_encap;
3902         u32 flags = 0;
3903         int priority;
3904
3905         if (mcast)
3906                 priority = MLX5_IB_FLOW_MCAST_PRIO;
3907         else
3908                 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3909
3910         esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3911                 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3912         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3913                 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3914                                         log_max_ft_size));
3915                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
3916                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3917                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3918                                               reformat_l3_tunnel_to_l2) &&
3919                     !esw_encap)
3920                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3921         } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3922                 max_table_size = BIT(
3923                         MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
3924                 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
3925                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3926         } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3927                 max_table_size = BIT(
3928                         MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
3929                 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3930                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3931                 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3932                     esw_encap)
3933                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3934                 priority = FDB_BYPASS_PATH;
3935         }
3936
3937         max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
3938
3939         ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3940         if (!ns)
3941                 return ERR_PTR(-ENOTSUPP);
3942
3943         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3944                 prio = &dev->flow_db->prios[priority];
3945         else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
3946                 prio = &dev->flow_db->egress_prios[priority];
3947         else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3948                 prio = &dev->flow_db->fdb;
3949
3950         if (!prio)
3951                 return ERR_PTR(-EINVAL);
3952
3953         if (prio->flow_table)
3954                 return prio;
3955
3956         return _get_prio(ns, prio, priority, max_table_size,
3957                          MLX5_FS_MAX_TYPES, flags);
3958 }
3959
3960 static struct mlx5_ib_flow_handler *
3961 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3962                       struct mlx5_ib_flow_prio *ft_prio,
3963                       struct mlx5_flow_destination *dst,
3964                       struct mlx5_ib_flow_matcher  *fs_matcher,
3965                       struct mlx5_flow_act *flow_act,
3966                       void *cmd_in, int inlen,
3967                       int dst_num)
3968 {
3969         struct mlx5_ib_flow_handler *handler;
3970         struct mlx5_flow_spec *spec;
3971         struct mlx5_flow_table *ft = ft_prio->flow_table;
3972         int err = 0;
3973
3974         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3975         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3976         if (!handler || !spec) {
3977                 err = -ENOMEM;
3978                 goto free;
3979         }
3980
3981         INIT_LIST_HEAD(&handler->list);
3982
3983         memcpy(spec->match_value, cmd_in, inlen);
3984         memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3985                fs_matcher->mask_len);
3986         spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3987
3988         handler->rule = mlx5_add_flow_rules(ft, spec,
3989                                             flow_act, dst, dst_num);
3990
3991         if (IS_ERR(handler->rule)) {
3992                 err = PTR_ERR(handler->rule);
3993                 goto free;
3994         }
3995
3996         ft_prio->refcount++;
3997         handler->prio = ft_prio;
3998         handler->dev = dev;
3999         ft_prio->flow_table = ft;
4000
4001 free:
4002         if (err)
4003                 kfree(handler);
4004         kvfree(spec);
4005         return err ? ERR_PTR(err) : handler;
4006 }
4007
4008 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4009                                 void *match_v)
4010 {
4011         void *match_c;
4012         void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4013         void *dmac, *dmac_mask;
4014         void *ipv4, *ipv4_mask;
4015
4016         if (!(fs_matcher->match_criteria_enable &
4017               (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4018                 return false;
4019
4020         match_c = fs_matcher->matcher_mask.match_params;
4021         match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4022                                            outer_headers);
4023         match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4024                                            outer_headers);
4025
4026         dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4027                             dmac_47_16);
4028         dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4029                                  dmac_47_16);
4030
4031         if (is_multicast_ether_addr(dmac) &&
4032             is_multicast_ether_addr(dmac_mask))
4033                 return true;
4034
4035         ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4036                             dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4037
4038         ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4039                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4040
4041         if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4042             ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4043                 return true;
4044
4045         return false;
4046 }
4047
4048 struct mlx5_ib_flow_handler *
4049 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4050                         struct mlx5_ib_flow_matcher *fs_matcher,
4051                         struct mlx5_flow_act *flow_act,
4052                         u32 counter_id,
4053                         void *cmd_in, int inlen, int dest_id,
4054                         int dest_type)
4055 {
4056         struct mlx5_flow_destination *dst;
4057         struct mlx5_ib_flow_prio *ft_prio;
4058         struct mlx5_ib_flow_handler *handler;
4059         int dst_num = 0;
4060         bool mcast;
4061         int err;
4062
4063         if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4064                 return ERR_PTR(-EOPNOTSUPP);
4065
4066         if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4067                 return ERR_PTR(-ENOMEM);
4068
4069         dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
4070         if (!dst)
4071                 return ERR_PTR(-ENOMEM);
4072
4073         mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4074         mutex_lock(&dev->flow_db->lock);
4075
4076         ft_prio = _get_flow_table(dev, fs_matcher, mcast);
4077         if (IS_ERR(ft_prio)) {
4078                 err = PTR_ERR(ft_prio);
4079                 goto unlock;
4080         }
4081
4082         if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
4083                 dst[dst_num].type = dest_type;
4084                 dst[dst_num].tir_num = dest_id;
4085                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4086         } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
4087                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4088                 dst[dst_num].ft_num = dest_id;
4089                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4090         } else {
4091                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
4092                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
4093         }
4094
4095         dst_num++;
4096
4097         if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4098                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4099                 dst[dst_num].counter_id = counter_id;
4100                 dst_num++;
4101         }
4102
4103         handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
4104                                         cmd_in, inlen, dst_num);
4105
4106         if (IS_ERR(handler)) {
4107                 err = PTR_ERR(handler);
4108                 goto destroy_ft;
4109         }
4110
4111         mutex_unlock(&dev->flow_db->lock);
4112         atomic_inc(&fs_matcher->usecnt);
4113         handler->flow_matcher = fs_matcher;
4114
4115         kfree(dst);
4116
4117         return handler;
4118
4119 destroy_ft:
4120         put_flow_table(dev, ft_prio, false);
4121 unlock:
4122         mutex_unlock(&dev->flow_db->lock);
4123         kfree(dst);
4124
4125         return ERR_PTR(err);
4126 }
4127
4128 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4129 {
4130         u32 flags = 0;
4131
4132         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4133                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4134
4135         return flags;
4136 }
4137
4138 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4139 static struct ib_flow_action *
4140 mlx5_ib_create_flow_action_esp(struct ib_device *device,
4141                                const struct ib_flow_action_attrs_esp *attr,
4142                                struct uverbs_attr_bundle *attrs)
4143 {
4144         struct mlx5_ib_dev *mdev = to_mdev(device);
4145         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4146         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4147         struct mlx5_ib_flow_action *action;
4148         u64 action_flags;
4149         u64 flags;
4150         int err = 0;
4151
4152         err = uverbs_get_flags64(
4153                 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4154                 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4155         if (err)
4156                 return ERR_PTR(err);
4157
4158         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4159
4160         /* We current only support a subset of the standard features. Only a
4161          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4162          * (with overlap). Full offload mode isn't supported.
4163          */
4164         if (!attr->keymat || attr->replay || attr->encap ||
4165             attr->spi || attr->seq || attr->tfc_pad ||
4166             attr->hard_limit_pkts ||
4167             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4168                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4169                 return ERR_PTR(-EOPNOTSUPP);
4170
4171         if (attr->keymat->protocol !=
4172             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4173                 return ERR_PTR(-EOPNOTSUPP);
4174
4175         aes_gcm = &attr->keymat->keymat.aes_gcm;
4176
4177         if (aes_gcm->icv_len != 16 ||
4178             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4179                 return ERR_PTR(-EOPNOTSUPP);
4180
4181         action = kmalloc(sizeof(*action), GFP_KERNEL);
4182         if (!action)
4183                 return ERR_PTR(-ENOMEM);
4184
4185         action->esp_aes_gcm.ib_flags = attr->flags;
4186         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4187                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4188         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4189         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4190                sizeof(accel_attrs.keymat.aes_gcm.salt));
4191         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4192                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4193         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4194         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4195         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4196
4197         accel_attrs.esn = attr->esn;
4198         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4199                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4200         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4201                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4202
4203         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4204                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4205
4206         action->esp_aes_gcm.ctx =
4207                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4208         if (IS_ERR(action->esp_aes_gcm.ctx)) {
4209                 err = PTR_ERR(action->esp_aes_gcm.ctx);
4210                 goto err_parse;
4211         }
4212
4213         action->esp_aes_gcm.ib_flags = attr->flags;
4214
4215         return &action->ib_action;
4216
4217 err_parse:
4218         kfree(action);
4219         return ERR_PTR(err);
4220 }
4221
4222 static int
4223 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4224                                const struct ib_flow_action_attrs_esp *attr,
4225                                struct uverbs_attr_bundle *attrs)
4226 {
4227         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4228         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4229         int err = 0;
4230
4231         if (attr->keymat || attr->replay || attr->encap ||
4232             attr->spi || attr->seq || attr->tfc_pad ||
4233             attr->hard_limit_pkts ||
4234             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4235                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4236                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4237                 return -EOPNOTSUPP;
4238
4239         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4240          * be modified.
4241          */
4242         if (!(maction->esp_aes_gcm.ib_flags &
4243               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4244             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4245                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4246                 return -EINVAL;
4247
4248         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4249                sizeof(accel_attrs));
4250
4251         accel_attrs.esn = attr->esn;
4252         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4253                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4254         else
4255                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4256
4257         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4258                                          &accel_attrs);
4259         if (err)
4260                 return err;
4261
4262         maction->esp_aes_gcm.ib_flags &=
4263                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4264         maction->esp_aes_gcm.ib_flags |=
4265                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4266
4267         return 0;
4268 }
4269
4270 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4271 {
4272         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4273
4274         switch (action->type) {
4275         case IB_FLOW_ACTION_ESP:
4276                 /*
4277                  * We only support aes_gcm by now, so we implicitly know this is
4278                  * the underline crypto.
4279                  */
4280                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4281                 break;
4282         case IB_FLOW_ACTION_UNSPECIFIED:
4283                 mlx5_ib_destroy_flow_action_raw(maction);
4284                 break;
4285         default:
4286                 WARN_ON(true);
4287                 break;
4288         }
4289
4290         kfree(maction);
4291         return 0;
4292 }
4293
4294 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4295 {
4296         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4297         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4298         int err;
4299         u16 uid;
4300
4301         uid = ibqp->pd ?
4302                 to_mpd(ibqp->pd)->uid : 0;
4303
4304         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4305                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4306                 return -EOPNOTSUPP;
4307         }
4308
4309         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4310         if (err)
4311                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4312                              ibqp->qp_num, gid->raw);
4313
4314         return err;
4315 }
4316
4317 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4318 {
4319         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4320         int err;
4321         u16 uid;
4322
4323         uid = ibqp->pd ?
4324                 to_mpd(ibqp->pd)->uid : 0;
4325         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4326         if (err)
4327                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4328                              ibqp->qp_num, gid->raw);
4329
4330         return err;
4331 }
4332
4333 static int init_node_data(struct mlx5_ib_dev *dev)
4334 {
4335         int err;
4336
4337         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4338         if (err)
4339                 return err;
4340
4341         dev->mdev->rev_id = dev->mdev->pdev->revision;
4342
4343         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4344 }
4345
4346 static ssize_t fw_pages_show(struct device *device,
4347                              struct device_attribute *attr, char *buf)
4348 {
4349         struct mlx5_ib_dev *dev =
4350                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4351
4352         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4353 }
4354 static DEVICE_ATTR_RO(fw_pages);
4355
4356 static ssize_t reg_pages_show(struct device *device,
4357                               struct device_attribute *attr, char *buf)
4358 {
4359         struct mlx5_ib_dev *dev =
4360                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4361
4362         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4363 }
4364 static DEVICE_ATTR_RO(reg_pages);
4365
4366 static ssize_t hca_type_show(struct device *device,
4367                              struct device_attribute *attr, char *buf)
4368 {
4369         struct mlx5_ib_dev *dev =
4370                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4371
4372         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4373 }
4374 static DEVICE_ATTR_RO(hca_type);
4375
4376 static ssize_t hw_rev_show(struct device *device,
4377                            struct device_attribute *attr, char *buf)
4378 {
4379         struct mlx5_ib_dev *dev =
4380                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4381
4382         return sprintf(buf, "%x\n", dev->mdev->rev_id);
4383 }
4384 static DEVICE_ATTR_RO(hw_rev);
4385
4386 static ssize_t board_id_show(struct device *device,
4387                              struct device_attribute *attr, char *buf)
4388 {
4389         struct mlx5_ib_dev *dev =
4390                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4391
4392         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4393                        dev->mdev->board_id);
4394 }
4395 static DEVICE_ATTR_RO(board_id);
4396
4397 static struct attribute *mlx5_class_attributes[] = {
4398         &dev_attr_hw_rev.attr,
4399         &dev_attr_hca_type.attr,
4400         &dev_attr_board_id.attr,
4401         &dev_attr_fw_pages.attr,
4402         &dev_attr_reg_pages.attr,
4403         NULL,
4404 };
4405
4406 static const struct attribute_group mlx5_attr_group = {
4407         .attrs = mlx5_class_attributes,
4408 };
4409
4410 static void pkey_change_handler(struct work_struct *work)
4411 {
4412         struct mlx5_ib_port_resources *ports =
4413                 container_of(work, struct mlx5_ib_port_resources,
4414                              pkey_change_work);
4415
4416         mutex_lock(&ports->devr->mutex);
4417         mlx5_ib_gsi_pkey_change(ports->gsi);
4418         mutex_unlock(&ports->devr->mutex);
4419 }
4420
4421 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4422 {
4423         struct mlx5_ib_qp *mqp;
4424         struct mlx5_ib_cq *send_mcq, *recv_mcq;
4425         struct mlx5_core_cq *mcq;
4426         struct list_head cq_armed_list;
4427         unsigned long flags_qp;
4428         unsigned long flags_cq;
4429         unsigned long flags;
4430
4431         INIT_LIST_HEAD(&cq_armed_list);
4432
4433         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4434         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4435         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4436                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4437                 if (mqp->sq.tail != mqp->sq.head) {
4438                         send_mcq = to_mcq(mqp->ibqp.send_cq);
4439                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
4440                         if (send_mcq->mcq.comp &&
4441                             mqp->ibqp.send_cq->comp_handler) {
4442                                 if (!send_mcq->mcq.reset_notify_added) {
4443                                         send_mcq->mcq.reset_notify_added = 1;
4444                                         list_add_tail(&send_mcq->mcq.reset_notify,
4445                                                       &cq_armed_list);
4446                                 }
4447                         }
4448                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4449                 }
4450                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4451                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4452                 /* no handling is needed for SRQ */
4453                 if (!mqp->ibqp.srq) {
4454                         if (mqp->rq.tail != mqp->rq.head) {
4455                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4456                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4457                                 if (recv_mcq->mcq.comp &&
4458                                     mqp->ibqp.recv_cq->comp_handler) {
4459                                         if (!recv_mcq->mcq.reset_notify_added) {
4460                                                 recv_mcq->mcq.reset_notify_added = 1;
4461                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
4462                                                               &cq_armed_list);
4463                                         }
4464                                 }
4465                                 spin_unlock_irqrestore(&recv_mcq->lock,
4466                                                        flags_cq);
4467                         }
4468                 }
4469                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4470         }
4471         /*At that point all inflight post send were put to be executed as of we
4472          * lock/unlock above locks Now need to arm all involved CQs.
4473          */
4474         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4475                 mcq->comp(mcq);
4476         }
4477         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4478 }
4479
4480 static void delay_drop_handler(struct work_struct *work)
4481 {
4482         int err;
4483         struct mlx5_ib_delay_drop *delay_drop =
4484                 container_of(work, struct mlx5_ib_delay_drop,
4485                              delay_drop_work);
4486
4487         atomic_inc(&delay_drop->events_cnt);
4488
4489         mutex_lock(&delay_drop->lock);
4490         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4491                                        delay_drop->timeout);
4492         if (err) {
4493                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4494                              delay_drop->timeout);
4495                 delay_drop->activate = false;
4496         }
4497         mutex_unlock(&delay_drop->lock);
4498 }
4499
4500 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4501                                  struct ib_event *ibev)
4502 {
4503         u8 port = (eqe->data.port.port >> 4) & 0xf;
4504
4505         switch (eqe->sub_type) {
4506         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4507                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4508                                             IB_LINK_LAYER_ETHERNET)
4509                         schedule_work(&ibdev->delay_drop.delay_drop_work);
4510                 break;
4511         default: /* do nothing */
4512                 return;
4513         }
4514 }
4515
4516 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4517                               struct ib_event *ibev)
4518 {
4519         u8 port = (eqe->data.port.port >> 4) & 0xf;
4520
4521         ibev->element.port_num = port;
4522
4523         switch (eqe->sub_type) {
4524         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4525         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4526         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4527                 /* In RoCE, port up/down events are handled in
4528                  * mlx5_netdev_event().
4529                  */
4530                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4531                                             IB_LINK_LAYER_ETHERNET)
4532                         return -EINVAL;
4533
4534                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4535                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4536                 break;
4537
4538         case MLX5_PORT_CHANGE_SUBTYPE_LID:
4539                 ibev->event = IB_EVENT_LID_CHANGE;
4540                 break;
4541
4542         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4543                 ibev->event = IB_EVENT_PKEY_CHANGE;
4544                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4545                 break;
4546
4547         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4548                 ibev->event = IB_EVENT_GID_CHANGE;
4549                 break;
4550
4551         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4552                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4553                 break;
4554         default:
4555                 return -EINVAL;
4556         }
4557
4558         return 0;
4559 }
4560
4561 static void mlx5_ib_handle_event(struct work_struct *_work)
4562 {
4563         struct mlx5_ib_event_work *work =
4564                 container_of(_work, struct mlx5_ib_event_work, work);
4565         struct mlx5_ib_dev *ibdev;
4566         struct ib_event ibev;
4567         bool fatal = false;
4568
4569         if (work->is_slave) {
4570                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4571                 if (!ibdev)
4572                         goto out;
4573         } else {
4574                 ibdev = work->dev;
4575         }
4576
4577         switch (work->event) {
4578         case MLX5_DEV_EVENT_SYS_ERROR:
4579                 ibev.event = IB_EVENT_DEVICE_FATAL;
4580                 mlx5_ib_handle_internal_error(ibdev);
4581                 ibev.element.port_num  = (u8)(unsigned long)work->param;
4582                 fatal = true;
4583                 break;
4584         case MLX5_EVENT_TYPE_PORT_CHANGE:
4585                 if (handle_port_change(ibdev, work->param, &ibev))
4586                         goto out;
4587                 break;
4588         case MLX5_EVENT_TYPE_GENERAL_EVENT:
4589                 handle_general_event(ibdev, work->param, &ibev);
4590                 /* fall through */
4591         default:
4592                 goto out;
4593         }
4594
4595         ibev.device = &ibdev->ib_dev;
4596
4597         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4598                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
4599                 goto out;
4600         }
4601
4602         if (ibdev->ib_active)
4603                 ib_dispatch_event(&ibev);
4604
4605         if (fatal)
4606                 ibdev->ib_active = false;
4607 out:
4608         kfree(work);
4609 }
4610
4611 static int mlx5_ib_event(struct notifier_block *nb,
4612                          unsigned long event, void *param)
4613 {
4614         struct mlx5_ib_event_work *work;
4615
4616         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4617         if (!work)
4618                 return NOTIFY_DONE;
4619
4620         INIT_WORK(&work->work, mlx5_ib_handle_event);
4621         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4622         work->is_slave = false;
4623         work->param = param;
4624         work->event = event;
4625
4626         queue_work(mlx5_ib_event_wq, &work->work);
4627
4628         return NOTIFY_OK;
4629 }
4630
4631 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4632                                     unsigned long event, void *param)
4633 {
4634         struct mlx5_ib_event_work *work;
4635
4636         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4637         if (!work)
4638                 return NOTIFY_DONE;
4639
4640         INIT_WORK(&work->work, mlx5_ib_handle_event);
4641         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4642         work->is_slave = true;
4643         work->param = param;
4644         work->event = event;
4645         queue_work(mlx5_ib_event_wq, &work->work);
4646
4647         return NOTIFY_OK;
4648 }
4649
4650 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4651 {
4652         struct mlx5_hca_vport_context vport_ctx;
4653         int err;
4654         int port;
4655
4656         for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
4657                 dev->mdev->port_caps[port - 1].has_smi = false;
4658                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4659                     MLX5_CAP_PORT_TYPE_IB) {
4660                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4661                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4662                                                                    port, 0,
4663                                                                    &vport_ctx);
4664                                 if (err) {
4665                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4666                                                     port, err);
4667                                         return err;
4668                                 }
4669                                 dev->mdev->port_caps[port - 1].has_smi =
4670                                         vport_ctx.has_smi;
4671                         } else {
4672                                 dev->mdev->port_caps[port - 1].has_smi = true;
4673                         }
4674                 }
4675         }
4676         return 0;
4677 }
4678
4679 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4680 {
4681         int port;
4682
4683         for (port = 1; port <= dev->num_ports; port++)
4684                 mlx5_query_ext_port_caps(dev, port);
4685 }
4686
4687 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4688 {
4689         struct ib_device_attr *dprops = NULL;
4690         struct ib_port_attr *pprops = NULL;
4691         int err = -ENOMEM;
4692         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4693
4694         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4695         if (!pprops)
4696                 goto out;
4697
4698         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4699         if (!dprops)
4700                 goto out;
4701
4702         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4703         if (err) {
4704                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4705                 goto out;
4706         }
4707
4708         memset(pprops, 0, sizeof(*pprops));
4709         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4710         if (err) {
4711                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4712                              port, err);
4713                 goto out;
4714         }
4715
4716         dev->mdev->port_caps[port - 1].pkey_table_len =
4717                                         dprops->max_pkeys;
4718         dev->mdev->port_caps[port - 1].gid_table_len =
4719                                         pprops->gid_tbl_len;
4720         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4721                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4722
4723 out:
4724         kfree(pprops);
4725         kfree(dprops);
4726
4727         return err;
4728 }
4729
4730 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4731 {
4732         /* For representors use port 1, is this is the only native
4733          * port
4734          */
4735         if (dev->is_rep)
4736                 return __get_port_caps(dev, 1);
4737         return __get_port_caps(dev, port);
4738 }
4739
4740 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4741 {
4742         int err;
4743
4744         err = mlx5_mr_cache_cleanup(dev);
4745         if (err)
4746                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4747
4748         if (dev->umrc.qp)
4749                 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4750         if (dev->umrc.cq)
4751                 ib_free_cq(dev->umrc.cq);
4752         if (dev->umrc.pd)
4753                 ib_dealloc_pd(dev->umrc.pd);
4754 }
4755
4756 enum {
4757         MAX_UMR_WR = 128,
4758 };
4759
4760 static int create_umr_res(struct mlx5_ib_dev *dev)
4761 {
4762         struct ib_qp_init_attr *init_attr = NULL;
4763         struct ib_qp_attr *attr = NULL;
4764         struct ib_pd *pd;
4765         struct ib_cq *cq;
4766         struct ib_qp *qp;
4767         int ret;
4768
4769         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4770         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4771         if (!attr || !init_attr) {
4772                 ret = -ENOMEM;
4773                 goto error_0;
4774         }
4775
4776         pd = ib_alloc_pd(&dev->ib_dev, 0);
4777         if (IS_ERR(pd)) {
4778                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4779                 ret = PTR_ERR(pd);
4780                 goto error_0;
4781         }
4782
4783         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4784         if (IS_ERR(cq)) {
4785                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4786                 ret = PTR_ERR(cq);
4787                 goto error_2;
4788         }
4789
4790         init_attr->send_cq = cq;
4791         init_attr->recv_cq = cq;
4792         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4793         init_attr->cap.max_send_wr = MAX_UMR_WR;
4794         init_attr->cap.max_send_sge = 1;
4795         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4796         init_attr->port_num = 1;
4797         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4798         if (IS_ERR(qp)) {
4799                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4800                 ret = PTR_ERR(qp);
4801                 goto error_3;
4802         }
4803         qp->device     = &dev->ib_dev;
4804         qp->real_qp    = qp;
4805         qp->uobject    = NULL;
4806         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4807         qp->send_cq    = init_attr->send_cq;
4808         qp->recv_cq    = init_attr->recv_cq;
4809
4810         attr->qp_state = IB_QPS_INIT;
4811         attr->port_num = 1;
4812         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4813                                 IB_QP_PORT, NULL);
4814         if (ret) {
4815                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4816                 goto error_4;
4817         }
4818
4819         memset(attr, 0, sizeof(*attr));
4820         attr->qp_state = IB_QPS_RTR;
4821         attr->path_mtu = IB_MTU_256;
4822
4823         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4824         if (ret) {
4825                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4826                 goto error_4;
4827         }
4828
4829         memset(attr, 0, sizeof(*attr));
4830         attr->qp_state = IB_QPS_RTS;
4831         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4832         if (ret) {
4833                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4834                 goto error_4;
4835         }
4836
4837         dev->umrc.qp = qp;
4838         dev->umrc.cq = cq;
4839         dev->umrc.pd = pd;
4840
4841         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4842         ret = mlx5_mr_cache_init(dev);
4843         if (ret) {
4844                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4845                 goto error_4;
4846         }
4847
4848         kfree(attr);
4849         kfree(init_attr);
4850
4851         return 0;
4852
4853 error_4:
4854         mlx5_ib_destroy_qp(qp, NULL);
4855         dev->umrc.qp = NULL;
4856
4857 error_3:
4858         ib_free_cq(cq);
4859         dev->umrc.cq = NULL;
4860
4861 error_2:
4862         ib_dealloc_pd(pd);
4863         dev->umrc.pd = NULL;
4864
4865 error_0:
4866         kfree(attr);
4867         kfree(init_attr);
4868         return ret;
4869 }
4870
4871 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4872 {
4873         switch (umr_fence_cap) {
4874         case MLX5_CAP_UMR_FENCE_NONE:
4875                 return MLX5_FENCE_MODE_NONE;
4876         case MLX5_CAP_UMR_FENCE_SMALL:
4877                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4878         default:
4879                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4880         }
4881 }
4882
4883 static int create_dev_resources(struct mlx5_ib_resources *devr)
4884 {
4885         struct ib_srq_init_attr attr;
4886         struct mlx5_ib_dev *dev;
4887         struct ib_device *ibdev;
4888         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4889         int port;
4890         int ret = 0;
4891
4892         dev = container_of(devr, struct mlx5_ib_dev, devr);
4893         ibdev = &dev->ib_dev;
4894
4895         mutex_init(&devr->mutex);
4896
4897         devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4898         if (!devr->p0)
4899                 return -ENOMEM;
4900
4901         devr->p0->device  = ibdev;
4902         devr->p0->uobject = NULL;
4903         atomic_set(&devr->p0->usecnt, 0);
4904
4905         ret = mlx5_ib_alloc_pd(devr->p0, NULL);
4906         if (ret)
4907                 goto error0;
4908
4909         devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4910         if (!devr->c0) {
4911                 ret = -ENOMEM;
4912                 goto error1;
4913         }
4914
4915         devr->c0->device = &dev->ib_dev;
4916         atomic_set(&devr->c0->usecnt, 0);
4917
4918         ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4919         if (ret)
4920                 goto err_create_cq;
4921
4922         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4923         if (IS_ERR(devr->x0)) {
4924                 ret = PTR_ERR(devr->x0);
4925                 goto error2;
4926         }
4927         devr->x0->device = &dev->ib_dev;
4928         devr->x0->inode = NULL;
4929         atomic_set(&devr->x0->usecnt, 0);
4930         mutex_init(&devr->x0->tgt_qp_mutex);
4931         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4932
4933         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4934         if (IS_ERR(devr->x1)) {
4935                 ret = PTR_ERR(devr->x1);
4936                 goto error3;
4937         }
4938         devr->x1->device = &dev->ib_dev;
4939         devr->x1->inode = NULL;
4940         atomic_set(&devr->x1->usecnt, 0);
4941         mutex_init(&devr->x1->tgt_qp_mutex);
4942         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4943
4944         memset(&attr, 0, sizeof(attr));
4945         attr.attr.max_sge = 1;
4946         attr.attr.max_wr = 1;
4947         attr.srq_type = IB_SRQT_XRC;
4948         attr.ext.cq = devr->c0;
4949         attr.ext.xrc.xrcd = devr->x0;
4950
4951         devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4952         if (!devr->s0) {
4953                 ret = -ENOMEM;
4954                 goto error4;
4955         }
4956
4957         devr->s0->device        = &dev->ib_dev;
4958         devr->s0->pd            = devr->p0;
4959         devr->s0->srq_type      = IB_SRQT_XRC;
4960         devr->s0->ext.xrc.xrcd  = devr->x0;
4961         devr->s0->ext.cq        = devr->c0;
4962         ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
4963         if (ret)
4964                 goto err_create;
4965
4966         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4967         atomic_inc(&devr->s0->ext.cq->usecnt);
4968         atomic_inc(&devr->p0->usecnt);
4969         atomic_set(&devr->s0->usecnt, 0);
4970
4971         memset(&attr, 0, sizeof(attr));
4972         attr.attr.max_sge = 1;
4973         attr.attr.max_wr = 1;
4974         attr.srq_type = IB_SRQT_BASIC;
4975         devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4976         if (!devr->s1) {
4977                 ret = -ENOMEM;
4978                 goto error5;
4979         }
4980
4981         devr->s1->device        = &dev->ib_dev;
4982         devr->s1->pd            = devr->p0;
4983         devr->s1->srq_type      = IB_SRQT_BASIC;
4984         devr->s1->ext.cq        = devr->c0;
4985
4986         ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
4987         if (ret)
4988                 goto error6;
4989
4990         atomic_inc(&devr->p0->usecnt);
4991         atomic_set(&devr->s1->usecnt, 0);
4992
4993         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4994                 INIT_WORK(&devr->ports[port].pkey_change_work,
4995                           pkey_change_handler);
4996                 devr->ports[port].devr = devr;
4997         }
4998
4999         return 0;
5000
5001 error6:
5002         kfree(devr->s1);
5003 error5:
5004         mlx5_ib_destroy_srq(devr->s0, NULL);
5005 err_create:
5006         kfree(devr->s0);
5007 error4:
5008         mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5009 error3:
5010         mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5011 error2:
5012         mlx5_ib_destroy_cq(devr->c0, NULL);
5013 err_create_cq:
5014         kfree(devr->c0);
5015 error1:
5016         mlx5_ib_dealloc_pd(devr->p0, NULL);
5017 error0:
5018         kfree(devr->p0);
5019         return ret;
5020 }
5021
5022 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5023 {
5024         int port;
5025
5026         mlx5_ib_destroy_srq(devr->s1, NULL);
5027         kfree(devr->s1);
5028         mlx5_ib_destroy_srq(devr->s0, NULL);
5029         kfree(devr->s0);
5030         mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5031         mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5032         mlx5_ib_destroy_cq(devr->c0, NULL);
5033         kfree(devr->c0);
5034         mlx5_ib_dealloc_pd(devr->p0, NULL);
5035         kfree(devr->p0);
5036
5037         /* Make sure no change P_Key work items are still executing */
5038         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
5039                 cancel_work_sync(&devr->ports[port].pkey_change_work);
5040 }
5041
5042 static u32 get_core_cap_flags(struct ib_device *ibdev,
5043                               struct mlx5_hca_vport_context *rep)
5044 {
5045         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5046         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5047         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5048         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
5049         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
5050         u32 ret = 0;
5051
5052         if (rep->grh_required)
5053                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5054
5055         if (ll == IB_LINK_LAYER_INFINIBAND)
5056                 return ret | RDMA_CORE_PORT_IBA_IB;
5057
5058         if (raw_support)
5059                 ret |= RDMA_CORE_PORT_RAW_PACKET;
5060
5061         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
5062                 return ret;
5063
5064         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
5065                 return ret;
5066
5067         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5068                 ret |= RDMA_CORE_PORT_IBA_ROCE;
5069
5070         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5071                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5072
5073         return ret;
5074 }
5075
5076 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5077                                struct ib_port_immutable *immutable)
5078 {
5079         struct ib_port_attr attr;
5080         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5081         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
5082         struct mlx5_hca_vport_context rep = {0};
5083         int err;
5084
5085         err = ib_query_port(ibdev, port_num, &attr);
5086         if (err)
5087                 return err;
5088
5089         if (ll == IB_LINK_LAYER_INFINIBAND) {
5090                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5091                                                    &rep);
5092                 if (err)
5093                         return err;
5094         }
5095
5096         immutable->pkey_tbl_len = attr.pkey_tbl_len;
5097         immutable->gid_tbl_len = attr.gid_tbl_len;
5098         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
5099         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5100                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
5101
5102         return 0;
5103 }
5104
5105 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5106                                    struct ib_port_immutable *immutable)
5107 {
5108         struct ib_port_attr attr;
5109         int err;
5110
5111         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5112
5113         err = ib_query_port(ibdev, port_num, &attr);
5114         if (err)
5115                 return err;
5116
5117         immutable->pkey_tbl_len = attr.pkey_tbl_len;
5118         immutable->gid_tbl_len = attr.gid_tbl_len;
5119         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5120
5121         return 0;
5122 }
5123
5124 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
5125 {
5126         struct mlx5_ib_dev *dev =
5127                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
5128         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5129                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5130                  fw_rev_sub(dev->mdev));
5131 }
5132
5133 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
5134 {
5135         struct mlx5_core_dev *mdev = dev->mdev;
5136         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5137                                                                  MLX5_FLOW_NAMESPACE_LAG);
5138         struct mlx5_flow_table *ft;
5139         int err;
5140
5141         if (!ns || !mlx5_lag_is_roce(mdev))
5142                 return 0;
5143
5144         err = mlx5_cmd_create_vport_lag(mdev);
5145         if (err)
5146                 return err;
5147
5148         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5149         if (IS_ERR(ft)) {
5150                 err = PTR_ERR(ft);
5151                 goto err_destroy_vport_lag;
5152         }
5153
5154         dev->flow_db->lag_demux_ft = ft;
5155         dev->lag_active = true;
5156         return 0;
5157
5158 err_destroy_vport_lag:
5159         mlx5_cmd_destroy_vport_lag(mdev);
5160         return err;
5161 }
5162
5163 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
5164 {
5165         struct mlx5_core_dev *mdev = dev->mdev;
5166
5167         if (dev->lag_active) {
5168                 dev->lag_active = false;
5169
5170                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5171                 dev->flow_db->lag_demux_ft = NULL;
5172
5173                 mlx5_cmd_destroy_vport_lag(mdev);
5174         }
5175 }
5176
5177 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5178 {
5179         int err;
5180
5181         dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5182         err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
5183         if (err) {
5184                 dev->port[port_num].roce.nb.notifier_call = NULL;
5185                 return err;
5186         }
5187
5188         return 0;
5189 }
5190
5191 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5192 {
5193         if (dev->port[port_num].roce.nb.notifier_call) {
5194                 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5195                 dev->port[port_num].roce.nb.notifier_call = NULL;
5196         }
5197 }
5198
5199 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
5200 {
5201         int err;
5202
5203         if (MLX5_CAP_GEN(dev->mdev, roce)) {
5204                 err = mlx5_nic_vport_enable_roce(dev->mdev);
5205                 if (err)
5206                         return err;
5207         }
5208
5209         err = mlx5_eth_lag_init(dev);
5210         if (err)
5211                 goto err_disable_roce;
5212
5213         return 0;
5214
5215 err_disable_roce:
5216         if (MLX5_CAP_GEN(dev->mdev, roce))
5217                 mlx5_nic_vport_disable_roce(dev->mdev);
5218
5219         return err;
5220 }
5221
5222 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
5223 {
5224         mlx5_eth_lag_cleanup(dev);
5225         if (MLX5_CAP_GEN(dev->mdev, roce))
5226                 mlx5_nic_vport_disable_roce(dev->mdev);
5227 }
5228
5229 struct mlx5_ib_counter {
5230         const char *name;
5231         size_t offset;
5232 };
5233
5234 #define INIT_Q_COUNTER(_name)           \
5235         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5236
5237 static const struct mlx5_ib_counter basic_q_cnts[] = {
5238         INIT_Q_COUNTER(rx_write_requests),
5239         INIT_Q_COUNTER(rx_read_requests),
5240         INIT_Q_COUNTER(rx_atomic_requests),
5241         INIT_Q_COUNTER(out_of_buffer),
5242 };
5243
5244 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
5245         INIT_Q_COUNTER(out_of_sequence),
5246 };
5247
5248 static const struct mlx5_ib_counter retrans_q_cnts[] = {
5249         INIT_Q_COUNTER(duplicate_request),
5250         INIT_Q_COUNTER(rnr_nak_retry_err),
5251         INIT_Q_COUNTER(packet_seq_err),
5252         INIT_Q_COUNTER(implied_nak_seq_err),
5253         INIT_Q_COUNTER(local_ack_timeout_err),
5254 };
5255
5256 #define INIT_CONG_COUNTER(_name)                \
5257         { .name = #_name, .offset =     \
5258                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5259
5260 static const struct mlx5_ib_counter cong_cnts[] = {
5261         INIT_CONG_COUNTER(rp_cnp_ignored),
5262         INIT_CONG_COUNTER(rp_cnp_handled),
5263         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5264         INIT_CONG_COUNTER(np_cnp_sent),
5265 };
5266
5267 static const struct mlx5_ib_counter extended_err_cnts[] = {
5268         INIT_Q_COUNTER(resp_local_length_error),
5269         INIT_Q_COUNTER(resp_cqe_error),
5270         INIT_Q_COUNTER(req_cqe_error),
5271         INIT_Q_COUNTER(req_remote_invalid_request),
5272         INIT_Q_COUNTER(req_remote_access_errors),
5273         INIT_Q_COUNTER(resp_remote_access_errors),
5274         INIT_Q_COUNTER(resp_cqe_flush_error),
5275         INIT_Q_COUNTER(req_cqe_flush_error),
5276 };
5277
5278 #define INIT_EXT_PPCNT_COUNTER(_name)           \
5279         { .name = #_name, .offset =     \
5280         MLX5_BYTE_OFF(ppcnt_reg, \
5281                       counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5282
5283 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5284         INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5285 };
5286
5287 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
5288 {
5289         int i;
5290
5291         for (i = 0; i < dev->num_ports; i++) {
5292                 if (dev->port[i].cnts.set_id_valid)
5293                         mlx5_core_dealloc_q_counter(dev->mdev,
5294                                                     dev->port[i].cnts.set_id);
5295                 kfree(dev->port[i].cnts.names);
5296                 kfree(dev->port[i].cnts.offsets);
5297         }
5298 }
5299
5300 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5301                                     struct mlx5_ib_counters *cnts)
5302 {
5303         u32 num_counters;
5304
5305         num_counters = ARRAY_SIZE(basic_q_cnts);
5306
5307         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5308                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5309
5310         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5311                 num_counters += ARRAY_SIZE(retrans_q_cnts);
5312
5313         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5314                 num_counters += ARRAY_SIZE(extended_err_cnts);
5315
5316         cnts->num_q_counters = num_counters;
5317
5318         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5319                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5320                 num_counters += ARRAY_SIZE(cong_cnts);
5321         }
5322         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5323                 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5324                 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5325         }
5326         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5327         if (!cnts->names)
5328                 return -ENOMEM;
5329
5330         cnts->offsets = kcalloc(num_counters,
5331                                 sizeof(cnts->offsets), GFP_KERNEL);
5332         if (!cnts->offsets)
5333                 goto err_names;
5334
5335         return 0;
5336
5337 err_names:
5338         kfree(cnts->names);
5339         cnts->names = NULL;
5340         return -ENOMEM;
5341 }
5342
5343 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5344                                   const char **names,
5345                                   size_t *offsets)
5346 {
5347         int i;
5348         int j = 0;
5349
5350         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5351                 names[j] = basic_q_cnts[i].name;
5352                 offsets[j] = basic_q_cnts[i].offset;
5353         }
5354
5355         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5356                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5357                         names[j] = out_of_seq_q_cnts[i].name;
5358                         offsets[j] = out_of_seq_q_cnts[i].offset;
5359                 }
5360         }
5361
5362         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5363                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5364                         names[j] = retrans_q_cnts[i].name;
5365                         offsets[j] = retrans_q_cnts[i].offset;
5366                 }
5367         }
5368
5369         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5370                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5371                         names[j] = extended_err_cnts[i].name;
5372                         offsets[j] = extended_err_cnts[i].offset;
5373                 }
5374         }
5375
5376         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5377                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5378                         names[j] = cong_cnts[i].name;
5379                         offsets[j] = cong_cnts[i].offset;
5380                 }
5381         }
5382
5383         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5384                 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5385                         names[j] = ext_ppcnt_cnts[i].name;
5386                         offsets[j] = ext_ppcnt_cnts[i].offset;
5387                 }
5388         }
5389 }
5390
5391 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5392 {
5393         int err = 0;
5394         int i;
5395         bool is_shared;
5396
5397         is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
5398
5399         for (i = 0; i < dev->num_ports; i++) {
5400                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5401                 if (err)
5402                         goto err_alloc;
5403
5404                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5405                                       dev->port[i].cnts.offsets);
5406
5407                 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5408                                                &dev->port[i].cnts.set_id,
5409                                                is_shared ?
5410                                                MLX5_SHARED_RESOURCE_UID : 0);
5411                 if (err) {
5412                         mlx5_ib_warn(dev,
5413                                      "couldn't allocate queue counter for port %d, err %d\n",
5414                                      i + 1, err);
5415                         goto err_alloc;
5416                 }
5417                 dev->port[i].cnts.set_id_valid = true;
5418         }
5419
5420         return 0;
5421
5422 err_alloc:
5423         mlx5_ib_dealloc_counters(dev);
5424         return err;
5425 }
5426
5427 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5428                                                     u8 port_num)
5429 {
5430         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5431         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5432
5433         /* We support only per port stats */
5434         if (port_num == 0)
5435                 return NULL;
5436
5437         return rdma_alloc_hw_stats_struct(port->cnts.names,
5438                                           port->cnts.num_q_counters +
5439                                           port->cnts.num_cong_counters +
5440                                           port->cnts.num_ext_ppcnt_counters,
5441                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5442 }
5443
5444 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5445                                     struct mlx5_ib_port *port,
5446                                     struct rdma_hw_stats *stats)
5447 {
5448         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5449         void *out;
5450         __be32 val;
5451         int ret, i;
5452
5453         out = kvzalloc(outlen, GFP_KERNEL);
5454         if (!out)
5455                 return -ENOMEM;
5456
5457         ret = mlx5_core_query_q_counter(mdev,
5458                                         port->cnts.set_id, 0,
5459                                         out, outlen);
5460         if (ret)
5461                 goto free;
5462
5463         for (i = 0; i < port->cnts.num_q_counters; i++) {
5464                 val = *(__be32 *)(out + port->cnts.offsets[i]);
5465                 stats->value[i] = (u64)be32_to_cpu(val);
5466         }
5467
5468 free:
5469         kvfree(out);
5470         return ret;
5471 }
5472
5473 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5474                                           struct mlx5_ib_port *port,
5475                                           struct rdma_hw_stats *stats)
5476 {
5477         int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5478         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5479         int ret, i;
5480         void *out;
5481
5482         out = kvzalloc(sz, GFP_KERNEL);
5483         if (!out)
5484                 return -ENOMEM;
5485
5486         ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5487         if (ret)
5488                 goto free;
5489
5490         for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5491                 stats->value[i + offset] =
5492                         be64_to_cpup((__be64 *)(out +
5493                                     port->cnts.offsets[i + offset]));
5494         }
5495
5496 free:
5497         kvfree(out);
5498         return ret;
5499 }
5500
5501 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5502                                 struct rdma_hw_stats *stats,
5503                                 u8 port_num, int index)
5504 {
5505         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5506         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5507         struct mlx5_core_dev *mdev;
5508         int ret, num_counters;
5509         u8 mdev_port_num;
5510
5511         if (!stats)
5512                 return -EINVAL;
5513
5514         num_counters = port->cnts.num_q_counters +
5515                        port->cnts.num_cong_counters +
5516                        port->cnts.num_ext_ppcnt_counters;
5517
5518         /* q_counters are per IB device, query the master mdev */
5519         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5520         if (ret)
5521                 return ret;
5522
5523         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5524                 ret =  mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5525                 if (ret)
5526                         return ret;
5527         }
5528
5529         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5530                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5531                                                     &mdev_port_num);
5532                 if (!mdev) {
5533                         /* If port is not affiliated yet, its in down state
5534                          * which doesn't have any counters yet, so it would be
5535                          * zero. So no need to read from the HCA.
5536                          */
5537                         goto done;
5538                 }
5539                 ret = mlx5_lag_query_cong_counters(dev->mdev,
5540                                                    stats->value +
5541                                                    port->cnts.num_q_counters,
5542                                                    port->cnts.num_cong_counters,
5543                                                    port->cnts.offsets +
5544                                                    port->cnts.num_q_counters);
5545
5546                 mlx5_ib_put_native_port_mdev(dev, port_num);
5547                 if (ret)
5548                         return ret;
5549         }
5550
5551 done:
5552         return num_counters;
5553 }
5554
5555 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5556                                  enum rdma_netdev_t type,
5557                                  struct rdma_netdev_alloc_params *params)
5558 {
5559         if (type != RDMA_NETDEV_IPOIB)
5560                 return -EOPNOTSUPP;
5561
5562         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5563 }
5564
5565 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5566 {
5567         if (!dev->delay_drop.dbg)
5568                 return;
5569         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5570         kfree(dev->delay_drop.dbg);
5571         dev->delay_drop.dbg = NULL;
5572 }
5573
5574 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5575 {
5576         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5577                 return;
5578
5579         cancel_work_sync(&dev->delay_drop.delay_drop_work);
5580         delay_drop_debugfs_cleanup(dev);
5581 }
5582
5583 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5584                                        size_t count, loff_t *pos)
5585 {
5586         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5587         char lbuf[20];
5588         int len;
5589
5590         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5591         return simple_read_from_buffer(buf, count, pos, lbuf, len);
5592 }
5593
5594 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5595                                         size_t count, loff_t *pos)
5596 {
5597         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5598         u32 timeout;
5599         u32 var;
5600
5601         if (kstrtouint_from_user(buf, count, 0, &var))
5602                 return -EFAULT;
5603
5604         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5605                         1000);
5606         if (timeout != var)
5607                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5608                             timeout);
5609
5610         delay_drop->timeout = timeout;
5611
5612         return count;
5613 }
5614
5615 static const struct file_operations fops_delay_drop_timeout = {
5616         .owner  = THIS_MODULE,
5617         .open   = simple_open,
5618         .write  = delay_drop_timeout_write,
5619         .read   = delay_drop_timeout_read,
5620 };
5621
5622 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5623 {
5624         struct mlx5_ib_dbg_delay_drop *dbg;
5625
5626         if (!mlx5_debugfs_root)
5627                 return 0;
5628
5629         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5630         if (!dbg)
5631                 return -ENOMEM;
5632
5633         dev->delay_drop.dbg = dbg;
5634
5635         dbg->dir_debugfs =
5636                 debugfs_create_dir("delay_drop",
5637                                    dev->mdev->priv.dbg_root);
5638         if (!dbg->dir_debugfs)
5639                 goto out_debugfs;
5640
5641         dbg->events_cnt_debugfs =
5642                 debugfs_create_atomic_t("num_timeout_events", 0400,
5643                                         dbg->dir_debugfs,
5644                                         &dev->delay_drop.events_cnt);
5645         if (!dbg->events_cnt_debugfs)
5646                 goto out_debugfs;
5647
5648         dbg->rqs_cnt_debugfs =
5649                 debugfs_create_atomic_t("num_rqs", 0400,
5650                                         dbg->dir_debugfs,
5651                                         &dev->delay_drop.rqs_cnt);
5652         if (!dbg->rqs_cnt_debugfs)
5653                 goto out_debugfs;
5654
5655         dbg->timeout_debugfs =
5656                 debugfs_create_file("timeout", 0600,
5657                                     dbg->dir_debugfs,
5658                                     &dev->delay_drop,
5659                                     &fops_delay_drop_timeout);
5660         if (!dbg->timeout_debugfs)
5661                 goto out_debugfs;
5662
5663         return 0;
5664
5665 out_debugfs:
5666         delay_drop_debugfs_cleanup(dev);
5667         return -ENOMEM;
5668 }
5669
5670 static void init_delay_drop(struct mlx5_ib_dev *dev)
5671 {
5672         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5673                 return;
5674
5675         mutex_init(&dev->delay_drop.lock);
5676         dev->delay_drop.dev = dev;
5677         dev->delay_drop.activate = false;
5678         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5679         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5680         atomic_set(&dev->delay_drop.rqs_cnt, 0);
5681         atomic_set(&dev->delay_drop.events_cnt, 0);
5682
5683         if (delay_drop_debugfs_init(dev))
5684                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5685 }
5686
5687 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5688 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5689                                       struct mlx5_ib_multiport_info *mpi)
5690 {
5691         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5692         struct mlx5_ib_port *port = &ibdev->port[port_num];
5693         int comps;
5694         int err;
5695         int i;
5696
5697         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5698
5699         spin_lock(&port->mp.mpi_lock);
5700         if (!mpi->ibdev) {
5701                 spin_unlock(&port->mp.mpi_lock);
5702                 return;
5703         }
5704
5705         if (mpi->mdev_events.notifier_call)
5706                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5707         mpi->mdev_events.notifier_call = NULL;
5708
5709         mpi->ibdev = NULL;
5710
5711         spin_unlock(&port->mp.mpi_lock);
5712         mlx5_remove_netdev_notifier(ibdev, port_num);
5713         spin_lock(&port->mp.mpi_lock);
5714
5715         comps = mpi->mdev_refcnt;
5716         if (comps) {
5717                 mpi->unaffiliate = true;
5718                 init_completion(&mpi->unref_comp);
5719                 spin_unlock(&port->mp.mpi_lock);
5720
5721                 for (i = 0; i < comps; i++)
5722                         wait_for_completion(&mpi->unref_comp);
5723
5724                 spin_lock(&port->mp.mpi_lock);
5725                 mpi->unaffiliate = false;
5726         }
5727
5728         port->mp.mpi = NULL;
5729
5730         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5731
5732         spin_unlock(&port->mp.mpi_lock);
5733
5734         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5735
5736         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5737         /* Log an error, still needed to cleanup the pointers and add
5738          * it back to the list.
5739          */
5740         if (err)
5741                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5742                             port_num + 1);
5743
5744         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
5745 }
5746
5747 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5748 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5749                                     struct mlx5_ib_multiport_info *mpi)
5750 {
5751         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5752         int err;
5753
5754         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5755         if (ibdev->port[port_num].mp.mpi) {
5756                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5757                             port_num + 1);
5758                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5759                 return false;
5760         }
5761
5762         ibdev->port[port_num].mp.mpi = mpi;
5763         mpi->ibdev = ibdev;
5764         mpi->mdev_events.notifier_call = NULL;
5765         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5766
5767         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5768         if (err)
5769                 goto unbind;
5770
5771         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5772         if (err)
5773                 goto unbind;
5774
5775         err = mlx5_add_netdev_notifier(ibdev, port_num);
5776         if (err) {
5777                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5778                             port_num + 1);
5779                 goto unbind;
5780         }
5781
5782         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5783         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5784
5785         mlx5_ib_init_cong_debugfs(ibdev, port_num);
5786
5787         return true;
5788
5789 unbind:
5790         mlx5_ib_unbind_slave_port(ibdev, mpi);
5791         return false;
5792 }
5793
5794 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5795 {
5796         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5797         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5798                                                           port_num + 1);
5799         struct mlx5_ib_multiport_info *mpi;
5800         int err;
5801         int i;
5802
5803         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5804                 return 0;
5805
5806         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5807                                                      &dev->sys_image_guid);
5808         if (err)
5809                 return err;
5810
5811         err = mlx5_nic_vport_enable_roce(dev->mdev);
5812         if (err)
5813                 return err;
5814
5815         mutex_lock(&mlx5_ib_multiport_mutex);
5816         for (i = 0; i < dev->num_ports; i++) {
5817                 bool bound = false;
5818
5819                 /* build a stub multiport info struct for the native port. */
5820                 if (i == port_num) {
5821                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5822                         if (!mpi) {
5823                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5824                                 mlx5_nic_vport_disable_roce(dev->mdev);
5825                                 return -ENOMEM;
5826                         }
5827
5828                         mpi->is_master = true;
5829                         mpi->mdev = dev->mdev;
5830                         mpi->sys_image_guid = dev->sys_image_guid;
5831                         dev->port[i].mp.mpi = mpi;
5832                         mpi->ibdev = dev;
5833                         mpi = NULL;
5834                         continue;
5835                 }
5836
5837                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5838                                     list) {
5839                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5840                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5841                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5842                         }
5843
5844                         if (bound) {
5845                                 dev_dbg(mpi->mdev->device,
5846                                         "removing port from unaffiliated list.\n");
5847                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5848                                 list_del(&mpi->list);
5849                                 break;
5850                         }
5851                 }
5852                 if (!bound) {
5853                         get_port_caps(dev, i + 1);
5854                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5855                                     i + 1);
5856                 }
5857         }
5858
5859         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5860         mutex_unlock(&mlx5_ib_multiport_mutex);
5861         return err;
5862 }
5863
5864 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5865 {
5866         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5867         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5868                                                           port_num + 1);
5869         int i;
5870
5871         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5872                 return;
5873
5874         mutex_lock(&mlx5_ib_multiport_mutex);
5875         for (i = 0; i < dev->num_ports; i++) {
5876                 if (dev->port[i].mp.mpi) {
5877                         /* Destroy the native port stub */
5878                         if (i == port_num) {
5879                                 kfree(dev->port[i].mp.mpi);
5880                                 dev->port[i].mp.mpi = NULL;
5881                         } else {
5882                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5883                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5884                         }
5885                 }
5886         }
5887
5888         mlx5_ib_dbg(dev, "removing from devlist\n");
5889         list_del(&dev->ib_dev_list);
5890         mutex_unlock(&mlx5_ib_multiport_mutex);
5891
5892         mlx5_nic_vport_disable_roce(dev->mdev);
5893 }
5894
5895 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5896         mlx5_ib_dm,
5897         UVERBS_OBJECT_DM,
5898         UVERBS_METHOD_DM_ALLOC,
5899         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5900                             UVERBS_ATTR_TYPE(u64),
5901                             UA_MANDATORY),
5902         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5903                             UVERBS_ATTR_TYPE(u16),
5904                             UA_OPTIONAL),
5905         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
5906                              enum mlx5_ib_uapi_dm_type,
5907                              UA_OPTIONAL));
5908
5909 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5910         mlx5_ib_flow_action,
5911         UVERBS_OBJECT_FLOW_ACTION,
5912         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5913         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5914                              enum mlx5_ib_uapi_flow_action_flags));
5915
5916 static const struct uapi_definition mlx5_ib_defs[] = {
5917 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
5918         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
5919         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
5920 #endif
5921
5922         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
5923                                 &mlx5_ib_flow_action),
5924         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
5925         {}
5926 };
5927
5928 static int mlx5_ib_read_counters(struct ib_counters *counters,
5929                                  struct ib_counters_read_attr *read_attr,
5930                                  struct uverbs_attr_bundle *attrs)
5931 {
5932         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5933         struct mlx5_read_counters_attr mread_attr = {};
5934         struct mlx5_ib_flow_counters_desc *desc;
5935         int ret, i;
5936
5937         mutex_lock(&mcounters->mcntrs_mutex);
5938         if (mcounters->cntrs_max_index > read_attr->ncounters) {
5939                 ret = -EINVAL;
5940                 goto err_bound;
5941         }
5942
5943         mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5944                                  GFP_KERNEL);
5945         if (!mread_attr.out) {
5946                 ret = -ENOMEM;
5947                 goto err_bound;
5948         }
5949
5950         mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5951         mread_attr.flags = read_attr->flags;
5952         ret = mcounters->read_counters(counters->device, &mread_attr);
5953         if (ret)
5954                 goto err_read;
5955
5956         /* do the pass over the counters data array to assign according to the
5957          * descriptions and indexing pairs
5958          */
5959         desc = mcounters->counters_data;
5960         for (i = 0; i < mcounters->ncounters; i++)
5961                 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5962
5963 err_read:
5964         kfree(mread_attr.out);
5965 err_bound:
5966         mutex_unlock(&mcounters->mcntrs_mutex);
5967         return ret;
5968 }
5969
5970 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5971 {
5972         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5973
5974         counters_clear_description(counters);
5975         if (mcounters->hw_cntrs_hndl)
5976                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5977                                 mcounters->hw_cntrs_hndl);
5978
5979         kfree(mcounters);
5980
5981         return 0;
5982 }
5983
5984 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5985                                                    struct uverbs_attr_bundle *attrs)
5986 {
5987         struct mlx5_ib_mcounters *mcounters;
5988
5989         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5990         if (!mcounters)
5991                 return ERR_PTR(-ENOMEM);
5992
5993         mutex_init(&mcounters->mcntrs_mutex);
5994
5995         return &mcounters->ibcntrs;
5996 }
5997
5998 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5999 {
6000         struct mlx5_core_dev *mdev = dev->mdev;
6001
6002         mlx5_ib_cleanup_multiport_master(dev);
6003         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6004                 srcu_barrier(&dev->mr_srcu);
6005                 cleanup_srcu_struct(&dev->mr_srcu);
6006         }
6007
6008         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
6009
6010         WARN_ON(dev->dm.steering_sw_icm_alloc_blocks &&
6011                 !bitmap_empty(
6012                         dev->dm.steering_sw_icm_alloc_blocks,
6013                         BIT(MLX5_CAP_DEV_MEM(mdev, log_steering_sw_icm_size) -
6014                             MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6015
6016         kfree(dev->dm.steering_sw_icm_alloc_blocks);
6017
6018         WARN_ON(dev->dm.header_modify_sw_icm_alloc_blocks &&
6019                 !bitmap_empty(dev->dm.header_modify_sw_icm_alloc_blocks,
6020                               BIT(MLX5_CAP_DEV_MEM(
6021                                           mdev, log_header_modify_sw_icm_size) -
6022                                   MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev))));
6023
6024         kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6025 }
6026
6027 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
6028 {
6029         struct mlx5_core_dev *mdev = dev->mdev;
6030         u64 header_modify_icm_blocks = 0;
6031         u64 steering_icm_blocks = 0;
6032         int err;
6033         int i;
6034
6035         for (i = 0; i < dev->num_ports; i++) {
6036                 spin_lock_init(&dev->port[i].mp.mpi_lock);
6037                 rwlock_init(&dev->port[i].roce.netdev_lock);
6038                 dev->port[i].roce.dev = dev;
6039                 dev->port[i].roce.native_port_num = i + 1;
6040                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
6041         }
6042
6043         err = mlx5_ib_init_multiport_master(dev);
6044         if (err)
6045                 return err;
6046
6047         err = set_has_smi_cap(dev);
6048         if (err)
6049                 return err;
6050
6051         if (!mlx5_core_mp_enabled(mdev)) {
6052                 for (i = 1; i <= dev->num_ports; i++) {
6053                         err = get_port_caps(dev, i);
6054                         if (err)
6055                                 break;
6056                 }
6057         } else {
6058                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6059         }
6060         if (err)
6061                 goto err_mp;
6062
6063         if (mlx5_use_mad_ifc(dev))
6064                 get_ext_port_caps(dev);
6065
6066         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
6067         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
6068         dev->ib_dev.phys_port_cnt       = dev->num_ports;
6069         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
6070         dev->ib_dev.dev.parent          = mdev->device;
6071
6072         mutex_init(&dev->cap_mask_mutex);
6073         INIT_LIST_HEAD(&dev->qp_list);
6074         spin_lock_init(&dev->reset_flow_resource_lock);
6075
6076         if (MLX5_CAP_GEN_64(mdev, general_obj_types) &
6077             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) {
6078                 if (MLX5_CAP64_DEV_MEM(mdev, steering_sw_icm_start_address)) {
6079                         steering_icm_blocks =
6080                                 BIT(MLX5_CAP_DEV_MEM(mdev,
6081                                                      log_steering_sw_icm_size) -
6082                                     MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6083
6084                         dev->dm.steering_sw_icm_alloc_blocks =
6085                                 kcalloc(BITS_TO_LONGS(steering_icm_blocks),
6086                                         sizeof(unsigned long), GFP_KERNEL);
6087                         if (!dev->dm.steering_sw_icm_alloc_blocks)
6088                                 goto err_mp;
6089                 }
6090
6091                 if (MLX5_CAP64_DEV_MEM(mdev,
6092                                        header_modify_sw_icm_start_address)) {
6093                         header_modify_icm_blocks = BIT(
6094                                 MLX5_CAP_DEV_MEM(
6095                                         mdev, log_header_modify_sw_icm_size) -
6096                                 MLX5_LOG_SW_ICM_BLOCK_SIZE(mdev));
6097
6098                         dev->dm.header_modify_sw_icm_alloc_blocks =
6099                                 kcalloc(BITS_TO_LONGS(header_modify_icm_blocks),
6100                                         sizeof(unsigned long), GFP_KERNEL);
6101                         if (!dev->dm.header_modify_sw_icm_alloc_blocks)
6102                                 goto err_dm;
6103                 }
6104         }
6105
6106         spin_lock_init(&dev->dm.lock);
6107         dev->dm.dev = mdev;
6108
6109         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6110                 err = init_srcu_struct(&dev->mr_srcu);
6111                 if (err)
6112                         goto err_dm;
6113         }
6114
6115         return 0;
6116
6117 err_dm:
6118         kfree(dev->dm.steering_sw_icm_alloc_blocks);
6119         kfree(dev->dm.header_modify_sw_icm_alloc_blocks);
6120
6121 err_mp:
6122         mlx5_ib_cleanup_multiport_master(dev);
6123
6124         return -ENOMEM;
6125 }
6126
6127 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6128 {
6129         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6130
6131         if (!dev->flow_db)
6132                 return -ENOMEM;
6133
6134         mutex_init(&dev->flow_db->lock);
6135
6136         return 0;
6137 }
6138
6139 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6140 {
6141         kfree(dev->flow_db);
6142 }
6143
6144 static const struct ib_device_ops mlx5_ib_dev_ops = {
6145         .owner = THIS_MODULE,
6146         .driver_id = RDMA_DRIVER_MLX5,
6147         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
6148
6149         .add_gid = mlx5_ib_add_gid,
6150         .alloc_mr = mlx5_ib_alloc_mr,
6151         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
6152         .alloc_pd = mlx5_ib_alloc_pd,
6153         .alloc_ucontext = mlx5_ib_alloc_ucontext,
6154         .attach_mcast = mlx5_ib_mcg_attach,
6155         .check_mr_status = mlx5_ib_check_mr_status,
6156         .create_ah = mlx5_ib_create_ah,
6157         .create_counters = mlx5_ib_create_counters,
6158         .create_cq = mlx5_ib_create_cq,
6159         .create_flow = mlx5_ib_create_flow,
6160         .create_qp = mlx5_ib_create_qp,
6161         .create_srq = mlx5_ib_create_srq,
6162         .dealloc_pd = mlx5_ib_dealloc_pd,
6163         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6164         .del_gid = mlx5_ib_del_gid,
6165         .dereg_mr = mlx5_ib_dereg_mr,
6166         .destroy_ah = mlx5_ib_destroy_ah,
6167         .destroy_counters = mlx5_ib_destroy_counters,
6168         .destroy_cq = mlx5_ib_destroy_cq,
6169         .destroy_flow = mlx5_ib_destroy_flow,
6170         .destroy_flow_action = mlx5_ib_destroy_flow_action,
6171         .destroy_qp = mlx5_ib_destroy_qp,
6172         .destroy_srq = mlx5_ib_destroy_srq,
6173         .detach_mcast = mlx5_ib_mcg_detach,
6174         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6175         .drain_rq = mlx5_ib_drain_rq,
6176         .drain_sq = mlx5_ib_drain_sq,
6177         .get_dev_fw_str = get_dev_fw_str,
6178         .get_dma_mr = mlx5_ib_get_dma_mr,
6179         .get_link_layer = mlx5_ib_port_link_layer,
6180         .map_mr_sg = mlx5_ib_map_mr_sg,
6181         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
6182         .mmap = mlx5_ib_mmap,
6183         .modify_cq = mlx5_ib_modify_cq,
6184         .modify_device = mlx5_ib_modify_device,
6185         .modify_port = mlx5_ib_modify_port,
6186         .modify_qp = mlx5_ib_modify_qp,
6187         .modify_srq = mlx5_ib_modify_srq,
6188         .poll_cq = mlx5_ib_poll_cq,
6189         .post_recv = mlx5_ib_post_recv,
6190         .post_send = mlx5_ib_post_send,
6191         .post_srq_recv = mlx5_ib_post_srq_recv,
6192         .process_mad = mlx5_ib_process_mad,
6193         .query_ah = mlx5_ib_query_ah,
6194         .query_device = mlx5_ib_query_device,
6195         .query_gid = mlx5_ib_query_gid,
6196         .query_pkey = mlx5_ib_query_pkey,
6197         .query_qp = mlx5_ib_query_qp,
6198         .query_srq = mlx5_ib_query_srq,
6199         .read_counters = mlx5_ib_read_counters,
6200         .reg_user_mr = mlx5_ib_reg_user_mr,
6201         .req_notify_cq = mlx5_ib_arm_cq,
6202         .rereg_user_mr = mlx5_ib_rereg_user_mr,
6203         .resize_cq = mlx5_ib_resize_cq,
6204
6205         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
6206         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
6207         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
6208         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
6209         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
6210 };
6211
6212 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6213         .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6214         .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6215 };
6216
6217 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6218         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6219 };
6220
6221 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6222         .get_vf_config = mlx5_ib_get_vf_config,
6223         .get_vf_stats = mlx5_ib_get_vf_stats,
6224         .set_vf_guid = mlx5_ib_set_vf_guid,
6225         .set_vf_link_state = mlx5_ib_set_vf_link_state,
6226 };
6227
6228 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6229         .alloc_mw = mlx5_ib_alloc_mw,
6230         .dealloc_mw = mlx5_ib_dealloc_mw,
6231 };
6232
6233 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6234         .alloc_xrcd = mlx5_ib_alloc_xrcd,
6235         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6236 };
6237
6238 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6239         .alloc_dm = mlx5_ib_alloc_dm,
6240         .dealloc_dm = mlx5_ib_dealloc_dm,
6241         .reg_dm_mr = mlx5_ib_reg_dm_mr,
6242 };
6243
6244 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
6245 {
6246         struct mlx5_core_dev *mdev = dev->mdev;
6247         int err;
6248
6249         dev->ib_dev.uverbs_cmd_mask     =
6250                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
6251                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
6252                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
6253                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
6254                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
6255                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
6256                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
6257                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
6258                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
6259                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
6260                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6261                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
6262                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
6263                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
6264                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
6265                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
6266                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
6267                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
6268                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
6269                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
6270                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
6271                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
6272                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
6273                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
6274                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
6275                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
6276         dev->ib_dev.uverbs_ex_cmd_mask =
6277                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
6278                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
6279                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
6280                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
6281                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ)        |
6282                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW)      |
6283                 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6284
6285         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6286             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
6287                 ib_set_device_ops(&dev->ib_dev,
6288                                   &mlx5_ib_dev_ipoib_enhanced_ops);
6289
6290         if (mlx5_core_is_pf(mdev))
6291                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
6292
6293         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6294
6295         if (MLX5_CAP_GEN(mdev, imaicl)) {
6296                 dev->ib_dev.uverbs_cmd_mask |=
6297                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
6298                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
6299                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
6300         }
6301
6302         if (MLX5_CAP_GEN(mdev, xrc)) {
6303                 dev->ib_dev.uverbs_cmd_mask |=
6304                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6305                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
6306                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
6307         }
6308
6309         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6310             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6311             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
6312                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
6313
6314         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
6315             MLX5_ACCEL_IPSEC_CAP_DEVICE)
6316                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
6317         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
6318
6319         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6320                 dev->ib_dev.driver_def = mlx5_ib_defs;
6321
6322         err = init_node_data(dev);
6323         if (err)
6324                 return err;
6325
6326         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
6327             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6328              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
6329                 mutex_init(&dev->lb.mutex);
6330
6331         return 0;
6332 }
6333
6334 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6335         .get_port_immutable = mlx5_port_immutable,
6336         .query_port = mlx5_ib_query_port,
6337 };
6338
6339 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6340 {
6341         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
6342         return 0;
6343 }
6344
6345 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6346         .get_port_immutable = mlx5_port_rep_immutable,
6347         .query_port = mlx5_ib_rep_query_port,
6348 };
6349
6350 static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
6351 {
6352         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
6353         return 0;
6354 }
6355
6356 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6357         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6358         .create_wq = mlx5_ib_create_wq,
6359         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6360         .destroy_wq = mlx5_ib_destroy_wq,
6361         .get_netdev = mlx5_ib_get_netdev,
6362         .modify_wq = mlx5_ib_modify_wq,
6363 };
6364
6365 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
6366 {
6367         u8 port_num;
6368
6369         dev->ib_dev.uverbs_ex_cmd_mask |=
6370                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6371                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6372                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6373                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6374                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6375         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
6376
6377         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6378
6379         /* Register only for native ports */
6380         return mlx5_add_netdev_notifier(dev, port_num);
6381 }
6382
6383 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6384 {
6385         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6386
6387         mlx5_remove_netdev_notifier(dev, port_num);
6388 }
6389
6390 static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6391 {
6392         struct mlx5_core_dev *mdev = dev->mdev;
6393         enum rdma_link_layer ll;
6394         int port_type_cap;
6395         int err = 0;
6396
6397         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6398         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6399
6400         if (ll == IB_LINK_LAYER_ETHERNET)
6401                 err = mlx5_ib_stage_common_roce_init(dev);
6402
6403         return err;
6404 }
6405
6406 static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6407 {
6408         mlx5_ib_stage_common_roce_cleanup(dev);
6409 }
6410
6411 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6412 {
6413         struct mlx5_core_dev *mdev = dev->mdev;
6414         enum rdma_link_layer ll;
6415         int port_type_cap;
6416         int err;
6417
6418         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6419         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6420
6421         if (ll == IB_LINK_LAYER_ETHERNET) {
6422                 err = mlx5_ib_stage_common_roce_init(dev);
6423                 if (err)
6424                         return err;
6425
6426                 err = mlx5_enable_eth(dev);
6427                 if (err)
6428                         goto cleanup;
6429         }
6430
6431         return 0;
6432 cleanup:
6433         mlx5_ib_stage_common_roce_cleanup(dev);
6434
6435         return err;
6436 }
6437
6438 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6439 {
6440         struct mlx5_core_dev *mdev = dev->mdev;
6441         enum rdma_link_layer ll;
6442         int port_type_cap;
6443
6444         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6445         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6446
6447         if (ll == IB_LINK_LAYER_ETHERNET) {
6448                 mlx5_disable_eth(dev);
6449                 mlx5_ib_stage_common_roce_cleanup(dev);
6450         }
6451 }
6452
6453 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6454 {
6455         return create_dev_resources(&dev->devr);
6456 }
6457
6458 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6459 {
6460         destroy_dev_resources(&dev->devr);
6461 }
6462
6463 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6464 {
6465         mlx5_ib_internal_fill_odp_caps(dev);
6466
6467         return mlx5_ib_odp_init_one(dev);
6468 }
6469
6470 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6471 {
6472         mlx5_ib_odp_cleanup_one(dev);
6473 }
6474
6475 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6476         .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6477         .get_hw_stats = mlx5_ib_get_hw_stats,
6478 };
6479
6480 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6481 {
6482         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6483                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
6484
6485                 return mlx5_ib_alloc_counters(dev);
6486         }
6487
6488         return 0;
6489 }
6490
6491 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6492 {
6493         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6494                 mlx5_ib_dealloc_counters(dev);
6495 }
6496
6497 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6498 {
6499         mlx5_ib_init_cong_debugfs(dev,
6500                                   mlx5_core_native_port_num(dev->mdev) - 1);
6501         return 0;
6502 }
6503
6504 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6505 {
6506         mlx5_ib_cleanup_cong_debugfs(dev,
6507                                      mlx5_core_native_port_num(dev->mdev) - 1);
6508 }
6509
6510 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6511 {
6512         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6513         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6514 }
6515
6516 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6517 {
6518         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6519 }
6520
6521 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6522 {
6523         int err;
6524
6525         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6526         if (err)
6527                 return err;
6528
6529         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6530         if (err)
6531                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6532
6533         return err;
6534 }
6535
6536 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6537 {
6538         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6539         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6540 }
6541
6542 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6543 {
6544         const char *name;
6545
6546         rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
6547         if (!mlx5_lag_is_roce(dev->mdev))
6548                 name = "mlx5_%d";
6549         else
6550                 name = "mlx5_bond_%d";
6551         return ib_register_device(&dev->ib_dev, name);
6552 }
6553
6554 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6555 {
6556         destroy_umrc_res(dev);
6557 }
6558
6559 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6560 {
6561         ib_unregister_device(&dev->ib_dev);
6562 }
6563
6564 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6565 {
6566         return create_umr_res(dev);
6567 }
6568
6569 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6570 {
6571         init_delay_drop(dev);
6572
6573         return 0;
6574 }
6575
6576 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6577 {
6578         cancel_delay_drop(dev);
6579 }
6580
6581 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6582 {
6583         dev->mdev_events.notifier_call = mlx5_ib_event;
6584         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6585         return 0;
6586 }
6587
6588 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6589 {
6590         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6591 }
6592
6593 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6594 {
6595         int uid;
6596
6597         uid = mlx5_ib_devx_create(dev, false);
6598         if (uid > 0)
6599                 dev->devx_whitelist_uid = uid;
6600
6601         return 0;
6602 }
6603 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6604 {
6605         if (dev->devx_whitelist_uid)
6606                 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6607 }
6608
6609 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6610                       const struct mlx5_ib_profile *profile,
6611                       int stage)
6612 {
6613         /* Number of stages to cleanup */
6614         while (stage) {
6615                 stage--;
6616                 if (profile->stage[stage].cleanup)
6617                         profile->stage[stage].cleanup(dev);
6618         }
6619
6620         kfree(dev->port);
6621         ib_dealloc_device(&dev->ib_dev);
6622 }
6623
6624 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6625                     const struct mlx5_ib_profile *profile)
6626 {
6627         int err;
6628         int i;
6629
6630         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6631                 if (profile->stage[i].init) {
6632                         err = profile->stage[i].init(dev);
6633                         if (err)
6634                                 goto err_out;
6635                 }
6636         }
6637
6638         dev->profile = profile;
6639         dev->ib_active = true;
6640
6641         return dev;
6642
6643 err_out:
6644         __mlx5_ib_remove(dev, profile, i);
6645
6646         return NULL;
6647 }
6648
6649 static const struct mlx5_ib_profile pf_profile = {
6650         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6651                      mlx5_ib_stage_init_init,
6652                      mlx5_ib_stage_init_cleanup),
6653         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6654                      mlx5_ib_stage_flow_db_init,
6655                      mlx5_ib_stage_flow_db_cleanup),
6656         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6657                      mlx5_ib_stage_caps_init,
6658                      NULL),
6659         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6660                      mlx5_ib_stage_non_default_cb,
6661                      NULL),
6662         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6663                      mlx5_ib_stage_roce_init,
6664                      mlx5_ib_stage_roce_cleanup),
6665         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6666                      mlx5_init_srq_table,
6667                      mlx5_cleanup_srq_table),
6668         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6669                      mlx5_ib_stage_dev_res_init,
6670                      mlx5_ib_stage_dev_res_cleanup),
6671         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6672                      mlx5_ib_stage_dev_notifier_init,
6673                      mlx5_ib_stage_dev_notifier_cleanup),
6674         STAGE_CREATE(MLX5_IB_STAGE_ODP,
6675                      mlx5_ib_stage_odp_init,
6676                      mlx5_ib_stage_odp_cleanup),
6677         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6678                      mlx5_ib_stage_counters_init,
6679                      mlx5_ib_stage_counters_cleanup),
6680         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6681                      mlx5_ib_stage_cong_debugfs_init,
6682                      mlx5_ib_stage_cong_debugfs_cleanup),
6683         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6684                      mlx5_ib_stage_uar_init,
6685                      mlx5_ib_stage_uar_cleanup),
6686         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6687                      mlx5_ib_stage_bfrag_init,
6688                      mlx5_ib_stage_bfrag_cleanup),
6689         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6690                      NULL,
6691                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6692         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6693                      mlx5_ib_stage_devx_init,
6694                      mlx5_ib_stage_devx_cleanup),
6695         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6696                      mlx5_ib_stage_ib_reg_init,
6697                      mlx5_ib_stage_ib_reg_cleanup),
6698         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6699                      mlx5_ib_stage_post_ib_reg_umr_init,
6700                      NULL),
6701         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6702                      mlx5_ib_stage_delay_drop_init,
6703                      mlx5_ib_stage_delay_drop_cleanup),
6704 };
6705
6706 const struct mlx5_ib_profile uplink_rep_profile = {
6707         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6708                      mlx5_ib_stage_init_init,
6709                      mlx5_ib_stage_init_cleanup),
6710         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6711                      mlx5_ib_stage_flow_db_init,
6712                      mlx5_ib_stage_flow_db_cleanup),
6713         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6714                      mlx5_ib_stage_caps_init,
6715                      NULL),
6716         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6717                      mlx5_ib_stage_rep_non_default_cb,
6718                      NULL),
6719         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6720                      mlx5_ib_stage_rep_roce_init,
6721                      mlx5_ib_stage_rep_roce_cleanup),
6722         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6723                      mlx5_init_srq_table,
6724                      mlx5_cleanup_srq_table),
6725         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6726                      mlx5_ib_stage_dev_res_init,
6727                      mlx5_ib_stage_dev_res_cleanup),
6728         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6729                      mlx5_ib_stage_dev_notifier_init,
6730                      mlx5_ib_stage_dev_notifier_cleanup),
6731         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6732                      mlx5_ib_stage_counters_init,
6733                      mlx5_ib_stage_counters_cleanup),
6734         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6735                      mlx5_ib_stage_uar_init,
6736                      mlx5_ib_stage_uar_cleanup),
6737         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6738                      mlx5_ib_stage_bfrag_init,
6739                      mlx5_ib_stage_bfrag_cleanup),
6740         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6741                      NULL,
6742                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6743         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6744                      mlx5_ib_stage_devx_init,
6745                      mlx5_ib_stage_devx_cleanup),
6746         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6747                      mlx5_ib_stage_ib_reg_init,
6748                      mlx5_ib_stage_ib_reg_cleanup),
6749         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6750                      mlx5_ib_stage_post_ib_reg_umr_init,
6751                      NULL),
6752 };
6753
6754 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6755 {
6756         struct mlx5_ib_multiport_info *mpi;
6757         struct mlx5_ib_dev *dev;
6758         bool bound = false;
6759         int err;
6760
6761         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6762         if (!mpi)
6763                 return NULL;
6764
6765         mpi->mdev = mdev;
6766
6767         err = mlx5_query_nic_vport_system_image_guid(mdev,
6768                                                      &mpi->sys_image_guid);
6769         if (err) {
6770                 kfree(mpi);
6771                 return NULL;
6772         }
6773
6774         mutex_lock(&mlx5_ib_multiport_mutex);
6775         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6776                 if (dev->sys_image_guid == mpi->sys_image_guid)
6777                         bound = mlx5_ib_bind_slave_port(dev, mpi);
6778
6779                 if (bound) {
6780                         rdma_roce_rescan_device(&dev->ib_dev);
6781                         break;
6782                 }
6783         }
6784
6785         if (!bound) {
6786                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6787                 dev_dbg(mdev->device,
6788                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
6789         }
6790         mutex_unlock(&mlx5_ib_multiport_mutex);
6791
6792         return mpi;
6793 }
6794
6795 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6796 {
6797         enum rdma_link_layer ll;
6798         struct mlx5_ib_dev *dev;
6799         int port_type_cap;
6800         int num_ports;
6801
6802         printk_once(KERN_INFO "%s", mlx5_version);
6803
6804         if (MLX5_ESWITCH_MANAGER(mdev) &&
6805             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6806                 if (!mlx5_core_mp_enabled(mdev))
6807                         mlx5_ib_register_vport_reps(mdev);
6808                 return mdev;
6809         }
6810
6811         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6812         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6813
6814         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6815                 return mlx5_ib_add_slave_port(mdev);
6816
6817         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6818                         MLX5_CAP_GEN(mdev, num_vhca_ports));
6819         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
6820         if (!dev)
6821                 return NULL;
6822         dev->port = kcalloc(num_ports, sizeof(*dev->port),
6823                              GFP_KERNEL);
6824         if (!dev->port) {
6825                 ib_dealloc_device((struct ib_device *)dev);
6826                 return NULL;
6827         }
6828
6829         dev->mdev = mdev;
6830         dev->num_ports = num_ports;
6831
6832         return __mlx5_ib_add(dev, &pf_profile);
6833 }
6834
6835 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6836 {
6837         struct mlx5_ib_multiport_info *mpi;
6838         struct mlx5_ib_dev *dev;
6839
6840         if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6841                 mlx5_ib_unregister_vport_reps(mdev);
6842                 return;
6843         }
6844
6845         if (mlx5_core_is_mp_slave(mdev)) {
6846                 mpi = context;
6847                 mutex_lock(&mlx5_ib_multiport_mutex);
6848                 if (mpi->ibdev)
6849                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6850                 list_del(&mpi->list);
6851                 mutex_unlock(&mlx5_ib_multiport_mutex);
6852                 return;
6853         }
6854
6855         dev = context;
6856         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6857 }
6858
6859 static struct mlx5_interface mlx5_ib_interface = {
6860         .add            = mlx5_ib_add,
6861         .remove         = mlx5_ib_remove,
6862         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6863 };
6864
6865 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6866 {
6867         mutex_lock(&xlt_emergency_page_mutex);
6868         return xlt_emergency_page;
6869 }
6870
6871 void mlx5_ib_put_xlt_emergency_page(void)
6872 {
6873         mutex_unlock(&xlt_emergency_page_mutex);
6874 }
6875
6876 static int __init mlx5_ib_init(void)
6877 {
6878         int err;
6879
6880         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6881         if (!xlt_emergency_page)
6882                 return -ENOMEM;
6883
6884         mutex_init(&xlt_emergency_page_mutex);
6885
6886         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6887         if (!mlx5_ib_event_wq) {
6888                 free_page(xlt_emergency_page);
6889                 return -ENOMEM;
6890         }
6891
6892         mlx5_ib_odp_init();
6893
6894         err = mlx5_register_interface(&mlx5_ib_interface);
6895
6896         return err;
6897 }
6898
6899 static void __exit mlx5_ib_cleanup(void)
6900 {
6901         mlx5_unregister_interface(&mlx5_ib_interface);
6902         destroy_workqueue(mlx5_ib_event_wq);
6903         mutex_destroy(&xlt_emergency_page_mutex);
6904         free_page(xlt_emergency_page);
6905 }
6906
6907 module_init(mlx5_ib_init);
6908 module_exit(mlx5_ib_cleanup);