drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_cache.h>
  26 #include "amdgpu.h"
  27 #include "gmc_v8_0.h"
  28 #include "amdgpu_ucode.h"
  29 #include "amdgpu_amdkfd.h"
  30
  31 #include "gmc/gmc_8_1_d.h"
  32 #include "gmc/gmc_8_1_sh_mask.h"
  33
  34 #include "bif/bif_5_0_d.h"
  35 #include "bif/bif_5_0_sh_mask.h"
  36
  37 #include "oss/oss_3_0_d.h"
  38 #include "oss/oss_3_0_sh_mask.h"
  39
  40 #include "dce/dce_10_0_d.h"
  41 #include "dce/dce_10_0_sh_mask.h"
  42
  43 #include "vid.h"
  44 #include "vi.h"
  45
  46 #include "amdgpu_atombios.h"
  47
  48 #include "ivsrcid/ivsrcid_vislands30.h"
  49
  50 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
  51 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  52 static int gmc_v8_0_wait_for_idle(void *handle);
  53
  54 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  55 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  56 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  57 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  58
  59 static const u32 golden_settings_tonga_a11[] =
  60 {
  61         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  62         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  63         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  64         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  66         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  67         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  68 };
  69
  70 static const u32 tonga_mgcg_cgcg_init[] =
  71 {
  72         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  73 };
  74
  75 static const u32 golden_settings_fiji_a10[] =
  76 {
  77         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  78         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  79         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  80         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  81 };
  82
  83 static const u32 fiji_mgcg_cgcg_init[] =
  84 {
  85         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  86 };
  87
  88 static const u32 golden_settings_polaris11_a11[] =
  89 {
  90         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  91         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  92         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  93         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  94 };
  95
  96 static const u32 golden_settings_polaris10_a11[] =
  97 {
  98         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  99         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 100         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 101         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 102         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 103 };
 104
 105 static const u32 cz_mgcg_cgcg_init[] =
 106 {
 107         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 108 };
 109
 110 static const u32 stoney_mgcg_cgcg_init[] =
 111 {
 112         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 113         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 114 };
 115
 116 static const u32 golden_settings_stoney_common[] =
 117 {
 118         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 119         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 120 };
 121
 122 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 123 {
 124         switch (adev->asic_type) {
 125         case CHIP_FIJI:
 126                 amdgpu_device_program_register_sequence(adev,
 127                                                         fiji_mgcg_cgcg_init,
 128                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 129                 amdgpu_device_program_register_sequence(adev,
 130                                                         golden_settings_fiji_a10,
 131                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 132                 break;
 133         case CHIP_TONGA:
 134                 amdgpu_device_program_register_sequence(adev,
 135                                                         tonga_mgcg_cgcg_init,
 136                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 137                 amdgpu_device_program_register_sequence(adev,
 138                                                         golden_settings_tonga_a11,
 139                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 140                 break;
 141         case CHIP_POLARIS11:
 142         case CHIP_POLARIS12:
 143         case CHIP_VEGAM:
 144                 amdgpu_device_program_register_sequence(adev,
 145                                                         golden_settings_polaris11_a11,
 146                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 147                 break;
 148         case CHIP_POLARIS10:
 149                 amdgpu_device_program_register_sequence(adev,
 150                                                         golden_settings_polaris10_a11,
 151                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 152                 break;
 153         case CHIP_CARRIZO:
 154                 amdgpu_device_program_register_sequence(adev,
 155                                                         cz_mgcg_cgcg_init,
 156                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 157                 break;
 158         case CHIP_STONEY:
 159                 amdgpu_device_program_register_sequence(adev,
 160                                                         stoney_mgcg_cgcg_init,
 161                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 162                 amdgpu_device_program_register_sequence(adev,
 163                                                         golden_settings_stoney_common,
 164                                                         ARRAY_SIZE(golden_settings_stoney_common));
 165                 break;
 166         default:
 167                 break;
 168         }
 169 }
 170
 171 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 172 {
 173         u32 blackout;
 174
 175         gmc_v8_0_wait_for_idle(adev);
 176
 177         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 178         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 179                 /* Block CPU access */
 180                 WREG32(mmBIF_FB_EN, 0);
 181                 /* blackout the MC */
 182                 blackout = REG_SET_FIELD(blackout,
 183                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 184                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 185         }
 186         /* wait for the MC to settle */
 187         udelay(100);
 188 }
 189
 190 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 191 {
 192         u32 tmp;
 193
 194         /* unblackout the MC */
 195         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 196         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 197         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 198         /* allow CPU access */
 199         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 200         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 201         WREG32(mmBIF_FB_EN, tmp);
 202 }
 203
 204 /**
 205  * gmc_v8_0_init_microcode - load ucode images from disk
 206  *
 207  * @adev: amdgpu_device pointer
 208  *
 209  * Use the firmware interface to load the ucode images into
 210  * the driver (not loaded into hw).
 211  * Returns 0 on success, error on failure.
 212  */
 213 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 214 {
 215         const char *chip_name;
 216         char fw_name[30];
 217         int err;
 218
 219         DRM_DEBUG("\n");
 220
 221         switch (adev->asic_type) {
 222         case CHIP_TONGA:
 223                 chip_name = "tonga";
 224                 break;
 225         case CHIP_POLARIS11:
 226                 chip_name = "polaris11";
 227                 break;
 228         case CHIP_POLARIS10:
 229                 chip_name = "polaris10";
 230                 break;
 231         case CHIP_POLARIS12:
 232                 chip_name = "polaris12";
 233                 break;
 234         case CHIP_FIJI:
 235         case CHIP_CARRIZO:
 236         case CHIP_STONEY:
 237         case CHIP_VEGAM:
 238                 return 0;
 239         default: BUG();
 240         }
 241
 242         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 243         err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
 244         if (err)
 245                 goto out;
 246         err = amdgpu_ucode_validate(adev->gmc.fw);
 247
 248 out:
 249         if (err) {
 250                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 251                 release_firmware(adev->gmc.fw);
 252                 adev->gmc.fw = NULL;
 253         }
 254         return err;
 255 }
 256
 257 /**
 258  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 259  *
 260  * @adev: amdgpu_device pointer
 261  *
 262  * Load the GDDR MC ucode into the hw (CIK).
 263  * Returns 0 on success, error on failure.
 264  */
 265 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 266 {
 267         const struct mc_firmware_header_v1_0 *hdr;
 268         const __le32 *fw_data = NULL;
 269         const __le32 *io_mc_regs = NULL;
 270         u32 running;
 271         int i, ucode_size, regs_size;
 272
 273         /* Skip MC ucode loading on SR-IOV capable boards.
 274          * vbios does this for us in asic_init in that case.
 275          * Skip MC ucode loading on VF, because hypervisor will do that
 276          * for this adaptor.
 277          */
 278         if (amdgpu_sriov_bios(adev))
 279                 return 0;
 280
 281         if (!adev->gmc.fw)
 282                 return -EINVAL;
 283
 284         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 285         amdgpu_ucode_print_mc_hdr(&hdr->header);
 286
 287         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 288         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 289         io_mc_regs = (const __le32 *)
 290                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 291         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 292         fw_data = (const __le32 *)
 293                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 294
 295         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 296
 297         if (running == 0) {
 298                 /* reset the engine and set to writable */
 299                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 300                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 301
 302                 /* load mc io regs */
 303                 for (i = 0; i < regs_size; i++) {
 304                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 305                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 306                 }
 307                 /* load the MC ucode */
 308                 for (i = 0; i < ucode_size; i++)
 309                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 310
 311                 /* put the engine back into the active state */
 312                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 313                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 314                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 315
 316                 /* wait for training to complete */
 317                 for (i = 0; i < adev->usec_timeout; i++) {
 318                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 319                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 320                                 break;
 321                         udelay(1);
 322                 }
 323                 for (i = 0; i < adev->usec_timeout; i++) {
 324                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 325                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 326                                 break;
 327                         udelay(1);
 328                 }
 329         }
 330
 331         return 0;
 332 }
 333
 334 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 335 {
 336         const struct mc_firmware_header_v1_0 *hdr;
 337         const __le32 *fw_data = NULL;
 338         const __le32 *io_mc_regs = NULL;
 339         u32 data, vbios_version;
 340         int i, ucode_size, regs_size;
 341
 342         /* Skip MC ucode loading on SR-IOV capable boards.
 343          * vbios does this for us in asic_init in that case.
 344          * Skip MC ucode loading on VF, because hypervisor will do that
 345          * for this adaptor.
 346          */
 347         if (amdgpu_sriov_bios(adev))
 348                 return 0;
 349
 350         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 351         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 352         vbios_version = data & 0xf;
 353
 354         if (vbios_version == 0)
 355                 return 0;
 356
 357         if (!adev->gmc.fw)
 358                 return -EINVAL;
 359
 360         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 361         amdgpu_ucode_print_mc_hdr(&hdr->header);
 362
 363         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 364         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 365         io_mc_regs = (const __le32 *)
 366                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 367         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 368         fw_data = (const __le32 *)
 369                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 370
 371         data = RREG32(mmMC_SEQ_MISC0);
 372         data &= ~(0x40);
 373         WREG32(mmMC_SEQ_MISC0, data);
 374
 375         /* load mc io regs */
 376         for (i = 0; i < regs_size; i++) {
 377                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 378                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 379         }
 380
 381         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 382         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 383
 384         /* load the MC ucode */
 385         for (i = 0; i < ucode_size; i++)
 386                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 387
 388         /* put the engine back into the active state */
 389         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 390         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 391         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 392
 393         /* wait for training to complete */
 394         for (i = 0; i < adev->usec_timeout; i++) {
 395                 data = RREG32(mmMC_SEQ_MISC0);
 396                 if (data & 0x80)
 397                         break;
 398                 udelay(1);
 399         }
 400
 401         return 0;
 402 }
 403
 404 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 405                                        struct amdgpu_gmc *mc)
 406 {
 407         u64 base = 0;
 408
 409         if (!amdgpu_sriov_vf(adev))
 410                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 411         base <<= 24;
 412
 413         amdgpu_device_vram_location(adev, &adev->gmc, base);
 414         amdgpu_device_gart_location(adev, mc);
 415 }
 416
 417 /**
 418  * gmc_v8_0_mc_program - program the GPU memory controller
 419  *
 420  * @adev: amdgpu_device pointer
 421  *
 422  * Set the location of vram, gart, and AGP in the GPU's
 423  * physical address space (CIK).
 424  */
 425 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 426 {
 427         u32 tmp;
 428         int i, j;
 429
 430         /* Initialize HDP */
 431         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 432                 WREG32((0xb05 + j), 0x00000000);
 433                 WREG32((0xb06 + j), 0x00000000);
 434                 WREG32((0xb07 + j), 0x00000000);
 435                 WREG32((0xb08 + j), 0x00000000);
 436                 WREG32((0xb09 + j), 0x00000000);
 437         }
 438         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 439
 440         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 441                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 442         }
 443         if (adev->mode_info.num_crtc) {
 444                 /* Lockout access through VGA aperture*/
 445                 tmp = RREG32(mmVGA_HDP_CONTROL);
 446                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 447                 WREG32(mmVGA_HDP_CONTROL, tmp);
 448
 449                 /* disable VGA render */
 450                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 451                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 452                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 453         }
 454         /* Update configuration */
 455         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 456                adev->gmc.vram_start >> 12);
 457         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 458                adev->gmc.vram_end >> 12);
 459         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 460                adev->vram_scratch.gpu_addr >> 12);
 461
 462         if (amdgpu_sriov_vf(adev)) {
 463                 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
 464                 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
 465                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 466                 /* XXX double check these! */
 467                 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
 468                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 469                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 470         }
 471
 472         WREG32(mmMC_VM_AGP_BASE, 0);
 473         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 474         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 475         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 476                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 477         }
 478
 479         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 480
 481         tmp = RREG32(mmHDP_MISC_CNTL);
 482         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 483         WREG32(mmHDP_MISC_CNTL, tmp);
 484
 485         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 486         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 487 }
 488
 489 /**
 490  * gmc_v8_0_mc_init - initialize the memory controller driver params
 491  *
 492  * @adev: amdgpu_device pointer
 493  *
 494  * Look up the amount of vram, vram width, and decide how to place
 495  * vram and gart within the GPU's physical address space (CIK).
 496  * Returns 0 for success.
 497  */
 498 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 499 {
 500         int r;
 501
 502         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 503         if (!adev->gmc.vram_width) {
 504                 u32 tmp;
 505                 int chansize, numchan;
 506
 507                 /* Get VRAM informations */
 508                 tmp = RREG32(mmMC_ARB_RAMCFG);
 509                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 510                         chansize = 64;
 511                 } else {
 512                         chansize = 32;
 513                 }
 514                 tmp = RREG32(mmMC_SHARED_CHMAP);
 515                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 516                 case 0:
 517                 default:
 518                         numchan = 1;
 519                         break;
 520                 case 1:
 521                         numchan = 2;
 522                         break;
 523                 case 2:
 524                         numchan = 4;
 525                         break;
 526                 case 3:
 527                         numchan = 8;
 528                         break;
 529                 case 4:
 530                         numchan = 3;
 531                         break;
 532                 case 5:
 533                         numchan = 6;
 534                         break;
 535                 case 6:
 536                         numchan = 10;
 537                         break;
 538                 case 7:
 539                         numchan = 12;
 540                         break;
 541                 case 8:
 542                         numchan = 16;
 543                         break;
 544                 }
 545                 adev->gmc.vram_width = numchan * chansize;
 546         }
 547         /* size in MB on si */
 548         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 549         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 550
 551         if (!(adev->flags & AMD_IS_APU)) {
 552                 r = amdgpu_device_resize_fb_bar(adev);
 553                 if (r)
 554                         return r;
 555         }
 556         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 557         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 558
 559 #ifdef CONFIG_X86_64
 560         if (adev->flags & AMD_IS_APU) {
 561                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 562                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 563         }
 564 #endif
 565
 566         /* In case the PCI BAR is larger than the actual amount of vram */
 567         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 568         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 569                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 570
 571         /* set the gart size */
 572         if (amdgpu_gart_size == -1) {
 573                 switch (adev->asic_type) {
 574                 case CHIP_POLARIS10: /* all engines support GPUVM */
 575                 case CHIP_POLARIS11: /* all engines support GPUVM */
 576                 case CHIP_POLARIS12: /* all engines support GPUVM */
 577                 case CHIP_VEGAM:     /* all engines support GPUVM */
 578                 default:
 579                         adev->gmc.gart_size = 256ULL << 20;
 580                         break;
 581                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 582                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 583                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 584                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 585                         adev->gmc.gart_size = 1024ULL << 20;
 586                         break;
 587                 }
 588         } else {
 589                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 590         }
 591
 592         gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
 593
 594         return 0;
 595 }
 596
 597 /*
 598  * GART
 599  * VMID 0 is the physical GPU addresses as used by the kernel.
 600  * VMIDs 1-15 are used for userspace clients and are handled
 601  * by the amdgpu vm/hsa code.
 602  */
 603
 604 /**
 605  * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
 606  *
 607  * @adev: amdgpu_device pointer
 608  * @vmid: vm instance to flush
 609  *
 610  * Flush the TLB for the requested page table (CIK).
 611  */
 612 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
 613                                         uint32_t vmid)
 614 {
 615         /* bits 0-15 are the VM contexts0-15 */
 616         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 617 }
 618
 619 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 620                                             unsigned vmid, uint64_t pd_addr)
 621 {
 622         uint32_t reg;
 623
 624         if (vmid < 8)
 625                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 626         else
 627                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 628         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 629
 630         /* bits 0-15 are the VM contexts0-15 */
 631         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 632
 633         return pd_addr;
 634 }
 635
 636 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 637                                         unsigned pasid)
 638 {
 639         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 640 }
 641
 642 /**
 643  * gmc_v8_0_set_pte_pde - update the page tables using MMIO
 644  *
 645  * @adev: amdgpu_device pointer
 646  * @cpu_pt_addr: cpu address of the page table
 647  * @gpu_page_idx: entry in the page table to update
 648  * @addr: dst addr to write into pte/pde
 649  * @flags: access flags
 650  *
 651  * Update the page tables using the CPU.
 652  */
 653 static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
 654                                 uint32_t gpu_page_idx, uint64_t addr,
 655                                 uint64_t flags)
 656 {
 657         void __iomem *ptr = (void *)cpu_pt_addr;
 658         uint64_t value;
 659
 660         /*
 661          * PTE format on VI:
 662          * 63:40 reserved
 663          * 39:12 4k physical page base address
 664          * 11:7 fragment
 665          * 6 write
 666          * 5 read
 667          * 4 exe
 668          * 3 reserved
 669          * 2 snooped
 670          * 1 system
 671          * 0 valid
 672          *
 673          * PDE format on VI:
 674          * 63:59 block fragment size
 675          * 58:40 reserved
 676          * 39:1 physical base address of PTE
 677          * bits 5:1 must be 0.
 678          * 0 valid
 679          */
 680         value = addr & 0x000000FFFFFFF000ULL;
 681         value |= flags;
 682         writeq(value, ptr + (gpu_page_idx * 8));
 683
 684         return 0;
 685 }
 686
 687 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 688                                           uint32_t flags)
 689 {
 690         uint64_t pte_flag = 0;
 691
 692         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 693                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 694         if (flags & AMDGPU_VM_PAGE_READABLE)
 695                 pte_flag |= AMDGPU_PTE_READABLE;
 696         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 697                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 698         if (flags & AMDGPU_VM_PAGE_PRT)
 699                 pte_flag |= AMDGPU_PTE_PRT;
 700
 701         return pte_flag;
 702 }
 703
 704 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
 705                                 uint64_t *addr, uint64_t *flags)
 706 {
 707         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 708 }
 709
 710 /**
 711  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 712  *
 713  * @adev: amdgpu_device pointer
 714  * @value: true redirects VM faults to the default page
 715  */
 716 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 717                                               bool value)
 718 {
 719         u32 tmp;
 720
 721         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 722         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 723                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 724         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 725                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 726         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 727                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 728         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 729                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 730         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 731                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 732         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 733                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 734         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 735                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 736         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 737 }
 738
 739 /**
 740  * gmc_v8_0_set_prt - set PRT VM fault
 741  *
 742  * @adev: amdgpu_device pointer
 743  * @enable: enable/disable VM fault handling for PRT
 744 */
 745 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 746 {
 747         u32 tmp;
 748
 749         if (enable && !adev->gmc.prt_warning) {
 750                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 751                 adev->gmc.prt_warning = true;
 752         }
 753
 754         tmp = RREG32(mmVM_PRT_CNTL);
 755         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 756                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 757         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 758                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 759         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 760                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 761         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 762                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 763         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 764                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 765         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 766                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 767         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 768                             MASK_PDE0_FAULT, enable);
 769         WREG32(mmVM_PRT_CNTL, tmp);
 770
 771         if (enable) {
 772                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 773                 uint32_t high = adev->vm_manager.max_pfn -
 774                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 775
 776                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 777                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 778                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 779                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 780                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 781                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 782                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 783                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 784         } else {
 785                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 786                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 787                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 788                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 789                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 790                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 791                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 792                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 793         }
 794 }
 795
 796 /**
 797  * gmc_v8_0_gart_enable - gart enable
 798  *
 799  * @adev: amdgpu_device pointer
 800  *
 801  * This sets up the TLBs, programs the page tables for VMID0,
 802  * sets up the hw for VMIDs 1-15 which are allocated on
 803  * demand, and sets up the global locations for the LDS, GDS,
 804  * and GPUVM for FSA64 clients (CIK).
 805  * Returns 0 for success, errors for failure.
 806  */
 807 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 808 {
 809         int r, i;
 810         u32 tmp, field;
 811
 812         if (adev->gart.robj == NULL) {
 813                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 814                 return -EINVAL;
 815         }
 816         r = amdgpu_gart_table_vram_pin(adev);
 817         if (r)
 818                 return r;
 819         /* Setup TLB control */
 820         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 821         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 822         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 823         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 824         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 825         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 826         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 827         /* Setup L2 cache */
 828         tmp = RREG32(mmVM_L2_CNTL);
 829         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 830         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 831         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 832         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 833         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 834         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 835         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 836         WREG32(mmVM_L2_CNTL, tmp);
 837         tmp = RREG32(mmVM_L2_CNTL2);
 838         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 839         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 840         WREG32(mmVM_L2_CNTL2, tmp);
 841
 842         field = adev->vm_manager.fragment_size;
 843         tmp = RREG32(mmVM_L2_CNTL3);
 844         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 845         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 846         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 847         WREG32(mmVM_L2_CNTL3, tmp);
 848         /* XXX: set to enable PTE/PDE in system memory */
 849         tmp = RREG32(mmVM_L2_CNTL4);
 850         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 851         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 852         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 853         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 854         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 855         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 856         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 857         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 858         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 859         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 860         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 861         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 862         WREG32(mmVM_L2_CNTL4, tmp);
 863         /* setup context0 */
 864         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 865         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 866         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 867         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 868                         (u32)(adev->dummy_page_addr >> 12));
 869         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 870         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 871         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 872         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 873         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 874         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 875
 876         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 877         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 878         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 879
 880         /* empty context1-15 */
 881         /* FIXME start with 4G, once using 2 level pt switch to full
 882          * vm size space
 883          */
 884         /* set vm size, must be a multiple of 4 */
 885         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 886         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 887         for (i = 1; i < 16; i++) {
 888                 if (i < 8)
 889                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 890                                adev->gart.table_addr >> 12);
 891                 else
 892                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 893                                adev->gart.table_addr >> 12);
 894         }
 895
 896         /* enable context1-15 */
 897         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 898                (u32)(adev->dummy_page_addr >> 12));
 899         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 900         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 901         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 902         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 903         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 904         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 905         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 906         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 907         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 908         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 909         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 910         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 911                             adev->vm_manager.block_size - 9);
 912         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 913         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 914                 gmc_v8_0_set_fault_enable_default(adev, false);
 915         else
 916                 gmc_v8_0_set_fault_enable_default(adev, true);
 917
 918         gmc_v8_0_flush_gpu_tlb(adev, 0);
 919         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 920                  (unsigned)(adev->gmc.gart_size >> 20),
 921                  (unsigned long long)adev->gart.table_addr);
 922         adev->gart.ready = true;
 923         return 0;
 924 }
 925
 926 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 927 {
 928         int r;
 929
 930         if (adev->gart.robj) {
 931                 WARN(1, "R600 PCIE GART already initialized\n");
 932                 return 0;
 933         }
 934         /* Initialize common gart structure */
 935         r = amdgpu_gart_init(adev);
 936         if (r)
 937                 return r;
 938         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 939         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 940         return amdgpu_gart_table_vram_alloc(adev);
 941 }
 942
 943 /**
 944  * gmc_v8_0_gart_disable - gart disable
 945  *
 946  * @adev: amdgpu_device pointer
 947  *
 948  * This disables all VM page table (CIK).
 949  */
 950 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 951 {
 952         u32 tmp;
 953
 954         /* Disable all tables */
 955         WREG32(mmVM_CONTEXT0_CNTL, 0);
 956         WREG32(mmVM_CONTEXT1_CNTL, 0);
 957         /* Setup TLB control */
 958         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 959         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 960         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 961         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 962         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 963         /* Setup L2 cache */
 964         tmp = RREG32(mmVM_L2_CNTL);
 965         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 966         WREG32(mmVM_L2_CNTL, tmp);
 967         WREG32(mmVM_L2_CNTL2, 0);
 968         amdgpu_gart_table_vram_unpin(adev);
 969 }
 970
 971 /**
 972  * gmc_v8_0_gart_fini - vm fini callback
 973  *
 974  * @adev: amdgpu_device pointer
 975  *
 976  * Tears down the driver GART/VM setup (CIK).
 977  */
 978 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 979 {
 980         amdgpu_gart_table_vram_free(adev);
 981         amdgpu_gart_fini(adev);
 982 }
 983
 984 /**
 985  * gmc_v8_0_vm_decode_fault - print human readable fault info
 986  *
 987  * @adev: amdgpu_device pointer
 988  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 989  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 990  *
 991  * Print human readable fault information (CIK).
 992  */
 993 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
 994                                      u32 addr, u32 mc_client, unsigned pasid)
 995 {
 996         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 997         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 998                                         PROTECTIONS);
 999         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1000                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1001         u32 mc_id;
1002
1003         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1004                               MEMORY_CLIENT_ID);
1005
1006         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1007                protections, vmid, pasid, addr,
1008                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1009                              MEMORY_CLIENT_RW) ?
1010                "write" : "read", block, mc_client, mc_id);
1011 }
1012
1013 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1014 {
1015         switch (mc_seq_vram_type) {
1016         case MC_SEQ_MISC0__MT__GDDR1:
1017                 return AMDGPU_VRAM_TYPE_GDDR1;
1018         case MC_SEQ_MISC0__MT__DDR2:
1019                 return AMDGPU_VRAM_TYPE_DDR2;
1020         case MC_SEQ_MISC0__MT__GDDR3:
1021                 return AMDGPU_VRAM_TYPE_GDDR3;
1022         case MC_SEQ_MISC0__MT__GDDR4:
1023                 return AMDGPU_VRAM_TYPE_GDDR4;
1024         case MC_SEQ_MISC0__MT__GDDR5:
1025                 return AMDGPU_VRAM_TYPE_GDDR5;
1026         case MC_SEQ_MISC0__MT__HBM:
1027                 return AMDGPU_VRAM_TYPE_HBM;
1028         case MC_SEQ_MISC0__MT__DDR3:
1029                 return AMDGPU_VRAM_TYPE_DDR3;
1030         default:
1031                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1032         }
1033 }
1034
1035 static int gmc_v8_0_early_init(void *handle)
1036 {
1037         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1038
1039         gmc_v8_0_set_gmc_funcs(adev);
1040         gmc_v8_0_set_irq_funcs(adev);
1041
1042         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1043         adev->gmc.shared_aperture_end =
1044                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1045         adev->gmc.private_aperture_start =
1046                 adev->gmc.shared_aperture_end + 1;
1047         adev->gmc.private_aperture_end =
1048                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1049
1050         return 0;
1051 }
1052
1053 static int gmc_v8_0_late_init(void *handle)
1054 {
1055         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1056
1057         amdgpu_bo_late_init(adev);
1058
1059         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1060                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1061         else
1062                 return 0;
1063 }
1064
1065 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1066 {
1067         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1068         unsigned size;
1069
1070         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1071                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1072         } else {
1073                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1074                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1075                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1076                         4);
1077         }
1078         /* return 0 if the pre-OS buffer uses up most of vram */
1079         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1080                 return 0;
1081         return size;
1082 }
1083
1084 #define mmMC_SEQ_MISC0_FIJI 0xA71
1085
1086 static int gmc_v8_0_sw_init(void *handle)
1087 {
1088         int r;
1089         int dma_bits;
1090         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1091
1092         if (adev->flags & AMD_IS_APU) {
1093                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1094         } else {
1095                 u32 tmp;
1096
1097                 if ((adev->asic_type == CHIP_FIJI) ||
1098                     (adev->asic_type == CHIP_VEGAM))
1099                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1100                 else
1101                         tmp = RREG32(mmMC_SEQ_MISC0);
1102                 tmp &= MC_SEQ_MISC0__MT__MASK;
1103                 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1104         }
1105
1106         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1107         if (r)
1108                 return r;
1109
1110         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1111         if (r)
1112                 return r;
1113
1114         /* Adjust VM size here.
1115          * Currently set to 4GB ((1 << 20) 4k pages).
1116          * Max GPUVM size for cayman and SI is 40 bits.
1117          */
1118         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1119
1120         /* Set the internal MC address mask
1121          * This is the max address of the GPU's
1122          * internal address space.
1123          */
1124         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1125
1126         /* set DMA mask + need_dma32 flags.
1127          * PCIE - can handle 40-bits.
1128          * IGP - can handle 40-bits
1129          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1130          */
1131         adev->need_dma32 = false;
1132         dma_bits = adev->need_dma32 ? 32 : 40;
1133         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1134         if (r) {
1135                 adev->need_dma32 = true;
1136                 dma_bits = 32;
1137                 pr_warn("amdgpu: No suitable DMA available\n");
1138         }
1139         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1140         if (r) {
1141                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1142                 pr_warn("amdgpu: No coherent DMA available\n");
1143         }
1144         adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1145
1146         r = gmc_v8_0_init_microcode(adev);
1147         if (r) {
1148                 DRM_ERROR("Failed to load mc firmware!\n");
1149                 return r;
1150         }
1151
1152         r = gmc_v8_0_mc_init(adev);
1153         if (r)
1154                 return r;
1155
1156         adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
1157
1158         /* Memory manager */
1159         r = amdgpu_bo_init(adev);
1160         if (r)
1161                 return r;
1162
1163         r = gmc_v8_0_gart_init(adev);
1164         if (r)
1165                 return r;
1166
1167         /*
1168          * number of VMs
1169          * VMID 0 is reserved for System
1170          * amdgpu graphics/compute will use VMIDs 1-7
1171          * amdkfd will use VMIDs 8-15
1172          */
1173         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1174         amdgpu_vm_manager_init(adev);
1175
1176         /* base offset of vram pages */
1177         if (adev->flags & AMD_IS_APU) {
1178                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1179
1180                 tmp <<= 22;
1181                 adev->vm_manager.vram_base_offset = tmp;
1182         } else {
1183                 adev->vm_manager.vram_base_offset = 0;
1184         }
1185
1186         adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1187                                         GFP_KERNEL);
1188         if (!adev->gmc.vm_fault_info)
1189                 return -ENOMEM;
1190         atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1191
1192         return 0;
1193 }
1194
1195 static int gmc_v8_0_sw_fini(void *handle)
1196 {
1197         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1198
1199         amdgpu_gem_force_release(adev);
1200         amdgpu_vm_manager_fini(adev);
1201         kfree(adev->gmc.vm_fault_info);
1202         gmc_v8_0_gart_fini(adev);
1203         amdgpu_bo_fini(adev);
1204         release_firmware(adev->gmc.fw);
1205         adev->gmc.fw = NULL;
1206
1207         return 0;
1208 }
1209
1210 static int gmc_v8_0_hw_init(void *handle)
1211 {
1212         int r;
1213         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1214
1215         gmc_v8_0_init_golden_registers(adev);
1216
1217         gmc_v8_0_mc_program(adev);
1218
1219         if (adev->asic_type == CHIP_TONGA) {
1220                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1221                 if (r) {
1222                         DRM_ERROR("Failed to load MC firmware!\n");
1223                         return r;
1224                 }
1225         } else if (adev->asic_type == CHIP_POLARIS11 ||
1226                         adev->asic_type == CHIP_POLARIS10 ||
1227                         adev->asic_type == CHIP_POLARIS12) {
1228                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1229                 if (r) {
1230                         DRM_ERROR("Failed to load MC firmware!\n");
1231                         return r;
1232                 }
1233         }
1234
1235         r = gmc_v8_0_gart_enable(adev);
1236         if (r)
1237                 return r;
1238
1239         return r;
1240 }
1241
1242 static int gmc_v8_0_hw_fini(void *handle)
1243 {
1244         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1245
1246         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1247         gmc_v8_0_gart_disable(adev);
1248
1249         return 0;
1250 }
1251
1252 static int gmc_v8_0_suspend(void *handle)
1253 {
1254         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1255
1256         gmc_v8_0_hw_fini(adev);
1257
1258         return 0;
1259 }
1260
1261 static int gmc_v8_0_resume(void *handle)
1262 {
1263         int r;
1264         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265
1266         r = gmc_v8_0_hw_init(adev);
1267         if (r)
1268                 return r;
1269
1270         amdgpu_vmid_reset_all(adev);
1271
1272         return 0;
1273 }
1274
1275 static bool gmc_v8_0_is_idle(void *handle)
1276 {
1277         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278         u32 tmp = RREG32(mmSRBM_STATUS);
1279
1280         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1281                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1282                 return false;
1283
1284         return true;
1285 }
1286
1287 static int gmc_v8_0_wait_for_idle(void *handle)
1288 {
1289         unsigned i;
1290         u32 tmp;
1291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292
1293         for (i = 0; i < adev->usec_timeout; i++) {
1294                 /* read MC_STATUS */
1295                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1296                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1297                                                SRBM_STATUS__MCC_BUSY_MASK |
1298                                                SRBM_STATUS__MCD_BUSY_MASK |
1299                                                SRBM_STATUS__VMC_BUSY_MASK |
1300                                                SRBM_STATUS__VMC1_BUSY_MASK);
1301                 if (!tmp)
1302                         return 0;
1303                 udelay(1);
1304         }
1305         return -ETIMEDOUT;
1306
1307 }
1308
1309 static bool gmc_v8_0_check_soft_reset(void *handle)
1310 {
1311         u32 srbm_soft_reset = 0;
1312         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313         u32 tmp = RREG32(mmSRBM_STATUS);
1314
1315         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1316                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1317                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1318
1319         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1320                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1321                 if (!(adev->flags & AMD_IS_APU))
1322                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1323                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1324         }
1325         if (srbm_soft_reset) {
1326                 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1327                 return true;
1328         } else {
1329                 adev->gmc.srbm_soft_reset = 0;
1330                 return false;
1331         }
1332 }
1333
1334 static int gmc_v8_0_pre_soft_reset(void *handle)
1335 {
1336         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1337
1338         if (!adev->gmc.srbm_soft_reset)
1339                 return 0;
1340
1341         gmc_v8_0_mc_stop(adev);
1342         if (gmc_v8_0_wait_for_idle(adev)) {
1343                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1344         }
1345
1346         return 0;
1347 }
1348
1349 static int gmc_v8_0_soft_reset(void *handle)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352         u32 srbm_soft_reset;
1353
1354         if (!adev->gmc.srbm_soft_reset)
1355                 return 0;
1356         srbm_soft_reset = adev->gmc.srbm_soft_reset;
1357
1358         if (srbm_soft_reset) {
1359                 u32 tmp;
1360
1361                 tmp = RREG32(mmSRBM_SOFT_RESET);
1362                 tmp |= srbm_soft_reset;
1363                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1364                 WREG32(mmSRBM_SOFT_RESET, tmp);
1365                 tmp = RREG32(mmSRBM_SOFT_RESET);
1366
1367                 udelay(50);
1368
1369                 tmp &= ~srbm_soft_reset;
1370                 WREG32(mmSRBM_SOFT_RESET, tmp);
1371                 tmp = RREG32(mmSRBM_SOFT_RESET);
1372
1373                 /* Wait a little for things to settle down */
1374                 udelay(50);
1375         }
1376
1377         return 0;
1378 }
1379
1380 static int gmc_v8_0_post_soft_reset(void *handle)
1381 {
1382         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1383
1384         if (!adev->gmc.srbm_soft_reset)
1385                 return 0;
1386
1387         gmc_v8_0_mc_resume(adev);
1388         return 0;
1389 }
1390
1391 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1392                                              struct amdgpu_irq_src *src,
1393                                              unsigned type,
1394                                              enum amdgpu_interrupt_state state)
1395 {
1396         u32 tmp;
1397         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1398                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1399                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1400                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1401                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1402                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1403                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1404
1405         switch (state) {
1406         case AMDGPU_IRQ_STATE_DISABLE:
1407                 /* system context */
1408                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1409                 tmp &= ~bits;
1410                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1411                 /* VMs */
1412                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1413                 tmp &= ~bits;
1414                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1415                 break;
1416         case AMDGPU_IRQ_STATE_ENABLE:
1417                 /* system context */
1418                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1419                 tmp |= bits;
1420                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1421                 /* VMs */
1422                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1423                 tmp |= bits;
1424                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1425                 break;
1426         default:
1427                 break;
1428         }
1429
1430         return 0;
1431 }
1432
1433 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1434                                       struct amdgpu_irq_src *source,
1435                                       struct amdgpu_iv_entry *entry)
1436 {
1437         u32 addr, status, mc_client, vmid;
1438
1439         if (amdgpu_sriov_vf(adev)) {
1440                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1441                         entry->src_id, entry->src_data[0]);
1442                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1443                 return 0;
1444         }
1445
1446         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1447         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1448         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1449         /* reset addr and status */
1450         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1451
1452         if (!addr && !status)
1453                 return 0;
1454
1455         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1456                 gmc_v8_0_set_fault_enable_default(adev, false);
1457
1458         if (printk_ratelimit()) {
1459                 struct amdgpu_task_info task_info = { 0 };
1460
1461                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1462
1463                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1464                         entry->src_id, entry->src_data[0], task_info.process_name,
1465                         task_info.tgid, task_info.task_name, task_info.pid);
1466                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1467                         addr);
1468                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1469                         status);
1470                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1471                                          entry->pasid);
1472         }
1473
1474         vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1475                              VMID);
1476         if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1477                 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1478                 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1479                 u32 protections = REG_GET_FIELD(status,
1480                                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1481                                         PROTECTIONS);
1482
1483                 info->vmid = vmid;
1484                 info->mc_id = REG_GET_FIELD(status,
1485                                             VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1486                                             MEMORY_CLIENT_ID);
1487                 info->status = status;
1488                 info->page_addr = addr;
1489                 info->prot_valid = protections & 0x7 ? true : false;
1490                 info->prot_read = protections & 0x8 ? true : false;
1491                 info->prot_write = protections & 0x10 ? true : false;
1492                 info->prot_exec = protections & 0x20 ? true : false;
1493                 mb();
1494                 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1495         }
1496
1497         return 0;
1498 }
1499
1500 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1501                                                      bool enable)
1502 {
1503         uint32_t data;
1504
1505         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1506                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1507                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1508                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1509
1510                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1511                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1512                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1513
1514                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1515                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1516                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1517
1518                 data = RREG32(mmMC_XPB_CLK_GAT);
1519                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1520                 WREG32(mmMC_XPB_CLK_GAT, data);
1521
1522                 data = RREG32(mmATC_MISC_CG);
1523                 data |= ATC_MISC_CG__ENABLE_MASK;
1524                 WREG32(mmATC_MISC_CG, data);
1525
1526                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1527                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1528                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1529
1530                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1531                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1532                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1533
1534                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1535                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1536                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1537
1538                 data = RREG32(mmVM_L2_CG);
1539                 data |= VM_L2_CG__ENABLE_MASK;
1540                 WREG32(mmVM_L2_CG, data);
1541         } else {
1542                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1543                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1544                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1545
1546                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1547                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1548                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1549
1550                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1551                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1552                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1553
1554                 data = RREG32(mmMC_XPB_CLK_GAT);
1555                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1556                 WREG32(mmMC_XPB_CLK_GAT, data);
1557
1558                 data = RREG32(mmATC_MISC_CG);
1559                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1560                 WREG32(mmATC_MISC_CG, data);
1561
1562                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1563                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1564                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1565
1566                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1567                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1568                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1569
1570                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1571                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1572                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1573
1574                 data = RREG32(mmVM_L2_CG);
1575                 data &= ~VM_L2_CG__ENABLE_MASK;
1576                 WREG32(mmVM_L2_CG, data);
1577         }
1578 }
1579
1580 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1581                                        bool enable)
1582 {
1583         uint32_t data;
1584
1585         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1586                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1587                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1588                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1589
1590                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1591                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1592                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1593
1594                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1595                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1596                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1597
1598                 data = RREG32(mmMC_XPB_CLK_GAT);
1599                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1600                 WREG32(mmMC_XPB_CLK_GAT, data);
1601
1602                 data = RREG32(mmATC_MISC_CG);
1603                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1604                 WREG32(mmATC_MISC_CG, data);
1605
1606                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1607                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1608                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1609
1610                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1611                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1612                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1613
1614                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1615                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1616                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1617
1618                 data = RREG32(mmVM_L2_CG);
1619                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1620                 WREG32(mmVM_L2_CG, data);
1621         } else {
1622                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1623                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1624                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1625
1626                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1627                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1628                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1629
1630                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1631                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1632                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1633
1634                 data = RREG32(mmMC_XPB_CLK_GAT);
1635                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1636                 WREG32(mmMC_XPB_CLK_GAT, data);
1637
1638                 data = RREG32(mmATC_MISC_CG);
1639                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1640                 WREG32(mmATC_MISC_CG, data);
1641
1642                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1643                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1644                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1645
1646                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1647                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1648                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1649
1650                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1651                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1652                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1653
1654                 data = RREG32(mmVM_L2_CG);
1655                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1656                 WREG32(mmVM_L2_CG, data);
1657         }
1658 }
1659
1660 static int gmc_v8_0_set_clockgating_state(void *handle,
1661                                           enum amd_clockgating_state state)
1662 {
1663         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1664
1665         if (amdgpu_sriov_vf(adev))
1666                 return 0;
1667
1668         switch (adev->asic_type) {
1669         case CHIP_FIJI:
1670                 fiji_update_mc_medium_grain_clock_gating(adev,
1671                                 state == AMD_CG_STATE_GATE);
1672                 fiji_update_mc_light_sleep(adev,
1673                                 state == AMD_CG_STATE_GATE);
1674                 break;
1675         default:
1676                 break;
1677         }
1678         return 0;
1679 }
1680
1681 static int gmc_v8_0_set_powergating_state(void *handle,
1682                                           enum amd_powergating_state state)
1683 {
1684         return 0;
1685 }
1686
1687 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1688 {
1689         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1690         int data;
1691
1692         if (amdgpu_sriov_vf(adev))
1693                 *flags = 0;
1694
1695         /* AMD_CG_SUPPORT_MC_MGCG */
1696         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1697         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1698                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1699
1700         /* AMD_CG_SUPPORT_MC_LS */
1701         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1702                 *flags |= AMD_CG_SUPPORT_MC_LS;
1703 }
1704
1705 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1706         .name = "gmc_v8_0",
1707         .early_init = gmc_v8_0_early_init,
1708         .late_init = gmc_v8_0_late_init,
1709         .sw_init = gmc_v8_0_sw_init,
1710         .sw_fini = gmc_v8_0_sw_fini,
1711         .hw_init = gmc_v8_0_hw_init,
1712         .hw_fini = gmc_v8_0_hw_fini,
1713         .suspend = gmc_v8_0_suspend,
1714         .resume = gmc_v8_0_resume,
1715         .is_idle = gmc_v8_0_is_idle,
1716         .wait_for_idle = gmc_v8_0_wait_for_idle,
1717         .check_soft_reset = gmc_v8_0_check_soft_reset,
1718         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1719         .soft_reset = gmc_v8_0_soft_reset,
1720         .post_soft_reset = gmc_v8_0_post_soft_reset,
1721         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1722         .set_powergating_state = gmc_v8_0_set_powergating_state,
1723         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1724 };
1725
1726 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1727         .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1728         .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1729         .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1730         .set_pte_pde = gmc_v8_0_set_pte_pde,
1731         .set_prt = gmc_v8_0_set_prt,
1732         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1733         .get_vm_pde = gmc_v8_0_get_vm_pde
1734 };
1735
1736 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1737         .set = gmc_v8_0_vm_fault_interrupt_state,
1738         .process = gmc_v8_0_process_interrupt,
1739 };
1740
1741 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1742 {
1743         if (adev->gmc.gmc_funcs == NULL)
1744                 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1745 }
1746
1747 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1748 {
1749         adev->gmc.vm_fault.num_types = 1;
1750         adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1751 }
1752
1753 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1754 {
1755         .type = AMD_IP_BLOCK_TYPE_GMC,
1756         .major = 8,
1757         .minor = 0,
1758         .rev = 0,
1759         .funcs = &gmc_v8_0_ip_funcs,
1760 };
1761
1762 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1763 {
1764         .type = AMD_IP_BLOCK_TYPE_GMC,
1765         .major = 8,
1766         .minor = 1,
1767         .rev = 0,
1768         .funcs = &gmc_v8_0_ip_funcs,
1769 };
1770
1771 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1772 {
1773         .type = AMD_IP_BLOCK_TYPE_GMC,
1774         .major = 8,
1775         .minor = 5,
1776         .rev = 0,
1777         .funcs = &gmc_v8_0_ip_funcs,
1778 };