drivers/gpu/drm/bridge/ite-it6505.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5 #include <linux/bits.h>
   6 #include <linux/debugfs.h>
   7 #include <linux/delay.h>
   8 #include <linux/device.h>
   9 #include <linux/err.h>
  10 #include <linux/extcon.h>
  11 #include <linux/fs.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/i2c.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/types.h>
  21 #include <linux/wait.h>
  22
  23 #include <crypto/hash.h>
  24
  25 #include <drm/display/drm_dp_helper.h>
  26 #include <drm/display/drm_hdcp_helper.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_bridge.h>
  29 #include <drm/drm_crtc.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_print.h>
  32 #include <drm/drm_probe_helper.h>
  33
  34 #include <sound/hdmi-codec.h>
  35
  36 #define REG_IC_VER 0x04
  37
  38 #define REG_RESET_CTRL 0x05
  39 #define VIDEO_RESET BIT(0)
  40 #define AUDIO_RESET BIT(1)
  41 #define ALL_LOGIC_RESET BIT(2)
  42 #define AUX_RESET BIT(3)
  43 #define HDCP_RESET BIT(4)
  44
  45 #define INT_STATUS_01 0x06
  46 #define INT_MASK_01 0x09
  47 #define INT_HPD_CHANGE 0
  48 #define INT_RECEIVE_HPD_IRQ 1
  49 #define INT_SCDT_CHANGE 2
  50 #define INT_HDCP_FAIL 3
  51 #define INT_HDCP_DONE 4
  52 #define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
  53 #define BIT_INT_HPD INT_HPD_CHANGE
  54 #define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
  55 #define BIT_INT_SCDT INT_SCDT_CHANGE
  56 #define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
  57 #define BIT_INT_HDCP_DONE INT_HDCP_DONE
  58
  59 #define INT_STATUS_02 0x07
  60 #define INT_MASK_02 0x0A
  61 #define INT_AUX_CMD_FAIL 0
  62 #define INT_HDCP_KSV_CHECK 1
  63 #define INT_AUDIO_FIFO_ERROR 2
  64 #define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
  65 #define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
  66 #define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
  67
  68 #define INT_STATUS_03 0x08
  69 #define INT_MASK_03 0x0B
  70 #define INT_LINK_TRAIN_FAIL 4
  71 #define INT_VID_FIFO_ERROR 5
  72 #define INT_IO_LATCH_FIFO_OVERFLOW 7
  73 #define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
  74 #define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
  75 #define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
  76
  77 #define REG_SYSTEM_STS 0x0D
  78 #define INT_STS BIT(0)
  79 #define HPD_STS BIT(1)
  80 #define VIDEO_STB BIT(2)
  81
  82 #define REG_LINK_TRAIN_STS 0x0E
  83 #define LINK_STATE_CR BIT(2)
  84 #define LINK_STATE_EQ BIT(3)
  85 #define LINK_STATE_NORP BIT(4)
  86
  87 #define REG_BANK_SEL 0x0F
  88 #define REG_CLK_CTRL0 0x10
  89 #define M_PCLK_DELAY 0x03
  90
  91 #define REG_AUX_OPT 0x11
  92 #define AUX_AUTO_RST BIT(0)
  93 #define AUX_FIX_FREQ BIT(3)
  94
  95 #define REG_DATA_CTRL0 0x12
  96 #define VIDEO_LATCH_EDGE BIT(4)
  97 #define ENABLE_PCLK_COUNTER BIT(7)
  98
  99 #define REG_PCLK_COUNTER_VALUE 0x13
 100
 101 #define REG_501_FIFO_CTRL 0x15
 102 #define RST_501_FIFO BIT(1)
 103
 104 #define REG_TRAIN_CTRL0 0x16
 105 #define FORCE_LBR BIT(0)
 106 #define LANE_COUNT_MASK 0x06
 107 #define LANE_SWAP BIT(3)
 108 #define SPREAD_AMP_5 BIT(4)
 109 #define FORCE_CR_DONE BIT(5)
 110 #define FORCE_EQ_DONE BIT(6)
 111
 112 #define REG_TRAIN_CTRL1 0x17
 113 #define AUTO_TRAIN BIT(0)
 114 #define MANUAL_TRAIN BIT(1)
 115 #define FORCE_RETRAIN BIT(2)
 116
 117 #define REG_AUX_CTRL 0x23
 118 #define CLR_EDID_FIFO BIT(0)
 119 #define AUX_USER_MODE BIT(1)
 120 #define AUX_NO_SEGMENT_WR BIT(6)
 121 #define AUX_EN_FIFO_READ BIT(7)
 122
 123 #define REG_AUX_ADR_0_7 0x24
 124 #define REG_AUX_ADR_8_15 0x25
 125 #define REG_AUX_ADR_16_19 0x26
 126 #define REG_AUX_OUT_DATA0 0x27
 127
 128 #define REG_AUX_CMD_REQ 0x2B
 129 #define AUX_BUSY BIT(5)
 130
 131 #define REG_AUX_DATA_0_7 0x2C
 132 #define REG_AUX_DATA_8_15 0x2D
 133 #define REG_AUX_DATA_16_23 0x2E
 134 #define REG_AUX_DATA_24_31 0x2F
 135
 136 #define REG_AUX_DATA_FIFO 0x2F
 137
 138 #define REG_AUX_ERROR_STS 0x9F
 139 #define M_AUX_REQ_FAIL 0x03
 140
 141 #define REG_HDCP_CTRL1 0x38
 142 #define HDCP_CP_ENABLE BIT(0)
 143
 144 #define REG_HDCP_TRIGGER 0x39
 145 #define HDCP_TRIGGER_START  BIT(0)
 146 #define HDCP_TRIGGER_CPIRQ  BIT(1)
 147 #define HDCP_TRIGGER_KSV_DONE  BIT(4)
 148 #define HDCP_TRIGGER_KSV_FAIL BIT(5)
 149
 150 #define REG_HDCP_CTRL2 0x3A
 151 #define HDCP_AN_SEL BIT(0)
 152 #define HDCP_AN_GEN BIT(1)
 153 #define HDCP_HW_HPDIRQ_ACT BIT(2)
 154 #define HDCP_EN_M0_READ BIT(5)
 155
 156 #define REG_M0_0_7 0x4C
 157 #define REG_AN_0_7 0x4C
 158 #define REG_SP_CTRL0 0x58
 159 #define REG_IP_CTRL1 0x59
 160 #define REG_IP_CTRL2 0x5A
 161
 162 #define REG_LINK_DRV 0x5C
 163 #define DRV_HS BIT(1)
 164
 165 #define REG_DRV_LN_DATA_SEL 0x5D
 166
 167 #define REG_AUX 0x5E
 168
 169 #define REG_VID_BUS_CTRL0 0x60
 170 #define IN_DDR BIT(2)
 171 #define DDR_CD (0x01 << 6)
 172
 173 #define REG_VID_BUS_CTRL1 0x61
 174 #define TX_FIFO_RESET BIT(1)
 175
 176 #define REG_INPUT_CTRL 0xA0
 177 #define INPUT_HSYNC_POL BIT(0)
 178 #define INPUT_VSYNC_POL BIT(2)
 179 #define INPUT_INTERLACED BIT(4)
 180
 181 #define REG_INPUT_HTOTAL 0xA1
 182 #define REG_INPUT_HACTIVE_START 0xA3
 183 #define REG_INPUT_HACTIVE_WIDTH 0xA5
 184 #define REG_INPUT_HFRONT_PORCH 0xA7
 185 #define REG_INPUT_HSYNC_WIDTH 0xA9
 186 #define REG_INPUT_VTOTAL 0xAB
 187 #define REG_INPUT_VACTIVE_START 0xAD
 188 #define REG_INPUT_VACTIVE_WIDTH 0xAF
 189 #define REG_INPUT_VFRONT_PORCH 0xB1
 190 #define REG_INPUT_VSYNC_WIDTH 0xB3
 191
 192 #define REG_AUDIO_SRC_CTRL 0xB8
 193 #define M_AUDIO_I2S_EN 0x0F
 194 #define EN_I2S0 BIT(0)
 195 #define EN_I2S1 BIT(1)
 196 #define EN_I2S2 BIT(2)
 197 #define EN_I2S3 BIT(3)
 198 #define AUDIO_FIFO_RESET BIT(7)
 199
 200 #define REG_AUDIO_FMT 0xB9
 201 #define REG_AUDIO_FIFO_SEL 0xBA
 202
 203 #define REG_AUDIO_CTRL0 0xBB
 204 #define AUDIO_FULL_PKT BIT(4)
 205 #define AUDIO_16B_BOUND BIT(5)
 206
 207 #define REG_AUDIO_CTRL1 0xBC
 208 #define REG_AUDIO_INPUT_FREQ 0xBE
 209
 210 #define REG_IEC958_STS0 0xBF
 211 #define REG_IEC958_STS1 0xC0
 212 #define REG_IEC958_STS2 0xC1
 213 #define REG_IEC958_STS3 0xC2
 214 #define REG_IEC958_STS4 0xC3
 215
 216 #define REG_HPD_IRQ_TIME 0xC9
 217 #define REG_AUX_DEBUG_MODE 0xCA
 218 #define REG_AUX_OPT2 0xCB
 219 #define REG_HDCP_OPT 0xCE
 220 #define REG_USER_DRV_PRE 0xCF
 221
 222 #define REG_DATA_MUTE_CTRL 0xD3
 223 #define ENABLE_ENHANCED_FRAME BIT(0)
 224 #define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
 225 #define EN_VID_MUTE BIT(4)
 226 #define EN_AUD_MUTE BIT(5)
 227
 228 #define REG_TIME_STMP_CTRL 0xD4
 229 #define EN_ENHANCE_VID_STMP BIT(0)
 230 #define EN_ENHANCE_AUD_STMP BIT(2)
 231 #define M_STAMP_STEP 0x30
 232 #define EN_SSC_GAT BIT(6)
 233
 234 #define REG_INFOFRAME_CTRL 0xE8
 235 #define EN_AVI_PKT BIT(0)
 236 #define EN_AUD_PKT BIT(1)
 237 #define EN_MPG_PKT BIT(2)
 238 #define EN_GEN_PKT BIT(3)
 239 #define EN_VID_TIME_STMP BIT(4)
 240 #define EN_AUD_TIME_STMP BIT(5)
 241 #define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
 242 #define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
 243
 244 #define REG_AUDIO_N_0_7 0xDE
 245 #define REG_AUDIO_N_8_15 0xDF
 246 #define REG_AUDIO_N_16_23 0xE0
 247
 248 #define REG_AVI_INFO_DB1 0xE9
 249 #define REG_AVI_INFO_DB2 0xEA
 250 #define REG_AVI_INFO_DB3 0xEB
 251 #define REG_AVI_INFO_DB4 0xEC
 252 #define REG_AVI_INFO_DB5 0xED
 253 #define REG_AVI_INFO_SUM 0xF6
 254
 255 #define REG_AUD_INFOFRAM_DB1 0xF7
 256 #define REG_AUD_INFOFRAM_DB2 0xF8
 257 #define REG_AUD_INFOFRAM_DB3 0xF9
 258 #define REG_AUD_INFOFRAM_DB4 0xFA
 259 #define REG_AUD_INFOFRAM_SUM 0xFB
 260
 261 /* the following six registers are in bank1 */
 262 #define REG_DRV_0_DB_800_MV 0x17E
 263 #define REG_PRE_0_DB_800_MV 0x17F
 264 #define REG_PRE_3P5_DB_800_MV 0x181
 265 #define REG_SSC_CTRL0 0x188
 266 #define REG_SSC_CTRL1 0x189
 267 #define REG_SSC_CTRL2 0x18A
 268
 269 #define RBR DP_LINK_BW_1_62
 270 #define HBR DP_LINK_BW_2_7
 271 #define HBR2 DP_LINK_BW_5_4
 272 #define HBR3 DP_LINK_BW_8_1
 273
 274 #define DPCD_V_1_1 0x11
 275 #define MISC_VERB 0xF0
 276 #define MISC_VERC 0x70
 277 #define I2S_INPUT_FORMAT_STANDARD 0
 278 #define I2S_INPUT_FORMAT_32BIT 1
 279 #define I2S_INPUT_LEFT_JUSTIFIED 0
 280 #define I2S_INPUT_RIGHT_JUSTIFIED 1
 281 #define I2S_DATA_1T_DELAY 0
 282 #define I2S_DATA_NO_DELAY 1
 283 #define I2S_WS_LEFT_CHANNEL 0
 284 #define I2S_WS_RIGHT_CHANNEL 1
 285 #define I2S_DATA_MSB_FIRST 0
 286 #define I2S_DATA_LSB_FIRST 1
 287 #define WORD_LENGTH_16BIT 0
 288 #define WORD_LENGTH_18BIT 1
 289 #define WORD_LENGTH_20BIT 2
 290 #define WORD_LENGTH_24BIT 3
 291 #define DEBUGFS_DIR_NAME "it6505-debugfs"
 292 #define READ_BUFFER_SIZE 400
 293
 294 /* Vendor option */
 295 #define HDCP_DESIRED 1
 296 #define MAX_LANE_COUNT 4
 297 #define MAX_LINK_RATE HBR
 298 #define AUTO_TRAIN_RETRY 3
 299 #define MAX_HDCP_DOWN_STREAM_COUNT 10
 300 #define MAX_CR_LEVEL 0x03
 301 #define MAX_EQ_LEVEL 0x03
 302 #define AUX_WAIT_TIMEOUT_MS 15
 303 #define AUX_FIFO_MAX_SIZE 32
 304 #define PIXEL_CLK_DELAY 1
 305 #define PIXEL_CLK_INVERSE 0
 306 #define ADJUST_PHASE_THRESHOLD 80000
 307 #define DPI_PIXEL_CLK_MAX 95000
 308 #define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
 309 #define DEFAULT_PWR_ON 0
 310 #define DEFAULT_DRV_HOLD 0
 311
 312 #define AUDIO_SELECT I2S
 313 #define AUDIO_TYPE LPCM
 314 #define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
 315 #define AUDIO_CHANNEL_COUNT 2
 316 #define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
 317 #define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
 318 #define I2S_DATA_DELAY I2S_DATA_1T_DELAY
 319 #define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
 320 #define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
 321 #define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
 322
 323 enum aux_cmd_type {
 324         CMD_AUX_NATIVE_READ = 0x0,
 325         CMD_AUX_NATIVE_WRITE = 0x5,
 326         CMD_AUX_I2C_EDID_READ = 0xB,
 327 };
 328
 329 enum aux_cmd_reply {
 330         REPLY_ACK,
 331         REPLY_NACK,
 332         REPLY_DEFER,
 333 };
 334
 335 enum link_train_status {
 336         LINK_IDLE,
 337         LINK_BUSY,
 338         LINK_OK,
 339 };
 340
 341 enum hdcp_state {
 342         HDCP_AUTH_IDLE,
 343         HDCP_AUTH_GOING,
 344         HDCP_AUTH_DONE,
 345 };
 346
 347 struct it6505_platform_data {
 348         struct regulator *pwr18;
 349         struct regulator *ovdd;
 350         struct gpio_desc *gpiod_reset;
 351 };
 352
 353 enum it6505_audio_select {
 354         I2S = 0,
 355         SPDIF,
 356 };
 357
 358 enum it6505_audio_sample_rate {
 359         SAMPLE_RATE_24K = 0x6,
 360         SAMPLE_RATE_32K = 0x3,
 361         SAMPLE_RATE_48K = 0x2,
 362         SAMPLE_RATE_96K = 0xA,
 363         SAMPLE_RATE_192K = 0xE,
 364         SAMPLE_RATE_44_1K = 0x0,
 365         SAMPLE_RATE_88_2K = 0x8,
 366         SAMPLE_RATE_176_4K = 0xC,
 367 };
 368
 369 enum it6505_audio_type {
 370         LPCM = 0,
 371         NLPCM,
 372         DSS,
 373 };
 374
 375 struct it6505_audio_data {
 376         enum it6505_audio_select select;
 377         enum it6505_audio_sample_rate sample_rate;
 378         enum it6505_audio_type type;
 379         u8 word_length;
 380         u8 channel_count;
 381         u8 i2s_input_format;
 382         u8 i2s_justified;
 383         u8 i2s_data_delay;
 384         u8 i2s_ws_channel;
 385         u8 i2s_data_sequence;
 386 };
 387
 388 struct it6505_audio_sample_rate_map {
 389         enum it6505_audio_sample_rate rate;
 390         int sample_rate_value;
 391 };
 392
 393 struct it6505_drm_dp_link {
 394         unsigned char revision;
 395         unsigned int rate;
 396         unsigned int num_lanes;
 397         unsigned long capabilities;
 398 };
 399
 400 struct debugfs_entries {
 401         char *name;
 402         const struct file_operations *fops;
 403 };
 404
 405 struct it6505 {
 406         struct drm_dp_aux aux;
 407         struct drm_bridge bridge;
 408         struct device *dev;
 409         struct it6505_drm_dp_link link;
 410         struct it6505_platform_data pdata;
 411         /*
 412          * Mutex protects extcon and interrupt functions from interfering
 413          * each other.
 414          */
 415         struct mutex extcon_lock;
 416         struct mutex mode_lock; /* used to bridge_detect */
 417         struct mutex aux_lock; /* used to aux data transfers */
 418         struct regmap *regmap;
 419         struct drm_display_mode source_output_mode;
 420         struct drm_display_mode video_info;
 421         struct notifier_block event_nb;
 422         struct extcon_dev *extcon;
 423         struct work_struct extcon_wq;
 424         int extcon_state;
 425         enum drm_connector_status connector_status;
 426         enum link_train_status link_state;
 427         struct work_struct link_works;
 428         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 429         u8 lane_count;
 430         u8 link_rate_bw_code;
 431         u8 sink_count;
 432         bool step_train;
 433         bool branch_device;
 434         bool enable_ssc;
 435         bool lane_swap_disabled;
 436         bool lane_swap;
 437         bool powered;
 438         bool hpd_state;
 439         u32 afe_setting;
 440         u32 max_dpi_pixel_clock;
 441         u32 max_lane_count;
 442         enum hdcp_state hdcp_status;
 443         struct delayed_work hdcp_work;
 444         struct work_struct hdcp_wait_ksv_list;
 445         struct completion extcon_completion;
 446         u8 auto_train_retry;
 447         bool hdcp_desired;
 448         bool is_repeater;
 449         u8 hdcp_down_stream_count;
 450         u8 bksvs[DRM_HDCP_KSV_LEN];
 451         u8 sha1_input[HDCP_SHA1_FIFO_LEN];
 452         bool enable_enhanced_frame;
 453         hdmi_codec_plugged_cb plugged_cb;
 454         struct device *codec_dev;
 455         struct delayed_work delayed_audio;
 456         struct it6505_audio_data audio;
 457         struct dentry *debugfs;
 458
 459         /* it6505 driver hold option */
 460         bool enable_drv_hold;
 461
 462         const struct drm_edid *cached_edid;
 463 };
 464
 465 struct it6505_step_train_para {
 466         u8 voltage_swing[MAX_LANE_COUNT];
 467         u8 pre_emphasis[MAX_LANE_COUNT];
 468 };
 469
 470 /*
 471  * Vendor option afe settings for different platforms
 472  * 0: without FPC cable
 473  * 1: with FPC cable
 474  */
 475
 476 static const u8 afe_setting_table[][3] = {
 477         {0x82, 0x00, 0x45},
 478         {0x93, 0x2A, 0x85}
 479 };
 480
 481 static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
 482         {SAMPLE_RATE_24K, 24000},
 483         {SAMPLE_RATE_32K, 32000},
 484         {SAMPLE_RATE_48K, 48000},
 485         {SAMPLE_RATE_96K, 96000},
 486         {SAMPLE_RATE_192K, 192000},
 487         {SAMPLE_RATE_44_1K, 44100},
 488         {SAMPLE_RATE_88_2K, 88200},
 489         {SAMPLE_RATE_176_4K, 176400},
 490 };
 491
 492 static const struct regmap_range it6505_bridge_volatile_ranges[] = {
 493         { .range_min = 0, .range_max = 0x1FF },
 494 };
 495
 496 static const struct regmap_access_table it6505_bridge_volatile_table = {
 497         .yes_ranges = it6505_bridge_volatile_ranges,
 498         .n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
 499 };
 500
 501 static const struct regmap_range_cfg it6505_regmap_banks[] = {
 502         {
 503                 .name = "it6505",
 504                 .range_min = 0x00,
 505                 .range_max = 0x1FF,
 506                 .selector_reg = REG_BANK_SEL,
 507                 .selector_mask = 0x1,
 508                 .selector_shift = 0,
 509                 .window_start = 0x00,
 510                 .window_len = 0x100,
 511         },
 512 };
 513
 514 static const struct regmap_config it6505_regmap_config = {
 515         .reg_bits = 8,
 516         .val_bits = 8,
 517         .volatile_table = &it6505_bridge_volatile_table,
 518         .cache_type = REGCACHE_NONE,
 519         .ranges = it6505_regmap_banks,
 520         .num_ranges = ARRAY_SIZE(it6505_regmap_banks),
 521         .max_register = 0x1FF,
 522 };
 523
 524 static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
 525 {
 526         unsigned int value;
 527         int err;
 528         struct device *dev = it6505->dev;
 529
 530         if (!it6505->powered)
 531                 return -ENODEV;
 532
 533         err = regmap_read(it6505->regmap, reg_addr, &value);
 534         if (err < 0) {
 535                 dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
 536                 return err;
 537         }
 538
 539         return value;
 540 }
 541
 542 static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
 543                         unsigned int reg_val)
 544 {
 545         int err;
 546         struct device *dev = it6505->dev;
 547
 548         if (!it6505->powered)
 549                 return -ENODEV;
 550
 551         err = regmap_write(it6505->regmap, reg_addr, reg_val);
 552
 553         if (err < 0) {
 554                 dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
 555                         reg_addr, reg_val, err);
 556                 return err;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
 563                            unsigned int mask, unsigned int value)
 564 {
 565         int err;
 566         struct device *dev = it6505->dev;
 567
 568         if (!it6505->powered)
 569                 return -ENODEV;
 570
 571         err = regmap_update_bits(it6505->regmap, reg, mask, value);
 572         if (err < 0) {
 573                 dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
 574                         reg, value, mask, err);
 575                 return err;
 576         }
 577
 578         return 0;
 579 }
 580
 581 static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
 582                                const char *prefix)
 583 {
 584         struct device *dev = it6505->dev;
 585         int val;
 586
 587         if (!drm_debug_enabled(DRM_UT_DRIVER))
 588                 return;
 589
 590         val = it6505_read(it6505, reg);
 591         if (val < 0)
 592                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
 593                                      prefix, reg, val);
 594         else
 595                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
 596                                      val);
 597 }
 598
 599 static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
 600 {
 601         u8 value;
 602         int ret;
 603         struct device *dev = it6505->dev;
 604
 605         ret = drm_dp_dpcd_readb(&it6505->aux, offset, &value);
 606         if (ret < 0) {
 607                 dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
 608                 return ret;
 609         }
 610         return value;
 611 }
 612
 613 static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
 614                              u8 datain)
 615 {
 616         int ret;
 617         struct device *dev = it6505->dev;
 618
 619         ret = drm_dp_dpcd_writeb(&it6505->aux, offset, datain);
 620         if (ret < 0) {
 621                 dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
 622                 return ret;
 623         }
 624         return 0;
 625 }
 626
 627 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
 628 {
 629         int ret;
 630         struct device *dev = it6505->dev;
 631
 632         ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);
 633
 634         if (ret < 0)
 635                 return ret;
 636
 637         DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
 638                              num, dpcd);
 639
 640         return 0;
 641 }
 642
 643 static void it6505_dump(struct it6505 *it6505)
 644 {
 645         unsigned int i, j;
 646         u8 regs[16];
 647         struct device *dev = it6505->dev;
 648
 649         for (i = 0; i <= 0xff; i += 16) {
 650                 for (j = 0; j < 16; j++)
 651                         regs[j] = it6505_read(it6505, i + j);
 652
 653                 DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
 654         }
 655 }
 656
 657 static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
 658 {
 659         int reg_0d;
 660
 661         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
 662
 663         if (reg_0d < 0)
 664                 return false;
 665
 666         return reg_0d & HPD_STS;
 667 }
 668
 669 static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
 670 {
 671         int val0, val1;
 672
 673         val0 = it6505_read(it6505, reg);
 674         if (val0 < 0)
 675                 return val0;
 676
 677         val1 = it6505_read(it6505, reg + 1);
 678         if (val1 < 0)
 679                 return val1;
 680
 681         return (val1 << 8) | val0;
 682 }
 683
 684 static void it6505_calc_video_info(struct it6505 *it6505)
 685 {
 686         struct device *dev = it6505->dev;
 687         int hsync_pol, vsync_pol, interlaced;
 688         int htotal, hdes, hdew, hfph, hsyncw;
 689         int vtotal, vdes, vdew, vfph, vsyncw;
 690         int rddata, i, pclk, sum = 0;
 691
 692         usleep_range(10000, 15000);
 693         rddata = it6505_read(it6505, REG_INPUT_CTRL);
 694         hsync_pol = rddata & INPUT_HSYNC_POL;
 695         vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
 696         interlaced = (rddata & INPUT_INTERLACED) >> 4;
 697
 698         htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
 699         hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
 700         hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
 701         hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
 702         hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
 703
 704         vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
 705         vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
 706         vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
 707         vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
 708         vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
 709
 710         DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
 711                              hsync_pol, vsync_pol, interlaced);
 712         DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
 713                              hdes, vdes);
 714
 715         for (i = 0; i < 3; i++) {
 716                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 717                                 ENABLE_PCLK_COUNTER);
 718                 usleep_range(10000, 15000);
 719                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 720                                 0x00);
 721                 rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
 722                          0xFFF;
 723
 724                 sum += rddata;
 725         }
 726
 727         if (sum == 0) {
 728                 DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
 729                 return;
 730         }
 731
 732         sum /= 3;
 733         pclk = 13500 * 2048 / sum;
 734         it6505->video_info.clock = pclk;
 735         it6505->video_info.hdisplay = hdew;
 736         it6505->video_info.hsync_start = hdew + hfph;
 737         it6505->video_info.hsync_end = hdew + hfph + hsyncw;
 738         it6505->video_info.htotal = htotal;
 739         it6505->video_info.vdisplay = vdew;
 740         it6505->video_info.vsync_start = vdew + vfph;
 741         it6505->video_info.vsync_end = vdew + vfph + vsyncw;
 742         it6505->video_info.vtotal = vtotal;
 743
 744         DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
 745                              DRM_MODE_ARG(&it6505->video_info));
 746 }
 747
 748 static int it6505_drm_dp_link_set_power(struct drm_dp_aux *aux,
 749                                         struct it6505_drm_dp_link *link,
 750                                         u8 mode)
 751 {
 752         u8 value;
 753         int err;
 754
 755         /* DP_SET_POWER register is only available on DPCD v1.1 and later */
 756         if (link->revision < DPCD_V_1_1)
 757                 return 0;
 758
 759         err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
 760         if (err < 0)
 761                 return err;
 762
 763         value &= ~DP_SET_POWER_MASK;
 764         value |= mode;
 765
 766         err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
 767         if (err < 0)
 768                 return err;
 769
 770         if (mode == DP_SET_POWER_D0) {
 771                 /*
 772                  * According to the DP 1.1 specification, a "Sink Device must
 773                  * exit the power saving state within 1 ms" (Section 2.5.3.1,
 774                  * Table 5-52, "Sink Control Field" (register 0x600).
 775                  */
 776                 usleep_range(1000, 2000);
 777         }
 778
 779         return 0;
 780 }
 781
 782 static void it6505_clear_int(struct it6505 *it6505)
 783 {
 784         it6505_write(it6505, INT_STATUS_01, 0xFF);
 785         it6505_write(it6505, INT_STATUS_02, 0xFF);
 786         it6505_write(it6505, INT_STATUS_03, 0xFF);
 787 }
 788
 789 static void it6505_int_mask_enable(struct it6505 *it6505)
 790 {
 791         it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
 792                      BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
 793                      BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
 794
 795         it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
 796                      BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
 797
 798         it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
 799                      BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
 800 }
 801
 802 static void it6505_int_mask_disable(struct it6505 *it6505)
 803 {
 804         it6505_write(it6505, INT_MASK_01, 0x00);
 805         it6505_write(it6505, INT_MASK_02, 0x00);
 806         it6505_write(it6505, INT_MASK_03, 0x00);
 807 }
 808
 809 static void it6505_lane_termination_on(struct it6505 *it6505)
 810 {
 811         int regcf;
 812
 813         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 814
 815         if (regcf == MISC_VERB)
 816                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x00);
 817
 818         if (regcf == MISC_VERC) {
 819                 if (it6505->lane_swap) {
 820                         switch (it6505->lane_count) {
 821                         case 1:
 822                         case 2:
 823                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 824                                                 0x0C, 0x08);
 825                                 break;
 826                         default:
 827                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 828                                                 0x0C, 0x0C);
 829                                 break;
 830                         }
 831                 } else {
 832                         switch (it6505->lane_count) {
 833                         case 1:
 834                         case 2:
 835                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 836                                                 0x0C, 0x04);
 837                                 break;
 838                         default:
 839                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 840                                                 0x0C, 0x0C);
 841                                 break;
 842                         }
 843                 }
 844         }
 845 }
 846
 847 static void it6505_lane_termination_off(struct it6505 *it6505)
 848 {
 849         int regcf;
 850
 851         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 852
 853         if (regcf == MISC_VERB)
 854                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 855
 856         if (regcf == MISC_VERC)
 857                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x0C, 0x00);
 858 }
 859
 860 static void it6505_lane_power_on(struct it6505 *it6505)
 861 {
 862         it6505_set_bits(it6505, REG_LINK_DRV, 0xF1,
 863                         (it6505->lane_swap ?
 864                                  GENMASK(7, 8 - it6505->lane_count) :
 865                                  GENMASK(3 + it6505->lane_count, 4)) |
 866                                 0x01);
 867 }
 868
 869 static void it6505_lane_power_off(struct it6505 *it6505)
 870 {
 871         it6505_set_bits(it6505, REG_LINK_DRV, 0xF0, 0x00);
 872 }
 873
 874 static void it6505_lane_off(struct it6505 *it6505)
 875 {
 876         it6505_lane_power_off(it6505);
 877         it6505_lane_termination_off(it6505);
 878 }
 879
 880 static void it6505_aux_termination_on(struct it6505 *it6505)
 881 {
 882         int regcf;
 883
 884         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 885
 886         if (regcf == MISC_VERB)
 887                 it6505_lane_termination_on(it6505);
 888
 889         if (regcf == MISC_VERC)
 890                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 891 }
 892
 893 static void it6505_aux_power_on(struct it6505 *it6505)
 894 {
 895         it6505_set_bits(it6505, REG_AUX, 0x02, 0x02);
 896 }
 897
 898 static void it6505_aux_on(struct it6505 *it6505)
 899 {
 900         it6505_aux_power_on(it6505);
 901         it6505_aux_termination_on(it6505);
 902 }
 903
 904 static void it6505_aux_reset(struct it6505 *it6505)
 905 {
 906         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
 907         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, 0x00);
 908 }
 909
 910 static void it6505_reset_logic(struct it6505 *it6505)
 911 {
 912         regmap_write(it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
 913         usleep_range(1000, 1500);
 914 }
 915
 916 static bool it6505_aux_op_finished(struct it6505 *it6505)
 917 {
 918         int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
 919
 920         if (reg2b < 0)
 921                 return false;
 922
 923         return (reg2b & AUX_BUSY) == 0;
 924 }
 925
 926 static int it6505_aux_wait(struct it6505 *it6505)
 927 {
 928         int status;
 929         unsigned long timeout;
 930         struct device *dev = it6505->dev;
 931
 932         timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
 933
 934         while (!it6505_aux_op_finished(it6505)) {
 935                 if (time_after(jiffies, timeout)) {
 936                         dev_err(dev, "Timed out waiting AUX to finish");
 937                         return -ETIMEDOUT;
 938                 }
 939                 usleep_range(1000, 2000);
 940         }
 941
 942         status = it6505_read(it6505, REG_AUX_ERROR_STS);
 943         if (status < 0) {
 944                 dev_err(dev, "Failed to read AUX channel: %d", status);
 945                 return status;
 946         }
 947
 948         return 0;
 949 }
 950
 951 static ssize_t it6505_aux_operation(struct it6505 *it6505,
 952                                     enum aux_cmd_type cmd,
 953                                     unsigned int address, u8 *buffer,
 954                                     size_t size, enum aux_cmd_reply *reply)
 955 {
 956         int i, ret;
 957         bool aux_write_check = false;
 958
 959         if (!it6505_get_sink_hpd_status(it6505))
 960                 return -EIO;
 961
 962         /* set AUX user mode */
 963         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
 964
 965 aux_op_start:
 966         if (cmd == CMD_AUX_I2C_EDID_READ) {
 967                 /* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
 968                 size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
 969                 /* Enable AUX FIFO read back and clear FIFO */
 970                 it6505_set_bits(it6505, REG_AUX_CTRL,
 971                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 972                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
 973
 974                 it6505_set_bits(it6505, REG_AUX_CTRL,
 975                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 976                                 AUX_EN_FIFO_READ);
 977         } else {
 978                 /* The DP AUX transmit buffer has 4 bytes. */
 979                 size = min_t(size_t, size, 4);
 980                 it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
 981                                 AUX_NO_SEGMENT_WR);
 982         }
 983
 984         /* Start Address[7:0] */
 985         it6505_write(it6505, REG_AUX_ADR_0_7, (address >> 0) & 0xFF);
 986         /* Start Address[15:8] */
 987         it6505_write(it6505, REG_AUX_ADR_8_15, (address >> 8) & 0xFF);
 988         /* WriteNum[3:0]+StartAdr[19:16] */
 989         it6505_write(it6505, REG_AUX_ADR_16_19,
 990                      ((address >> 16) & 0x0F) | ((size - 1) << 4));
 991
 992         if (cmd == CMD_AUX_NATIVE_WRITE)
 993                 regmap_bulk_write(it6505->regmap, REG_AUX_OUT_DATA0, buffer,
 994                                   size);
 995
 996         /* Aux Fire */
 997         it6505_write(it6505, REG_AUX_CMD_REQ, cmd);
 998
 999         ret = it6505_aux_wait(it6505);
1000         if (ret < 0)
1001                 goto aux_op_err;
1002
1003         ret = it6505_read(it6505, REG_AUX_ERROR_STS);
1004         if (ret < 0)
1005                 goto aux_op_err;
1006
1007         switch ((ret >> 6) & 0x3) {
1008         case 0:
1009                 *reply = REPLY_ACK;
1010                 break;
1011         case 1:
1012                 *reply = REPLY_DEFER;
1013                 ret = -EAGAIN;
1014                 goto aux_op_err;
1015         case 2:
1016                 *reply = REPLY_NACK;
1017                 ret = -EIO;
1018                 goto aux_op_err;
1019         case 3:
1020                 ret = -ETIMEDOUT;
1021                 goto aux_op_err;
1022         }
1023
1024         /* Read back Native Write data */
1025         if (cmd == CMD_AUX_NATIVE_WRITE) {
1026                 aux_write_check = true;
1027                 cmd = CMD_AUX_NATIVE_READ;
1028                 goto aux_op_start;
1029         }
1030
1031         if (cmd == CMD_AUX_I2C_EDID_READ) {
1032                 for (i = 0; i < size; i++) {
1033                         ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1034                         if (ret < 0)
1035                                 goto aux_op_err;
1036                         buffer[i] = ret;
1037                 }
1038         } else {
1039                 for (i = 0; i < size; i++) {
1040                         ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1041                         if (ret < 0)
1042                                 goto aux_op_err;
1043
1044                         if (aux_write_check && buffer[size - 1 - i] != ret) {
1045                                 ret = -EINVAL;
1046                                 goto aux_op_err;
1047                         }
1048
1049                         buffer[size - 1 - i] = ret;
1050                 }
1051         }
1052
1053         ret = i;
1054
1055 aux_op_err:
1056         if (cmd == CMD_AUX_I2C_EDID_READ) {
1057                 /* clear AUX FIFO */
1058                 it6505_set_bits(it6505, REG_AUX_CTRL,
1059                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1060                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1061                 it6505_set_bits(it6505, REG_AUX_CTRL,
1062                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO, 0x00);
1063         }
1064
1065         /* Leave AUX user mode */
1066         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, 0);
1067
1068         return ret;
1069 }
1070
1071 static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1072                                       enum aux_cmd_type cmd,
1073                                       unsigned int address, u8 *buffer,
1074                                       size_t size, enum aux_cmd_reply *reply)
1075 {
1076         int i, ret_size, ret = 0, request_size;
1077
1078         mutex_lock(&it6505->aux_lock);
1079         for (i = 0; i < size; i += 4) {
1080                 request_size = min((int)size - i, 4);
1081                 ret_size = it6505_aux_operation(it6505, cmd, address + i,
1082                                                 buffer + i, request_size,
1083                                                 reply);
1084                 if (ret_size < 0) {
1085                         ret = ret_size;
1086                         goto aux_op_err;
1087                 }
1088
1089                 ret += ret_size;
1090         }
1091
1092 aux_op_err:
1093         mutex_unlock(&it6505->aux_lock);
1094         return ret;
1095 }
1096
1097 static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1098                                    struct drm_dp_aux_msg *msg)
1099 {
1100         struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1101         u8 cmd;
1102         bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1103         int ret;
1104         enum aux_cmd_reply reply;
1105
1106         /* IT6505 doesn't support arbitrary I2C read / write. */
1107         if (is_i2c)
1108                 return -EINVAL;
1109
1110         switch (msg->request) {
1111         case DP_AUX_NATIVE_READ:
1112                 cmd = CMD_AUX_NATIVE_READ;
1113                 break;
1114         case DP_AUX_NATIVE_WRITE:
1115                 cmd = CMD_AUX_NATIVE_WRITE;
1116                 break;
1117         default:
1118                 return -EINVAL;
1119         }
1120
1121         ret = it6505_aux_do_transfer(it6505, cmd, msg->address, msg->buffer,
1122                                      msg->size, &reply);
1123         if (ret < 0)
1124                 return ret;
1125
1126         switch (reply) {
1127         case REPLY_ACK:
1128                 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1129                 break;
1130         case REPLY_NACK:
1131                 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1132                 break;
1133         case REPLY_DEFER:
1134                 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1135                 break;
1136         }
1137
1138         return ret;
1139 }
1140
1141 static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1142                                  size_t len)
1143 {
1144         struct it6505 *it6505 = data;
1145         struct device *dev = it6505->dev;
1146         enum aux_cmd_reply reply;
1147         int offset, ret, aux_retry = 100;
1148
1149         it6505_aux_reset(it6505);
1150         DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1151
1152         for (offset = 0; offset < EDID_LENGTH;) {
1153                 ret = it6505_aux_do_transfer(it6505, CMD_AUX_I2C_EDID_READ,
1154                                              block * EDID_LENGTH + offset,
1155                                              buf + offset, 8, &reply);
1156
1157                 if (ret < 0 && ret != -EAGAIN)
1158                         return ret;
1159
1160                 switch (reply) {
1161                 case REPLY_ACK:
1162                         DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1163                                              buf + offset);
1164                         offset += 8;
1165                         aux_retry = 100;
1166                         break;
1167                 case REPLY_NACK:
1168                         return -EIO;
1169                 case REPLY_DEFER:
1170                         msleep(20);
1171                         if (!(--aux_retry))
1172                                 return -EIO;
1173                 }
1174         }
1175
1176         return 0;
1177 }
1178
1179 static void it6505_variable_config(struct it6505 *it6505)
1180 {
1181         it6505->link_rate_bw_code = HBR;
1182         it6505->lane_count = MAX_LANE_COUNT;
1183         it6505->link_state = LINK_IDLE;
1184         it6505->hdcp_desired = HDCP_DESIRED;
1185         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1186         it6505->audio.select = AUDIO_SELECT;
1187         it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1188         it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1189         it6505->audio.type = AUDIO_TYPE;
1190         it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1191         it6505->audio.i2s_justified = I2S_JUSTIFIED;
1192         it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1193         it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1194         it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1195         it6505->audio.word_length = AUDIO_WORD_LENGTH;
1196         memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1197         memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1198 }
1199
1200 static int it6505_send_video_infoframe(struct it6505 *it6505,
1201                                        struct hdmi_avi_infoframe *frame)
1202 {
1203         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1204         int err;
1205         struct device *dev = it6505->dev;
1206
1207         err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
1208         if (err < 0) {
1209                 dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1210                 return err;
1211         }
1212
1213         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, 0x00);
1214         if (err)
1215                 return err;
1216
1217         err = regmap_bulk_write(it6505->regmap, REG_AVI_INFO_DB1,
1218                                 buffer + HDMI_INFOFRAME_HEADER_SIZE,
1219                                 frame->length);
1220         if (err)
1221                 return err;
1222
1223         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1224                               EN_AVI_PKT);
1225         if (err)
1226                 return err;
1227
1228         return 0;
1229 }
1230
1231 static void it6505_get_extcon_property(struct it6505 *it6505)
1232 {
1233         int err;
1234         union extcon_property_value property;
1235         struct device *dev = it6505->dev;
1236
1237         if (it6505->extcon && !it6505->lane_swap_disabled) {
1238                 err = extcon_get_property(it6505->extcon, EXTCON_DISP_DP,
1239                                           EXTCON_PROP_USB_TYPEC_POLARITY,
1240                                           &property);
1241                 if (err) {
1242                         dev_err(dev, "get property fail!");
1243                         return;
1244                 }
1245                 it6505->lane_swap = property.intval;
1246         }
1247 }
1248
1249 static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1250                                         const struct drm_display_mode *mode)
1251 {
1252         int clock = mode->clock;
1253
1254         it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1255                         clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1256         it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1257                         PIXEL_CLK_INVERSE << 4);
1258 }
1259
1260 static void it6505_link_reset_step_train(struct it6505 *it6505)
1261 {
1262         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1263                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1264         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1265                           DP_TRAINING_PATTERN_DISABLE);
1266 }
1267
1268 static void it6505_init(struct it6505 *it6505)
1269 {
1270         it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1271         it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1272         it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1273         it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1274         it6505_write(it6505, REG_VID_BUS_CTRL1, 0x01);
1275         it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1276
1277         /* chip internal setting, don't modify */
1278         it6505_write(it6505, REG_HPD_IRQ_TIME, 0xF5);
1279         it6505_write(it6505, REG_AUX_DEBUG_MODE, 0x4D);
1280         it6505_write(it6505, REG_AUX_OPT2, 0x17);
1281         it6505_write(it6505, REG_HDCP_OPT, 0x60);
1282         it6505_write(it6505, REG_DATA_MUTE_CTRL,
1283                      EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1284         it6505_write(it6505, REG_TIME_STMP_CTRL,
1285                      EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1286         it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00);
1287         it6505_write(it6505, REG_DRV_0_DB_800_MV,
1288                      afe_setting_table[it6505->afe_setting][0]);
1289         it6505_write(it6505, REG_PRE_0_DB_800_MV,
1290                      afe_setting_table[it6505->afe_setting][1]);
1291         it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1292                      afe_setting_table[it6505->afe_setting][2]);
1293         it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1294         it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1295         it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1296 }
1297
1298 static void it6505_video_disable(struct it6505 *it6505)
1299 {
1300         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1301         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1302         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1303 }
1304
1305 static void it6505_video_reset(struct it6505 *it6505)
1306 {
1307         it6505_link_reset_step_train(it6505);
1308         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1309         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1310         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1311         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1312         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);
1313         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);
1314 }
1315
1316 static void it6505_update_video_parameter(struct it6505 *it6505,
1317                                           const struct drm_display_mode *mode)
1318 {
1319         it6505_clk_phase_adjustment(it6505, mode);
1320         it6505_video_disable(it6505);
1321 }
1322
1323 static bool it6505_audio_input(struct it6505 *it6505)
1324 {
1325         int reg05, regbe;
1326
1327         reg05 = it6505_read(it6505, REG_RESET_CTRL);
1328         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1329         usleep_range(3000, 4000);
1330         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1331         it6505_write(it6505, REG_RESET_CTRL, reg05);
1332
1333         return regbe != 0xFF;
1334 }
1335
1336 static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1337 {
1338         enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1339         u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1340
1341         /* Channel Status */
1342         it6505_write(it6505, REG_IEC958_STS0, it6505->audio.type << 1);
1343         it6505_write(it6505, REG_IEC958_STS1, 0x00);
1344         it6505_write(it6505, REG_IEC958_STS2, 0x00);
1345         it6505_write(it6505, REG_IEC958_STS3, sample_rate);
1346         it6505_write(it6505, REG_IEC958_STS4, (~sample_rate << 4) |
1347                      audio_word_length_map[it6505->audio.word_length]);
1348 }
1349
1350 static void it6505_setup_audio_format(struct it6505 *it6505)
1351 {
1352         /* I2S MODE */
1353         it6505_write(it6505, REG_AUDIO_FMT,
1354                      (it6505->audio.word_length << 5) |
1355                      (it6505->audio.i2s_data_sequence << 4) |
1356                      (it6505->audio.i2s_ws_channel << 3) |
1357                      (it6505->audio.i2s_data_delay << 2) |
1358                      (it6505->audio.i2s_justified << 1) |
1359                      it6505->audio.i2s_input_format);
1360         if (it6505->audio.select == SPDIF) {
1361                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0x00);
1362                 /* 0x30 = 128*FS */
1363                 it6505_set_bits(it6505, REG_AUX_OPT, 0xF0, 0x30);
1364         } else {
1365                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0xE4);
1366         }
1367
1368         it6505_write(it6505, REG_AUDIO_CTRL0, 0x20);
1369         it6505_write(it6505, REG_AUDIO_CTRL1, 0x00);
1370 }
1371
1372 static void it6505_enable_audio_source(struct it6505 *it6505)
1373 {
1374         unsigned int audio_source_count;
1375
1376         audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1377                                  - 1;
1378
1379         audio_source_count |= it6505->audio.select << 4;
1380
1381         it6505_write(it6505, REG_AUDIO_SRC_CTRL, audio_source_count);
1382 }
1383
1384 static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1385 {
1386         struct device *dev = it6505->dev;
1387         u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1388
1389         DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1390                              audio_info_ca[it6505->audio.channel_count - 1]);
1391
1392         it6505_write(it6505, REG_AUD_INFOFRAM_DB1, it6505->audio.channel_count
1393                      - 1);
1394         it6505_write(it6505, REG_AUD_INFOFRAM_DB2, 0x00);
1395         it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1396                      audio_info_ca[it6505->audio.channel_count - 1]);
1397         it6505_write(it6505, REG_AUD_INFOFRAM_DB4, 0x00);
1398         it6505_write(it6505, REG_AUD_INFOFRAM_SUM, 0x00);
1399
1400         /* Enable Audio InfoFrame */
1401         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1402                         EN_AUD_CTRL_PKT);
1403 }
1404
1405 static void it6505_disable_audio(struct it6505 *it6505)
1406 {
1407         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1408         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, 0x00);
1409         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, 0x00);
1410         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1411 }
1412
1413 static void it6505_enable_audio(struct it6505 *it6505)
1414 {
1415         struct device *dev = it6505->dev;
1416         int regbe;
1417
1418         DRM_DEV_DEBUG_DRIVER(dev, "start");
1419         it6505_disable_audio(it6505);
1420
1421         it6505_setup_audio_channel_status(it6505);
1422         it6505_setup_audio_format(it6505);
1423         it6505_enable_audio_source(it6505);
1424         it6505_enable_audio_infoframe(it6505);
1425
1426         it6505_write(it6505, REG_AUDIO_N_0_7, 0x00);
1427         it6505_write(it6505, REG_AUDIO_N_8_15, 0x80);
1428         it6505_write(it6505, REG_AUDIO_N_16_23, 0x00);
1429
1430         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1431                         AUDIO_FIFO_RESET);
1432         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, 0x00);
1433         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1434         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1435         DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1436                              regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1437         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, 0x00);
1438 }
1439
1440 static bool it6505_use_step_train_check(struct it6505 *it6505)
1441 {
1442         if (it6505->link.revision >= 0x12)
1443                 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1444
1445         return true;
1446 }
1447
1448 static void it6505_parse_link_capabilities(struct it6505 *it6505)
1449 {
1450         struct device *dev = it6505->dev;
1451         struct it6505_drm_dp_link *link = &it6505->link;
1452         int bcaps;
1453
1454         if (it6505->dpcd[0] == 0) {
1455                 dev_err(dev, "DPCD is not initialized");
1456                 return;
1457         }
1458
1459         memset(link, 0, sizeof(*link));
1460
1461         link->revision = it6505->dpcd[0];
1462         link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]);
1463         link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;
1464
1465         if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)
1466                 link->capabilities = DP_ENHANCED_FRAME_CAP;
1467
1468         DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1469                              link->revision >> 4, link->revision & 0x0F);
1470
1471         DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1472                              link->rate / 100000, link->rate / 1000 % 100);
1473
1474         it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link->rate);
1475         DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1476                              it6505->link_rate_bw_code);
1477         it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1478                                           MAX_LINK_RATE);
1479
1480         it6505->lane_count = link->num_lanes;
1481         DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1482                              it6505->lane_count);
1483         it6505->lane_count = min_t(int, it6505->lane_count,
1484                                    it6505->max_lane_count);
1485
1486         it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
1487         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1488                              it6505->branch_device ? "" : "Not ");
1489
1490         it6505->enable_enhanced_frame = link->capabilities;
1491         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1492                              it6505->enable_enhanced_frame ? "" : "Not ");
1493
1494         it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1495                                 DP_MAX_DOWNSPREAD_0_5);
1496         DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1497                              it6505->enable_ssc ? "0.5" : "0",
1498                              it6505->enable_ssc ? "" : "Not ");
1499
1500         it6505->step_train = it6505_use_step_train_check(it6505);
1501         if (it6505->step_train)
1502                 DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1503
1504         bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1505         DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1506         if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1507                 it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1508                 DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1509                                      it6505->is_repeater ? "repeater" :
1510                                      "receiver");
1511         } else {
1512                 DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1513                 it6505->hdcp_desired = false;
1514         }
1515         DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1516                              it6505->hdcp_desired ? "desired" : "undesired");
1517 }
1518
1519 static void it6505_setup_ssc(struct it6505 *it6505)
1520 {
1521         it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1522                         it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1523         if (it6505->enable_ssc) {
1524                 it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1525                 it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1526                 it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1527                 it6505_write(it6505, REG_SP_CTRL0, 0x07);
1528                 it6505_write(it6505, REG_IP_CTRL1, 0x29);
1529                 it6505_write(it6505, REG_IP_CTRL2, 0x03);
1530                 /* Stamp Interrupt Step */
1531                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1532                                 0x10);
1533                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1534                                   DP_SPREAD_AMP_0_5);
1535         } else {
1536                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, 0x00);
1537                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1538                                 0x00);
1539         }
1540 }
1541
1542 static inline void it6505_link_rate_setup(struct it6505 *it6505)
1543 {
1544         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1545                         (it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1546         it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1547                         (it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1548 }
1549
1550 static void it6505_lane_count_setup(struct it6505 *it6505)
1551 {
1552         it6505_get_extcon_property(it6505);
1553         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1554                         it6505->lane_swap ? LANE_SWAP : 0x00);
1555         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1556                         (it6505->lane_count - 1) << 1);
1557 }
1558
1559 static void it6505_link_training_setup(struct it6505 *it6505)
1560 {
1561         struct device *dev = it6505->dev;
1562
1563         if (it6505->enable_enhanced_frame)
1564                 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1565                                 ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1566
1567         it6505_link_rate_setup(it6505);
1568         it6505_lane_count_setup(it6505);
1569         it6505_setup_ssc(it6505);
1570         DRM_DEV_DEBUG_DRIVER(dev,
1571                              "%s, %d lanes, %sable ssc, %sable enhanced frame",
1572                              it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1573                              it6505->lane_count,
1574                              it6505->enable_ssc ? "en" : "dis",
1575                              it6505->enable_enhanced_frame ? "en" : "dis");
1576 }
1577
1578 static bool it6505_link_start_auto_train(struct it6505 *it6505)
1579 {
1580         int timeout = 500, link_training_state;
1581         bool state = false;
1582
1583         mutex_lock(&it6505->aux_lock);
1584         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1585                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1586         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1587         it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1588
1589         while (timeout > 0) {
1590                 usleep_range(1000, 2000);
1591                 link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1592
1593                 if (link_training_state > 0 &&
1594                     (link_training_state & LINK_STATE_NORP)) {
1595                         state = true;
1596                         goto unlock;
1597                 }
1598
1599                 timeout--;
1600         }
1601 unlock:
1602         mutex_unlock(&it6505->aux_lock);
1603
1604         return state;
1605 }
1606
1607 static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1608 {
1609         u8 values[2];
1610         int err;
1611         struct drm_dp_aux *aux = &it6505->aux;
1612
1613         values[0] = it6505->link_rate_bw_code;
1614         values[1] = it6505->lane_count;
1615
1616         if (it6505->enable_enhanced_frame)
1617                 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1618
1619         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
1620         if (err < 0)
1621                 return err;
1622
1623         return 0;
1624 }
1625
1626 static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1627 {
1628         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1629 }
1630
1631 static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1632 {
1633         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1634 }
1635
1636 static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1637                                                    u8 lane_count)
1638 {
1639         u8 i;
1640
1641         for (i = 0; i < lane_count; i++) {
1642                 if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1643                         return true;
1644         }
1645
1646         return false;
1647 }
1648
1649 static bool
1650 step_train_lane_voltage_para_set(struct it6505 *it6505,
1651                                  struct it6505_step_train_para
1652                                  *lane_voltage_pre_emphasis,
1653                                  u8 *lane_voltage_pre_emphasis_set)
1654 {
1655         u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1656         u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1657         u8 i;
1658
1659         for (i = 0; i < it6505->lane_count; i++) {
1660                 voltage_swing[i] &= 0x03;
1661                 lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1662                 if (it6505_check_voltage_swing_max(voltage_swing[i]))
1663                         lane_voltage_pre_emphasis_set[i] |=
1664                                 DP_TRAIN_MAX_SWING_REACHED;
1665
1666                 pre_emphasis[i] &= 0x03;
1667                 lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1668                         << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1669                 if (it6505_check_pre_emphasis_max(pre_emphasis[i]))
1670                         lane_voltage_pre_emphasis_set[i] |=
1671                                 DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1672                 it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1673                                   lane_voltage_pre_emphasis_set[i]);
1674
1675                 if (lane_voltage_pre_emphasis_set[i] !=
1676                     it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1677                         return false;
1678         }
1679
1680         return true;
1681 }
1682
1683 static bool
1684 it6505_step_cr_train(struct it6505 *it6505,
1685                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1686 {
1687         u8 loop_count = 0, i = 0, j;
1688         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1689         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1690         int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1691         const struct drm_dp_aux *aux = &it6505->aux;
1692
1693         it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1694                           it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1695         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1696                           DP_TRAINING_PATTERN_1);
1697
1698         while (loop_count < 5 && i < 10) {
1699                 i++;
1700                 if (!step_train_lane_voltage_para_set(it6505,
1701                                                       lane_voltage_pre_emphasis,
1702                                                       lane_level_config))
1703                         continue;
1704                 drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);
1705                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1706
1707                 if (drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) {
1708                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1709                                         FORCE_CR_DONE);
1710                         return true;
1711                 }
1712                 DRM_DEV_DEBUG_DRIVER(it6505->dev, "cr not done");
1713
1714                 if (it6505_check_max_voltage_swing_reached(lane_level_config,
1715                                                            it6505->lane_count))
1716                         goto cr_train_fail;
1717
1718                 for (j = 0; j < it6505->lane_count; j++) {
1719                         lane_voltage_pre_emphasis->voltage_swing[j] =
1720                                 drm_dp_get_adjust_request_voltage(link_status,
1721                                                                   j) >>
1722                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1723                         lane_voltage_pre_emphasis->pre_emphasis[j] =
1724                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1725                                                                j) >>
1726                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1727                         if (voltage_swing_adjust ==
1728                              lane_voltage_pre_emphasis->voltage_swing[j] &&
1729                             pre_emphasis_adjust ==
1730                              lane_voltage_pre_emphasis->pre_emphasis[j]) {
1731                                 loop_count++;
1732                                 continue;
1733                         }
1734
1735                         voltage_swing_adjust =
1736                                 lane_voltage_pre_emphasis->voltage_swing[j];
1737                         pre_emphasis_adjust =
1738                                 lane_voltage_pre_emphasis->pre_emphasis[j];
1739                         loop_count = 0;
1740
1741                         if (voltage_swing_adjust + pre_emphasis_adjust >
1742                             MAX_EQ_LEVEL)
1743                                 lane_voltage_pre_emphasis->voltage_swing[j] =
1744                                         MAX_EQ_LEVEL -
1745                                         lane_voltage_pre_emphasis
1746                                                 ->pre_emphasis[j];
1747                 }
1748         }
1749
1750 cr_train_fail:
1751         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1752                           DP_TRAINING_PATTERN_DISABLE);
1753
1754         return false;
1755 }
1756
1757 static bool
1758 it6505_step_eq_train(struct it6505 *it6505,
1759                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1760 {
1761         u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1762         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1763         const struct drm_dp_aux *aux = &it6505->aux;
1764
1765         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1766                           DP_TRAINING_PATTERN_2);
1767
1768         while (loop_count < 6) {
1769                 loop_count++;
1770
1771                 if (!step_train_lane_voltage_para_set(it6505,
1772                                                       lane_voltage_pre_emphasis,
1773                                                       lane_level_config))
1774                         continue;
1775
1776                 drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);
1777                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1778
1779                 if (!drm_dp_clock_recovery_ok(link_status, it6505->lane_count))
1780                         goto eq_train_fail;
1781
1782                 if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
1783                         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1784                                           DP_TRAINING_PATTERN_DISABLE);
1785                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1786                                         FORCE_EQ_DONE);
1787                         return true;
1788                 }
1789                 DRM_DEV_DEBUG_DRIVER(it6505->dev, "eq not done");
1790
1791                 for (i = 0; i < it6505->lane_count; i++) {
1792                         lane_voltage_pre_emphasis->voltage_swing[i] =
1793                                 drm_dp_get_adjust_request_voltage(link_status,
1794                                                                   i) >>
1795                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1796                         lane_voltage_pre_emphasis->pre_emphasis[i] =
1797                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1798                                                                i) >>
1799                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1800
1801                         if (lane_voltage_pre_emphasis->voltage_swing[i] +
1802                                     lane_voltage_pre_emphasis->pre_emphasis[i] >
1803                             MAX_EQ_LEVEL)
1804                                 lane_voltage_pre_emphasis->voltage_swing[i] =
1805                                         0x03 - lane_voltage_pre_emphasis
1806                                                        ->pre_emphasis[i];
1807                 }
1808         }
1809
1810 eq_train_fail:
1811         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1812                           DP_TRAINING_PATTERN_DISABLE);
1813         return false;
1814 }
1815
1816 static bool it6505_link_start_step_train(struct it6505 *it6505)
1817 {
1818         int err;
1819         struct it6505_step_train_para lane_voltage_pre_emphasis = {
1820                 .voltage_swing = { 0 },
1821                 .pre_emphasis = { 0 },
1822         };
1823
1824         DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
1825         err = it6505_drm_dp_link_configure(it6505);
1826
1827         if (err < 0)
1828                 return false;
1829         if (!it6505_step_cr_train(it6505, &lane_voltage_pre_emphasis))
1830                 return false;
1831         if (!it6505_step_eq_train(it6505, &lane_voltage_pre_emphasis))
1832                 return false;
1833         return true;
1834 }
1835
1836 static bool it6505_get_video_status(struct it6505 *it6505)
1837 {
1838         int reg_0d;
1839
1840         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
1841
1842         if (reg_0d < 0)
1843                 return false;
1844
1845         return reg_0d & VIDEO_STB;
1846 }
1847
1848 static void it6505_reset_hdcp(struct it6505 *it6505)
1849 {
1850         it6505->hdcp_status = HDCP_AUTH_IDLE;
1851         /* Disable CP_Desired */
1852         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1853         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
1854 }
1855
1856 static void it6505_start_hdcp(struct it6505 *it6505)
1857 {
1858         struct device *dev = it6505->dev;
1859
1860         DRM_DEV_DEBUG_DRIVER(dev, "start");
1861         it6505_reset_hdcp(it6505);
1862         queue_delayed_work(system_wq, &it6505->hdcp_work,
1863                            msecs_to_jiffies(2400));
1864 }
1865
1866 static void it6505_stop_hdcp(struct it6505 *it6505)
1867 {
1868         it6505_reset_hdcp(it6505);
1869         cancel_delayed_work(&it6505->hdcp_work);
1870 }
1871
1872 static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
1873 {
1874         int i, ones = 0;
1875
1876         /* KSV has 20 1's and 20 0's */
1877         for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
1878                 ones += hweight8(ksv[i]);
1879         if (ones != 20)
1880                 return false;
1881         return true;
1882 }
1883
1884 static void it6505_hdcp_part1_auth(struct it6505 *it6505)
1885 {
1886         struct device *dev = it6505->dev;
1887         u8 hdcp_bcaps;
1888
1889         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, 0x00);
1890         /* Disable CP_Desired */
1891         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1892
1893         usleep_range(1000, 1500);
1894         hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1895         DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
1896                              hdcp_bcaps);
1897
1898         if (!hdcp_bcaps)
1899                 return;
1900
1901         /* clear the repeater List Chk Done and fail bit */
1902         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
1903                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
1904                         0x00);
1905
1906         /* Enable An Generator */
1907         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
1908         /* delay1ms(10);*/
1909         usleep_range(10000, 15000);
1910         /* Stop An Generator */
1911         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, 0x00);
1912
1913         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
1914
1915         it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
1916                         HDCP_TRIGGER_START);
1917
1918         it6505->hdcp_status = HDCP_AUTH_GOING;
1919 }
1920
1921 static int it6505_sha1_digest(struct it6505 *it6505, u8 *sha1_input,
1922                               unsigned int size, u8 *output_av)
1923 {
1924         struct shash_desc *desc;
1925         struct crypto_shash *tfm;
1926         int err;
1927         struct device *dev = it6505->dev;
1928
1929         tfm = crypto_alloc_shash("sha1", 0, 0);
1930         if (IS_ERR(tfm)) {
1931                 dev_err(dev, "crypto_alloc_shash sha1 failed");
1932                 return PTR_ERR(tfm);
1933         }
1934         desc = kzalloc(sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
1935         if (!desc) {
1936                 crypto_free_shash(tfm);
1937                 return -ENOMEM;
1938         }
1939
1940         desc->tfm = tfm;
1941         err = crypto_shash_digest(desc, sha1_input, size, output_av);
1942         if (err)
1943                 dev_err(dev, "crypto_shash_digest sha1 failed");
1944
1945         crypto_free_shash(tfm);
1946         kfree(desc);
1947         return err;
1948 }
1949
1950 static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
1951 {
1952         struct device *dev = it6505->dev;
1953         u8 binfo[2];
1954         int down_stream_count, i, err, msg_count = 0;
1955
1956         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, binfo,
1957                               ARRAY_SIZE(binfo));
1958
1959         if (err < 0) {
1960                 dev_err(dev, "Read binfo value Fail");
1961                 return err;
1962         }
1963
1964         down_stream_count = binfo[0] & 0x7F;
1965         DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
1966                              binfo);
1967
1968         if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
1969                 dev_err(dev, "HDCP max cascade device exceed");
1970                 return 0;
1971         }
1972
1973         if (!down_stream_count ||
1974             down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
1975                 dev_err(dev, "HDCP down stream count Error %d",
1976                         down_stream_count);
1977                 return 0;
1978         }
1979
1980         for (i = 0; i < down_stream_count; i++) {
1981                 err = it6505_get_dpcd(it6505, DP_AUX_HDCP_KSV_FIFO +
1982                                       (i % 3) * DRM_HDCP_KSV_LEN,
1983                                       sha1_input + msg_count,
1984                                       DRM_HDCP_KSV_LEN);
1985
1986                 if (err < 0)
1987                         return err;
1988
1989                 msg_count += 5;
1990         }
1991
1992         it6505->hdcp_down_stream_count = down_stream_count;
1993         sha1_input[msg_count++] = binfo[0];
1994         sha1_input[msg_count++] = binfo[1];
1995
1996         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
1997                         HDCP_EN_M0_READ);
1998
1999         err = regmap_bulk_read(it6505->regmap, REG_M0_0_7,
2000                                sha1_input + msg_count, 8);
2001
2002         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, 0x00);
2003
2004         if (err < 0) {
2005                 dev_err(dev, " Warning, Read M value Fail");
2006                 return err;
2007         }
2008
2009         msg_count += 8;
2010
2011         return msg_count;
2012 }
2013
2014 static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
2015 {
2016         struct device *dev = it6505->dev;
2017         u8 av[5][4], bv[5][4];
2018         int i, err;
2019
2020         i = it6505_setup_sha1_input(it6505, it6505->sha1_input);
2021         if (i <= 0) {
2022                 dev_err(dev, "SHA-1 Input length error %d", i);
2023                 return false;
2024         }
2025
2026         it6505_sha1_digest(it6505, it6505->sha1_input, i, (u8 *)av);
2027
2028         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), (u8 *)bv,
2029                               sizeof(bv));
2030
2031         if (err < 0) {
2032                 dev_err(dev, "Read V' value Fail");
2033                 return false;
2034         }
2035
2036         for (i = 0; i < 5; i++)
2037                 if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2038                     bv[i][1] != av[i][2] || bv[i][0] != av[i][3])
2039                         return false;
2040
2041         DRM_DEV_DEBUG_DRIVER(dev, "V' all match!!");
2042         return true;
2043 }
2044
2045 static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2046 {
2047         struct it6505 *it6505 = container_of(work, struct it6505,
2048                                              hdcp_wait_ksv_list);
2049         struct device *dev = it6505->dev;
2050         unsigned int timeout = 5000;
2051         u8 bstatus = 0;
2052         bool ksv_list_check;
2053
2054         timeout /= 20;
2055         while (timeout > 0) {
2056                 if (!it6505_get_sink_hpd_status(it6505))
2057                         return;
2058
2059                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2060
2061                 if (bstatus & DP_BSTATUS_READY)
2062                         break;
2063
2064                 msleep(20);
2065                 timeout--;
2066         }
2067
2068         if (timeout == 0) {
2069                 DRM_DEV_DEBUG_DRIVER(dev, "timeout and ksv list wait failed");
2070                 goto timeout;
2071         }
2072
2073         ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2074         DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2075                              ksv_list_check ? "pass" : "fail");
2076         if (ksv_list_check) {
2077                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2078                                 HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2079                 return;
2080         }
2081 timeout:
2082         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2083                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
2084                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL);
2085 }
2086
2087 static void it6505_hdcp_work(struct work_struct *work)
2088 {
2089         struct it6505 *it6505 = container_of(work, struct it6505,
2090                                              hdcp_work.work);
2091         struct device *dev = it6505->dev;
2092         int ret;
2093         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2094
2095         DRM_DEV_DEBUG_DRIVER(dev, "start");
2096
2097         if (!it6505_get_sink_hpd_status(it6505))
2098                 return;
2099
2100         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2101         DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2102                              (int)sizeof(link_status), link_status);
2103
2104         if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
2105             !it6505_get_video_status(it6505)) {
2106                 DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2107                 return;
2108         }
2109
2110         ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, it6505->bksvs,
2111                               ARRAY_SIZE(it6505->bksvs));
2112         if (ret < 0) {
2113                 dev_err(dev, "fail to get bksv  ret: %d", ret);
2114                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2115                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2116         }
2117
2118         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2119                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2120
2121         if (!it6505_hdcp_is_ksv_valid(it6505->bksvs)) {
2122                 dev_err(dev, "Display Port bksv not valid");
2123                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2124                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2125         }
2126
2127         it6505_hdcp_part1_auth(it6505);
2128 }
2129
2130 static void it6505_show_hdcp_info(struct it6505 *it6505)
2131 {
2132         struct device *dev = it6505->dev;
2133         int i;
2134         u8 *sha1 = it6505->sha1_input;
2135
2136         DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2137                              it6505->hdcp_status, it6505->is_repeater);
2138         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2139                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2140
2141         if (it6505->is_repeater) {
2142                 DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2143                                      it6505->hdcp_down_stream_count);
2144                 DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2145                                      (int)ARRAY_SIZE(it6505->sha1_input),
2146                                      it6505->sha1_input);
2147                 for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2148                         DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2149                                              DRM_HDCP_KSV_LEN, sha1);
2150                         sha1 += DRM_HDCP_KSV_LEN;
2151                 }
2152                 DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2153                                      sha1, sha1 + 2);
2154         }
2155 }
2156
2157 static void it6505_stop_link_train(struct it6505 *it6505)
2158 {
2159         it6505->link_state = LINK_IDLE;
2160         cancel_work_sync(&it6505->link_works);
2161         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2162 }
2163
2164 static void it6505_link_train_ok(struct it6505 *it6505)
2165 {
2166         struct device *dev = it6505->dev;
2167
2168         it6505->link_state = LINK_OK;
2169         /* disalbe mute enable avi info frame */
2170         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, 0x00);
2171         it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2172                         EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2173
2174         if (it6505_audio_input(it6505)) {
2175                 DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2176                 it6505_enable_audio(it6505);
2177         }
2178
2179         if (it6505->hdcp_desired)
2180                 it6505_start_hdcp(it6505);
2181 }
2182
2183 static void it6505_link_step_train_process(struct it6505 *it6505)
2184 {
2185         struct device *dev = it6505->dev;
2186         int ret, i, step_retry = 3;
2187
2188         DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2189
2190         if (it6505->sink_count == 0) {
2191                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2192                                      it6505->sink_count);
2193                 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2194                                 FORCE_EQ_DONE);
2195                 return;
2196         }
2197
2198         if (!it6505->step_train) {
2199                 DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2200                 return;
2201         }
2202
2203         /* step training start here */
2204         for (i = 0; i < step_retry; i++) {
2205                 it6505_link_reset_step_train(it6505);
2206                 ret = it6505_link_start_step_train(it6505);
2207                 DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2208                                      ret ? "pass" : "failed", i + 1);
2209                 if (ret) {
2210                         it6505_link_train_ok(it6505);
2211                         return;
2212                 }
2213         }
2214
2215         DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2216         it6505->link_state = LINK_IDLE;
2217         it6505_video_reset(it6505);
2218 }
2219
2220 static void it6505_link_training_work(struct work_struct *work)
2221 {
2222         struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2223         struct device *dev = it6505->dev;
2224         int ret;
2225
2226         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2227                              it6505->sink_count);
2228
2229         if (!it6505_get_sink_hpd_status(it6505))
2230                 return;
2231
2232         it6505_link_training_setup(it6505);
2233         it6505_reset_hdcp(it6505);
2234         it6505_aux_reset(it6505);
2235
2236         if (it6505->auto_train_retry < 1) {
2237                 it6505_link_step_train_process(it6505);
2238                 return;
2239         }
2240
2241         ret = it6505_link_start_auto_train(it6505);
2242         DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2243                              ret ? "pass" : "failed", it6505->auto_train_retry);
2244
2245         if (ret) {
2246                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2247                 it6505_link_train_ok(it6505);
2248                 return;
2249         } else {
2250                 it6505->auto_train_retry--;
2251         }
2252
2253         it6505_dump(it6505);
2254 }
2255
2256 static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2257 {
2258         enum drm_connector_status status = it6505->connector_status;
2259
2260         if (it6505->plugged_cb && it6505->codec_dev)
2261                 it6505->plugged_cb(it6505->codec_dev,
2262                                    status == connector_status_connected);
2263 }
2264
2265 static void it6505_remove_edid(struct it6505 *it6505)
2266 {
2267         drm_edid_free(it6505->cached_edid);
2268         it6505->cached_edid = NULL;
2269 }
2270
2271 static int it6505_process_hpd_irq(struct it6505 *it6505)
2272 {
2273         struct device *dev = it6505->dev;
2274         int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2275         u8 link_status[DP_LINK_STATUS_SIZE];
2276
2277         if (!it6505_get_sink_hpd_status(it6505)) {
2278                 DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2279                 it6505->sink_count = 0;
2280                 return 0;
2281         }
2282
2283         ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2284         if (ret < 0)
2285                 return ret;
2286
2287         dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2288         DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2289                              dpcd_sink_count, it6505->sink_count);
2290
2291         if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2292                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2293                 it6505->sink_count = dpcd_sink_count;
2294                 it6505_reset_logic(it6505);
2295                 it6505_int_mask_enable(it6505);
2296                 it6505_init(it6505);
2297                 it6505_remove_edid(it6505);
2298                 return 0;
2299         }
2300
2301         dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2302         if (dp_irq_vector < 0)
2303                 return dp_irq_vector;
2304
2305         DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2306
2307         if (dp_irq_vector & DP_CP_IRQ) {
2308                 it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2309                                 HDCP_TRIGGER_CPIRQ);
2310
2311                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2312                 if (bstatus < 0)
2313                         return bstatus;
2314
2315                 DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2316         }
2317
2318         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2319         if (ret < 0) {
2320                 dev_err(dev, "Fail to read link status ret: %d", ret);
2321                 return ret;
2322         }
2323
2324         DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2325                              (int)ARRAY_SIZE(link_status), link_status);
2326
2327         if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
2328                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2329                 it6505_video_reset(it6505);
2330         }
2331
2332         return 0;
2333 }
2334
2335 static void it6505_irq_hpd(struct it6505 *it6505)
2336 {
2337         struct device *dev = it6505->dev;
2338         int dp_sink_count;
2339
2340         it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2341         DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2342                              it6505->hpd_state ? "high" : "low");
2343
2344         if (it6505->hpd_state) {
2345                 wait_for_completion_timeout(&it6505->extcon_completion,
2346                                             msecs_to_jiffies(1000));
2347                 it6505_aux_on(it6505);
2348                 if (it6505->dpcd[0] == 0) {
2349                         it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
2350                                         ARRAY_SIZE(it6505->dpcd));
2351                         it6505_variable_config(it6505);
2352                         it6505_parse_link_capabilities(it6505);
2353                 }
2354                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2355
2356                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2357                                              DP_SET_POWER_D0);
2358                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2359                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2360
2361                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2362                                      it6505->sink_count);
2363
2364                 it6505_lane_termination_on(it6505);
2365                 it6505_lane_power_on(it6505);
2366
2367                 /*
2368                  * for some dongle which issue HPD_irq
2369                  * when sink count change from  0->1
2370                  * it6505 not able to receive HPD_IRQ
2371                  * if HW never go into trainig done
2372                  */
2373
2374                 if (it6505->branch_device && it6505->sink_count == 0)
2375                         schedule_work(&it6505->link_works);
2376
2377                 if (!it6505_get_video_status(it6505))
2378                         it6505_video_reset(it6505);
2379         } else {
2380                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2381                 it6505_remove_edid(it6505);
2382
2383                 if (it6505->hdcp_desired)
2384                         it6505_stop_hdcp(it6505);
2385
2386                 it6505_video_disable(it6505);
2387                 it6505_disable_audio(it6505);
2388                 it6505_stop_link_train(it6505);
2389                 it6505_lane_off(it6505);
2390                 it6505_link_reset_step_train(it6505);
2391         }
2392
2393         if (it6505->bridge.dev)
2394                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2395 }
2396
2397 static void it6505_irq_hpd_irq(struct it6505 *it6505)
2398 {
2399         struct device *dev = it6505->dev;
2400
2401         DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2402
2403         if (it6505_process_hpd_irq(it6505) < 0)
2404                 DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2405 }
2406
2407 static void it6505_irq_scdt(struct it6505 *it6505)
2408 {
2409         struct device *dev = it6505->dev;
2410         bool data;
2411
2412         data = it6505_get_video_status(it6505);
2413         DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2414                              data ? "stable" : "unstable");
2415         it6505_calc_video_info(it6505);
2416         it6505_link_reset_step_train(it6505);
2417
2418         if (data)
2419                 schedule_work(&it6505->link_works);
2420 }
2421
2422 static void it6505_irq_hdcp_done(struct it6505 *it6505)
2423 {
2424         struct device *dev = it6505->dev;
2425
2426         DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2427         it6505->hdcp_status = HDCP_AUTH_DONE;
2428         it6505_show_hdcp_info(it6505);
2429 }
2430
2431 static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2432 {
2433         struct device *dev = it6505->dev;
2434
2435         DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2436         it6505->hdcp_status = HDCP_AUTH_IDLE;
2437         it6505_show_hdcp_info(it6505);
2438         it6505_start_hdcp(it6505);
2439 }
2440
2441 static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2442 {
2443         struct device *dev = it6505->dev;
2444
2445         DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2446 }
2447
2448 static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2449 {
2450         struct device *dev = it6505->dev;
2451
2452         DRM_DEV_DEBUG_DRIVER(dev, "HDCP event Interrupt");
2453         schedule_work(&it6505->hdcp_wait_ksv_list);
2454 }
2455
2456 static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2457 {
2458         struct device *dev = it6505->dev;
2459
2460         DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2461
2462         if (it6505_audio_input(it6505))
2463                 it6505_enable_audio(it6505);
2464 }
2465
2466 static void it6505_irq_link_train_fail(struct it6505 *it6505)
2467 {
2468         struct device *dev = it6505->dev;
2469
2470         DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2471         schedule_work(&it6505->link_works);
2472 }
2473
2474 static void it6505_irq_video_fifo_error(struct it6505 *it6505)
2475 {
2476         struct device *dev = it6505->dev;
2477
2478         DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt");
2479         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2480         flush_work(&it6505->link_works);
2481         it6505_stop_hdcp(it6505);
2482         it6505_video_reset(it6505);
2483 }
2484
2485 static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505)
2486 {
2487         struct device *dev = it6505->dev;
2488
2489         DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt");
2490         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2491         flush_work(&it6505->link_works);
2492         it6505_stop_hdcp(it6505);
2493         it6505_video_reset(it6505);
2494 }
2495
2496 static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2497 {
2498         return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2499 }
2500
2501 static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2502 {
2503         struct it6505 *it6505 = data;
2504         struct device *dev = it6505->dev;
2505         static const struct {
2506                 int bit;
2507                 void (*handler)(struct it6505 *it6505);
2508         } irq_vec[] = {
2509                 { BIT_INT_HPD, it6505_irq_hpd },
2510                 { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2511                 { BIT_INT_SCDT, it6505_irq_scdt },
2512                 { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2513                 { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2514                 { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2515                 { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2516                 { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2517                 { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2518                 { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error },
2519                 { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow },
2520         };
2521         int int_status[3], i;
2522
2523         if (it6505->enable_drv_hold || !it6505->powered)
2524                 return IRQ_HANDLED;
2525
2526         pm_runtime_get_sync(dev);
2527
2528         int_status[0] = it6505_read(it6505, INT_STATUS_01);
2529         int_status[1] = it6505_read(it6505, INT_STATUS_02);
2530         int_status[2] = it6505_read(it6505, INT_STATUS_03);
2531
2532         it6505_write(it6505, INT_STATUS_01, int_status[0]);
2533         it6505_write(it6505, INT_STATUS_02, int_status[1]);
2534         it6505_write(it6505, INT_STATUS_03, int_status[2]);
2535
2536         DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2537         DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2538         DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2539         it6505_debug_print(it6505, REG_SYSTEM_STS, "");
2540
2541         if (it6505_test_bit(irq_vec[0].bit, (unsigned int *)int_status))
2542                 irq_vec[0].handler(it6505);
2543
2544         if (it6505->hpd_state) {
2545                 for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2546                         if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))
2547                                 irq_vec[i].handler(it6505);
2548                 }
2549         }
2550
2551         pm_runtime_put_sync(dev);
2552
2553         return IRQ_HANDLED;
2554 }
2555
2556 static int it6505_poweron(struct it6505 *it6505)
2557 {
2558         struct device *dev = it6505->dev;
2559         struct it6505_platform_data *pdata = &it6505->pdata;
2560         int err;
2561
2562         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2563
2564         if (it6505->powered) {
2565                 DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2566                 return 0;
2567         }
2568
2569         if (pdata->pwr18) {
2570                 err = regulator_enable(pdata->pwr18);
2571                 if (err) {
2572                         DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2573                                              err);
2574                         return err;
2575                 }
2576         }
2577
2578         if (pdata->ovdd) {
2579                 /* time interval between IVDD and OVDD at least be 1ms */
2580                 usleep_range(1000, 2000);
2581                 err = regulator_enable(pdata->ovdd);
2582                 if (err) {
2583                         regulator_disable(pdata->pwr18);
2584                         return err;
2585                 }
2586         }
2587         /* time interval between OVDD and SYSRSTN at least be 10ms */
2588         if (pdata->gpiod_reset) {
2589                 usleep_range(10000, 20000);
2590                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2591                 usleep_range(1000, 2000);
2592                 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2593                 usleep_range(10000, 20000);
2594         }
2595
2596         it6505->powered = true;
2597         it6505_reset_logic(it6505);
2598         it6505_int_mask_enable(it6505);
2599         it6505_init(it6505);
2600         it6505_lane_off(it6505);
2601
2602         return 0;
2603 }
2604
2605 static int it6505_poweroff(struct it6505 *it6505)
2606 {
2607         struct device *dev = it6505->dev;
2608         struct it6505_platform_data *pdata = &it6505->pdata;
2609         int err;
2610
2611         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2612
2613         if (!it6505->powered) {
2614                 DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2615                 return 0;
2616         }
2617
2618         if (pdata->gpiod_reset)
2619                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2620
2621         if (pdata->pwr18) {
2622                 err = regulator_disable(pdata->pwr18);
2623                 if (err)
2624                         return err;
2625         }
2626
2627         if (pdata->ovdd) {
2628                 err = regulator_disable(pdata->ovdd);
2629                 if (err)
2630                         return err;
2631         }
2632
2633         it6505->powered = false;
2634         it6505->sink_count = 0;
2635
2636         return 0;
2637 }
2638
2639 static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2640 {
2641         struct device *dev = it6505->dev;
2642         enum drm_connector_status status = connector_status_disconnected;
2643         int dp_sink_count;
2644
2645         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2646                              it6505->sink_count, it6505->powered);
2647
2648         mutex_lock(&it6505->mode_lock);
2649
2650         if (!it6505->powered)
2651                 goto unlock;
2652
2653         if (it6505->enable_drv_hold) {
2654                 status = it6505->hpd_state ? connector_status_connected :
2655                                              connector_status_disconnected;
2656                 goto unlock;
2657         }
2658
2659         if (it6505->hpd_state) {
2660                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2661                                              DP_SET_POWER_D0);
2662                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2663                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2664                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2665                                      it6505->sink_count, it6505->branch_device);
2666
2667                 if (it6505->branch_device) {
2668                         status = (it6505->sink_count != 0) ?
2669                                  connector_status_connected :
2670                                  connector_status_disconnected;
2671                 } else {
2672                         status = connector_status_connected;
2673                 }
2674         } else {
2675                 it6505->sink_count = 0;
2676                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2677         }
2678
2679 unlock:
2680         if (it6505->connector_status != status) {
2681                 it6505->connector_status = status;
2682                 it6505_plugged_status_to_codec(it6505);
2683         }
2684
2685         mutex_unlock(&it6505->mode_lock);
2686
2687         return status;
2688 }
2689
2690 static int it6505_extcon_notifier(struct notifier_block *self,
2691                                   unsigned long event, void *ptr)
2692 {
2693         struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2694
2695         schedule_work(&it6505->extcon_wq);
2696         return NOTIFY_DONE;
2697 }
2698
2699 static void it6505_extcon_work(struct work_struct *work)
2700 {
2701         struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2702         struct device *dev = it6505->dev;
2703         int state, ret;
2704
2705         if (it6505->enable_drv_hold)
2706                 return;
2707
2708         mutex_lock(&it6505->extcon_lock);
2709
2710         state = extcon_get_state(it6505->extcon, EXTCON_DISP_DP);
2711         DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2712
2713         if (state == it6505->extcon_state || unlikely(state < 0))
2714                 goto unlock;
2715         it6505->extcon_state = state;
2716         if (state) {
2717                 DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2718                 msleep(100);
2719                 ret = pm_runtime_get_sync(dev);
2720
2721                 /*
2722                  * On system resume, extcon_work can be triggered before
2723                  * pm_runtime_force_resume re-enables runtime power management.
2724                  * Handling the error here to make sure the bridge is powered on.
2725                  */
2726                 if (ret < 0)
2727                         it6505_poweron(it6505);
2728
2729                 complete_all(&it6505->extcon_completion);
2730         } else {
2731                 DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2732                 pm_runtime_put_sync(dev);
2733                 reinit_completion(&it6505->extcon_completion);
2734
2735                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2736                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2737                 DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2738         }
2739
2740 unlock:
2741         mutex_unlock(&it6505->extcon_lock);
2742 }
2743
2744 static int it6505_use_notifier_module(struct it6505 *it6505)
2745 {
2746         int ret;
2747         struct device *dev = it6505->dev;
2748
2749         it6505->event_nb.notifier_call = it6505_extcon_notifier;
2750         INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2751         ret = devm_extcon_register_notifier(it6505->dev,
2752                                             it6505->extcon, EXTCON_DISP_DP,
2753                                             &it6505->event_nb);
2754         if (ret) {
2755                 dev_err(dev, "failed to register notifier for DP");
2756                 return ret;
2757         }
2758
2759         schedule_work(&it6505->extcon_wq);
2760
2761         return 0;
2762 }
2763
2764 static void it6505_remove_notifier_module(struct it6505 *it6505)
2765 {
2766         if (it6505->extcon) {
2767                 devm_extcon_unregister_notifier(it6505->dev,
2768                                                 it6505->extcon, EXTCON_DISP_DP,
2769                                                 &it6505->event_nb);
2770
2771                 flush_work(&it6505->extcon_wq);
2772         }
2773 }
2774
2775 static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2776 {
2777         struct it6505 *it6505 = container_of(work, struct it6505,
2778                                              delayed_audio.work);
2779
2780         DRM_DEV_DEBUG_DRIVER(it6505->dev, "start");
2781
2782         if (!it6505->powered)
2783                 return;
2784
2785         if (!it6505->enable_drv_hold)
2786                 it6505_enable_audio(it6505);
2787 }
2788
2789 static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2790                                                        struct hdmi_codec_params
2791                                                        *params)
2792 {
2793         struct device *dev = it6505->dev;
2794         int i = 0;
2795
2796         DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2797                              params->sample_rate, params->sample_width,
2798                              params->cea.channels);
2799
2800         if (!it6505->bridge.encoder)
2801                 return -ENODEV;
2802
2803         if (params->cea.channels <= 1 || params->cea.channels > 8) {
2804                 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2805                                      it6505->audio.channel_count);
2806                 return -EINVAL;
2807         }
2808
2809         it6505->audio.channel_count = params->cea.channels;
2810
2811         while (i < ARRAY_SIZE(audio_sample_rate_map) &&
2812                params->sample_rate !=
2813                        audio_sample_rate_map[i].sample_rate_value) {
2814                 i++;
2815         }
2816         if (i == ARRAY_SIZE(audio_sample_rate_map)) {
2817                 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
2818                                      params->sample_rate);
2819                 return -EINVAL;
2820         }
2821         it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
2822
2823         switch (params->sample_width) {
2824         case 16:
2825                 it6505->audio.word_length = WORD_LENGTH_16BIT;
2826                 break;
2827         case 18:
2828                 it6505->audio.word_length = WORD_LENGTH_18BIT;
2829                 break;
2830         case 20:
2831                 it6505->audio.word_length = WORD_LENGTH_20BIT;
2832                 break;
2833         case 24:
2834         case 32:
2835                 it6505->audio.word_length = WORD_LENGTH_24BIT;
2836                 break;
2837         default:
2838                 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
2839                                      params->sample_width);
2840                 return -EINVAL;
2841         }
2842
2843         return 0;
2844 }
2845
2846 static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
2847 {
2848         struct it6505 *it6505 = dev_get_drvdata(dev);
2849
2850         if (it6505->powered)
2851                 it6505_disable_audio(it6505);
2852 }
2853
2854 static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
2855                                                        void *data,
2856                                                        hdmi_codec_plugged_cb fn,
2857                                                        struct device *codec_dev)
2858 {
2859         struct it6505 *it6505 = data;
2860
2861         it6505->plugged_cb = fn;
2862         it6505->codec_dev = codec_dev;
2863         it6505_plugged_status_to_codec(it6505);
2864
2865         return 0;
2866 }
2867
2868 static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
2869 {
2870         return container_of(bridge, struct it6505, bridge);
2871 }
2872
2873 static int it6505_bridge_attach(struct drm_bridge *bridge,
2874                                 enum drm_bridge_attach_flags flags)
2875 {
2876         struct it6505 *it6505 = bridge_to_it6505(bridge);
2877         struct device *dev = it6505->dev;
2878         int ret;
2879
2880         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2881                 DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
2882                 return -EINVAL;
2883         }
2884
2885         if (!bridge->encoder) {
2886                 dev_err(dev, "Parent encoder object not found");
2887                 return -ENODEV;
2888         }
2889
2890         /* Register aux channel */
2891         it6505->aux.drm_dev = bridge->dev;
2892
2893         ret = drm_dp_aux_register(&it6505->aux);
2894
2895         if (ret < 0) {
2896                 dev_err(dev, "Failed to register aux: %d", ret);
2897                 return ret;
2898         }
2899
2900         if (it6505->extcon) {
2901                 ret = it6505_use_notifier_module(it6505);
2902                 if (ret < 0) {
2903                         dev_err(dev, "use notifier module failed");
2904                         return ret;
2905                 }
2906         }
2907
2908         return 0;
2909 }
2910
2911 static void it6505_bridge_detach(struct drm_bridge *bridge)
2912 {
2913         struct it6505 *it6505 = bridge_to_it6505(bridge);
2914
2915         flush_work(&it6505->link_works);
2916         it6505_remove_notifier_module(it6505);
2917 }
2918
2919 static enum drm_mode_status
2920 it6505_bridge_mode_valid(struct drm_bridge *bridge,
2921                          const struct drm_display_info *info,
2922                          const struct drm_display_mode *mode)
2923 {
2924         struct it6505 *it6505 = bridge_to_it6505(bridge);
2925
2926         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2927                 return MODE_NO_INTERLACE;
2928
2929         if (mode->clock > it6505->max_dpi_pixel_clock)
2930                 return MODE_CLOCK_HIGH;
2931
2932         it6505->video_info.clock = mode->clock;
2933
2934         return MODE_OK;
2935 }
2936
2937 static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
2938                                         struct drm_bridge_state *old_state)
2939 {
2940         struct it6505 *it6505 = bridge_to_it6505(bridge);
2941         struct device *dev = it6505->dev;
2942         struct drm_atomic_state *state = old_state->base.state;
2943         struct hdmi_avi_infoframe frame;
2944         struct drm_crtc_state *crtc_state;
2945         struct drm_connector_state *conn_state;
2946         struct drm_display_mode *mode;
2947         struct drm_connector *connector;
2948         int ret;
2949
2950         DRM_DEV_DEBUG_DRIVER(dev, "start");
2951
2952         connector = drm_atomic_get_new_connector_for_encoder(state,
2953                                                              bridge->encoder);
2954
2955         if (WARN_ON(!connector))
2956                 return;
2957
2958         conn_state = drm_atomic_get_new_connector_state(state, connector);
2959
2960         if (WARN_ON(!conn_state))
2961                 return;
2962
2963         crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
2964
2965         if (WARN_ON(!crtc_state))
2966                 return;
2967
2968         mode = &crtc_state->adjusted_mode;
2969
2970         if (WARN_ON(!mode))
2971                 return;
2972
2973         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2974                                                        connector,
2975                                                        mode);
2976         if (ret)
2977                 dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
2978
2979         it6505_update_video_parameter(it6505, mode);
2980
2981         ret = it6505_send_video_infoframe(it6505, &frame);
2982
2983         if (ret)
2984                 dev_err(dev, "Failed to send AVI infoframe: %d", ret);
2985
2986         it6505_int_mask_enable(it6505);
2987         it6505_video_reset(it6505);
2988
2989         it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2990                                      DP_SET_POWER_D0);
2991 }
2992
2993 static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
2994                                          struct drm_bridge_state *old_state)
2995 {
2996         struct it6505 *it6505 = bridge_to_it6505(bridge);
2997         struct device *dev = it6505->dev;
2998
2999         DRM_DEV_DEBUG_DRIVER(dev, "start");
3000
3001         if (it6505->powered) {
3002                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
3003                                              DP_SET_POWER_D3);
3004                 it6505_video_disable(it6505);
3005         }
3006 }
3007
3008 static void it6505_bridge_atomic_pre_enable(struct drm_bridge *bridge,
3009                                             struct drm_bridge_state *old_state)
3010 {
3011         struct it6505 *it6505 = bridge_to_it6505(bridge);
3012         struct device *dev = it6505->dev;
3013
3014         DRM_DEV_DEBUG_DRIVER(dev, "start");
3015
3016         pm_runtime_get_sync(dev);
3017 }
3018
3019 static void it6505_bridge_atomic_post_disable(struct drm_bridge *bridge,
3020                                               struct drm_bridge_state *old_state)
3021 {
3022         struct it6505 *it6505 = bridge_to_it6505(bridge);
3023         struct device *dev = it6505->dev;
3024
3025         DRM_DEV_DEBUG_DRIVER(dev, "start");
3026
3027         pm_runtime_put_sync(dev);
3028 }
3029
3030 static enum drm_connector_status
3031 it6505_bridge_detect(struct drm_bridge *bridge)
3032 {
3033         struct it6505 *it6505 = bridge_to_it6505(bridge);
3034
3035         return it6505_detect(it6505);
3036 }
3037
3038 static const struct drm_edid *it6505_bridge_edid_read(struct drm_bridge *bridge,
3039                                                       struct drm_connector *connector)
3040 {
3041         struct it6505 *it6505 = bridge_to_it6505(bridge);
3042         struct device *dev = it6505->dev;
3043
3044         if (!it6505->cached_edid) {
3045                 it6505->cached_edid = drm_edid_read_custom(connector,
3046                                                            it6505_get_edid_block,
3047                                                            it6505);
3048
3049                 if (!it6505->cached_edid) {
3050                         DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
3051                         return NULL;
3052                 }
3053         }
3054
3055         return drm_edid_dup(it6505->cached_edid);
3056 }
3057
3058 static const struct drm_bridge_funcs it6505_bridge_funcs = {
3059         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3060         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3061         .atomic_reset = drm_atomic_helper_bridge_reset,
3062         .attach = it6505_bridge_attach,
3063         .detach = it6505_bridge_detach,
3064         .mode_valid = it6505_bridge_mode_valid,
3065         .atomic_enable = it6505_bridge_atomic_enable,
3066         .atomic_disable = it6505_bridge_atomic_disable,
3067         .atomic_pre_enable = it6505_bridge_atomic_pre_enable,
3068         .atomic_post_disable = it6505_bridge_atomic_post_disable,
3069         .detect = it6505_bridge_detect,
3070         .edid_read = it6505_bridge_edid_read,
3071 };
3072
3073 static __maybe_unused int it6505_bridge_resume(struct device *dev)
3074 {
3075         struct it6505 *it6505 = dev_get_drvdata(dev);
3076
3077         return it6505_poweron(it6505);
3078 }
3079
3080 static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3081 {
3082         struct it6505 *it6505 = dev_get_drvdata(dev);
3083
3084         return it6505_poweroff(it6505);
3085 }
3086
3087 static const struct dev_pm_ops it6505_bridge_pm_ops = {
3088         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
3089         SET_RUNTIME_PM_OPS(it6505_bridge_suspend, it6505_bridge_resume, NULL)
3090 };
3091
3092 static int it6505_init_pdata(struct it6505 *it6505)
3093 {
3094         struct it6505_platform_data *pdata = &it6505->pdata;
3095         struct device *dev = it6505->dev;
3096
3097         /* 1.0V digital core power regulator  */
3098         pdata->pwr18 = devm_regulator_get(dev, "pwr18");
3099         if (IS_ERR(pdata->pwr18)) {
3100                 dev_err(dev, "pwr18 regulator not found");
3101                 return PTR_ERR(pdata->pwr18);
3102         }
3103
3104         pdata->ovdd = devm_regulator_get(dev, "ovdd");
3105         if (IS_ERR(pdata->ovdd)) {
3106                 dev_err(dev, "ovdd regulator not found");
3107                 return PTR_ERR(pdata->ovdd);
3108         }
3109
3110         pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
3111         if (IS_ERR(pdata->gpiod_reset)) {
3112                 dev_err(dev, "gpiod_reset gpio not found");
3113                 return PTR_ERR(pdata->gpiod_reset);
3114         }
3115
3116         return 0;
3117 }
3118
3119 static int it6505_get_data_lanes_count(const struct device_node *endpoint,
3120                                        const unsigned int min,
3121                                        const unsigned int max)
3122 {
3123         int ret;
3124
3125         ret = of_property_count_u32_elems(endpoint, "data-lanes");
3126         if (ret < 0)
3127                 return ret;
3128
3129         if (ret < min || ret > max)
3130                 return -EINVAL;
3131
3132         return ret;
3133 }
3134
3135 static void it6505_parse_dt(struct it6505 *it6505)
3136 {
3137         struct device *dev = it6505->dev;
3138         struct device_node *np = dev->of_node, *ep = NULL;
3139         int len;
3140         u64 link_frequencies;
3141         u32 data_lanes[4];
3142         u32 *afe_setting = &it6505->afe_setting;
3143         u32 *max_lane_count = &it6505->max_lane_count;
3144         u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock;
3145
3146         it6505->lane_swap_disabled =
3147                 device_property_read_bool(dev, "no-laneswap");
3148
3149         if (it6505->lane_swap_disabled)
3150                 it6505->lane_swap = false;
3151
3152         if (device_property_read_u32(dev, "afe-setting", afe_setting) == 0) {
3153                 if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3154                         dev_err(dev, "afe setting error, use default");
3155                         *afe_setting = 0;
3156                 }
3157         } else {
3158                 *afe_setting = 0;
3159         }
3160
3161         ep = of_graph_get_endpoint_by_regs(np, 1, 0);
3162         of_node_put(ep);
3163
3164         if (ep) {
3165                 len = it6505_get_data_lanes_count(ep, 1, 4);
3166
3167                 if (len > 0 && len != 3) {
3168                         of_property_read_u32_array(ep, "data-lanes",
3169                                                    data_lanes, len);
3170                         *max_lane_count = len;
3171                 } else {
3172                         *max_lane_count = MAX_LANE_COUNT;
3173                         dev_err(dev, "error data-lanes, use default");
3174                 }
3175         } else {
3176                 *max_lane_count = MAX_LANE_COUNT;
3177                 dev_err(dev, "error endpoint, use default");
3178         }
3179
3180         ep = of_graph_get_endpoint_by_regs(np, 0, 0);
3181         of_node_put(ep);
3182
3183         if (ep) {
3184                 len = of_property_read_variable_u64_array(ep,
3185                                                           "link-frequencies",
3186                                                           &link_frequencies, 0,
3187                                                           1);
3188                 if (len >= 0) {
3189                         do_div(link_frequencies, 1000);
3190                         if (link_frequencies > 297000) {
3191                                 dev_err(dev,
3192                                         "max pixel clock error, use default");
3193                                 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3194                         } else {
3195                                 *max_dpi_pixel_clock = link_frequencies;
3196                         }
3197                 } else {
3198                         dev_err(dev, "error link frequencies, use default");
3199                         *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3200                 }
3201         } else {
3202                 dev_err(dev, "error endpoint, use default");
3203                 *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX;
3204         }
3205
3206         DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u",
3207                              it6505->afe_setting, it6505->max_lane_count);
3208         DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz",
3209                              it6505->max_dpi_pixel_clock);
3210 }
3211
3212 static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3213                                            size_t len, loff_t *ppos)
3214 {
3215         struct it6505 *it6505 = file->private_data;
3216         struct drm_display_mode *vid;
3217         u8 read_buf[READ_BUFFER_SIZE];
3218         u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3219         ssize_t ret, count;
3220
3221         if (!it6505)
3222                 return -ENODEV;
3223
3224         it6505_calc_video_info(it6505);
3225         vid = &it6505->video_info;
3226         str += scnprintf(str, end - str, "---video timing---\n");
3227         str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
3228                          vid->clock / 1000, vid->clock % 1000);
3229         str += scnprintf(str, end - str, "HTotal:%d\n", vid->htotal);
3230         str += scnprintf(str, end - str, "HActive:%d\n", vid->hdisplay);
3231         str += scnprintf(str, end - str, "HFrontPorch:%d\n",
3232                          vid->hsync_start - vid->hdisplay);
3233         str += scnprintf(str, end - str, "HSyncWidth:%d\n",
3234                          vid->hsync_end - vid->hsync_start);
3235         str += scnprintf(str, end - str, "HBackPorch:%d\n",
3236                          vid->htotal - vid->hsync_end);
3237         str += scnprintf(str, end - str, "VTotal:%d\n", vid->vtotal);
3238         str += scnprintf(str, end - str, "VActive:%d\n", vid->vdisplay);
3239         str += scnprintf(str, end - str, "VFrontPorch:%d\n",
3240                          vid->vsync_start - vid->vdisplay);
3241         str += scnprintf(str, end - str, "VSyncWidth:%d\n",
3242                          vid->vsync_end - vid->vsync_start);
3243         str += scnprintf(str, end - str, "VBackPorch:%d\n",
3244                          vid->vtotal - vid->vsync_end);
3245
3246         count = str - read_buf;
3247         ret = simple_read_from_buffer(buf, len, ppos, read_buf, count);
3248
3249         return ret;
3250 }
3251
3252 static int force_power_on_off_debugfs_write(void *data, u64 value)
3253 {
3254         struct it6505 *it6505 = data;
3255
3256         if (!it6505)
3257                 return -ENODEV;
3258
3259         if (value)
3260                 it6505_poweron(it6505);
3261         else
3262                 it6505_poweroff(it6505);
3263
3264         return 0;
3265 }
3266
3267 static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3268 {
3269         struct it6505 *it6505 = data;
3270
3271         if (!it6505)
3272                 return -ENODEV;
3273
3274         *buf = it6505->enable_drv_hold;
3275
3276         return 0;
3277 }
3278
3279 static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3280 {
3281         struct it6505 *it6505 = data;
3282
3283         if (!it6505)
3284                 return -ENODEV;
3285
3286         it6505->enable_drv_hold = drv_hold;
3287
3288         if (it6505->enable_drv_hold) {
3289                 it6505_int_mask_disable(it6505);
3290         } else {
3291                 it6505_clear_int(it6505);
3292                 it6505_int_mask_enable(it6505);
3293
3294                 if (it6505->powered) {
3295                         it6505->connector_status =
3296                                         it6505_get_sink_hpd_status(it6505) ?
3297                                         connector_status_connected :
3298                                         connector_status_disconnected;
3299                 } else {
3300                         it6505->connector_status =
3301                                         connector_status_disconnected;
3302                 }
3303         }
3304
3305         return 0;
3306 }
3307
3308 static const struct file_operations receive_timing_fops = {
3309         .owner = THIS_MODULE,
3310         .open = simple_open,
3311         .read = receive_timing_debugfs_show,
3312         .llseek = default_llseek,
3313 };
3314
3315 DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3316                          force_power_on_off_debugfs_write, "%llu\n");
3317
3318 DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3319                          enable_drv_hold_debugfs_write, "%llu\n");
3320
3321 static const struct debugfs_entries debugfs_entry[] = {
3322         { "receive_timing", &receive_timing_fops },
3323         { "force_power_on_off", &fops_force_power },
3324         { "enable_drv_hold", &fops_enable_drv_hold },
3325         { NULL, NULL },
3326 };
3327
3328 static void debugfs_create_files(struct it6505 *it6505)
3329 {
3330         int i = 0;
3331
3332         while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3333                 debugfs_create_file(debugfs_entry[i].name, 0644,
3334                                     it6505->debugfs, it6505,
3335                                     debugfs_entry[i].fops);
3336                 i++;
3337         }
3338 }
3339
3340 static void debugfs_init(struct it6505 *it6505)
3341 {
3342         struct device *dev = it6505->dev;
3343
3344         it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3345
3346         if (IS_ERR(it6505->debugfs)) {
3347                 dev_err(dev, "failed to create debugfs root");
3348                 return;
3349         }
3350
3351         debugfs_create_files(it6505);
3352 }
3353
3354 static void it6505_debugfs_remove(struct it6505 *it6505)
3355 {
3356         debugfs_remove_recursive(it6505->debugfs);
3357 }
3358
3359 static void it6505_shutdown(struct i2c_client *client)
3360 {
3361         struct it6505 *it6505 = dev_get_drvdata(&client->dev);
3362
3363         if (it6505->powered)
3364                 it6505_lane_off(it6505);
3365 }
3366
3367 static int it6505_i2c_probe(struct i2c_client *client)
3368 {
3369         struct it6505 *it6505;
3370         struct device *dev = &client->dev;
3371         struct extcon_dev *extcon;
3372         int err, intp_irq;
3373
3374         it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
3375         if (!it6505)
3376                 return -ENOMEM;
3377
3378         mutex_init(&it6505->extcon_lock);
3379         mutex_init(&it6505->mode_lock);
3380         mutex_init(&it6505->aux_lock);
3381
3382         it6505->bridge.of_node = client->dev.of_node;
3383         it6505->connector_status = connector_status_disconnected;
3384         it6505->dev = &client->dev;
3385         i2c_set_clientdata(client, it6505);
3386
3387         /* get extcon device from DTS */
3388         extcon = extcon_get_edev_by_phandle(dev, 0);
3389         if (PTR_ERR(extcon) == -EPROBE_DEFER)
3390                 return -EPROBE_DEFER;
3391         if (IS_ERR(extcon)) {
3392                 dev_err(dev, "can not get extcon device!");
3393                 return PTR_ERR(extcon);
3394         }
3395
3396         it6505->extcon = extcon;
3397
3398         it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3399         if (IS_ERR(it6505->regmap)) {
3400                 dev_err(dev, "regmap i2c init failed");
3401                 err = PTR_ERR(it6505->regmap);
3402                 return err;
3403         }
3404
3405         err = it6505_init_pdata(it6505);
3406         if (err) {
3407                 dev_err(dev, "Failed to initialize pdata: %d", err);
3408                 return err;
3409         }
3410
3411         it6505_parse_dt(it6505);
3412
3413         intp_irq = client->irq;
3414
3415         if (!intp_irq) {
3416                 dev_err(dev, "Failed to get INTP IRQ");
3417                 err = -ENODEV;
3418                 return err;
3419         }
3420
3421         err = devm_request_threaded_irq(&client->dev, intp_irq, NULL,
3422                                         it6505_int_threaded_handler,
3423                                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3424                                         "it6505-intp", it6505);
3425         if (err) {
3426                 dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3427                 return err;
3428         }
3429
3430         INIT_WORK(&it6505->link_works, it6505_link_training_work);
3431         INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3432         INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3433         init_completion(&it6505->extcon_completion);
3434         memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3435         it6505->powered = false;
3436         it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3437
3438         if (DEFAULT_PWR_ON)
3439                 it6505_poweron(it6505);
3440
3441         DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3442         debugfs_init(it6505);
3443         pm_runtime_enable(dev);
3444
3445         it6505->aux.name = "DP-AUX";
3446         it6505->aux.dev = dev;
3447         it6505->aux.transfer = it6505_aux_transfer;
3448         drm_dp_aux_init(&it6505->aux);
3449
3450         it6505->bridge.funcs = &it6505_bridge_funcs;
3451         it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3452         it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3453                              DRM_BRIDGE_OP_HPD;
3454         drm_bridge_add(&it6505->bridge);
3455
3456         return 0;
3457 }
3458
3459 static void it6505_i2c_remove(struct i2c_client *client)
3460 {
3461         struct it6505 *it6505 = i2c_get_clientdata(client);
3462
3463         drm_bridge_remove(&it6505->bridge);
3464         drm_dp_aux_unregister(&it6505->aux);
3465         it6505_debugfs_remove(it6505);
3466         it6505_poweroff(it6505);
3467         it6505_remove_edid(it6505);
3468 }
3469
3470 static const struct i2c_device_id it6505_id[] = {
3471         { "it6505", 0 },
3472         { }
3473 };
3474
3475 MODULE_DEVICE_TABLE(i2c, it6505_id);
3476
3477 static const struct of_device_id it6505_of_match[] = {
3478         { .compatible = "ite,it6505" },
3479         { }
3480 };
3481
3482 static struct i2c_driver it6505_i2c_driver = {
3483         .driver = {
3484                 .name = "it6505",
3485                 .of_match_table = it6505_of_match,
3486                 .pm = &it6505_bridge_pm_ops,
3487         },
3488         .probe = it6505_i2c_probe,
3489         .remove = it6505_i2c_remove,
3490         .shutdown = it6505_shutdown,
3491         .id_table = it6505_id,
3492 };
3493
3494 module_i2c_driver(it6505_i2c_driver);
3495
3496 MODULE_AUTHOR("Allen Chen <[email protected]>");
3497 MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3498 MODULE_LICENSE("GPL v2");