2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __AMDGPU_GFX_H__
25 #define __AMDGPU_GFX_H__
27 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
28 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
30 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
33 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
36 * amdgpu_gfx_create_bitmask - create a bitmask
38 * @bit_width: length of the mask
40 * create a variable length bit mask.
41 * Returns the bitmask.
43 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
45 return (u32)((1ULL << bit_width) - 1);
48 static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev,
49 int mec, int pipe, int queue)
53 bit += mec * adev->gfx.mec.num_pipe_per_mec
54 * adev->gfx.mec.num_queue_per_pipe;
55 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
61 static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
62 int *mec, int *pipe, int *queue)
64 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
65 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
66 % adev->gfx.mec.num_pipe_per_mec;
67 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
68 / adev->gfx.mec.num_pipe_per_mec;
71 static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
72 int mec, int pipe, int queue)
74 return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),
75 adev->gfx.mec.queue_bitmap);