drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 103 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 104 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 105 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 106 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 107 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 108 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 109 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 110 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 111 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 112 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 113 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 114 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 115 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 116 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 117 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 118 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 119 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 120 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 121 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 122 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 123 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 124
 125 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 126 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 127 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 128 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 129 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 130 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 131 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 132 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 133 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 134 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 135 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 136 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 137
 138 #define mmCPG_PSP_DEBUG                         0x5c10
 139 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 140 #define mmCPC_PSP_DEBUG                         0x5c11
 141 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 142 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 143 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 144
 145 //CC_GC_SA_UNIT_DISABLE
 146 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 147 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 148 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 149 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 150 //GC_USER_SA_UNIT_DISABLE
 151 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 152 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 153 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 154 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 155 //PA_SC_ENHANCE_3
 156 #define mmPA_SC_ENHANCE_3                       0x1085
 157 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 158 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 159 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 160
 161 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 162 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 163
 164 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 165 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 166 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 167 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 168
 169 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 170 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 171
 172 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 173 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 174 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 175 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 176 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 177 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 178
 179 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 180 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 181 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 182 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 183 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 184 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 185 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 186 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 187 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 188 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 190
 191 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 192 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 193 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 194 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 195 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 196 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 197
 198 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 199 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 200 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 201 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 202 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 203 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 204
 205 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 206 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 207 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 208 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 209 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 210 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 211
 212 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 213 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 214 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 215 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 216 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 217 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 218
 219 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 220 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 221 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 222 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 223 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 224 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 225
 226 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 227 {
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 268 };
 269
 270 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 271 {
 272         /* Pending on emulation bring up */
 273 };
 274
 275 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 276 {
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1329 };
1330
1331 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1332 {
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1371 };
1372
1373 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1374 {
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1415 };
1416
1417 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1418 {
1419         static void *scratch_reg0;
1420         static void *scratch_reg1;
1421         static void *spare_int;
1422         uint32_t i = 0;
1423         uint32_t retries = 50000;
1424
1425         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1426         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1427         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1428
1429         if (amdgpu_sriov_runtime(adev)) {
1430                 pr_err("shouldn't call rlcg write register during runtime\n");
1431                 return;
1432         }
1433
1434         writel(v, scratch_reg0);
1435         writel(offset | 0x80000000, scratch_reg1);
1436         writel(1, spare_int);
1437         for (i = 0; i < retries; i++) {
1438                 u32 tmp;
1439
1440                 tmp = readl(scratch_reg1);
1441                 if (!(tmp & 0x80000000))
1442                         break;
1443
1444                 udelay(10);
1445         }
1446
1447         if (i >= retries)
1448                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1449 }
1450
1451 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1452 {
1453         /* Pending on emulation bring up */
1454 };
1455
1456 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1457 {
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2078 };
2079
2080 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2081 {
2082         /* Pending on emulation bring up */
2083 };
2084
2085 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2086 {
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3139 };
3140
3141 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3142 {
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3185 };
3186
3187 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3188 {
3189         /* Pending on emulation bring up */
3190 };
3191
3192 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3193 {
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3235
3236         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3238 };
3239
3240 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3241 {
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3265
3266         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3268 };
3269
3270 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3271 {
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3307 };
3308
3309 #define DEFAULT_SH_MEM_CONFIG \
3310         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3311          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3312          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3313          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3314
3315
3316 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3317 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3318 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3319 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3320 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3321                                  struct amdgpu_cu_info *cu_info);
3322 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3323 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3324                                    u32 sh_num, u32 instance);
3325 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3326
3327 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3328 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3329 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3330 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3331 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3332 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3333 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3334 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3335 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3336 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3337
3338 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3339 {
3340         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3341         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3342                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3343         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3344         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3345         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3346         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3347         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3348         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3349 }
3350
3351 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3352                                  struct amdgpu_ring *ring)
3353 {
3354         struct amdgpu_device *adev = kiq_ring->adev;
3355         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3356         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3357         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3358
3359         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3360         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3361         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3362                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3363                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3364                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3365                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3366                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3367                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3368                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3369                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3370                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3371         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3372         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3373         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3374         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3375         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3376 }
3377
3378 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3379                                    struct amdgpu_ring *ring,
3380                                    enum amdgpu_unmap_queues_action action,
3381                                    u64 gpu_addr, u64 seq)
3382 {
3383         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3384
3385         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3386         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3387                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3388                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3389                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3390                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3391         amdgpu_ring_write(kiq_ring,
3392                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3393
3394         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3395                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3396                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3397                 amdgpu_ring_write(kiq_ring, seq);
3398         } else {
3399                 amdgpu_ring_write(kiq_ring, 0);
3400                 amdgpu_ring_write(kiq_ring, 0);
3401                 amdgpu_ring_write(kiq_ring, 0);
3402         }
3403 }
3404
3405 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3406                                    struct amdgpu_ring *ring,
3407                                    u64 addr,
3408                                    u64 seq)
3409 {
3410         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3411
3412         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3413         amdgpu_ring_write(kiq_ring,
3414                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3415                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3416                           PACKET3_QUERY_STATUS_COMMAND(2));
3417         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3418                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3419                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3420         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3421         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3422         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3423         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3424 }
3425
3426 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3427                                 uint16_t pasid, uint32_t flush_type,
3428                                 bool all_hub)
3429 {
3430         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3431         amdgpu_ring_write(kiq_ring,
3432                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3433                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3434                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3435                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3436 }
3437
3438 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3439         .kiq_set_resources = gfx10_kiq_set_resources,
3440         .kiq_map_queues = gfx10_kiq_map_queues,
3441         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3442         .kiq_query_status = gfx10_kiq_query_status,
3443         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3444         .set_resources_size = 8,
3445         .map_queues_size = 7,
3446         .unmap_queues_size = 6,
3447         .query_status_size = 7,
3448         .invalidate_tlbs_size = 2,
3449 };
3450
3451 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3452 {
3453         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3454 }
3455
3456 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3457 {
3458         switch (adev->asic_type) {
3459         case CHIP_NAVI10:
3460                 soc15_program_register_sequence(adev,
3461                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3462                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3463                 break;
3464         case CHIP_NAVI14:
3465                 soc15_program_register_sequence(adev,
3466                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3467                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3468                 break;
3469         case CHIP_NAVI12:
3470                 soc15_program_register_sequence(adev,
3471                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3472                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3473                 break;
3474         default:
3475                 break;
3476         }
3477 }
3478
3479 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3480 {
3481         switch (adev->asic_type) {
3482         case CHIP_NAVI10:
3483                 soc15_program_register_sequence(adev,
3484                                                 golden_settings_gc_10_1,
3485                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3486                 soc15_program_register_sequence(adev,
3487                                                 golden_settings_gc_10_0_nv10,
3488                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3489                 break;
3490         case CHIP_NAVI14:
3491                 soc15_program_register_sequence(adev,
3492                                                 golden_settings_gc_10_1_1,
3493                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3494                 soc15_program_register_sequence(adev,
3495                                                 golden_settings_gc_10_1_nv14,
3496                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3497                 break;
3498         case CHIP_NAVI12:
3499                 soc15_program_register_sequence(adev,
3500                                                 golden_settings_gc_10_1_2,
3501                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3502                 soc15_program_register_sequence(adev,
3503                                                 golden_settings_gc_10_1_2_nv12,
3504                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3505                 break;
3506         case CHIP_SIENNA_CICHLID:
3507                 soc15_program_register_sequence(adev,
3508                                                 golden_settings_gc_10_3,
3509                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3510                 soc15_program_register_sequence(adev,
3511                                                 golden_settings_gc_10_3_sienna_cichlid,
3512                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3513                 break;
3514         case CHIP_NAVY_FLOUNDER:
3515                 soc15_program_register_sequence(adev,
3516                                                 golden_settings_gc_10_3_2,
3517                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3518                 break;
3519         case CHIP_VANGOGH:
3520                 soc15_program_register_sequence(adev,
3521                                                 golden_settings_gc_10_3_vangogh,
3522                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3523                 break;
3524         case CHIP_DIMGREY_CAVEFISH:
3525                 soc15_program_register_sequence(adev,
3526                                                 golden_settings_gc_10_3_4,
3527                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3528                 break;
3529         default:
3530                 break;
3531         }
3532         gfx_v10_0_init_spm_golden_registers(adev);
3533 }
3534
3535 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3536 {
3537         adev->gfx.scratch.num_reg = 8;
3538         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3539         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3540 }
3541
3542 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3543                                        bool wc, uint32_t reg, uint32_t val)
3544 {
3545         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3546         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3547                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3548         amdgpu_ring_write(ring, reg);
3549         amdgpu_ring_write(ring, 0);
3550         amdgpu_ring_write(ring, val);
3551 }
3552
3553 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3554                                   int mem_space, int opt, uint32_t addr0,
3555                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3556                                   uint32_t inv)
3557 {
3558         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3559         amdgpu_ring_write(ring,
3560                           /* memory (1) or register (0) */
3561                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3562                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3563                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3564                            WAIT_REG_MEM_ENGINE(eng_sel)));
3565
3566         if (mem_space)
3567                 BUG_ON(addr0 & 0x3); /* Dword align */
3568         amdgpu_ring_write(ring, addr0);
3569         amdgpu_ring_write(ring, addr1);
3570         amdgpu_ring_write(ring, ref);
3571         amdgpu_ring_write(ring, mask);
3572         amdgpu_ring_write(ring, inv); /* poll interval */
3573 }
3574
3575 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3576 {
3577         struct amdgpu_device *adev = ring->adev;
3578         uint32_t scratch;
3579         uint32_t tmp = 0;
3580         unsigned i;
3581         int r;
3582
3583         r = amdgpu_gfx_scratch_get(adev, &scratch);
3584         if (r) {
3585                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3586                 return r;
3587         }
3588
3589         WREG32(scratch, 0xCAFEDEAD);
3590
3591         r = amdgpu_ring_alloc(ring, 3);
3592         if (r) {
3593                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3594                           ring->idx, r);
3595                 amdgpu_gfx_scratch_free(adev, scratch);
3596                 return r;
3597         }
3598
3599         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3600         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3601         amdgpu_ring_write(ring, 0xDEADBEEF);
3602         amdgpu_ring_commit(ring);
3603
3604         for (i = 0; i < adev->usec_timeout; i++) {
3605                 tmp = RREG32(scratch);
3606                 if (tmp == 0xDEADBEEF)
3607                         break;
3608                 if (amdgpu_emu_mode == 1)
3609                         msleep(1);
3610                 else
3611                         udelay(1);
3612         }
3613
3614         if (i >= adev->usec_timeout)
3615                 r = -ETIMEDOUT;
3616
3617         amdgpu_gfx_scratch_free(adev, scratch);
3618
3619         return r;
3620 }
3621
3622 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3623 {
3624         struct amdgpu_device *adev = ring->adev;
3625         struct amdgpu_ib ib;
3626         struct dma_fence *f = NULL;
3627         unsigned index;
3628         uint64_t gpu_addr;
3629         uint32_t tmp;
3630         long r;
3631
3632         r = amdgpu_device_wb_get(adev, &index);
3633         if (r)
3634                 return r;
3635
3636         gpu_addr = adev->wb.gpu_addr + (index * 4);
3637         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3638         memset(&ib, 0, sizeof(ib));
3639         r = amdgpu_ib_get(adev, NULL, 16,
3640                                         AMDGPU_IB_POOL_DIRECT, &ib);
3641         if (r)
3642                 goto err1;
3643
3644         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3645         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3646         ib.ptr[2] = lower_32_bits(gpu_addr);
3647         ib.ptr[3] = upper_32_bits(gpu_addr);
3648         ib.ptr[4] = 0xDEADBEEF;
3649         ib.length_dw = 5;
3650
3651         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3652         if (r)
3653                 goto err2;
3654
3655         r = dma_fence_wait_timeout(f, false, timeout);
3656         if (r == 0) {
3657                 r = -ETIMEDOUT;
3658                 goto err2;
3659         } else if (r < 0) {
3660                 goto err2;
3661         }
3662
3663         tmp = adev->wb.wb[index];
3664         if (tmp == 0xDEADBEEF)
3665                 r = 0;
3666         else
3667                 r = -EINVAL;
3668 err2:
3669         amdgpu_ib_free(adev, &ib, NULL);
3670         dma_fence_put(f);
3671 err1:
3672         amdgpu_device_wb_free(adev, index);
3673         return r;
3674 }
3675
3676 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3677 {
3678         release_firmware(adev->gfx.pfp_fw);
3679         adev->gfx.pfp_fw = NULL;
3680         release_firmware(adev->gfx.me_fw);
3681         adev->gfx.me_fw = NULL;
3682         release_firmware(adev->gfx.ce_fw);
3683         adev->gfx.ce_fw = NULL;
3684         release_firmware(adev->gfx.rlc_fw);
3685         adev->gfx.rlc_fw = NULL;
3686         release_firmware(adev->gfx.mec_fw);
3687         adev->gfx.mec_fw = NULL;
3688         release_firmware(adev->gfx.mec2_fw);
3689         adev->gfx.mec2_fw = NULL;
3690
3691         kfree(adev->gfx.rlc.register_list_format);
3692 }
3693
3694 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3695 {
3696         adev->gfx.cp_fw_write_wait = false;
3697
3698         switch (adev->asic_type) {
3699         case CHIP_NAVI10:
3700         case CHIP_NAVI12:
3701         case CHIP_NAVI14:
3702                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3703                     (adev->gfx.me_feature_version >= 27) &&
3704                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3705                     (adev->gfx.pfp_feature_version >= 27) &&
3706                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3707                     (adev->gfx.mec_feature_version >= 27))
3708                         adev->gfx.cp_fw_write_wait = true;
3709                 break;
3710         case CHIP_SIENNA_CICHLID:
3711         case CHIP_NAVY_FLOUNDER:
3712         case CHIP_VANGOGH:
3713         case CHIP_DIMGREY_CAVEFISH:
3714                 adev->gfx.cp_fw_write_wait = true;
3715                 break;
3716         default:
3717                 break;
3718         }
3719
3720         if (!adev->gfx.cp_fw_write_wait)
3721                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3722 }
3723
3724
3725 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3726 {
3727         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3728
3729         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3730         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3731         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3732         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3733         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3734         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3735         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3736         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3737         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3738         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3739         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3740         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3741         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3742         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3743                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3744 }
3745
3746 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3747 {
3748         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3749
3750         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3751         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3752         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3753         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3754         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3755 }
3756
3757 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3758 {
3759         bool ret = false;
3760
3761         switch (adev->pdev->revision) {
3762         case 0xc2:
3763         case 0xc3:
3764                 ret = true;
3765                 break;
3766         default:
3767                 ret = false;
3768                 break;
3769         }
3770
3771         return ret ;
3772 }
3773
3774 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3775 {
3776         switch (adev->asic_type) {
3777         case CHIP_NAVI10:
3778                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3779                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3780                 break;
3781         case CHIP_VANGOGH:
3782                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3783                 break;
3784         default:
3785                 break;
3786         }
3787 }
3788
3789 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3790 {
3791         const char *chip_name;
3792         char fw_name[40];
3793         char wks[10];
3794         int err;
3795         struct amdgpu_firmware_info *info = NULL;
3796         const struct common_firmware_header *header = NULL;
3797         const struct gfx_firmware_header_v1_0 *cp_hdr;
3798         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3799         unsigned int *tmp = NULL;
3800         unsigned int i = 0;
3801         uint16_t version_major;
3802         uint16_t version_minor;
3803
3804         DRM_DEBUG("\n");
3805
3806         memset(wks, 0, sizeof(wks));
3807         switch (adev->asic_type) {
3808         case CHIP_NAVI10:
3809                 chip_name = "navi10";
3810                 break;
3811         case CHIP_NAVI14:
3812                 chip_name = "navi14";
3813                 if (!(adev->pdev->device == 0x7340 &&
3814                       adev->pdev->revision != 0x00))
3815                         snprintf(wks, sizeof(wks), "_wks");
3816                 break;
3817         case CHIP_NAVI12:
3818                 chip_name = "navi12";
3819                 break;
3820         case CHIP_SIENNA_CICHLID:
3821                 chip_name = "sienna_cichlid";
3822                 break;
3823         case CHIP_NAVY_FLOUNDER:
3824                 chip_name = "navy_flounder";
3825                 break;
3826         case CHIP_VANGOGH:
3827                 chip_name = "vangogh";
3828                 break;
3829         case CHIP_DIMGREY_CAVEFISH:
3830                 chip_name = "dimgrey_cavefish";
3831                 break;
3832         default:
3833                 BUG();
3834         }
3835
3836         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3837         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3838         if (err)
3839                 goto out;
3840         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3841         if (err)
3842                 goto out;
3843         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3844         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3845         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3846
3847         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3848         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3849         if (err)
3850                 goto out;
3851         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3852         if (err)
3853                 goto out;
3854         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3855         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3856         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3857
3858         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3859         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3860         if (err)
3861                 goto out;
3862         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3863         if (err)
3864                 goto out;
3865         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3866         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3867         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3868
3869         if (!amdgpu_sriov_vf(adev)) {
3870                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3871                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3872                 if (err)
3873                         goto out;
3874                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3875                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3876                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3877                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3878
3879                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3880                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3881                 adev->gfx.rlc.save_and_restore_offset =
3882                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3883                 adev->gfx.rlc.clear_state_descriptor_offset =
3884                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3885                 adev->gfx.rlc.avail_scratch_ram_locations =
3886                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3887                 adev->gfx.rlc.reg_restore_list_size =
3888                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3889                 adev->gfx.rlc.reg_list_format_start =
3890                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3891                 adev->gfx.rlc.reg_list_format_separate_start =
3892                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3893                 adev->gfx.rlc.starting_offsets_start =
3894                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3895                 adev->gfx.rlc.reg_list_format_size_bytes =
3896                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3897                 adev->gfx.rlc.reg_list_size_bytes =
3898                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3899                 adev->gfx.rlc.register_list_format =
3900                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3901                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3902                 if (!adev->gfx.rlc.register_list_format) {
3903                         err = -ENOMEM;
3904                         goto out;
3905                 }
3906
3907                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3908                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3909                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3910                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3911
3912                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3913
3914                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3915                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3916                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3917                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3918
3919                 if (version_major == 2) {
3920                         if (version_minor >= 1)
3921                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3922                         if (version_minor == 2)
3923                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3924                 }
3925         }
3926
3927         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3928         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3929         if (err)
3930                 goto out;
3931         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3932         if (err)
3933                 goto out;
3934         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3935         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3936         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3937
3938         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3939         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3940         if (!err) {
3941                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3942                 if (err)
3943                         goto out;
3944                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3945                 adev->gfx.mec2_fw->data;
3946                 adev->gfx.mec2_fw_version =
3947                 le32_to_cpu(cp_hdr->header.ucode_version);
3948                 adev->gfx.mec2_feature_version =
3949                 le32_to_cpu(cp_hdr->ucode_feature_version);
3950         } else {
3951                 err = 0;
3952                 adev->gfx.mec2_fw = NULL;
3953         }
3954
3955         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3956                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3957                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3958                 info->fw = adev->gfx.pfp_fw;
3959                 header = (const struct common_firmware_header *)info->fw->data;
3960                 adev->firmware.fw_size +=
3961                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3962
3963                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3964                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3965                 info->fw = adev->gfx.me_fw;
3966                 header = (const struct common_firmware_header *)info->fw->data;
3967                 adev->firmware.fw_size +=
3968                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3969
3970                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3971                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3972                 info->fw = adev->gfx.ce_fw;
3973                 header = (const struct common_firmware_header *)info->fw->data;
3974                 adev->firmware.fw_size +=
3975                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3976
3977                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3978                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3979                 info->fw = adev->gfx.rlc_fw;
3980                 if (info->fw) {
3981                         header = (const struct common_firmware_header *)info->fw->data;
3982                         adev->firmware.fw_size +=
3983                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3984                 }
3985                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3986                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3987                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3988                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3989                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3990                         info->fw = adev->gfx.rlc_fw;
3991                         adev->firmware.fw_size +=
3992                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3993
3994                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3995                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3996                         info->fw = adev->gfx.rlc_fw;
3997                         adev->firmware.fw_size +=
3998                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3999
4000                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4001                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4002                         info->fw = adev->gfx.rlc_fw;
4003                         adev->firmware.fw_size +=
4004                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4005
4006                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4007                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4008                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4009                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4010                                 info->fw = adev->gfx.rlc_fw;
4011                                 adev->firmware.fw_size +=
4012                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4013
4014                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4015                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4016                                 info->fw = adev->gfx.rlc_fw;
4017                                 adev->firmware.fw_size +=
4018                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4019                         }
4020                 }
4021
4022                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4023                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4024                 info->fw = adev->gfx.mec_fw;
4025                 header = (const struct common_firmware_header *)info->fw->data;
4026                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4027                 adev->firmware.fw_size +=
4028                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4029                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4030
4031                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4032                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4033                 info->fw = adev->gfx.mec_fw;
4034                 adev->firmware.fw_size +=
4035                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4036
4037                 if (adev->gfx.mec2_fw) {
4038                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4039                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4040                         info->fw = adev->gfx.mec2_fw;
4041                         header = (const struct common_firmware_header *)info->fw->data;
4042                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4043                         adev->firmware.fw_size +=
4044                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4045                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4046                                       PAGE_SIZE);
4047                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4048                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4049                         info->fw = adev->gfx.mec2_fw;
4050                         adev->firmware.fw_size +=
4051                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4052                                       PAGE_SIZE);
4053                 }
4054         }
4055
4056         gfx_v10_0_check_fw_write_wait(adev);
4057 out:
4058         if (err) {
4059                 dev_err(adev->dev,
4060                         "gfx10: Failed to load firmware \"%s\"\n",
4061                         fw_name);
4062                 release_firmware(adev->gfx.pfp_fw);
4063                 adev->gfx.pfp_fw = NULL;
4064                 release_firmware(adev->gfx.me_fw);
4065                 adev->gfx.me_fw = NULL;
4066                 release_firmware(adev->gfx.ce_fw);
4067                 adev->gfx.ce_fw = NULL;
4068                 release_firmware(adev->gfx.rlc_fw);
4069                 adev->gfx.rlc_fw = NULL;
4070                 release_firmware(adev->gfx.mec_fw);
4071                 adev->gfx.mec_fw = NULL;
4072                 release_firmware(adev->gfx.mec2_fw);
4073                 adev->gfx.mec2_fw = NULL;
4074         }
4075
4076         gfx_v10_0_check_gfxoff_flag(adev);
4077
4078         return err;
4079 }
4080
4081 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4082 {
4083         u32 count = 0;
4084         const struct cs_section_def *sect = NULL;
4085         const struct cs_extent_def *ext = NULL;
4086
4087         /* begin clear state */
4088         count += 2;
4089         /* context control state */
4090         count += 3;
4091
4092         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4093                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4094                         if (sect->id == SECT_CONTEXT)
4095                                 count += 2 + ext->reg_count;
4096                         else
4097                                 return 0;
4098                 }
4099         }
4100
4101         /* set PA_SC_TILE_STEERING_OVERRIDE */
4102         count += 3;
4103         /* end clear state */
4104         count += 2;
4105         /* clear state */
4106         count += 2;
4107
4108         return count;
4109 }
4110
4111 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4112                                     volatile u32 *buffer)
4113 {
4114         u32 count = 0, i;
4115         const struct cs_section_def *sect = NULL;
4116         const struct cs_extent_def *ext = NULL;
4117         int ctx_reg_offset;
4118
4119         if (adev->gfx.rlc.cs_data == NULL)
4120                 return;
4121         if (buffer == NULL)
4122                 return;
4123
4124         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4125         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4126
4127         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4128         buffer[count++] = cpu_to_le32(0x80000000);
4129         buffer[count++] = cpu_to_le32(0x80000000);
4130
4131         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4132                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4133                         if (sect->id == SECT_CONTEXT) {
4134                                 buffer[count++] =
4135                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4136                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4137                                                 PACKET3_SET_CONTEXT_REG_START);
4138                                 for (i = 0; i < ext->reg_count; i++)
4139                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4140                         } else {
4141                                 return;
4142                         }
4143                 }
4144         }
4145
4146         ctx_reg_offset =
4147                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4148         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4149         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4150         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4151
4152         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4153         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4154
4155         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4156         buffer[count++] = cpu_to_le32(0);
4157 }
4158
4159 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4160 {
4161         /* clear state block */
4162         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4163                         &adev->gfx.rlc.clear_state_gpu_addr,
4164                         (void **)&adev->gfx.rlc.cs_ptr);
4165
4166         /* jump table block */
4167         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4168                         &adev->gfx.rlc.cp_table_gpu_addr,
4169                         (void **)&adev->gfx.rlc.cp_table_ptr);
4170 }
4171
4172 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4173 {
4174         const struct cs_section_def *cs_data;
4175         int r;
4176
4177         adev->gfx.rlc.cs_data = gfx10_cs_data;
4178
4179         cs_data = adev->gfx.rlc.cs_data;
4180
4181         if (cs_data) {
4182                 /* init clear state block */
4183                 r = amdgpu_gfx_rlc_init_csb(adev);
4184                 if (r)
4185                         return r;
4186         }
4187
4188         /* init spm vmid with 0xf */
4189         if (adev->gfx.rlc.funcs->update_spm_vmid)
4190                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4191
4192         return 0;
4193 }
4194
4195 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4196 {
4197         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4198         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4199 }
4200
4201 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4202 {
4203         int r;
4204
4205         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4206
4207         amdgpu_gfx_graphics_queue_acquire(adev);
4208
4209         r = gfx_v10_0_init_microcode(adev);
4210         if (r)
4211                 DRM_ERROR("Failed to load gfx firmware!\n");
4212
4213         return r;
4214 }
4215
4216 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4217 {
4218         int r;
4219         u32 *hpd;
4220         const __le32 *fw_data = NULL;
4221         unsigned fw_size;
4222         u32 *fw = NULL;
4223         size_t mec_hpd_size;
4224
4225         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4226
4227         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4228
4229         /* take ownership of the relevant compute queues */
4230         amdgpu_gfx_compute_queue_acquire(adev);
4231         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4232
4233         if (mec_hpd_size) {
4234                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4235                                               AMDGPU_GEM_DOMAIN_GTT,
4236                                               &adev->gfx.mec.hpd_eop_obj,
4237                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4238                                               (void **)&hpd);
4239                 if (r) {
4240                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4241                         gfx_v10_0_mec_fini(adev);
4242                         return r;
4243                 }
4244
4245                 memset(hpd, 0, mec_hpd_size);
4246
4247                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4248                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4249         }
4250
4251         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4252                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4253
4254                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4255                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4256                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4257
4258                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4259                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4260                                               &adev->gfx.mec.mec_fw_obj,
4261                                               &adev->gfx.mec.mec_fw_gpu_addr,
4262                                               (void **)&fw);
4263                 if (r) {
4264                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4265                         gfx_v10_0_mec_fini(adev);
4266                         return r;
4267                 }
4268
4269                 memcpy(fw, fw_data, fw_size);
4270
4271                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4272                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4273         }
4274
4275         return 0;
4276 }
4277
4278 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4279 {
4280         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4281                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4282                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4283         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4284 }
4285
4286 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4287                            uint32_t thread, uint32_t regno,
4288                            uint32_t num, uint32_t *out)
4289 {
4290         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4291                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4292                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4293                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4294                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4295         while (num--)
4296                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4297 }
4298
4299 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4300 {
4301         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4302          * field when performing a select_se_sh so it should be
4303          * zero here */
4304         WARN_ON(simd != 0);
4305
4306         /* type 2 wave data */
4307         dst[(*no_fields)++] = 2;
4308         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4309         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4310         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4311         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4312         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4313         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4314         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4315         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4316         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4317         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4318         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4319         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4320         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4321         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4322         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4323 }
4324
4325 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4326                                      uint32_t wave, uint32_t start,
4327                                      uint32_t size, uint32_t *dst)
4328 {
4329         WARN_ON(simd != 0);
4330
4331         wave_read_regs(
4332                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4333                 dst);
4334 }
4335
4336 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4337                                       uint32_t wave, uint32_t thread,
4338                                       uint32_t start, uint32_t size,
4339                                       uint32_t *dst)
4340 {
4341         wave_read_regs(
4342                 adev, wave, thread,
4343                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4344 }
4345
4346 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4347                                        u32 me, u32 pipe, u32 q, u32 vm)
4348 {
4349         nv_grbm_select(adev, me, pipe, q, vm);
4350 }
4351
4352 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4353                                           bool enable)
4354 {
4355         uint32_t data, def;
4356
4357         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4358
4359         if (enable)
4360                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4361         else
4362                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4363
4364         if (data != def)
4365                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4366 }
4367
4368 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4369         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4370         .select_se_sh = &gfx_v10_0_select_se_sh,
4371         .read_wave_data = &gfx_v10_0_read_wave_data,
4372         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4373         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4374         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4375         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4376         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4377 };
4378
4379 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4380 {
4381         u32 gb_addr_config;
4382
4383         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4384
4385         switch (adev->asic_type) {
4386         case CHIP_NAVI10:
4387         case CHIP_NAVI14:
4388         case CHIP_NAVI12:
4389                 adev->gfx.config.max_hw_contexts = 8;
4390                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4391                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4392                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4393                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4394                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4395                 break;
4396         case CHIP_SIENNA_CICHLID:
4397         case CHIP_NAVY_FLOUNDER:
4398         case CHIP_VANGOGH:
4399         case CHIP_DIMGREY_CAVEFISH:
4400                 adev->gfx.config.max_hw_contexts = 8;
4401                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4402                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4403                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4404                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4405                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4406                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4407                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4408                 break;
4409         default:
4410                 BUG();
4411                 break;
4412         }
4413
4414         adev->gfx.config.gb_addr_config = gb_addr_config;
4415
4416         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4417                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4418                                       GB_ADDR_CONFIG, NUM_PIPES);
4419
4420         adev->gfx.config.max_tile_pipes =
4421                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4422
4423         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4424                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4425                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4426         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4427                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4428                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4429         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4430                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4431                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4432         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4433                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4434                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4435 }
4436
4437 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4438                                    int me, int pipe, int queue)
4439 {
4440         int r;
4441         struct amdgpu_ring *ring;
4442         unsigned int irq_type;
4443
4444         ring = &adev->gfx.gfx_ring[ring_id];
4445
4446         ring->me = me;
4447         ring->pipe = pipe;
4448         ring->queue = queue;
4449
4450         ring->ring_obj = NULL;
4451         ring->use_doorbell = true;
4452
4453         if (!ring_id)
4454                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4455         else
4456                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4457         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4458
4459         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4460         r = amdgpu_ring_init(adev, ring, 1024,
4461                              &adev->gfx.eop_irq, irq_type,
4462                              AMDGPU_RING_PRIO_DEFAULT);
4463         if (r)
4464                 return r;
4465         return 0;
4466 }
4467
4468 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4469                                        int mec, int pipe, int queue)
4470 {
4471         int r;
4472         unsigned irq_type;
4473         struct amdgpu_ring *ring;
4474         unsigned int hw_prio;
4475
4476         ring = &adev->gfx.compute_ring[ring_id];
4477
4478         /* mec0 is me1 */
4479         ring->me = mec + 1;
4480         ring->pipe = pipe;
4481         ring->queue = queue;
4482
4483         ring->ring_obj = NULL;
4484         ring->use_doorbell = true;
4485         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4486         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4487                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4488         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4489
4490         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4491                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4492                 + ring->pipe;
4493         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
4494                                                             ring->queue) ?
4495                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4496         /* type-2 packets are deprecated on MEC, use type-3 instead */
4497         r = amdgpu_ring_init(adev, ring, 1024,
4498                              &adev->gfx.eop_irq, irq_type, hw_prio);
4499         if (r)
4500                 return r;
4501
4502         return 0;
4503 }
4504
4505 static int gfx_v10_0_sw_init(void *handle)
4506 {
4507         int i, j, k, r, ring_id = 0;
4508         struct amdgpu_kiq *kiq;
4509         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4510
4511         switch (adev->asic_type) {
4512         case CHIP_NAVI10:
4513         case CHIP_NAVI14:
4514         case CHIP_NAVI12:
4515                 adev->gfx.me.num_me = 1;
4516                 adev->gfx.me.num_pipe_per_me = 1;
4517                 adev->gfx.me.num_queue_per_pipe = 1;
4518                 adev->gfx.mec.num_mec = 2;
4519                 adev->gfx.mec.num_pipe_per_mec = 4;
4520                 adev->gfx.mec.num_queue_per_pipe = 8;
4521                 break;
4522         case CHIP_SIENNA_CICHLID:
4523         case CHIP_NAVY_FLOUNDER:
4524         case CHIP_VANGOGH:
4525         case CHIP_DIMGREY_CAVEFISH:
4526                 adev->gfx.me.num_me = 1;
4527                 adev->gfx.me.num_pipe_per_me = 1;
4528                 adev->gfx.me.num_queue_per_pipe = 1;
4529                 adev->gfx.mec.num_mec = 2;
4530                 adev->gfx.mec.num_pipe_per_mec = 4;
4531                 adev->gfx.mec.num_queue_per_pipe = 4;
4532                 break;
4533         default:
4534                 adev->gfx.me.num_me = 1;
4535                 adev->gfx.me.num_pipe_per_me = 1;
4536                 adev->gfx.me.num_queue_per_pipe = 1;
4537                 adev->gfx.mec.num_mec = 1;
4538                 adev->gfx.mec.num_pipe_per_mec = 4;
4539                 adev->gfx.mec.num_queue_per_pipe = 8;
4540                 break;
4541         }
4542
4543         /* KIQ event */
4544         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4545                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4546                               &adev->gfx.kiq.irq);
4547         if (r)
4548                 return r;
4549
4550         /* EOP Event */
4551         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4552                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4553                               &adev->gfx.eop_irq);
4554         if (r)
4555                 return r;
4556
4557         /* Privileged reg */
4558         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4559                               &adev->gfx.priv_reg_irq);
4560         if (r)
4561                 return r;
4562
4563         /* Privileged inst */
4564         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4565                               &adev->gfx.priv_inst_irq);
4566         if (r)
4567                 return r;
4568
4569         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4570
4571         gfx_v10_0_scratch_init(adev);
4572
4573         r = gfx_v10_0_me_init(adev);
4574         if (r)
4575                 return r;
4576
4577         r = gfx_v10_0_rlc_init(adev);
4578         if (r) {
4579                 DRM_ERROR("Failed to init rlc BOs!\n");
4580                 return r;
4581         }
4582
4583         r = gfx_v10_0_mec_init(adev);
4584         if (r) {
4585                 DRM_ERROR("Failed to init MEC BOs!\n");
4586                 return r;
4587         }
4588
4589         /* set up the gfx ring */
4590         for (i = 0; i < adev->gfx.me.num_me; i++) {
4591                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4592                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4593                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4594                                         continue;
4595
4596                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4597                                                             i, k, j);
4598                                 if (r)
4599                                         return r;
4600                                 ring_id++;
4601                         }
4602                 }
4603         }
4604
4605         ring_id = 0;
4606         /* set up the compute queues - allocate horizontally across pipes */
4607         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4608                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4609                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4610                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4611                                                                      j))
4612                                         continue;
4613
4614                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4615                                                                 i, k, j);
4616                                 if (r)
4617                                         return r;
4618
4619                                 ring_id++;
4620                         }
4621                 }
4622         }
4623
4624         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4625         if (r) {
4626                 DRM_ERROR("Failed to init KIQ BOs!\n");
4627                 return r;
4628         }
4629
4630         kiq = &adev->gfx.kiq;
4631         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4632         if (r)
4633                 return r;
4634
4635         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4636         if (r)
4637                 return r;
4638
4639         /* allocate visible FB for rlc auto-loading fw */
4640         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4641                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4642                 if (r)
4643                         return r;
4644         }
4645
4646         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4647
4648         gfx_v10_0_gpu_early_init(adev);
4649
4650         return 0;
4651 }
4652
4653 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4654 {
4655         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4656                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4657                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4658 }
4659
4660 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4661 {
4662         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4663                               &adev->gfx.ce.ce_fw_gpu_addr,
4664                               (void **)&adev->gfx.ce.ce_fw_ptr);
4665 }
4666
4667 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4668 {
4669         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4670                               &adev->gfx.me.me_fw_gpu_addr,
4671                               (void **)&adev->gfx.me.me_fw_ptr);
4672 }
4673
4674 static int gfx_v10_0_sw_fini(void *handle)
4675 {
4676         int i;
4677         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4678
4679         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4680                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4681         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4682                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4683
4684         amdgpu_gfx_mqd_sw_fini(adev);
4685         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4686         amdgpu_gfx_kiq_fini(adev);
4687
4688         gfx_v10_0_pfp_fini(adev);
4689         gfx_v10_0_ce_fini(adev);
4690         gfx_v10_0_me_fini(adev);
4691         gfx_v10_0_rlc_fini(adev);
4692         gfx_v10_0_mec_fini(adev);
4693
4694         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4695                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4696
4697         gfx_v10_0_free_microcode(adev);
4698
4699         return 0;
4700 }
4701
4702 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4703                                    u32 sh_num, u32 instance)
4704 {
4705         u32 data;
4706
4707         if (instance == 0xffffffff)
4708                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4709                                      INSTANCE_BROADCAST_WRITES, 1);
4710         else
4711                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4712                                      instance);
4713
4714         if (se_num == 0xffffffff)
4715                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4716                                      1);
4717         else
4718                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4719
4720         if (sh_num == 0xffffffff)
4721                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4722                                      1);
4723         else
4724                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4725
4726         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4727 }
4728
4729 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4730 {
4731         u32 data, mask;
4732
4733         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4734         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4735
4736         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4737         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4738
4739         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4740                                          adev->gfx.config.max_sh_per_se);
4741
4742         return (~data) & mask;
4743 }
4744
4745 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4746 {
4747         int i, j;
4748         u32 data;
4749         u32 active_rbs = 0;
4750         u32 bitmap;
4751         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4752                                         adev->gfx.config.max_sh_per_se;
4753
4754         mutex_lock(&adev->grbm_idx_mutex);
4755         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4756                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4757                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4758                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4759                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4760                                 continue;
4761                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4762                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4763                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4764                                                rb_bitmap_width_per_sh);
4765                 }
4766         }
4767         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4768         mutex_unlock(&adev->grbm_idx_mutex);
4769
4770         adev->gfx.config.backend_enable_mask = active_rbs;
4771         adev->gfx.config.num_rbs = hweight32(active_rbs);
4772 }
4773
4774 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4775 {
4776         uint32_t num_sc;
4777         uint32_t enabled_rb_per_sh;
4778         uint32_t active_rb_bitmap;
4779         uint32_t num_rb_per_sc;
4780         uint32_t num_packer_per_sc;
4781         uint32_t pa_sc_tile_steering_override;
4782
4783         /* for ASICs that integrates GFX v10.3
4784          * pa_sc_tile_steering_override should be set to 0 */
4785         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4786                 return 0;
4787
4788         /* init num_sc */
4789         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4790                         adev->gfx.config.num_sc_per_sh;
4791         /* init num_rb_per_sc */
4792         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4793         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4794         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4795         /* init num_packer_per_sc */
4796         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4797
4798         pa_sc_tile_steering_override = 0;
4799         pa_sc_tile_steering_override |=
4800                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4801                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4802         pa_sc_tile_steering_override |=
4803                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4804                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4805         pa_sc_tile_steering_override |=
4806                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4807                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4808
4809         return pa_sc_tile_steering_override;
4810 }
4811
4812 #define DEFAULT_SH_MEM_BASES    (0x6000)
4813
4814 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4815 {
4816         int i;
4817         uint32_t sh_mem_bases;
4818
4819         /*
4820          * Configure apertures:
4821          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4822          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4823          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4824          */
4825         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4826
4827         mutex_lock(&adev->srbm_mutex);
4828         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4829                 nv_grbm_select(adev, 0, 0, 0, i);
4830                 /* CP and shaders */
4831                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4832                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4833         }
4834         nv_grbm_select(adev, 0, 0, 0, 0);
4835         mutex_unlock(&adev->srbm_mutex);
4836
4837         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4838            acccess. These should be enabled by FW for target VMIDs. */
4839         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4840                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4841                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4842                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4843                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4844         }
4845 }
4846
4847 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4848 {
4849         int vmid;
4850
4851         /*
4852          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4853          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4854          * the driver can enable them for graphics. VMID0 should maintain
4855          * access so that HWS firmware can save/restore entries.
4856          */
4857         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4858                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4859                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4860                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4861                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4862         }
4863 }
4864
4865
4866 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4867 {
4868         int i, j, k;
4869         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4870         u32 tmp, wgp_active_bitmap = 0;
4871         u32 gcrd_targets_disable_tcp = 0;
4872         u32 utcl_invreq_disable = 0;
4873         /*
4874          * GCRD_TARGETS_DISABLE field contains
4875          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4876          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4877          */
4878         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4879                 2 * max_wgp_per_sh + /* TCP */
4880                 max_wgp_per_sh + /* SQC */
4881                 4); /* GL1C */
4882         /*
4883          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4884          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4885          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4886          */
4887         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4888                 2 * max_wgp_per_sh + /* TCP */
4889                 2 * max_wgp_per_sh + /* SQC */
4890                 4 + /* RMI */
4891                 1); /* SQG */
4892
4893         if (adev->asic_type == CHIP_NAVI10 ||
4894             adev->asic_type == CHIP_NAVI14 ||
4895             adev->asic_type == CHIP_NAVI12) {
4896                 mutex_lock(&adev->grbm_idx_mutex);
4897                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4898                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4899                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4900                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4901                                 /*
4902                                  * Set corresponding TCP bits for the inactive WGPs in
4903                                  * GCRD_SA_TARGETS_DISABLE
4904                                  */
4905                                 gcrd_targets_disable_tcp = 0;
4906                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4907                                 utcl_invreq_disable = 0;
4908
4909                                 for (k = 0; k < max_wgp_per_sh; k++) {
4910                                         if (!(wgp_active_bitmap & (1 << k))) {
4911                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4912                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4913                                                         (3 << (2 * (max_wgp_per_sh + k)));
4914                                         }
4915                                 }
4916
4917                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4918                                 /* only override TCP & SQC bits */
4919                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4920                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4921                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4922
4923                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4924                                 /* only override TCP bits */
4925                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4926                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4927                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4928                         }
4929                 }
4930
4931                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4932                 mutex_unlock(&adev->grbm_idx_mutex);
4933         }
4934 }
4935
4936 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4937 {
4938         /* TCCs are global (not instanced). */
4939         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4940                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4941
4942         adev->gfx.config.tcc_disabled_mask =
4943                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4944                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4945 }
4946
4947 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4948 {
4949         u32 tmp;
4950         int i;
4951
4952         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4953
4954         gfx_v10_0_setup_rb(adev);
4955         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4956         gfx_v10_0_get_tcc_info(adev);
4957         adev->gfx.config.pa_sc_tile_steering_override =
4958                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4959
4960         /* XXX SH_MEM regs */
4961         /* where to put LDS, scratch, GPUVM in FSA64 space */
4962         mutex_lock(&adev->srbm_mutex);
4963         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4964                 nv_grbm_select(adev, 0, 0, 0, i);
4965                 /* CP and shaders */
4966                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4967                 if (i != 0) {
4968                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4969                                 (adev->gmc.private_aperture_start >> 48));
4970                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4971                                 (adev->gmc.shared_aperture_start >> 48));
4972                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4973                 }
4974         }
4975         nv_grbm_select(adev, 0, 0, 0, 0);
4976
4977         mutex_unlock(&adev->srbm_mutex);
4978
4979         gfx_v10_0_init_compute_vmid(adev);
4980         gfx_v10_0_init_gds_vmid(adev);
4981
4982 }
4983
4984 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4985                                                bool enable)
4986 {
4987         u32 tmp;
4988
4989         if (amdgpu_sriov_vf(adev))
4990                 return;
4991
4992         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4993
4994         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4995                             enable ? 1 : 0);
4996         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4997                             enable ? 1 : 0);
4998         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4999                             enable ? 1 : 0);
5000         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5001                             enable ? 1 : 0);
5002
5003         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5004 }
5005
5006 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5007 {
5008         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5009
5010         /* csib */
5011         if (adev->asic_type == CHIP_NAVI12) {
5012                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5013                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5014                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5015                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5016                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5017         } else {
5018                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5019                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5020                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5021                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5022                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5023         }
5024         return 0;
5025 }
5026
5027 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5028 {
5029         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5030
5031         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5032         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5033 }
5034
5035 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5036 {
5037         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5038         udelay(50);
5039         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5040         udelay(50);
5041 }
5042
5043 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5044                                              bool enable)
5045 {
5046         uint32_t rlc_pg_cntl;
5047
5048         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5049
5050         if (!enable) {
5051                 /* RLC_PG_CNTL[23] = 0 (default)
5052                  * RLC will wait for handshake acks with SMU
5053                  * GFXOFF will be enabled
5054                  * RLC_PG_CNTL[23] = 1
5055                  * RLC will not issue any message to SMU
5056                  * hence no handshake between SMU & RLC
5057                  * GFXOFF will be disabled
5058                  */
5059                 rlc_pg_cntl |= 0x800000;
5060         } else
5061                 rlc_pg_cntl &= ~0x800000;
5062         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5063 }
5064
5065 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5066 {
5067         /* TODO: enable rlc & smu handshake until smu
5068          * and gfxoff feature works as expected */
5069         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5070                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5071
5072         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5073         udelay(50);
5074 }
5075
5076 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5077 {
5078         uint32_t tmp;
5079
5080         /* enable Save Restore Machine */
5081         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5082         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5083         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5084         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5085 }
5086
5087 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5088 {
5089         const struct rlc_firmware_header_v2_0 *hdr;
5090         const __le32 *fw_data;
5091         unsigned i, fw_size;
5092
5093         if (!adev->gfx.rlc_fw)
5094                 return -EINVAL;
5095
5096         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5097         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5098
5099         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5100                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5101         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5102
5103         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5104                      RLCG_UCODE_LOADING_START_ADDRESS);
5105
5106         for (i = 0; i < fw_size; i++)
5107                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5108                              le32_to_cpup(fw_data++));
5109
5110         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5111
5112         return 0;
5113 }
5114
5115 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5116 {
5117         int r;
5118
5119         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5120
5121                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5122                 if (r)
5123                         return r;
5124
5125                 gfx_v10_0_init_csb(adev);
5126
5127                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5128                         gfx_v10_0_rlc_enable_srm(adev);
5129         } else {
5130                 if (amdgpu_sriov_vf(adev)) {
5131                         gfx_v10_0_init_csb(adev);
5132                         return 0;
5133                 }
5134
5135                 adev->gfx.rlc.funcs->stop(adev);
5136
5137                 /* disable CG */
5138                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5139
5140                 /* disable PG */
5141                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5142
5143                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5144                         /* legacy rlc firmware loading */
5145                         r = gfx_v10_0_rlc_load_microcode(adev);
5146                         if (r)
5147                                 return r;
5148                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5149                         /* rlc backdoor autoload firmware */
5150                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5151                         if (r)
5152                                 return r;
5153                 }
5154
5155                 gfx_v10_0_init_csb(adev);
5156
5157                 adev->gfx.rlc.funcs->start(adev);
5158
5159                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5160                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5161                         if (r)
5162                                 return r;
5163                 }
5164         }
5165         return 0;
5166 }
5167
5168 static struct {
5169         FIRMWARE_ID     id;
5170         unsigned int    offset;
5171         unsigned int    size;
5172 } rlc_autoload_info[FIRMWARE_ID_MAX];
5173
5174 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5175 {
5176         int ret;
5177         RLC_TABLE_OF_CONTENT *rlc_toc;
5178
5179         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5180                                         AMDGPU_GEM_DOMAIN_GTT,
5181                                         &adev->gfx.rlc.rlc_toc_bo,
5182                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5183                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5184         if (ret) {
5185                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5186                 return ret;
5187         }
5188
5189         /* Copy toc from psp sos fw to rlc toc buffer */
5190         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5191
5192         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5193         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5194                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5195                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5196                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5197                         /* Offset needs 4KB alignment */
5198                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5199                 }
5200
5201                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5202                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5203                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5204
5205                 rlc_toc++;
5206         }
5207
5208         return 0;
5209 }
5210
5211 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5212 {
5213         uint32_t total_size = 0;
5214         FIRMWARE_ID id;
5215         int ret;
5216
5217         ret = gfx_v10_0_parse_rlc_toc(adev);
5218         if (ret) {
5219                 dev_err(adev->dev, "failed to parse rlc toc\n");
5220                 return 0;
5221         }
5222
5223         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5224                 total_size += rlc_autoload_info[id].size;
5225
5226         /* In case the offset in rlc toc ucode is aligned */
5227         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5228                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5229                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5230
5231         return total_size;
5232 }
5233
5234 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5235 {
5236         int r;
5237         uint32_t total_size;
5238
5239         total_size = gfx_v10_0_calc_toc_total_size(adev);
5240
5241         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5242                                       AMDGPU_GEM_DOMAIN_GTT,
5243                                       &adev->gfx.rlc.rlc_autoload_bo,
5244                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5245                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5246         if (r) {
5247                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5248                 return r;
5249         }
5250
5251         return 0;
5252 }
5253
5254 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5255 {
5256         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5257                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5258                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5259         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5260                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5261                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5262 }
5263
5264 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5265                                                        FIRMWARE_ID id,
5266                                                        const void *fw_data,
5267                                                        uint32_t fw_size)
5268 {
5269         uint32_t toc_offset;
5270         uint32_t toc_fw_size;
5271         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5272
5273         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5274                 return;
5275
5276         toc_offset = rlc_autoload_info[id].offset;
5277         toc_fw_size = rlc_autoload_info[id].size;
5278
5279         if (fw_size == 0)
5280                 fw_size = toc_fw_size;
5281
5282         if (fw_size > toc_fw_size)
5283                 fw_size = toc_fw_size;
5284
5285         memcpy(ptr + toc_offset, fw_data, fw_size);
5286
5287         if (fw_size < toc_fw_size)
5288                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5289 }
5290
5291 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5292 {
5293         void *data;
5294         uint32_t size;
5295
5296         data = adev->gfx.rlc.rlc_toc_buf;
5297         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5298
5299         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5300                                                    FIRMWARE_ID_RLC_TOC,
5301                                                    data, size);
5302 }
5303
5304 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5305 {
5306         const __le32 *fw_data;
5307         uint32_t fw_size;
5308         const struct gfx_firmware_header_v1_0 *cp_hdr;
5309         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5310
5311         /* pfp ucode */
5312         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5313                 adev->gfx.pfp_fw->data;
5314         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5315                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5316         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5317         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5318                                                    FIRMWARE_ID_CP_PFP,
5319                                                    fw_data, fw_size);
5320
5321         /* ce ucode */
5322         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5323                 adev->gfx.ce_fw->data;
5324         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5325                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5326         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5327         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5328                                                    FIRMWARE_ID_CP_CE,
5329                                                    fw_data, fw_size);
5330
5331         /* me ucode */
5332         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5333                 adev->gfx.me_fw->data;
5334         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5335                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5336         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5337         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5338                                                    FIRMWARE_ID_CP_ME,
5339                                                    fw_data, fw_size);
5340
5341         /* rlc ucode */
5342         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5343                 adev->gfx.rlc_fw->data;
5344         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5345                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5346         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5347         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5348                                                    FIRMWARE_ID_RLC_G_UCODE,
5349                                                    fw_data, fw_size);
5350
5351         /* mec1 ucode */
5352         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5353                 adev->gfx.mec_fw->data;
5354         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5355                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5356         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5357                 cp_hdr->jt_size * 4;
5358         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5359                                                    FIRMWARE_ID_CP_MEC,
5360                                                    fw_data, fw_size);
5361         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5362 }
5363
5364 /* Temporarily put sdma part here */
5365 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5366 {
5367         const __le32 *fw_data;
5368         uint32_t fw_size;
5369         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5370         int i;
5371
5372         for (i = 0; i < adev->sdma.num_instances; i++) {
5373                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5374                         adev->sdma.instance[i].fw->data;
5375                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5376                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5377                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5378
5379                 if (i == 0) {
5380                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5381                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5382                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5383                                 FIRMWARE_ID_SDMA0_JT,
5384                                 (uint32_t *)fw_data +
5385                                 sdma_hdr->jt_offset,
5386                                 sdma_hdr->jt_size * 4);
5387                 } else if (i == 1) {
5388                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5389                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5390                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5391                                 FIRMWARE_ID_SDMA1_JT,
5392                                 (uint32_t *)fw_data +
5393                                 sdma_hdr->jt_offset,
5394                                 sdma_hdr->jt_size * 4);
5395                 }
5396         }
5397 }
5398
5399 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5400 {
5401         uint32_t rlc_g_offset, rlc_g_size, tmp;
5402         uint64_t gpu_addr;
5403
5404         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5405         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5406         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5407
5408         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5409         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5410         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5411
5412         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5413         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5414         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5415
5416         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5417         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5418                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5419                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5420                 return -EINVAL;
5421         }
5422
5423         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5424         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5425                 DRM_ERROR("RLC ROM should halt itself\n");
5426                 return -EINVAL;
5427         }
5428
5429         return 0;
5430 }
5431
5432 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5433 {
5434         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5435         uint32_t tmp;
5436         int i;
5437         uint64_t addr;
5438
5439         /* Trigger an invalidation of the L1 instruction caches */
5440         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5441         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5442         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5443
5444         /* Wait for invalidation complete */
5445         for (i = 0; i < usec_timeout; i++) {
5446                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5447                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5448                         INVALIDATE_CACHE_COMPLETE))
5449                         break;
5450                 udelay(1);
5451         }
5452
5453         if (i >= usec_timeout) {
5454                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5455                 return -EINVAL;
5456         }
5457
5458         /* Program me ucode address into intruction cache address register */
5459         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5460                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5461         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5462                         lower_32_bits(addr) & 0xFFFFF000);
5463         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5464                         upper_32_bits(addr));
5465
5466         return 0;
5467 }
5468
5469 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5470 {
5471         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5472         uint32_t tmp;
5473         int i;
5474         uint64_t addr;
5475
5476         /* Trigger an invalidation of the L1 instruction caches */
5477         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5478         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5479         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5480
5481         /* Wait for invalidation complete */
5482         for (i = 0; i < usec_timeout; i++) {
5483                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5484                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5485                         INVALIDATE_CACHE_COMPLETE))
5486                         break;
5487                 udelay(1);
5488         }
5489
5490         if (i >= usec_timeout) {
5491                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5492                 return -EINVAL;
5493         }
5494
5495         /* Program ce ucode address into intruction cache address register */
5496         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5497                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5498         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5499                         lower_32_bits(addr) & 0xFFFFF000);
5500         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5501                         upper_32_bits(addr));
5502
5503         return 0;
5504 }
5505
5506 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5507 {
5508         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5509         uint32_t tmp;
5510         int i;
5511         uint64_t addr;
5512
5513         /* Trigger an invalidation of the L1 instruction caches */
5514         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5515         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5516         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5517
5518         /* Wait for invalidation complete */
5519         for (i = 0; i < usec_timeout; i++) {
5520                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5521                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5522                         INVALIDATE_CACHE_COMPLETE))
5523                         break;
5524                 udelay(1);
5525         }
5526
5527         if (i >= usec_timeout) {
5528                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5529                 return -EINVAL;
5530         }
5531
5532         /* Program pfp ucode address into intruction cache address register */
5533         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5534                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5535         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5536                         lower_32_bits(addr) & 0xFFFFF000);
5537         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5538                         upper_32_bits(addr));
5539
5540         return 0;
5541 }
5542
5543 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5544 {
5545         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5546         uint32_t tmp;
5547         int i;
5548         uint64_t addr;
5549
5550         /* Trigger an invalidation of the L1 instruction caches */
5551         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5552         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5553         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5554
5555         /* Wait for invalidation complete */
5556         for (i = 0; i < usec_timeout; i++) {
5557                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5558                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5559                         INVALIDATE_CACHE_COMPLETE))
5560                         break;
5561                 udelay(1);
5562         }
5563
5564         if (i >= usec_timeout) {
5565                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5566                 return -EINVAL;
5567         }
5568
5569         /* Program mec1 ucode address into intruction cache address register */
5570         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5571                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5572         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5573                         lower_32_bits(addr) & 0xFFFFF000);
5574         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5575                         upper_32_bits(addr));
5576
5577         return 0;
5578 }
5579
5580 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5581 {
5582         uint32_t cp_status;
5583         uint32_t bootload_status;
5584         int i, r;
5585
5586         for (i = 0; i < adev->usec_timeout; i++) {
5587                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5588                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5589                 if ((cp_status == 0) &&
5590                     (REG_GET_FIELD(bootload_status,
5591                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5592                         break;
5593                 }
5594                 udelay(1);
5595         }
5596
5597         if (i >= adev->usec_timeout) {
5598                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5599                 return -ETIMEDOUT;
5600         }
5601
5602         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5603                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5604                 if (r)
5605                         return r;
5606
5607                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5608                 if (r)
5609                         return r;
5610
5611                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5612                 if (r)
5613                         return r;
5614
5615                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5616                 if (r)
5617                         return r;
5618         }
5619
5620         return 0;
5621 }
5622
5623 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5624 {
5625         int i;
5626         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5627
5628         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5629         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5630         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5631
5632         if (adev->asic_type == CHIP_NAVI12) {
5633                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5634         } else {
5635                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5636         }
5637
5638         for (i = 0; i < adev->usec_timeout; i++) {
5639                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5640                         break;
5641                 udelay(1);
5642         }
5643
5644         if (i >= adev->usec_timeout)
5645                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5646
5647         return 0;
5648 }
5649
5650 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5651 {
5652         int r;
5653         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5654         const __le32 *fw_data;
5655         unsigned i, fw_size;
5656         uint32_t tmp;
5657         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5658
5659         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5660                 adev->gfx.pfp_fw->data;
5661
5662         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5663
5664         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5665                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5666         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5667
5668         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5669                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5670                                       &adev->gfx.pfp.pfp_fw_obj,
5671                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5672                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5673         if (r) {
5674                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5675                 gfx_v10_0_pfp_fini(adev);
5676                 return r;
5677         }
5678
5679         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5680
5681         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5682         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5683
5684         /* Trigger an invalidation of the L1 instruction caches */
5685         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5686         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5687         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5688
5689         /* Wait for invalidation complete */
5690         for (i = 0; i < usec_timeout; i++) {
5691                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5692                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5693                         INVALIDATE_CACHE_COMPLETE))
5694                         break;
5695                 udelay(1);
5696         }
5697
5698         if (i >= usec_timeout) {
5699                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5700                 return -EINVAL;
5701         }
5702
5703         if (amdgpu_emu_mode == 1)
5704                 adev->nbio.funcs->hdp_flush(adev, NULL);
5705
5706         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5707         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5708         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5709         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5710         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5711         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5712         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5713                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5714         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5715                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5716
5717         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5718
5719         for (i = 0; i < pfp_hdr->jt_size; i++)
5720                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5721                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5722
5723         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5724
5725         return 0;
5726 }
5727
5728 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5729 {
5730         int r;
5731         const struct gfx_firmware_header_v1_0 *ce_hdr;
5732         const __le32 *fw_data;
5733         unsigned i, fw_size;
5734         uint32_t tmp;
5735         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5736
5737         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5738                 adev->gfx.ce_fw->data;
5739
5740         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5741
5742         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5743                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5744         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5745
5746         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5747                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5748                                       &adev->gfx.ce.ce_fw_obj,
5749                                       &adev->gfx.ce.ce_fw_gpu_addr,
5750                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5751         if (r) {
5752                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5753                 gfx_v10_0_ce_fini(adev);
5754                 return r;
5755         }
5756
5757         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5758
5759         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5760         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5761
5762         /* Trigger an invalidation of the L1 instruction caches */
5763         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5764         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5765         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5766
5767         /* Wait for invalidation complete */
5768         for (i = 0; i < usec_timeout; i++) {
5769                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5770                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5771                         INVALIDATE_CACHE_COMPLETE))
5772                         break;
5773                 udelay(1);
5774         }
5775
5776         if (i >= usec_timeout) {
5777                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5778                 return -EINVAL;
5779         }
5780
5781         if (amdgpu_emu_mode == 1)
5782                 adev->nbio.funcs->hdp_flush(adev, NULL);
5783
5784         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5785         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5786         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5787         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5788         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5789         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5790                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5791         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5792                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5793
5794         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5795
5796         for (i = 0; i < ce_hdr->jt_size; i++)
5797                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5798                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5799
5800         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5801
5802         return 0;
5803 }
5804
5805 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5806 {
5807         int r;
5808         const struct gfx_firmware_header_v1_0 *me_hdr;
5809         const __le32 *fw_data;
5810         unsigned i, fw_size;
5811         uint32_t tmp;
5812         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5813
5814         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5815                 adev->gfx.me_fw->data;
5816
5817         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5818
5819         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5820                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5821         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5822
5823         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5824                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5825                                       &adev->gfx.me.me_fw_obj,
5826                                       &adev->gfx.me.me_fw_gpu_addr,
5827                                       (void **)&adev->gfx.me.me_fw_ptr);
5828         if (r) {
5829                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5830                 gfx_v10_0_me_fini(adev);
5831                 return r;
5832         }
5833
5834         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5835
5836         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5837         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5838
5839         /* Trigger an invalidation of the L1 instruction caches */
5840         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5841         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5842         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5843
5844         /* Wait for invalidation complete */
5845         for (i = 0; i < usec_timeout; i++) {
5846                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5847                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5848                         INVALIDATE_CACHE_COMPLETE))
5849                         break;
5850                 udelay(1);
5851         }
5852
5853         if (i >= usec_timeout) {
5854                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5855                 return -EINVAL;
5856         }
5857
5858         if (amdgpu_emu_mode == 1)
5859                 adev->nbio.funcs->hdp_flush(adev, NULL);
5860
5861         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5862         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5863         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5864         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5865         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5866         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5867                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5868         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5869                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5870
5871         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5872
5873         for (i = 0; i < me_hdr->jt_size; i++)
5874                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5875                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5876
5877         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5878
5879         return 0;
5880 }
5881
5882 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5883 {
5884         int r;
5885
5886         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5887                 return -EINVAL;
5888
5889         gfx_v10_0_cp_gfx_enable(adev, false);
5890
5891         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5892         if (r) {
5893                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5894                 return r;
5895         }
5896
5897         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5898         if (r) {
5899                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5900                 return r;
5901         }
5902
5903         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5904         if (r) {
5905                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5906                 return r;
5907         }
5908
5909         return 0;
5910 }
5911
5912 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5913 {
5914         struct amdgpu_ring *ring;
5915         const struct cs_section_def *sect = NULL;
5916         const struct cs_extent_def *ext = NULL;
5917         int r, i;
5918         int ctx_reg_offset;
5919
5920         /* init the CP */
5921         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5922                      adev->gfx.config.max_hw_contexts - 1);
5923         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5924
5925         gfx_v10_0_cp_gfx_enable(adev, true);
5926
5927         ring = &adev->gfx.gfx_ring[0];
5928         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5929         if (r) {
5930                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5931                 return r;
5932         }
5933
5934         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5935         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5936
5937         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5938         amdgpu_ring_write(ring, 0x80000000);
5939         amdgpu_ring_write(ring, 0x80000000);
5940
5941         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5942                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5943                         if (sect->id == SECT_CONTEXT) {
5944                                 amdgpu_ring_write(ring,
5945                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5946                                                           ext->reg_count));
5947                                 amdgpu_ring_write(ring, ext->reg_index -
5948                                                   PACKET3_SET_CONTEXT_REG_START);
5949                                 for (i = 0; i < ext->reg_count; i++)
5950                                         amdgpu_ring_write(ring, ext->extent[i]);
5951                         }
5952                 }
5953         }
5954
5955         ctx_reg_offset =
5956                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5957         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5958         amdgpu_ring_write(ring, ctx_reg_offset);
5959         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5960
5961         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5962         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5963
5964         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5965         amdgpu_ring_write(ring, 0);
5966
5967         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5968         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5969         amdgpu_ring_write(ring, 0x8000);
5970         amdgpu_ring_write(ring, 0x8000);
5971
5972         amdgpu_ring_commit(ring);
5973
5974         /* submit cs packet to copy state 0 to next available state */
5975         if (adev->gfx.num_gfx_rings > 1) {
5976                 /* maximum supported gfx ring is 2 */
5977                 ring = &adev->gfx.gfx_ring[1];
5978                 r = amdgpu_ring_alloc(ring, 2);
5979                 if (r) {
5980                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5981                         return r;
5982                 }
5983
5984                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5985                 amdgpu_ring_write(ring, 0);
5986
5987                 amdgpu_ring_commit(ring);
5988         }
5989         return 0;
5990 }
5991
5992 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5993                                          CP_PIPE_ID pipe)
5994 {
5995         u32 tmp;
5996
5997         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5998         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5999
6000         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6001 }
6002
6003 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6004                                           struct amdgpu_ring *ring)
6005 {
6006         u32 tmp;
6007
6008         if (!amdgpu_async_gfx_ring) {
6009                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6010                 if (ring->use_doorbell) {
6011                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6012                                                 DOORBELL_OFFSET, ring->doorbell_index);
6013                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6014                                                 DOORBELL_EN, 1);
6015                 } else {
6016                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6017                                                 DOORBELL_EN, 0);
6018                 }
6019                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6020         }
6021         switch (adev->asic_type) {
6022         case CHIP_SIENNA_CICHLID:
6023         case CHIP_NAVY_FLOUNDER:
6024         case CHIP_VANGOGH:
6025         case CHIP_DIMGREY_CAVEFISH:
6026                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6027                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6028                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6029
6030                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6031                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6032                 break;
6033         default:
6034                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6035                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6036                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6037
6038                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6039                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6040                 break;
6041         }
6042 }
6043
6044 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6045 {
6046         struct amdgpu_ring *ring;
6047         u32 tmp;
6048         u32 rb_bufsz;
6049         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6050         u32 i;
6051
6052         /* Set the write pointer delay */
6053         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6054
6055         /* set the RB to use vmid 0 */
6056         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6057
6058         /* Init gfx ring 0 for pipe 0 */
6059         mutex_lock(&adev->srbm_mutex);
6060         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6061
6062         /* Set ring buffer size */
6063         ring = &adev->gfx.gfx_ring[0];
6064         rb_bufsz = order_base_2(ring->ring_size / 8);
6065         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6066         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6067 #ifdef __BIG_ENDIAN
6068         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6069 #endif
6070         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6071
6072         /* Initialize the ring buffer's write pointers */
6073         ring->wptr = 0;
6074         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6075         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6076
6077         /* set the wb address wether it's enabled or not */
6078         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6079         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6080         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6081                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6082
6083         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6084         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6085                      lower_32_bits(wptr_gpu_addr));
6086         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6087                      upper_32_bits(wptr_gpu_addr));
6088
6089         mdelay(1);
6090         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6091
6092         rb_addr = ring->gpu_addr >> 8;
6093         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6094         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6095
6096         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6097
6098         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6099         mutex_unlock(&adev->srbm_mutex);
6100
6101         /* Init gfx ring 1 for pipe 1 */
6102         if (adev->gfx.num_gfx_rings > 1) {
6103                 mutex_lock(&adev->srbm_mutex);
6104                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6105                 /* maximum supported gfx ring is 2 */
6106                 ring = &adev->gfx.gfx_ring[1];
6107                 rb_bufsz = order_base_2(ring->ring_size / 8);
6108                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6109                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6110                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6111                 /* Initialize the ring buffer's write pointers */
6112                 ring->wptr = 0;
6113                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6114                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6115                 /* Set the wb address wether it's enabled or not */
6116                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6117                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6118                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6119                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6120                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6121                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6122                              lower_32_bits(wptr_gpu_addr));
6123                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6124                              upper_32_bits(wptr_gpu_addr));
6125
6126                 mdelay(1);
6127                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6128
6129                 rb_addr = ring->gpu_addr >> 8;
6130                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6131                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6132                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6133
6134                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6135                 mutex_unlock(&adev->srbm_mutex);
6136         }
6137         /* Switch to pipe 0 */
6138         mutex_lock(&adev->srbm_mutex);
6139         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6140         mutex_unlock(&adev->srbm_mutex);
6141
6142         /* start the ring */
6143         gfx_v10_0_cp_gfx_start(adev);
6144
6145         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6146                 ring = &adev->gfx.gfx_ring[i];
6147                 ring->sched.ready = true;
6148         }
6149
6150         return 0;
6151 }
6152
6153 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6154 {
6155         if (enable) {
6156                 switch (adev->asic_type) {
6157                 case CHIP_SIENNA_CICHLID:
6158                 case CHIP_NAVY_FLOUNDER:
6159                 case CHIP_VANGOGH:
6160                 case CHIP_DIMGREY_CAVEFISH:
6161                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6162                         break;
6163                 default:
6164                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6165                         break;
6166                 }
6167         } else {
6168                 switch (adev->asic_type) {
6169                 case CHIP_SIENNA_CICHLID:
6170                 case CHIP_NAVY_FLOUNDER:
6171                 case CHIP_VANGOGH:
6172                 case CHIP_DIMGREY_CAVEFISH:
6173                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6174                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6175                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6176                         break;
6177                 default:
6178                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6179                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6180                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6181                         break;
6182                 }
6183                 adev->gfx.kiq.ring.sched.ready = false;
6184         }
6185         udelay(50);
6186 }
6187
6188 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6189 {
6190         const struct gfx_firmware_header_v1_0 *mec_hdr;
6191         const __le32 *fw_data;
6192         unsigned i;
6193         u32 tmp;
6194         u32 usec_timeout = 50000; /* Wait for 50 ms */
6195
6196         if (!adev->gfx.mec_fw)
6197                 return -EINVAL;
6198
6199         gfx_v10_0_cp_compute_enable(adev, false);
6200
6201         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6202         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6203
6204         fw_data = (const __le32 *)
6205                 (adev->gfx.mec_fw->data +
6206                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6207
6208         /* Trigger an invalidation of the L1 instruction caches */
6209         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6210         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6211         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6212
6213         /* Wait for invalidation complete */
6214         for (i = 0; i < usec_timeout; i++) {
6215                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6216                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6217                                        INVALIDATE_CACHE_COMPLETE))
6218                         break;
6219                 udelay(1);
6220         }
6221
6222         if (i >= usec_timeout) {
6223                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6224                 return -EINVAL;
6225         }
6226
6227         if (amdgpu_emu_mode == 1)
6228                 adev->nbio.funcs->hdp_flush(adev, NULL);
6229
6230         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6231         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6232         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6233         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6234         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6235
6236         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6237                      0xFFFFF000);
6238         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6239                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6240
6241         /* MEC1 */
6242         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6243
6244         for (i = 0; i < mec_hdr->jt_size; i++)
6245                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6246                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6247
6248         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6249
6250         /*
6251          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6252          * different microcode than MEC1.
6253          */
6254
6255         return 0;
6256 }
6257
6258 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6259 {
6260         uint32_t tmp;
6261         struct amdgpu_device *adev = ring->adev;
6262
6263         /* tell RLC which is KIQ queue */
6264         switch (adev->asic_type) {
6265         case CHIP_SIENNA_CICHLID:
6266         case CHIP_NAVY_FLOUNDER:
6267         case CHIP_VANGOGH:
6268         case CHIP_DIMGREY_CAVEFISH:
6269                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6270                 tmp &= 0xffffff00;
6271                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6272                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6273                 tmp |= 0x80;
6274                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6275                 break;
6276         default:
6277                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6278                 tmp &= 0xffffff00;
6279                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6280                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6281                 tmp |= 0x80;
6282                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6283                 break;
6284         }
6285 }
6286
6287 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6288 {
6289         struct amdgpu_device *adev = ring->adev;
6290         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6291         uint64_t hqd_gpu_addr, wb_gpu_addr;
6292         uint32_t tmp;
6293         uint32_t rb_bufsz;
6294
6295         /* set up gfx hqd wptr */
6296         mqd->cp_gfx_hqd_wptr = 0;
6297         mqd->cp_gfx_hqd_wptr_hi = 0;
6298
6299         /* set the pointer to the MQD */
6300         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6301         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6302
6303         /* set up mqd control */
6304         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6305         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6306         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6307         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6308         mqd->cp_gfx_mqd_control = tmp;
6309
6310         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6311         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6312         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6313         mqd->cp_gfx_hqd_vmid = 0;
6314
6315         /* set up default queue priority level
6316          * 0x0 = low priority, 0x1 = high priority */
6317         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6318         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6319         mqd->cp_gfx_hqd_queue_priority = tmp;
6320
6321         /* set up time quantum */
6322         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6323         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6324         mqd->cp_gfx_hqd_quantum = tmp;
6325
6326         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6327         hqd_gpu_addr = ring->gpu_addr >> 8;
6328         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6329         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6330
6331         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6332         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6333         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6334         mqd->cp_gfx_hqd_rptr_addr_hi =
6335                 upper_32_bits(wb_gpu_addr) & 0xffff;
6336
6337         /* set up rb_wptr_poll addr */
6338         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6339         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6340         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6341
6342         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6343         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6344         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6345         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6346         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6347 #ifdef __BIG_ENDIAN
6348         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6349 #endif
6350         mqd->cp_gfx_hqd_cntl = tmp;
6351
6352         /* set up cp_doorbell_control */
6353         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6354         if (ring->use_doorbell) {
6355                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6356                                     DOORBELL_OFFSET, ring->doorbell_index);
6357                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6358                                     DOORBELL_EN, 1);
6359         } else
6360                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6361                                     DOORBELL_EN, 0);
6362         mqd->cp_rb_doorbell_control = tmp;
6363
6364         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6365          *otherwise the range of the second ring will override the first ring */
6366         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6367                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6368
6369         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6370         ring->wptr = 0;
6371         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6372
6373         /* active the queue */
6374         mqd->cp_gfx_hqd_active = 1;
6375
6376         return 0;
6377 }
6378
6379 #ifdef BRING_UP_DEBUG
6380 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6381 {
6382         struct amdgpu_device *adev = ring->adev;
6383         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6384
6385         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6386         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6387         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6388
6389         /* set GFX_MQD_BASE */
6390         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6391         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6392
6393         /* set GFX_MQD_CONTROL */
6394         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6395
6396         /* set GFX_HQD_VMID to 0 */
6397         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6398
6399         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6400                         mqd->cp_gfx_hqd_queue_priority);
6401         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6402
6403         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6404         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6405         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6406
6407         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6408         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6409         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6410
6411         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6412         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6413
6414         /* set RB_WPTR_POLL_ADDR */
6415         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6416         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6417
6418         /* set RB_DOORBELL_CONTROL */
6419         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6420
6421         /* active the queue */
6422         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6423
6424         return 0;
6425 }
6426 #endif
6427
6428 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6429 {
6430         struct amdgpu_device *adev = ring->adev;
6431         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6432         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6433
6434         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6435                 memset((void *)mqd, 0, sizeof(*mqd));
6436                 mutex_lock(&adev->srbm_mutex);
6437                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6438                 gfx_v10_0_gfx_mqd_init(ring);
6439 #ifdef BRING_UP_DEBUG
6440                 gfx_v10_0_gfx_queue_init_register(ring);
6441 #endif
6442                 nv_grbm_select(adev, 0, 0, 0, 0);
6443                 mutex_unlock(&adev->srbm_mutex);
6444                 if (adev->gfx.me.mqd_backup[mqd_idx])
6445                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6446         } else if (amdgpu_in_reset(adev)) {
6447                 /* reset mqd with the backup copy */
6448                 if (adev->gfx.me.mqd_backup[mqd_idx])
6449                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6450                 /* reset the ring */
6451                 ring->wptr = 0;
6452                 adev->wb.wb[ring->wptr_offs] = 0;
6453                 amdgpu_ring_clear_ring(ring);
6454 #ifdef BRING_UP_DEBUG
6455                 mutex_lock(&adev->srbm_mutex);
6456                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6457                 gfx_v10_0_gfx_queue_init_register(ring);
6458                 nv_grbm_select(adev, 0, 0, 0, 0);
6459                 mutex_unlock(&adev->srbm_mutex);
6460 #endif
6461         } else {
6462                 amdgpu_ring_clear_ring(ring);
6463         }
6464
6465         return 0;
6466 }
6467
6468 #ifndef BRING_UP_DEBUG
6469 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6470 {
6471         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6472         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6473         int r, i;
6474
6475         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6476                 return -EINVAL;
6477
6478         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6479                                         adev->gfx.num_gfx_rings);
6480         if (r) {
6481                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6482                 return r;
6483         }
6484
6485         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6486                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6487
6488         return amdgpu_ring_test_helper(kiq_ring);
6489 }
6490 #endif
6491
6492 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6493 {
6494         int r, i;
6495         struct amdgpu_ring *ring;
6496
6497         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6498                 ring = &adev->gfx.gfx_ring[i];
6499
6500                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6501                 if (unlikely(r != 0))
6502                         goto done;
6503
6504                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6505                 if (!r) {
6506                         r = gfx_v10_0_gfx_init_queue(ring);
6507                         amdgpu_bo_kunmap(ring->mqd_obj);
6508                         ring->mqd_ptr = NULL;
6509                 }
6510                 amdgpu_bo_unreserve(ring->mqd_obj);
6511                 if (r)
6512                         goto done;
6513         }
6514 #ifndef BRING_UP_DEBUG
6515         r = gfx_v10_0_kiq_enable_kgq(adev);
6516         if (r)
6517                 goto done;
6518 #endif
6519         r = gfx_v10_0_cp_gfx_start(adev);
6520         if (r)
6521                 goto done;
6522
6523         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6524                 ring = &adev->gfx.gfx_ring[i];
6525                 ring->sched.ready = true;
6526         }
6527 done:
6528         return r;
6529 }
6530
6531 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6532 {
6533         struct amdgpu_device *adev = ring->adev;
6534
6535         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6536                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
6537                                                               ring->queue)) {
6538                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6539                         mqd->cp_hqd_queue_priority =
6540                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6541                 }
6542         }
6543 }
6544
6545 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6546 {
6547         struct amdgpu_device *adev = ring->adev;
6548         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6549         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6550         uint32_t tmp;
6551
6552         mqd->header = 0xC0310800;
6553         mqd->compute_pipelinestat_enable = 0x00000001;
6554         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6555         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6556         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6557         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6558         mqd->compute_misc_reserved = 0x00000003;
6559
6560         eop_base_addr = ring->eop_gpu_addr >> 8;
6561         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6562         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6563
6564         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6565         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6566         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6567                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6568
6569         mqd->cp_hqd_eop_control = tmp;
6570
6571         /* enable doorbell? */
6572         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6573
6574         if (ring->use_doorbell) {
6575                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6576                                     DOORBELL_OFFSET, ring->doorbell_index);
6577                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6578                                     DOORBELL_EN, 1);
6579                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6580                                     DOORBELL_SOURCE, 0);
6581                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6582                                     DOORBELL_HIT, 0);
6583         } else {
6584                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6585                                     DOORBELL_EN, 0);
6586         }
6587
6588         mqd->cp_hqd_pq_doorbell_control = tmp;
6589
6590         /* disable the queue if it's active */
6591         ring->wptr = 0;
6592         mqd->cp_hqd_dequeue_request = 0;
6593         mqd->cp_hqd_pq_rptr = 0;
6594         mqd->cp_hqd_pq_wptr_lo = 0;
6595         mqd->cp_hqd_pq_wptr_hi = 0;
6596
6597         /* set the pointer to the MQD */
6598         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6599         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6600
6601         /* set MQD vmid to 0 */
6602         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6603         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6604         mqd->cp_mqd_control = tmp;
6605
6606         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6607         hqd_gpu_addr = ring->gpu_addr >> 8;
6608         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6609         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6610
6611         /* set up the HQD, this is similar to CP_RB0_CNTL */
6612         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6613         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6614                             (order_base_2(ring->ring_size / 4) - 1));
6615         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6616                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6617 #ifdef __BIG_ENDIAN
6618         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6619 #endif
6620         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6621         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6622         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6623         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6624         mqd->cp_hqd_pq_control = tmp;
6625
6626         /* set the wb address whether it's enabled or not */
6627         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6628         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6629         mqd->cp_hqd_pq_rptr_report_addr_hi =
6630                 upper_32_bits(wb_gpu_addr) & 0xffff;
6631
6632         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6633         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6634         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6635         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6636
6637         tmp = 0;
6638         /* enable the doorbell if requested */
6639         if (ring->use_doorbell) {
6640                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6641                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6642                                 DOORBELL_OFFSET, ring->doorbell_index);
6643
6644                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6645                                     DOORBELL_EN, 1);
6646                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6647                                     DOORBELL_SOURCE, 0);
6648                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6649                                     DOORBELL_HIT, 0);
6650         }
6651
6652         mqd->cp_hqd_pq_doorbell_control = tmp;
6653
6654         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6655         ring->wptr = 0;
6656         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6657
6658         /* set the vmid for the queue */
6659         mqd->cp_hqd_vmid = 0;
6660
6661         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6662         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6663         mqd->cp_hqd_persistent_state = tmp;
6664
6665         /* set MIN_IB_AVAIL_SIZE */
6666         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6667         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6668         mqd->cp_hqd_ib_control = tmp;
6669
6670         /* set static priority for a compute queue/ring */
6671         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6672
6673         /* map_queues packet doesn't need activate the queue,
6674          * so only kiq need set this field.
6675          */
6676         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6677                 mqd->cp_hqd_active = 1;
6678
6679         return 0;
6680 }
6681
6682 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6683 {
6684         struct amdgpu_device *adev = ring->adev;
6685         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6686         int j;
6687
6688         /* inactivate the queue */
6689         if (amdgpu_sriov_vf(adev))
6690                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6691
6692         /* disable wptr polling */
6693         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6694
6695         /* write the EOP addr */
6696         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6697                mqd->cp_hqd_eop_base_addr_lo);
6698         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6699                mqd->cp_hqd_eop_base_addr_hi);
6700
6701         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6702         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6703                mqd->cp_hqd_eop_control);
6704
6705         /* enable doorbell? */
6706         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6707                mqd->cp_hqd_pq_doorbell_control);
6708
6709         /* disable the queue if it's active */
6710         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6711                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6712                 for (j = 0; j < adev->usec_timeout; j++) {
6713                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6714                                 break;
6715                         udelay(1);
6716                 }
6717                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6718                        mqd->cp_hqd_dequeue_request);
6719                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6720                        mqd->cp_hqd_pq_rptr);
6721                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6722                        mqd->cp_hqd_pq_wptr_lo);
6723                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6724                        mqd->cp_hqd_pq_wptr_hi);
6725         }
6726
6727         /* set the pointer to the MQD */
6728         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6729                mqd->cp_mqd_base_addr_lo);
6730         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6731                mqd->cp_mqd_base_addr_hi);
6732
6733         /* set MQD vmid to 0 */
6734         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6735                mqd->cp_mqd_control);
6736
6737         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6738         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6739                mqd->cp_hqd_pq_base_lo);
6740         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6741                mqd->cp_hqd_pq_base_hi);
6742
6743         /* set up the HQD, this is similar to CP_RB0_CNTL */
6744         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6745                mqd->cp_hqd_pq_control);
6746
6747         /* set the wb address whether it's enabled or not */
6748         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6749                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6750         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6751                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6752
6753         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6754         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6755                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6756         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6757                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6758
6759         /* enable the doorbell if requested */
6760         if (ring->use_doorbell) {
6761                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6762                         (adev->doorbell_index.kiq * 2) << 2);
6763                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6764                         (adev->doorbell_index.userqueue_end * 2) << 2);
6765         }
6766
6767         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6768                mqd->cp_hqd_pq_doorbell_control);
6769
6770         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6771         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6772                mqd->cp_hqd_pq_wptr_lo);
6773         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6774                mqd->cp_hqd_pq_wptr_hi);
6775
6776         /* set the vmid for the queue */
6777         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6778
6779         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6780                mqd->cp_hqd_persistent_state);
6781
6782         /* activate the queue */
6783         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6784                mqd->cp_hqd_active);
6785
6786         if (ring->use_doorbell)
6787                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6788
6789         return 0;
6790 }
6791
6792 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6793 {
6794         struct amdgpu_device *adev = ring->adev;
6795         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6796         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6797
6798         gfx_v10_0_kiq_setting(ring);
6799
6800         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6801                 /* reset MQD to a clean status */
6802                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6803                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6804
6805                 /* reset ring buffer */
6806                 ring->wptr = 0;
6807                 amdgpu_ring_clear_ring(ring);
6808
6809                 mutex_lock(&adev->srbm_mutex);
6810                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6811                 gfx_v10_0_kiq_init_register(ring);
6812                 nv_grbm_select(adev, 0, 0, 0, 0);
6813                 mutex_unlock(&adev->srbm_mutex);
6814         } else {
6815                 memset((void *)mqd, 0, sizeof(*mqd));
6816                 mutex_lock(&adev->srbm_mutex);
6817                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6818                 gfx_v10_0_compute_mqd_init(ring);
6819                 gfx_v10_0_kiq_init_register(ring);
6820                 nv_grbm_select(adev, 0, 0, 0, 0);
6821                 mutex_unlock(&adev->srbm_mutex);
6822
6823                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6824                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6825         }
6826
6827         return 0;
6828 }
6829
6830 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6831 {
6832         struct amdgpu_device *adev = ring->adev;
6833         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6834         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6835
6836         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6837                 memset((void *)mqd, 0, sizeof(*mqd));
6838                 mutex_lock(&adev->srbm_mutex);
6839                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6840                 gfx_v10_0_compute_mqd_init(ring);
6841                 nv_grbm_select(adev, 0, 0, 0, 0);
6842                 mutex_unlock(&adev->srbm_mutex);
6843
6844                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6845                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6846         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6847                 /* reset MQD to a clean status */
6848                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6849                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6850
6851                 /* reset ring buffer */
6852                 ring->wptr = 0;
6853                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6854                 amdgpu_ring_clear_ring(ring);
6855         } else {
6856                 amdgpu_ring_clear_ring(ring);
6857         }
6858
6859         return 0;
6860 }
6861
6862 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6863 {
6864         struct amdgpu_ring *ring;
6865         int r;
6866
6867         ring = &adev->gfx.kiq.ring;
6868
6869         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6870         if (unlikely(r != 0))
6871                 return r;
6872
6873         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6874         if (unlikely(r != 0))
6875                 return r;
6876
6877         gfx_v10_0_kiq_init_queue(ring);
6878         amdgpu_bo_kunmap(ring->mqd_obj);
6879         ring->mqd_ptr = NULL;
6880         amdgpu_bo_unreserve(ring->mqd_obj);
6881         ring->sched.ready = true;
6882         return 0;
6883 }
6884
6885 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6886 {
6887         struct amdgpu_ring *ring = NULL;
6888         int r = 0, i;
6889
6890         gfx_v10_0_cp_compute_enable(adev, true);
6891
6892         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6893                 ring = &adev->gfx.compute_ring[i];
6894
6895                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6896                 if (unlikely(r != 0))
6897                         goto done;
6898                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6899                 if (!r) {
6900                         r = gfx_v10_0_kcq_init_queue(ring);
6901                         amdgpu_bo_kunmap(ring->mqd_obj);
6902                         ring->mqd_ptr = NULL;
6903                 }
6904                 amdgpu_bo_unreserve(ring->mqd_obj);
6905                 if (r)
6906                         goto done;
6907         }
6908
6909         r = amdgpu_gfx_enable_kcq(adev);
6910 done:
6911         return r;
6912 }
6913
6914 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6915 {
6916         int r, i;
6917         struct amdgpu_ring *ring;
6918
6919         if (!(adev->flags & AMD_IS_APU))
6920                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6921
6922         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6923                 /* legacy firmware loading */
6924                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6925                 if (r)
6926                         return r;
6927
6928                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6929                 if (r)
6930                         return r;
6931         }
6932
6933         r = gfx_v10_0_kiq_resume(adev);
6934         if (r)
6935                 return r;
6936
6937         r = gfx_v10_0_kcq_resume(adev);
6938         if (r)
6939                 return r;
6940
6941         if (!amdgpu_async_gfx_ring) {
6942                 r = gfx_v10_0_cp_gfx_resume(adev);
6943                 if (r)
6944                         return r;
6945         } else {
6946                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6947                 if (r)
6948                         return r;
6949         }
6950
6951         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6952                 ring = &adev->gfx.gfx_ring[i];
6953                 r = amdgpu_ring_test_helper(ring);
6954                 if (r)
6955                         return r;
6956         }
6957
6958         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6959                 ring = &adev->gfx.compute_ring[i];
6960                 r = amdgpu_ring_test_helper(ring);
6961                 if (r)
6962                         return r;
6963         }
6964
6965         return 0;
6966 }
6967
6968 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6969 {
6970         gfx_v10_0_cp_gfx_enable(adev, enable);
6971         gfx_v10_0_cp_compute_enable(adev, enable);
6972 }
6973
6974 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6975 {
6976         uint32_t data, pattern = 0xDEADBEEF;
6977
6978         /* check if mmVGT_ESGS_RING_SIZE_UMD
6979          * has been remapped to mmVGT_ESGS_RING_SIZE */
6980         switch (adev->asic_type) {
6981         case CHIP_SIENNA_CICHLID:
6982         case CHIP_NAVY_FLOUNDER:
6983         case CHIP_DIMGREY_CAVEFISH:
6984                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6985                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6986                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6987
6988                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6989                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6990                         return true;
6991                 } else {
6992                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6993                         return false;
6994                 }
6995                 break;
6996         case CHIP_VANGOGH:
6997                 return true;
6998         default:
6999                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7000                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7001                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7002
7003                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7004                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7005                         return true;
7006                 } else {
7007                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7008                         return false;
7009                 }
7010                 break;
7011         }
7012 }
7013
7014 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7015 {
7016         uint32_t data;
7017
7018         /* initialize cam_index to 0
7019          * index will auto-inc after each data writting */
7020         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7021
7022         switch (adev->asic_type) {
7023         case CHIP_SIENNA_CICHLID:
7024         case CHIP_NAVY_FLOUNDER:
7025         case CHIP_VANGOGH:
7026         case CHIP_DIMGREY_CAVEFISH:
7027                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7028                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7029                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7030                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7031                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7032                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7033                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7034
7035                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7036                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7037                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7038                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7039                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7040                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7041                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7042
7043                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7044                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7045                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7046                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7047                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7048                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7049                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7050
7051                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7052                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7053                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7054                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7055                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7056                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7057                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7058
7059                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7060                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7061                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7062                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7063                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7064                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7065                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7066
7067                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7068                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7069                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7070                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7071                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7072                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7073                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7074
7075                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7076                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7077                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7078                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7079                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7080                 break;
7081         default:
7082                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7083                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7084                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7085                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7086                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7087                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7088                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7089
7090                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7091                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7092                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7093                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7094                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7095                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7096                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7097
7098                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7099                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7100                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7101                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7102                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7103                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7104                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7105
7106                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7107                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7108                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7109                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7110                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7111                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7112                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7113
7114                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7115                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7116                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7117                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7118                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7119                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7120                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7121
7122                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7123                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7124                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7125                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7126                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7127                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7128                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7129
7130                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7131                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7132                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7133                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7134                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7135                 break;
7136         }
7137
7138         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7139         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7140 }
7141
7142 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7143 {
7144         uint32_t data;
7145         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7146         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7147         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7148
7149         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7150         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7151         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7152 }
7153
7154 static int gfx_v10_0_hw_init(void *handle)
7155 {
7156         int r;
7157         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7158
7159         if (!amdgpu_emu_mode)
7160                 gfx_v10_0_init_golden_registers(adev);
7161
7162         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7163                 /**
7164                  * For gfx 10, rlc firmware loading relies on smu firmware is
7165                  * loaded firstly, so in direct type, it has to load smc ucode
7166                  * here before rlc.
7167                  */
7168                 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) {
7169                         r = smu_load_microcode(&adev->smu);
7170                         if (r)
7171                                 return r;
7172
7173                         r = smu_check_fw_status(&adev->smu);
7174                         if (r) {
7175                                 pr_err("SMC firmware status is not correct\n");
7176                                 return r;
7177                         }
7178                 }
7179                 gfx_v10_0_disable_gpa_mode(adev);
7180         }
7181
7182         /* if GRBM CAM not remapped, set up the remapping */
7183         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7184                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7185
7186         gfx_v10_0_constants_init(adev);
7187
7188         r = gfx_v10_0_rlc_resume(adev);
7189         if (r)
7190                 return r;
7191
7192         /*
7193          * init golden registers and rlc resume may override some registers,
7194          * reconfig them here
7195          */
7196         gfx_v10_0_tcp_harvest(adev);
7197
7198         r = gfx_v10_0_cp_resume(adev);
7199         if (r)
7200                 return r;
7201
7202         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7203                 gfx_v10_3_program_pbb_mode(adev);
7204
7205         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7206                 gfx_v10_3_set_power_brake_sequence(adev);
7207
7208         return r;
7209 }
7210
7211 #ifndef BRING_UP_DEBUG
7212 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7213 {
7214         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7215         struct amdgpu_ring *kiq_ring = &kiq->ring;
7216         int i;
7217
7218         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7219                 return -EINVAL;
7220
7221         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7222                                         adev->gfx.num_gfx_rings))
7223                 return -ENOMEM;
7224
7225         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7226                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7227                                            PREEMPT_QUEUES, 0, 0);
7228
7229         return amdgpu_ring_test_helper(kiq_ring);
7230 }
7231 #endif
7232
7233 static int gfx_v10_0_hw_fini(void *handle)
7234 {
7235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7236         int r;
7237         uint32_t tmp;
7238
7239         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7240         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7241
7242         if (!adev->in_pci_err_recovery) {
7243 #ifndef BRING_UP_DEBUG
7244                 if (amdgpu_async_gfx_ring) {
7245                         r = gfx_v10_0_kiq_disable_kgq(adev);
7246                         if (r)
7247                                 DRM_ERROR("KGQ disable failed\n");
7248                 }
7249 #endif
7250                 if (amdgpu_gfx_disable_kcq(adev))
7251                         DRM_ERROR("KCQ disable failed\n");
7252         }
7253
7254         if (amdgpu_sriov_vf(adev)) {
7255                 gfx_v10_0_cp_gfx_enable(adev, false);
7256                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7257                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7258                 tmp &= 0xffffff00;
7259                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7260
7261                 return 0;
7262         }
7263         gfx_v10_0_cp_enable(adev, false);
7264         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7265
7266         return 0;
7267 }
7268
7269 static int gfx_v10_0_suspend(void *handle)
7270 {
7271         return gfx_v10_0_hw_fini(handle);
7272 }
7273
7274 static int gfx_v10_0_resume(void *handle)
7275 {
7276         return gfx_v10_0_hw_init(handle);
7277 }
7278
7279 static bool gfx_v10_0_is_idle(void *handle)
7280 {
7281         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7282
7283         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7284                                 GRBM_STATUS, GUI_ACTIVE))
7285                 return false;
7286         else
7287                 return true;
7288 }
7289
7290 static int gfx_v10_0_wait_for_idle(void *handle)
7291 {
7292         unsigned i;
7293         u32 tmp;
7294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7295
7296         for (i = 0; i < adev->usec_timeout; i++) {
7297                 /* read MC_STATUS */
7298                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7299                         GRBM_STATUS__GUI_ACTIVE_MASK;
7300
7301                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7302                         return 0;
7303                 udelay(1);
7304         }
7305         return -ETIMEDOUT;
7306 }
7307
7308 static int gfx_v10_0_soft_reset(void *handle)
7309 {
7310         u32 grbm_soft_reset = 0;
7311         u32 tmp;
7312         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7313
7314         /* GRBM_STATUS */
7315         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7316         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7317                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7318                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7319                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7320                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7321                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7322                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7323                                                 1);
7324                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7325                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7326                                                 1);
7327         }
7328
7329         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7330                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7331                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7332                                                 1);
7333         }
7334
7335         /* GRBM_STATUS2 */
7336         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7337         switch (adev->asic_type) {
7338         case CHIP_SIENNA_CICHLID:
7339         case CHIP_NAVY_FLOUNDER:
7340         case CHIP_VANGOGH:
7341         case CHIP_DIMGREY_CAVEFISH:
7342                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7343                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7344                                                         GRBM_SOFT_RESET,
7345                                                         SOFT_RESET_RLC,
7346                                                         1);
7347                 break;
7348         default:
7349                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7350                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7351                                                         GRBM_SOFT_RESET,
7352                                                         SOFT_RESET_RLC,
7353                                                         1);
7354                 break;
7355         }
7356
7357         if (grbm_soft_reset) {
7358                 /* stop the rlc */
7359                 gfx_v10_0_rlc_stop(adev);
7360
7361                 /* Disable GFX parsing/prefetching */
7362                 gfx_v10_0_cp_gfx_enable(adev, false);
7363
7364                 /* Disable MEC parsing/prefetching */
7365                 gfx_v10_0_cp_compute_enable(adev, false);
7366
7367                 if (grbm_soft_reset) {
7368                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7369                         tmp |= grbm_soft_reset;
7370                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7371                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7372                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7373
7374                         udelay(50);
7375
7376                         tmp &= ~grbm_soft_reset;
7377                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7378                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7379                 }
7380
7381                 /* Wait a little for things to settle down */
7382                 udelay(50);
7383         }
7384         return 0;
7385 }
7386
7387 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7388 {
7389         uint64_t clock;
7390
7391         amdgpu_gfx_off_ctrl(adev, false);
7392         mutex_lock(&adev->gfx.gpu_clock_mutex);
7393         switch (adev->asic_type) {
7394         case CHIP_VANGOGH:
7395                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7396                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7397                 break;
7398         default:
7399                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7400                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7401                 break;
7402         }
7403         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7404         amdgpu_gfx_off_ctrl(adev, true);
7405         return clock;
7406 }
7407
7408 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7409                                            uint32_t vmid,
7410                                            uint32_t gds_base, uint32_t gds_size,
7411                                            uint32_t gws_base, uint32_t gws_size,
7412                                            uint32_t oa_base, uint32_t oa_size)
7413 {
7414         struct amdgpu_device *adev = ring->adev;
7415
7416         /* GDS Base */
7417         gfx_v10_0_write_data_to_reg(ring, 0, false,
7418                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7419                                     gds_base);
7420
7421         /* GDS Size */
7422         gfx_v10_0_write_data_to_reg(ring, 0, false,
7423                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7424                                     gds_size);
7425
7426         /* GWS */
7427         gfx_v10_0_write_data_to_reg(ring, 0, false,
7428                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7429                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7430
7431         /* OA */
7432         gfx_v10_0_write_data_to_reg(ring, 0, false,
7433                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7434                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7435 }
7436
7437 static int gfx_v10_0_early_init(void *handle)
7438 {
7439         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7440
7441         switch (adev->asic_type) {
7442         case CHIP_NAVI10:
7443         case CHIP_NAVI14:
7444         case CHIP_NAVI12:
7445                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7446                 break;
7447         case CHIP_SIENNA_CICHLID:
7448         case CHIP_NAVY_FLOUNDER:
7449         case CHIP_VANGOGH:
7450         case CHIP_DIMGREY_CAVEFISH:
7451                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7452                 break;
7453         default:
7454                 break;
7455         }
7456
7457         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7458                                           AMDGPU_MAX_COMPUTE_RINGS);
7459
7460         gfx_v10_0_set_kiq_pm4_funcs(adev);
7461         gfx_v10_0_set_ring_funcs(adev);
7462         gfx_v10_0_set_irq_funcs(adev);
7463         gfx_v10_0_set_gds_init(adev);
7464         gfx_v10_0_set_rlc_funcs(adev);
7465
7466         return 0;
7467 }
7468
7469 static int gfx_v10_0_late_init(void *handle)
7470 {
7471         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7472         int r;
7473
7474         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7475         if (r)
7476                 return r;
7477
7478         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7479         if (r)
7480                 return r;
7481
7482         return 0;
7483 }
7484
7485 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7486 {
7487         uint32_t rlc_cntl;
7488
7489         /* if RLC is not enabled, do nothing */
7490         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7491         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7492 }
7493
7494 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7495 {
7496         uint32_t data;
7497         unsigned i;
7498
7499         data = RLC_SAFE_MODE__CMD_MASK;
7500         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7501
7502         switch (adev->asic_type) {
7503         case CHIP_SIENNA_CICHLID:
7504         case CHIP_NAVY_FLOUNDER:
7505         case CHIP_VANGOGH:
7506         case CHIP_DIMGREY_CAVEFISH:
7507                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7508
7509                 /* wait for RLC_SAFE_MODE */
7510                 for (i = 0; i < adev->usec_timeout; i++) {
7511                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7512                                            RLC_SAFE_MODE, CMD))
7513                                 break;
7514                         udelay(1);
7515                 }
7516                 break;
7517         default:
7518                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7519
7520                 /* wait for RLC_SAFE_MODE */
7521                 for (i = 0; i < adev->usec_timeout; i++) {
7522                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7523                                            RLC_SAFE_MODE, CMD))
7524                                 break;
7525                         udelay(1);
7526                 }
7527                 break;
7528         }
7529 }
7530
7531 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7532 {
7533         uint32_t data;
7534
7535         data = RLC_SAFE_MODE__CMD_MASK;
7536         switch (adev->asic_type) {
7537         case CHIP_SIENNA_CICHLID:
7538         case CHIP_NAVY_FLOUNDER:
7539         case CHIP_VANGOGH:
7540         case CHIP_DIMGREY_CAVEFISH:
7541                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7542                 break;
7543         default:
7544                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7545                 break;
7546         }
7547 }
7548
7549 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7550                                                       bool enable)
7551 {
7552         uint32_t data, def;
7553
7554         /* It is disabled by HW by default */
7555         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7556                 /* 0 - Disable some blocks' MGCG */
7557                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7558                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7559                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7560                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7561
7562                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7563                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7564                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7565                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7566                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7567                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7568                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7569
7570                 if (def != data)
7571                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7572
7573                 /* MGLS is a global flag to control all MGLS in GFX */
7574                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7575                         /* 2 - RLC memory Light sleep */
7576                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7577                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7578                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7579                                 if (def != data)
7580                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7581                         }
7582                         /* 3 - CP memory Light sleep */
7583                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7584                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7585                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7586                                 if (def != data)
7587                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7588                         }
7589                 }
7590         } else {
7591                 /* 1 - MGCG_OVERRIDE */
7592                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7593                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7594                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7595                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7596                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7597                 if (def != data)
7598                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7599
7600                 /* 2 - disable MGLS in CP */
7601                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7602                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7603                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7604                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7605                 }
7606
7607                 /* 3 - disable MGLS in RLC */
7608                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7609                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7610                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7611                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7612                 }
7613
7614         }
7615 }
7616
7617 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7618                                            bool enable)
7619 {
7620         uint32_t data, def;
7621
7622         /* Enable 3D CGCG/CGLS */
7623         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7624                 /* write cmd to clear cgcg/cgls ov */
7625                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7626                 /* unset CGCG override */
7627                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7628                 /* update CGCG and CGLS override bits */
7629                 if (def != data)
7630                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7631                 /* enable 3Dcgcg FSM(0x0000363f) */
7632                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7633                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7634                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7635                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7636                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7637                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7638                 if (def != data)
7639                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7640
7641                 /* set IDLE_POLL_COUNT(0x00900100) */
7642                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7643                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7644                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7645                 if (def != data)
7646                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7647         } else {
7648                 /* Disable CGCG/CGLS */
7649                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7650                 /* disable cgcg, cgls should be disabled */
7651                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7652                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7653                 /* disable cgcg and cgls in FSM */
7654                 if (def != data)
7655                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7656         }
7657 }
7658
7659 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7660                                                       bool enable)
7661 {
7662         uint32_t def, data;
7663
7664         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7665                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7666                 /* unset CGCG override */
7667                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7668                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7669                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7670                 else
7671                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7672                 /* update CGCG and CGLS override bits */
7673                 if (def != data)
7674                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7675
7676                 /* enable cgcg FSM(0x0000363F) */
7677                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7678                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7679                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7680                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7681                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7682                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7683                 if (def != data)
7684                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7685
7686                 /* set IDLE_POLL_COUNT(0x00900100) */
7687                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7688                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7689                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7690                 if (def != data)
7691                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7692         } else {
7693                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7694                 /* reset CGCG/CGLS bits */
7695                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7696                 /* disable cgcg and cgls in FSM */
7697                 if (def != data)
7698                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7699         }
7700 }
7701
7702 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7703                                                       bool enable)
7704 {
7705         uint32_t def, data;
7706
7707         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7708                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7709                 /* unset FGCG override */
7710                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7711                 /* update FGCG override bits */
7712                 if (def != data)
7713                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7714
7715                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7716                 /* unset RLC SRAM CLK GATER override */
7717                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7718                 /* update RLC SRAM CLK GATER override bits */
7719                 if (def != data)
7720                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7721         } else {
7722                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7723                 /* reset FGCG bits */
7724                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7725                 /* disable FGCG*/
7726                 if (def != data)
7727                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7728
7729                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7730                 /* reset RLC SRAM CLK GATER bits */
7731                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7732                 /* disable RLC SRAM CLK*/
7733                 if (def != data)
7734                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7735         }
7736 }
7737
7738 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7739                                             bool enable)
7740 {
7741         amdgpu_gfx_rlc_enter_safe_mode(adev);
7742
7743         if (enable) {
7744                 /* enable FGCG firstly*/
7745                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7746                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7747                  * ===  MGCG + MGLS ===
7748                  */
7749                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7750                 /* ===  CGCG /CGLS for GFX 3D Only === */
7751                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7752                 /* ===  CGCG + CGLS === */
7753                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7754         } else {
7755                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7756                  * ===  CGCG + CGLS ===
7757                  */
7758                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7759                 /* ===  CGCG /CGLS for GFX 3D Only === */
7760                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7761                 /* ===  MGCG + MGLS === */
7762                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7763                 /* disable fgcg at last*/
7764                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7765         }
7766
7767         if (adev->cg_flags &
7768             (AMD_CG_SUPPORT_GFX_MGCG |
7769              AMD_CG_SUPPORT_GFX_CGLS |
7770              AMD_CG_SUPPORT_GFX_CGCG |
7771              AMD_CG_SUPPORT_GFX_3D_CGCG |
7772              AMD_CG_SUPPORT_GFX_3D_CGLS))
7773                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7774
7775         amdgpu_gfx_rlc_exit_safe_mode(adev);
7776
7777         return 0;
7778 }
7779
7780 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7781 {
7782         u32 reg, data;
7783
7784         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7785         if (amdgpu_sriov_is_pp_one_vf(adev))
7786                 data = RREG32_NO_KIQ(reg);
7787         else
7788                 data = RREG32(reg);
7789
7790         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7791         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7792
7793         if (amdgpu_sriov_is_pp_one_vf(adev))
7794                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7795         else
7796                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7797 }
7798
7799 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7800                                         uint32_t offset,
7801                                         struct soc15_reg_rlcg *entries, int arr_size)
7802 {
7803         int i;
7804         uint32_t reg;
7805
7806         if (!entries)
7807                 return false;
7808
7809         for (i = 0; i < arr_size; i++) {
7810                 const struct soc15_reg_rlcg *entry;
7811
7812                 entry = &entries[i];
7813                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7814                 if (offset == reg)
7815                         return true;
7816         }
7817
7818         return false;
7819 }
7820
7821 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7822 {
7823         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7824 }
7825
7826 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7827 {
7828         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7829
7830         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7831                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7832         else
7833                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7834
7835         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7836 }
7837
7838 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7839 {
7840         amdgpu_gfx_rlc_enter_safe_mode(adev);
7841
7842         gfx_v10_cntl_power_gating(adev, enable);
7843
7844         amdgpu_gfx_rlc_exit_safe_mode(adev);
7845 }
7846
7847 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7848         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7849         .set_safe_mode = gfx_v10_0_set_safe_mode,
7850         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7851         .init = gfx_v10_0_rlc_init,
7852         .get_csb_size = gfx_v10_0_get_csb_size,
7853         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7854         .resume = gfx_v10_0_rlc_resume,
7855         .stop = gfx_v10_0_rlc_stop,
7856         .reset = gfx_v10_0_rlc_reset,
7857         .start = gfx_v10_0_rlc_start,
7858         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7859 };
7860
7861 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7862         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7863         .set_safe_mode = gfx_v10_0_set_safe_mode,
7864         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7865         .init = gfx_v10_0_rlc_init,
7866         .get_csb_size = gfx_v10_0_get_csb_size,
7867         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7868         .resume = gfx_v10_0_rlc_resume,
7869         .stop = gfx_v10_0_rlc_stop,
7870         .reset = gfx_v10_0_rlc_reset,
7871         .start = gfx_v10_0_rlc_start,
7872         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7873         .rlcg_wreg = gfx_v10_rlcg_wreg,
7874         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7875 };
7876
7877 static int gfx_v10_0_set_powergating_state(void *handle,
7878                                           enum amd_powergating_state state)
7879 {
7880         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7881         bool enable = (state == AMD_PG_STATE_GATE);
7882
7883         if (amdgpu_sriov_vf(adev))
7884                 return 0;
7885
7886         switch (adev->asic_type) {
7887         case CHIP_NAVI10:
7888         case CHIP_NAVI14:
7889         case CHIP_NAVI12:
7890         case CHIP_SIENNA_CICHLID:
7891         case CHIP_NAVY_FLOUNDER:
7892         case CHIP_DIMGREY_CAVEFISH:
7893                 amdgpu_gfx_off_ctrl(adev, enable);
7894                 break;
7895         case CHIP_VANGOGH:
7896                 gfx_v10_cntl_pg(adev, enable);
7897                 break;
7898         default:
7899                 break;
7900         }
7901         return 0;
7902 }
7903
7904 static int gfx_v10_0_set_clockgating_state(void *handle,
7905                                           enum amd_clockgating_state state)
7906 {
7907         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7908
7909         if (amdgpu_sriov_vf(adev))
7910                 return 0;
7911
7912         switch (adev->asic_type) {
7913         case CHIP_NAVI10:
7914         case CHIP_NAVI14:
7915         case CHIP_NAVI12:
7916         case CHIP_SIENNA_CICHLID:
7917         case CHIP_NAVY_FLOUNDER:
7918         case CHIP_VANGOGH:
7919         case CHIP_DIMGREY_CAVEFISH:
7920                 gfx_v10_0_update_gfx_clock_gating(adev,
7921                                                  state == AMD_CG_STATE_GATE);
7922                 break;
7923         default:
7924                 break;
7925         }
7926         return 0;
7927 }
7928
7929 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7930 {
7931         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7932         int data;
7933
7934         /* AMD_CG_SUPPORT_GFX_FGCG */
7935         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7936         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
7937                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
7938
7939         /* AMD_CG_SUPPORT_GFX_MGCG */
7940         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7941         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7942                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7943
7944         /* AMD_CG_SUPPORT_GFX_CGCG */
7945         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7946         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7947                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7948
7949         /* AMD_CG_SUPPORT_GFX_CGLS */
7950         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7951                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7952
7953         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7954         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7955         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7956                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7957
7958         /* AMD_CG_SUPPORT_GFX_CP_LS */
7959         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7960         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7961                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7962
7963         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7964         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7965         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7966                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7967
7968         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7969         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7970                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7971 }
7972
7973 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7974 {
7975         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7976 }
7977
7978 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7979 {
7980         struct amdgpu_device *adev = ring->adev;
7981         u64 wptr;
7982
7983         /* XXX check if swapping is necessary on BE */
7984         if (ring->use_doorbell) {
7985                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7986         } else {
7987                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7988                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7989         }
7990
7991         return wptr;
7992 }
7993
7994 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7995 {
7996         struct amdgpu_device *adev = ring->adev;
7997
7998         if (ring->use_doorbell) {
7999                 /* XXX check if swapping is necessary on BE */
8000                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8001                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8002         } else {
8003                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8004                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8005         }
8006 }
8007
8008 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8009 {
8010         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8011 }
8012
8013 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8014 {
8015         u64 wptr;
8016
8017         /* XXX check if swapping is necessary on BE */
8018         if (ring->use_doorbell)
8019                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8020         else
8021                 BUG();
8022         return wptr;
8023 }
8024
8025 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8026 {
8027         struct amdgpu_device *adev = ring->adev;
8028
8029         /* XXX check if swapping is necessary on BE */
8030         if (ring->use_doorbell) {
8031                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8032                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8033         } else {
8034                 BUG(); /* only DOORBELL method supported on gfx10 now */
8035         }
8036 }
8037
8038 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8039 {
8040         struct amdgpu_device *adev = ring->adev;
8041         u32 ref_and_mask, reg_mem_engine;
8042         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8043
8044         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8045                 switch (ring->me) {
8046                 case 1:
8047                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8048                         break;
8049                 case 2:
8050                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8051                         break;
8052                 default:
8053                         return;
8054                 }
8055                 reg_mem_engine = 0;
8056         } else {
8057                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8058                 reg_mem_engine = 1; /* pfp */
8059         }
8060
8061         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8062                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8063                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8064                                ref_and_mask, ref_and_mask, 0x20);
8065 }
8066
8067 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8068                                        struct amdgpu_job *job,
8069                                        struct amdgpu_ib *ib,
8070                                        uint32_t flags)
8071 {
8072         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8073         u32 header, control = 0;
8074
8075         if (ib->flags & AMDGPU_IB_FLAG_CE)
8076                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8077         else
8078                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8079
8080         control |= ib->length_dw | (vmid << 24);
8081
8082         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8083                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8084
8085                 if (flags & AMDGPU_IB_PREEMPTED)
8086                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8087
8088                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8089                         gfx_v10_0_ring_emit_de_meta(ring,
8090                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8091         }
8092
8093         amdgpu_ring_write(ring, header);
8094         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8095         amdgpu_ring_write(ring,
8096 #ifdef __BIG_ENDIAN
8097                 (2 << 0) |
8098 #endif
8099                 lower_32_bits(ib->gpu_addr));
8100         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8101         amdgpu_ring_write(ring, control);
8102 }
8103
8104 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8105                                            struct amdgpu_job *job,
8106                                            struct amdgpu_ib *ib,
8107                                            uint32_t flags)
8108 {
8109         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8110         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8111
8112         /* Currently, there is a high possibility to get wave ID mismatch
8113          * between ME and GDS, leading to a hw deadlock, because ME generates
8114          * different wave IDs than the GDS expects. This situation happens
8115          * randomly when at least 5 compute pipes use GDS ordered append.
8116          * The wave IDs generated by ME are also wrong after suspend/resume.
8117          * Those are probably bugs somewhere else in the kernel driver.
8118          *
8119          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8120          * GDS to 0 for this ring (me/pipe).
8121          */
8122         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8123                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8124                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8125                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8126         }
8127
8128         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8129         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8130         amdgpu_ring_write(ring,
8131 #ifdef __BIG_ENDIAN
8132                                 (2 << 0) |
8133 #endif
8134                                 lower_32_bits(ib->gpu_addr));
8135         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8136         amdgpu_ring_write(ring, control);
8137 }
8138
8139 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8140                                      u64 seq, unsigned flags)
8141 {
8142         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8143         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8144
8145         /* RELEASE_MEM - flush caches, send int */
8146         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8147         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8148                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8149                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8150                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8151                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8152                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8153                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8154         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8155                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8156
8157         /*
8158          * the address should be Qword aligned if 64bit write, Dword
8159          * aligned if only send 32bit data low (discard data high)
8160          */
8161         if (write64bit)
8162                 BUG_ON(addr & 0x7);
8163         else
8164                 BUG_ON(addr & 0x3);
8165         amdgpu_ring_write(ring, lower_32_bits(addr));
8166         amdgpu_ring_write(ring, upper_32_bits(addr));
8167         amdgpu_ring_write(ring, lower_32_bits(seq));
8168         amdgpu_ring_write(ring, upper_32_bits(seq));
8169         amdgpu_ring_write(ring, 0);
8170 }
8171
8172 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8173 {
8174         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8175         uint32_t seq = ring->fence_drv.sync_seq;
8176         uint64_t addr = ring->fence_drv.gpu_addr;
8177
8178         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8179                                upper_32_bits(addr), seq, 0xffffffff, 4);
8180 }
8181
8182 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8183                                          unsigned vmid, uint64_t pd_addr)
8184 {
8185         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8186
8187         /* compute doesn't have PFP */
8188         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8189                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8190                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8191                 amdgpu_ring_write(ring, 0x0);
8192         }
8193 }
8194
8195 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8196                                           u64 seq, unsigned int flags)
8197 {
8198         struct amdgpu_device *adev = ring->adev;
8199
8200         /* we only allocate 32bit for each seq wb address */
8201         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8202
8203         /* write fence seq to the "addr" */
8204         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8205         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8206                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8207         amdgpu_ring_write(ring, lower_32_bits(addr));
8208         amdgpu_ring_write(ring, upper_32_bits(addr));
8209         amdgpu_ring_write(ring, lower_32_bits(seq));
8210
8211         if (flags & AMDGPU_FENCE_FLAG_INT) {
8212                 /* set register to trigger INT */
8213                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8214                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8215                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8216                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8217                 amdgpu_ring_write(ring, 0);
8218                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8219         }
8220 }
8221
8222 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8223 {
8224         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8225         amdgpu_ring_write(ring, 0);
8226 }
8227
8228 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8229                                          uint32_t flags)
8230 {
8231         uint32_t dw2 = 0;
8232
8233         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8234                 gfx_v10_0_ring_emit_ce_meta(ring,
8235                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8236
8237         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8238         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8239                 /* set load_global_config & load_global_uconfig */
8240                 dw2 |= 0x8001;
8241                 /* set load_cs_sh_regs */
8242                 dw2 |= 0x01000000;
8243                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8244                 dw2 |= 0x10002;
8245
8246                 /* set load_ce_ram if preamble presented */
8247                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8248                         dw2 |= 0x10000000;
8249         } else {
8250                 /* still load_ce_ram if this is the first time preamble presented
8251                  * although there is no context switch happens.
8252                  */
8253                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8254                         dw2 |= 0x10000000;
8255         }
8256
8257         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8258         amdgpu_ring_write(ring, dw2);
8259         amdgpu_ring_write(ring, 0);
8260 }
8261
8262 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8263 {
8264         unsigned ret;
8265
8266         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8267         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8268         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8269         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8270         ret = ring->wptr & ring->buf_mask;
8271         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8272
8273         return ret;
8274 }
8275
8276 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8277 {
8278         unsigned cur;
8279         BUG_ON(offset > ring->buf_mask);
8280         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8281
8282         cur = (ring->wptr - 1) & ring->buf_mask;
8283         if (likely(cur > offset))
8284                 ring->ring[offset] = cur - offset;
8285         else
8286                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8287 }
8288
8289 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8290 {
8291         int i, r = 0;
8292         struct amdgpu_device *adev = ring->adev;
8293         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8294         struct amdgpu_ring *kiq_ring = &kiq->ring;
8295         unsigned long flags;
8296
8297         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8298                 return -EINVAL;
8299
8300         spin_lock_irqsave(&kiq->ring_lock, flags);
8301
8302         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8303                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8304                 return -ENOMEM;
8305         }
8306
8307         /* assert preemption condition */
8308         amdgpu_ring_set_preempt_cond_exec(ring, false);
8309
8310         /* assert IB preemption, emit the trailing fence */
8311         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8312                                    ring->trail_fence_gpu_addr,
8313                                    ++ring->trail_seq);
8314         amdgpu_ring_commit(kiq_ring);
8315
8316         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8317
8318         /* poll the trailing fence */
8319         for (i = 0; i < adev->usec_timeout; i++) {
8320                 if (ring->trail_seq ==
8321                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8322                         break;
8323                 udelay(1);
8324         }
8325
8326         if (i >= adev->usec_timeout) {
8327                 r = -EINVAL;
8328                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8329         }
8330
8331         /* deassert preemption condition */
8332         amdgpu_ring_set_preempt_cond_exec(ring, true);
8333         return r;
8334 }
8335
8336 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8337 {
8338         struct amdgpu_device *adev = ring->adev;
8339         struct v10_ce_ib_state ce_payload = {0};
8340         uint64_t csa_addr;
8341         int cnt;
8342
8343         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8344         csa_addr = amdgpu_csa_vaddr(ring->adev);
8345
8346         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8347         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8348                                  WRITE_DATA_DST_SEL(8) |
8349                                  WR_CONFIRM) |
8350                                  WRITE_DATA_CACHE_POLICY(0));
8351         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8352                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8353         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8354                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8355
8356         if (resume)
8357                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8358                                            offsetof(struct v10_gfx_meta_data,
8359                                                     ce_payload),
8360                                            sizeof(ce_payload) >> 2);
8361         else
8362                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8363                                            sizeof(ce_payload) >> 2);
8364 }
8365
8366 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8367 {
8368         struct amdgpu_device *adev = ring->adev;
8369         struct v10_de_ib_state de_payload = {0};
8370         uint64_t csa_addr, gds_addr;
8371         int cnt;
8372
8373         csa_addr = amdgpu_csa_vaddr(ring->adev);
8374         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8375                          PAGE_SIZE);
8376         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8377         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8378
8379         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8380         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8381         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8382                                  WRITE_DATA_DST_SEL(8) |
8383                                  WR_CONFIRM) |
8384                                  WRITE_DATA_CACHE_POLICY(0));
8385         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8386                               offsetof(struct v10_gfx_meta_data, de_payload)));
8387         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8388                               offsetof(struct v10_gfx_meta_data, de_payload)));
8389
8390         if (resume)
8391                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8392                                            offsetof(struct v10_gfx_meta_data,
8393                                                     de_payload),
8394                                            sizeof(de_payload) >> 2);
8395         else
8396                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8397                                            sizeof(de_payload) >> 2);
8398 }
8399
8400 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8401                                     bool secure)
8402 {
8403         uint32_t v = secure ? FRAME_TMZ : 0;
8404
8405         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8406         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8407 }
8408
8409 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8410                                      uint32_t reg_val_offs)
8411 {
8412         struct amdgpu_device *adev = ring->adev;
8413
8414         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8415         amdgpu_ring_write(ring, 0 |     /* src: register*/
8416                                 (5 << 8) |      /* dst: memory */
8417                                 (1 << 20));     /* write confirm */
8418         amdgpu_ring_write(ring, reg);
8419         amdgpu_ring_write(ring, 0);
8420         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8421                                 reg_val_offs * 4));
8422         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8423                                 reg_val_offs * 4));
8424 }
8425
8426 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8427                                    uint32_t val)
8428 {
8429         uint32_t cmd = 0;
8430
8431         switch (ring->funcs->type) {
8432         case AMDGPU_RING_TYPE_GFX:
8433                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8434                 break;
8435         case AMDGPU_RING_TYPE_KIQ:
8436                 cmd = (1 << 16); /* no inc addr */
8437                 break;
8438         default:
8439                 cmd = WR_CONFIRM;
8440                 break;
8441         }
8442         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8443         amdgpu_ring_write(ring, cmd);
8444         amdgpu_ring_write(ring, reg);
8445         amdgpu_ring_write(ring, 0);
8446         amdgpu_ring_write(ring, val);
8447 }
8448
8449 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8450                                         uint32_t val, uint32_t mask)
8451 {
8452         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8453 }
8454
8455 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8456                                                    uint32_t reg0, uint32_t reg1,
8457                                                    uint32_t ref, uint32_t mask)
8458 {
8459         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8460         struct amdgpu_device *adev = ring->adev;
8461         bool fw_version_ok = false;
8462
8463         fw_version_ok = adev->gfx.cp_fw_write_wait;
8464
8465         if (fw_version_ok)
8466                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8467                                        ref, mask, 0x20);
8468         else
8469                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8470                                                            ref, mask);
8471 }
8472
8473 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8474                                          unsigned vmid)
8475 {
8476         struct amdgpu_device *adev = ring->adev;
8477         uint32_t value = 0;
8478
8479         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8480         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8481         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8482         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8483         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8484 }
8485
8486 static void
8487 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8488                                       uint32_t me, uint32_t pipe,
8489                                       enum amdgpu_interrupt_state state)
8490 {
8491         uint32_t cp_int_cntl, cp_int_cntl_reg;
8492
8493         if (!me) {
8494                 switch (pipe) {
8495                 case 0:
8496                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8497                         break;
8498                 case 1:
8499                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8500                         break;
8501                 default:
8502                         DRM_DEBUG("invalid pipe %d\n", pipe);
8503                         return;
8504                 }
8505         } else {
8506                 DRM_DEBUG("invalid me %d\n", me);
8507                 return;
8508         }
8509
8510         switch (state) {
8511         case AMDGPU_IRQ_STATE_DISABLE:
8512                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8513                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8514                                             TIME_STAMP_INT_ENABLE, 0);
8515                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8516                 break;
8517         case AMDGPU_IRQ_STATE_ENABLE:
8518                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8519                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8520                                             TIME_STAMP_INT_ENABLE, 1);
8521                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8522                 break;
8523         default:
8524                 break;
8525         }
8526 }
8527
8528 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8529                                                      int me, int pipe,
8530                                                      enum amdgpu_interrupt_state state)
8531 {
8532         u32 mec_int_cntl, mec_int_cntl_reg;
8533
8534         /*
8535          * amdgpu controls only the first MEC. That's why this function only
8536          * handles the setting of interrupts for this specific MEC. All other
8537          * pipes' interrupts are set by amdkfd.
8538          */
8539
8540         if (me == 1) {
8541                 switch (pipe) {
8542                 case 0:
8543                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8544                         break;
8545                 case 1:
8546                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8547                         break;
8548                 case 2:
8549                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8550                         break;
8551                 case 3:
8552                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8553                         break;
8554                 default:
8555                         DRM_DEBUG("invalid pipe %d\n", pipe);
8556                         return;
8557                 }
8558         } else {
8559                 DRM_DEBUG("invalid me %d\n", me);
8560                 return;
8561         }
8562
8563         switch (state) {
8564         case AMDGPU_IRQ_STATE_DISABLE:
8565                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8566                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8567                                              TIME_STAMP_INT_ENABLE, 0);
8568                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8569                 break;
8570         case AMDGPU_IRQ_STATE_ENABLE:
8571                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8572                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8573                                              TIME_STAMP_INT_ENABLE, 1);
8574                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8575                 break;
8576         default:
8577                 break;
8578         }
8579 }
8580
8581 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8582                                             struct amdgpu_irq_src *src,
8583                                             unsigned type,
8584                                             enum amdgpu_interrupt_state state)
8585 {
8586         switch (type) {
8587         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8588                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8589                 break;
8590         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8591                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8592                 break;
8593         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8594                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8595                 break;
8596         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8597                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8598                 break;
8599         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8600                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8601                 break;
8602         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8603                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8604                 break;
8605         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8606                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8607                 break;
8608         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8609                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8610                 break;
8611         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8612                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8613                 break;
8614         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8615                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8616                 break;
8617         default:
8618                 break;
8619         }
8620         return 0;
8621 }
8622
8623 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8624                              struct amdgpu_irq_src *source,
8625                              struct amdgpu_iv_entry *entry)
8626 {
8627         int i;
8628         u8 me_id, pipe_id, queue_id;
8629         struct amdgpu_ring *ring;
8630
8631         DRM_DEBUG("IH: CP EOP\n");
8632         me_id = (entry->ring_id & 0x0c) >> 2;
8633         pipe_id = (entry->ring_id & 0x03) >> 0;
8634         queue_id = (entry->ring_id & 0x70) >> 4;
8635
8636         switch (me_id) {
8637         case 0:
8638                 if (pipe_id == 0)
8639                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8640                 else
8641                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8642                 break;
8643         case 1:
8644         case 2:
8645                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8646                         ring = &adev->gfx.compute_ring[i];
8647                         /* Per-queue interrupt is supported for MEC starting from VI.
8648                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8649                           */
8650                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8651                                 amdgpu_fence_process(ring);
8652                 }
8653                 break;
8654         }
8655         return 0;
8656 }
8657
8658 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8659                                               struct amdgpu_irq_src *source,
8660                                               unsigned type,
8661                                               enum amdgpu_interrupt_state state)
8662 {
8663         switch (state) {
8664         case AMDGPU_IRQ_STATE_DISABLE:
8665         case AMDGPU_IRQ_STATE_ENABLE:
8666                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8667                                PRIV_REG_INT_ENABLE,
8668                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8669                 break;
8670         default:
8671                 break;
8672         }
8673
8674         return 0;
8675 }
8676
8677 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8678                                                struct amdgpu_irq_src *source,
8679                                                unsigned type,
8680                                                enum amdgpu_interrupt_state state)
8681 {
8682         switch (state) {
8683         case AMDGPU_IRQ_STATE_DISABLE:
8684         case AMDGPU_IRQ_STATE_ENABLE:
8685                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8686                                PRIV_INSTR_INT_ENABLE,
8687                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8688                 break;
8689         default:
8690                 break;
8691         }
8692
8693         return 0;
8694 }
8695
8696 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8697                                         struct amdgpu_iv_entry *entry)
8698 {
8699         u8 me_id, pipe_id, queue_id;
8700         struct amdgpu_ring *ring;
8701         int i;
8702
8703         me_id = (entry->ring_id & 0x0c) >> 2;
8704         pipe_id = (entry->ring_id & 0x03) >> 0;
8705         queue_id = (entry->ring_id & 0x70) >> 4;
8706
8707         switch (me_id) {
8708         case 0:
8709                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8710                         ring = &adev->gfx.gfx_ring[i];
8711                         /* we only enabled 1 gfx queue per pipe for now */
8712                         if (ring->me == me_id && ring->pipe == pipe_id)
8713                                 drm_sched_fault(&ring->sched);
8714                 }
8715                 break;
8716         case 1:
8717         case 2:
8718                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8719                         ring = &adev->gfx.compute_ring[i];
8720                         if (ring->me == me_id && ring->pipe == pipe_id &&
8721                             ring->queue == queue_id)
8722                                 drm_sched_fault(&ring->sched);
8723                 }
8724                 break;
8725         default:
8726                 BUG();
8727         }
8728 }
8729
8730 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8731                                   struct amdgpu_irq_src *source,
8732                                   struct amdgpu_iv_entry *entry)
8733 {
8734         DRM_ERROR("Illegal register access in command stream\n");
8735         gfx_v10_0_handle_priv_fault(adev, entry);
8736         return 0;
8737 }
8738
8739 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8740                                    struct amdgpu_irq_src *source,
8741                                    struct amdgpu_iv_entry *entry)
8742 {
8743         DRM_ERROR("Illegal instruction in command stream\n");
8744         gfx_v10_0_handle_priv_fault(adev, entry);
8745         return 0;
8746 }
8747
8748 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8749                                              struct amdgpu_irq_src *src,
8750                                              unsigned int type,
8751                                              enum amdgpu_interrupt_state state)
8752 {
8753         uint32_t tmp, target;
8754         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8755
8756         if (ring->me == 1)
8757                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8758         else
8759                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8760         target += ring->pipe;
8761
8762         switch (type) {
8763         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8764                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8765                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8766                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8767                                             GENERIC2_INT_ENABLE, 0);
8768                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8769
8770                         tmp = RREG32(target);
8771                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8772                                             GENERIC2_INT_ENABLE, 0);
8773                         WREG32(target, tmp);
8774                 } else {
8775                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8776                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8777                                             GENERIC2_INT_ENABLE, 1);
8778                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8779
8780                         tmp = RREG32(target);
8781                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8782                                             GENERIC2_INT_ENABLE, 1);
8783                         WREG32(target, tmp);
8784                 }
8785                 break;
8786         default:
8787                 BUG(); /* kiq only support GENERIC2_INT now */
8788                 break;
8789         }
8790         return 0;
8791 }
8792
8793 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8794                              struct amdgpu_irq_src *source,
8795                              struct amdgpu_iv_entry *entry)
8796 {
8797         u8 me_id, pipe_id, queue_id;
8798         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8799
8800         me_id = (entry->ring_id & 0x0c) >> 2;
8801         pipe_id = (entry->ring_id & 0x03) >> 0;
8802         queue_id = (entry->ring_id & 0x70) >> 4;
8803         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8804                    me_id, pipe_id, queue_id);
8805
8806         amdgpu_fence_process(ring);
8807         return 0;
8808 }
8809
8810 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8811 {
8812         const unsigned int gcr_cntl =
8813                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8814                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8815                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8816                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8817                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8818                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8819                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8820                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8821
8822         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8823         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8824         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8825         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8826         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8827         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8828         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8829         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8830         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8831 }
8832
8833 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8834         .name = "gfx_v10_0",
8835         .early_init = gfx_v10_0_early_init,
8836         .late_init = gfx_v10_0_late_init,
8837         .sw_init = gfx_v10_0_sw_init,
8838         .sw_fini = gfx_v10_0_sw_fini,
8839         .hw_init = gfx_v10_0_hw_init,
8840         .hw_fini = gfx_v10_0_hw_fini,
8841         .suspend = gfx_v10_0_suspend,
8842         .resume = gfx_v10_0_resume,
8843         .is_idle = gfx_v10_0_is_idle,
8844         .wait_for_idle = gfx_v10_0_wait_for_idle,
8845         .soft_reset = gfx_v10_0_soft_reset,
8846         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8847         .set_powergating_state = gfx_v10_0_set_powergating_state,
8848         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8849 };
8850
8851 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8852         .type = AMDGPU_RING_TYPE_GFX,
8853         .align_mask = 0xff,
8854         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8855         .support_64bit_ptrs = true,
8856         .vmhub = AMDGPU_GFXHUB_0,
8857         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8858         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8859         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8860         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8861                 5 + /* COND_EXEC */
8862                 7 + /* PIPELINE_SYNC */
8863                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8864                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8865                 2 + /* VM_FLUSH */
8866                 8 + /* FENCE for VM_FLUSH */
8867                 20 + /* GDS switch */
8868                 4 + /* double SWITCH_BUFFER,
8869                      * the first COND_EXEC jump to the place
8870                      * just prior to this double SWITCH_BUFFER
8871                      */
8872                 5 + /* COND_EXEC */
8873                 7 + /* HDP_flush */
8874                 4 + /* VGT_flush */
8875                 14 + /* CE_META */
8876                 31 + /* DE_META */
8877                 3 + /* CNTX_CTRL */
8878                 5 + /* HDP_INVL */
8879                 8 + 8 + /* FENCE x2 */
8880                 2 + /* SWITCH_BUFFER */
8881                 8, /* gfx_v10_0_emit_mem_sync */
8882         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8883         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8884         .emit_fence = gfx_v10_0_ring_emit_fence,
8885         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8886         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8887         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8888         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8889         .test_ring = gfx_v10_0_ring_test_ring,
8890         .test_ib = gfx_v10_0_ring_test_ib,
8891         .insert_nop = amdgpu_ring_insert_nop,
8892         .pad_ib = amdgpu_ring_generic_pad_ib,
8893         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8894         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8895         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8896         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8897         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8898         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8899         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8900         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8901         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8902         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8903         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8904 };
8905
8906 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8907         .type = AMDGPU_RING_TYPE_COMPUTE,
8908         .align_mask = 0xff,
8909         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8910         .support_64bit_ptrs = true,
8911         .vmhub = AMDGPU_GFXHUB_0,
8912         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8913         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8914         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8915         .emit_frame_size =
8916                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8917                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8918                 5 + /* hdp invalidate */
8919                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8920                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8921                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8922                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8923                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8924                 8, /* gfx_v10_0_emit_mem_sync */
8925         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8926         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8927         .emit_fence = gfx_v10_0_ring_emit_fence,
8928         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8929         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8930         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8931         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8932         .test_ring = gfx_v10_0_ring_test_ring,
8933         .test_ib = gfx_v10_0_ring_test_ib,
8934         .insert_nop = amdgpu_ring_insert_nop,
8935         .pad_ib = amdgpu_ring_generic_pad_ib,
8936         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8937         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8938         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8939         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8940 };
8941
8942 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8943         .type = AMDGPU_RING_TYPE_KIQ,
8944         .align_mask = 0xff,
8945         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8946         .support_64bit_ptrs = true,
8947         .vmhub = AMDGPU_GFXHUB_0,
8948         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8949         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8950         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8951         .emit_frame_size =
8952                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8953                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8954                 5 + /*hdp invalidate */
8955                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8956                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8957                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8958                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8959                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8960         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8961         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8962         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8963         .test_ring = gfx_v10_0_ring_test_ring,
8964         .test_ib = gfx_v10_0_ring_test_ib,
8965         .insert_nop = amdgpu_ring_insert_nop,
8966         .pad_ib = amdgpu_ring_generic_pad_ib,
8967         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8968         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8969         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8970         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8971 };
8972
8973 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8974 {
8975         int i;
8976
8977         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8978
8979         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8980                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8981
8982         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8983                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8984 }
8985
8986 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8987         .set = gfx_v10_0_set_eop_interrupt_state,
8988         .process = gfx_v10_0_eop_irq,
8989 };
8990
8991 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8992         .set = gfx_v10_0_set_priv_reg_fault_state,
8993         .process = gfx_v10_0_priv_reg_irq,
8994 };
8995
8996 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8997         .set = gfx_v10_0_set_priv_inst_fault_state,
8998         .process = gfx_v10_0_priv_inst_irq,
8999 };
9000
9001 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9002         .set = gfx_v10_0_kiq_set_interrupt_state,
9003         .process = gfx_v10_0_kiq_irq,
9004 };
9005
9006 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9007 {
9008         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9009         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9010
9011         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9012         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9013
9014         adev->gfx.priv_reg_irq.num_types = 1;
9015         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9016
9017         adev->gfx.priv_inst_irq.num_types = 1;
9018         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9019 }
9020
9021 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9022 {
9023         switch (adev->asic_type) {
9024         case CHIP_NAVI10:
9025         case CHIP_NAVI14:
9026         case CHIP_SIENNA_CICHLID:
9027         case CHIP_NAVY_FLOUNDER:
9028         case CHIP_VANGOGH:
9029         case CHIP_DIMGREY_CAVEFISH:
9030                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9031                 break;
9032         case CHIP_NAVI12:
9033                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9034                 break;
9035         default:
9036                 break;
9037         }
9038 }
9039
9040 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9041 {
9042         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9043                             adev->gfx.config.max_sh_per_se *
9044                             adev->gfx.config.max_shader_engines;
9045
9046         adev->gds.gds_size = 0x10000;
9047         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9048         adev->gds.gws_size = 64;
9049         adev->gds.oa_size = 16;
9050 }
9051
9052 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9053                                                           u32 bitmap)
9054 {
9055         u32 data;
9056
9057         if (!bitmap)
9058                 return;
9059
9060         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9061         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9062
9063         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9064 }
9065
9066 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9067 {
9068         u32 data, wgp_bitmask;
9069         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9070         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9071
9072         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9073         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9074
9075         wgp_bitmask =
9076                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9077
9078         return (~data) & wgp_bitmask;
9079 }
9080
9081 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9082 {
9083         u32 wgp_idx, wgp_active_bitmap;
9084         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9085
9086         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9087         cu_active_bitmap = 0;
9088
9089         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9090                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9091                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9092                 if (wgp_active_bitmap & (1 << wgp_idx))
9093                         cu_active_bitmap |= cu_bitmap_per_wgp;
9094         }
9095
9096         return cu_active_bitmap;
9097 }
9098
9099 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9100                                  struct amdgpu_cu_info *cu_info)
9101 {
9102         int i, j, k, counter, active_cu_number = 0;
9103         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9104         unsigned disable_masks[4 * 2];
9105
9106         if (!adev || !cu_info)
9107                 return -EINVAL;
9108
9109         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9110
9111         mutex_lock(&adev->grbm_idx_mutex);
9112         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9113                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9114                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9115                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9116                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9117                                 continue;
9118                         mask = 1;
9119                         ao_bitmap = 0;
9120                         counter = 0;
9121                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9122                         if (i < 4 && j < 2)
9123                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9124                                         adev, disable_masks[i * 2 + j]);
9125                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9126                         cu_info->bitmap[i][j] = bitmap;
9127
9128                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9129                                 if (bitmap & mask) {
9130                                         if (counter < adev->gfx.config.max_cu_per_sh)
9131                                                 ao_bitmap |= mask;
9132                                         counter++;
9133                                 }
9134                                 mask <<= 1;
9135                         }
9136                         active_cu_number += counter;
9137                         if (i < 2 && j < 2)
9138                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9139                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9140                 }
9141         }
9142         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9143         mutex_unlock(&adev->grbm_idx_mutex);
9144
9145         cu_info->number = active_cu_number;
9146         cu_info->ao_cu_mask = ao_cu_mask;
9147         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9148
9149         return 0;
9150 }
9151
9152 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9153 {
9154         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9155
9156         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9157         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9158         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9159
9160         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9161         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9162         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9163
9164         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9165                                                 adev->gfx.config.max_shader_engines);
9166         disabled_sa = efuse_setting | vbios_setting;
9167         disabled_sa &= max_sa_mask;
9168
9169         return disabled_sa;
9170 }
9171
9172 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9173 {
9174         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9175         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9176
9177         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9178
9179         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9180         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9181         max_shader_engines = adev->gfx.config.max_shader_engines;
9182
9183         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9184                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9185                 disabled_sa_per_se &= max_sa_per_se_mask;
9186                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9187                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9188                         break;
9189                 }
9190         }
9191 }
9192
9193 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9194 {
9195         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9196                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9197                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9198                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9199
9200         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9201         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9202                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9203                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9204                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9205                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9206
9207         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9208                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9209                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9210                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9211
9212         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9213
9214         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9215                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9216 }
9217
9218 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9219 {
9220         .type = AMD_IP_BLOCK_TYPE_GFX,
9221         .major = 10,
9222         .minor = 0,
9223         .rev = 0,
9224         .funcs = &gfx_v10_0_ip_funcs,
9225 };