drivers/gpu/drm/mediatek/mtk_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/component.h>
   8 #include <linux/iopoll.h>
   9 #include <linux/irq.h>
  10 #include <linux/of.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/phy/phy.h>
  13 #include <linux/platform_device.h>
  14
  15 #include <video/mipi_display.h>
  16 #include <video/videomode.h>
  17
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_bridge.h>
  20 #include <drm/drm_bridge_connector.h>
  21 #include <drm/drm_mipi_dsi.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drm_print.h>
  25 #include <drm/drm_probe_helper.h>
  26 #include <drm/drm_simple_kms_helper.h>
  27
  28 #include "mtk_drm_ddp_comp.h"
  29
  30 #define DSI_START               0x00
  31
  32 #define DSI_INTEN               0x08
  33
  34 #define DSI_INTSTA              0x0c
  35 #define LPRX_RD_RDY_INT_FLAG            BIT(0)
  36 #define CMD_DONE_INT_FLAG               BIT(1)
  37 #define TE_RDY_INT_FLAG                 BIT(2)
  38 #define VM_DONE_INT_FLAG                BIT(3)
  39 #define EXT_TE_RDY_INT_FLAG             BIT(4)
  40 #define DSI_BUSY                        BIT(31)
  41
  42 #define DSI_CON_CTRL            0x10
  43 #define DSI_RESET                       BIT(0)
  44 #define DSI_EN                          BIT(1)
  45 #define DPHY_RESET                      BIT(2)
  46
  47 #define DSI_MODE_CTRL           0x14
  48 #define MODE                            (3)
  49 #define CMD_MODE                        0
  50 #define SYNC_PULSE_MODE                 1
  51 #define SYNC_EVENT_MODE                 2
  52 #define BURST_MODE                      3
  53 #define FRM_MODE                        BIT(16)
  54 #define MIX_MODE                        BIT(17)
  55
  56 #define DSI_TXRX_CTRL           0x18
  57 #define VC_NUM                          BIT(1)
  58 #define LANE_NUM                        (0xf << 2)
  59 #define DIS_EOT                         BIT(6)
  60 #define NULL_EN                         BIT(7)
  61 #define TE_FREERUN                      BIT(8)
  62 #define EXT_TE_EN                       BIT(9)
  63 #define EXT_TE_EDGE                     BIT(10)
  64 #define MAX_RTN_SIZE                    (0xf << 12)
  65 #define HSTX_CKLP_EN                    BIT(16)
  66
  67 #define DSI_PSCTRL              0x1c
  68 #define DSI_PS_WC                       0x3fff
  69 #define DSI_PS_SEL                      (3 << 16)
  70 #define PACKED_PS_16BIT_RGB565          (0 << 16)
  71 #define LOOSELY_PS_18BIT_RGB666         (1 << 16)
  72 #define PACKED_PS_18BIT_RGB666          (2 << 16)
  73 #define PACKED_PS_24BIT_RGB888          (3 << 16)
  74
  75 #define DSI_VSA_NL              0x20
  76 #define DSI_VBP_NL              0x24
  77 #define DSI_VFP_NL              0x28
  78 #define DSI_VACT_NL             0x2C
  79 #define DSI_SIZE_CON            0x38
  80 #define DSI_HSA_WC              0x50
  81 #define DSI_HBP_WC              0x54
  82 #define DSI_HFP_WC              0x58
  83
  84 #define DSI_CMDQ_SIZE           0x60
  85 #define CMDQ_SIZE                       0x3f
  86
  87 #define DSI_HSTX_CKL_WC         0x64
  88
  89 #define DSI_RX_DATA0            0x74
  90 #define DSI_RX_DATA1            0x78
  91 #define DSI_RX_DATA2            0x7c
  92 #define DSI_RX_DATA3            0x80
  93
  94 #define DSI_RACK                0x84
  95 #define RACK                            BIT(0)
  96
  97 #define DSI_PHY_LCCON           0x104
  98 #define LC_HS_TX_EN                     BIT(0)
  99 #define LC_ULPM_EN                      BIT(1)
 100 #define LC_WAKEUP_EN                    BIT(2)
 101
 102 #define DSI_PHY_LD0CON          0x108
 103 #define LD0_HS_TX_EN                    BIT(0)
 104 #define LD0_ULPM_EN                     BIT(1)
 105 #define LD0_WAKEUP_EN                   BIT(2)
 106
 107 #define DSI_PHY_TIMECON0        0x110
 108 #define LPX                             (0xff << 0)
 109 #define HS_PREP                         (0xff << 8)
 110 #define HS_ZERO                         (0xff << 16)
 111 #define HS_TRAIL                        (0xff << 24)
 112
 113 #define DSI_PHY_TIMECON1        0x114
 114 #define TA_GO                           (0xff << 0)
 115 #define TA_SURE                         (0xff << 8)
 116 #define TA_GET                          (0xff << 16)
 117 #define DA_HS_EXIT                      (0xff << 24)
 118
 119 #define DSI_PHY_TIMECON2        0x118
 120 #define CONT_DET                        (0xff << 0)
 121 #define CLK_ZERO                        (0xff << 16)
 122 #define CLK_TRAIL                       (0xff << 24)
 123
 124 #define DSI_PHY_TIMECON3        0x11c
 125 #define CLK_HS_PREP                     (0xff << 0)
 126 #define CLK_HS_POST                     (0xff << 8)
 127 #define CLK_HS_EXIT                     (0xff << 16)
 128
 129 #define DSI_VM_CMD_CON          0x130
 130 #define VM_CMD_EN                       BIT(0)
 131 #define TS_VFP_EN                       BIT(5)
 132
 133 #define DSI_SHADOW_DEBUG        0x190U
 134 #define FORCE_COMMIT                    BIT(0)
 135 #define BYPASS_SHADOW                   BIT(1)
 136
 137 #define CONFIG                          (0xff << 0)
 138 #define SHORT_PACKET                    0
 139 #define LONG_PACKET                     2
 140 #define BTA                             BIT(2)
 141 #define DATA_ID                         (0xff << 8)
 142 #define DATA_0                          (0xff << 16)
 143 #define DATA_1                          (0xff << 24)
 144
 145 #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 146
 147 #define MTK_DSI_HOST_IS_READ(type) \
 148         ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
 149         (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
 150         (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
 151         (type == MIPI_DSI_DCS_READ))
 152
 153 struct mtk_phy_timing {
 154         u32 lpx;
 155         u32 da_hs_prepare;
 156         u32 da_hs_zero;
 157         u32 da_hs_trail;
 158
 159         u32 ta_go;
 160         u32 ta_sure;
 161         u32 ta_get;
 162         u32 da_hs_exit;
 163
 164         u32 clk_hs_zero;
 165         u32 clk_hs_trail;
 166
 167         u32 clk_hs_prepare;
 168         u32 clk_hs_post;
 169         u32 clk_hs_exit;
 170 };
 171
 172 struct phy;
 173
 174 struct mtk_dsi_driver_data {
 175         const u32 reg_cmdq_off;
 176         bool has_shadow_ctl;
 177         bool has_size_ctl;
 178 };
 179
 180 struct mtk_dsi {
 181         struct mtk_ddp_comp ddp_comp;
 182         struct device *dev;
 183         struct mipi_dsi_host host;
 184         struct drm_encoder encoder;
 185         struct drm_bridge bridge;
 186         struct drm_bridge *next_bridge;
 187         struct drm_connector *connector;
 188         struct phy *phy;
 189
 190         void __iomem *regs;
 191
 192         struct clk *engine_clk;
 193         struct clk *digital_clk;
 194         struct clk *hs_clk;
 195
 196         u32 data_rate;
 197
 198         unsigned long mode_flags;
 199         enum mipi_dsi_pixel_format format;
 200         unsigned int lanes;
 201         struct videomode vm;
 202         struct mtk_phy_timing phy_timing;
 203         int refcount;
 204         bool enabled;
 205         u32 irq_data;
 206         wait_queue_head_t irq_wait_queue;
 207         const struct mtk_dsi_driver_data *driver_data;
 208 };
 209
 210 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)
 211 {
 212         return container_of(b, struct mtk_dsi, bridge);
 213 }
 214
 215 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
 216 {
 217         return container_of(h, struct mtk_dsi, host);
 218 }
 219
 220 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
 221 {
 222         u32 temp = readl(dsi->regs + offset);
 223
 224         writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 225 }
 226
 227 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 228 {
 229         u32 timcon0, timcon1, timcon2, timcon3;
 230         u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
 231         struct mtk_phy_timing *timing = &dsi->phy_timing;
 232
 233         timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
 234         timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
 235         timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
 236                              timing->da_hs_prepare;
 237         timing->da_hs_trail = timing->da_hs_prepare + 1;
 238
 239         timing->ta_go = 4 * timing->lpx - 2;
 240         timing->ta_sure = timing->lpx + 2;
 241         timing->ta_get = 4 * timing->lpx;
 242         timing->da_hs_exit = 2 * timing->lpx + 1;
 243
 244         timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
 245         timing->clk_hs_post = timing->clk_hs_prepare + 8;
 246         timing->clk_hs_trail = timing->clk_hs_prepare;
 247         timing->clk_hs_zero = timing->clk_hs_trail * 4;
 248         timing->clk_hs_exit = 2 * timing->clk_hs_trail;
 249
 250         timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
 251                   timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
 252         timcon1 = timing->ta_go | timing->ta_sure << 8 |
 253                   timing->ta_get << 16 | timing->da_hs_exit << 24;
 254         timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
 255                   timing->clk_hs_trail << 24;
 256         timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
 257                   timing->clk_hs_exit << 16;
 258
 259         writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
 260         writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
 261         writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
 262         writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
 263 }
 264
 265 static void mtk_dsi_enable(struct mtk_dsi *dsi)
 266 {
 267         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
 268 }
 269
 270 static void mtk_dsi_disable(struct mtk_dsi *dsi)
 271 {
 272         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 273 }
 274
 275 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 276 {
 277         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
 278         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 279 }
 280
 281 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
 282 {
 283         mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
 284         mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
 285 }
 286
 287 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 288 {
 289         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 290         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 291 }
 292
 293 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 294 {
 295         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 296         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
 297         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 298 }
 299
 300 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 301 {
 302         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
 303         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 304 }
 305
 306 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 307 {
 308         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 309         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
 310         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 311 }
 312
 313 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 314 {
 315         return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
 316 }
 317
 318 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 319 {
 320         if (enter && !mtk_dsi_clk_hs_state(dsi))
 321                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
 322         else if (!enter && mtk_dsi_clk_hs_state(dsi))
 323                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 324 }
 325
 326 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
 327 {
 328         u32 vid_mode = CMD_MODE;
 329
 330         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 331                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 332                         vid_mode = BURST_MODE;
 333                 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 334                         vid_mode = SYNC_PULSE_MODE;
 335                 else
 336                         vid_mode = SYNC_EVENT_MODE;
 337         }
 338
 339         writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 340 }
 341
 342 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
 343 {
 344         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
 345         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
 346 }
 347
 348 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
 349 {
 350         struct videomode *vm = &dsi->vm;
 351         u32 dsi_buf_bpp, ps_wc;
 352         u32 ps_bpp_mode;
 353
 354         if (dsi->format == MIPI_DSI_FMT_RGB565)
 355                 dsi_buf_bpp = 2;
 356         else
 357                 dsi_buf_bpp = 3;
 358
 359         ps_wc = vm->hactive * dsi_buf_bpp;
 360         ps_bpp_mode = ps_wc;
 361
 362         switch (dsi->format) {
 363         case MIPI_DSI_FMT_RGB888:
 364                 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
 365                 break;
 366         case MIPI_DSI_FMT_RGB666:
 367                 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
 368                 break;
 369         case MIPI_DSI_FMT_RGB666_PACKED:
 370                 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
 371                 break;
 372         case MIPI_DSI_FMT_RGB565:
 373                 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
 374                 break;
 375         }
 376
 377         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 378         writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
 379         writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 380 }
 381
 382 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
 383 {
 384         u32 tmp_reg;
 385
 386         switch (dsi->lanes) {
 387         case 1:
 388                 tmp_reg = 1 << 2;
 389                 break;
 390         case 2:
 391                 tmp_reg = 3 << 2;
 392                 break;
 393         case 3:
 394                 tmp_reg = 7 << 2;
 395                 break;
 396         case 4:
 397                 tmp_reg = 0xf << 2;
 398                 break;
 399         default:
 400                 tmp_reg = 0xf << 2;
 401                 break;
 402         }
 403
 404         tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
 405         tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
 406
 407         writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 408 }
 409
 410 static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
 411 {
 412         u32 dsi_tmp_buf_bpp;
 413         u32 tmp_reg;
 414
 415         switch (dsi->format) {
 416         case MIPI_DSI_FMT_RGB888:
 417                 tmp_reg = PACKED_PS_24BIT_RGB888;
 418                 dsi_tmp_buf_bpp = 3;
 419                 break;
 420         case MIPI_DSI_FMT_RGB666:
 421                 tmp_reg = LOOSELY_PS_18BIT_RGB666;
 422                 dsi_tmp_buf_bpp = 3;
 423                 break;
 424         case MIPI_DSI_FMT_RGB666_PACKED:
 425                 tmp_reg = PACKED_PS_18BIT_RGB666;
 426                 dsi_tmp_buf_bpp = 3;
 427                 break;
 428         case MIPI_DSI_FMT_RGB565:
 429                 tmp_reg = PACKED_PS_16BIT_RGB565;
 430                 dsi_tmp_buf_bpp = 2;
 431                 break;
 432         default:
 433                 tmp_reg = PACKED_PS_24BIT_RGB888;
 434                 dsi_tmp_buf_bpp = 3;
 435                 break;
 436         }
 437
 438         tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
 439         writel(tmp_reg, dsi->regs + DSI_PSCTRL);
 440 }
 441
 442 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 443 {
 444         u32 horizontal_sync_active_byte;
 445         u32 horizontal_backporch_byte;
 446         u32 horizontal_frontporch_byte;
 447         u32 dsi_tmp_buf_bpp, data_phy_cycles;
 448         struct mtk_phy_timing *timing = &dsi->phy_timing;
 449
 450         struct videomode *vm = &dsi->vm;
 451
 452         if (dsi->format == MIPI_DSI_FMT_RGB565)
 453                 dsi_tmp_buf_bpp = 2;
 454         else
 455                 dsi_tmp_buf_bpp = 3;
 456
 457         writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
 458         writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
 459         writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
 460         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 461
 462         if (dsi->driver_data->has_size_ctl)
 463                 writel(vm->vactive << 16 | vm->hactive,
 464                        dsi->regs + DSI_SIZE_CON);
 465
 466         horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 467
 468         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 469                 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp;
 470         else
 471                 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *
 472                                             dsi_tmp_buf_bpp;
 473
 474         data_phy_cycles = timing->lpx + timing->da_hs_prepare +
 475                           timing->da_hs_zero + timing->da_hs_exit;
 476
 477         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
 478                 if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
 479                     data_phy_cycles * dsi->lanes + 18) {
 480                         horizontal_frontporch_byte =
 481                                 vm->hfront_porch * dsi_tmp_buf_bpp -
 482                                 (data_phy_cycles * dsi->lanes + 18) *
 483                                 vm->hfront_porch /
 484                                 (vm->hfront_porch + vm->hback_porch);
 485
 486                         horizontal_backporch_byte =
 487                                 horizontal_backporch_byte -
 488                                 (data_phy_cycles * dsi->lanes + 18) *
 489                                 vm->hback_porch /
 490                                 (vm->hfront_porch + vm->hback_porch);
 491                 } else {
 492                         DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
 493                         horizontal_frontporch_byte = vm->hfront_porch *
 494                                                      dsi_tmp_buf_bpp;
 495                 }
 496         } else {
 497                 if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
 498                     data_phy_cycles * dsi->lanes + 12) {
 499                         horizontal_frontporch_byte =
 500                                 vm->hfront_porch * dsi_tmp_buf_bpp -
 501                                 (data_phy_cycles * dsi->lanes + 12) *
 502                                 vm->hfront_porch /
 503                                 (vm->hfront_porch + vm->hback_porch);
 504                         horizontal_backporch_byte = horizontal_backporch_byte -
 505                                 (data_phy_cycles * dsi->lanes + 12) *
 506                                 vm->hback_porch /
 507                                 (vm->hfront_porch + vm->hback_porch);
 508                 } else {
 509                         DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
 510                         horizontal_frontporch_byte = vm->hfront_porch *
 511                                                      dsi_tmp_buf_bpp;
 512                 }
 513         }
 514
 515         writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 516         writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 517         writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
 518
 519         mtk_dsi_ps_control(dsi);
 520 }
 521
 522 static void mtk_dsi_start(struct mtk_dsi *dsi)
 523 {
 524         writel(0, dsi->regs + DSI_START);
 525         writel(1, dsi->regs + DSI_START);
 526 }
 527
 528 static void mtk_dsi_stop(struct mtk_dsi *dsi)
 529 {
 530         writel(0, dsi->regs + DSI_START);
 531 }
 532
 533 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
 534 {
 535         writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
 536 }
 537
 538 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
 539 {
 540         u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 541
 542         writel(inten, dsi->regs + DSI_INTEN);
 543 }
 544
 545 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
 546 {
 547         dsi->irq_data |= irq_bit;
 548 }
 549
 550 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
 551 {
 552         dsi->irq_data &= ~irq_bit;
 553 }
 554
 555 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
 556                                      unsigned int timeout)
 557 {
 558         s32 ret = 0;
 559         unsigned long jiffies = msecs_to_jiffies(timeout);
 560
 561         ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
 562                                                dsi->irq_data & irq_flag,
 563                                                jiffies);
 564         if (ret == 0) {
 565                 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
 566
 567                 mtk_dsi_enable(dsi);
 568                 mtk_dsi_reset_engine(dsi);
 569         }
 570
 571         return ret;
 572 }
 573
 574 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
 575 {
 576         struct mtk_dsi *dsi = dev_id;
 577         u32 status, tmp;
 578         u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 579
 580         status = readl(dsi->regs + DSI_INTSTA) & flag;
 581
 582         if (status) {
 583                 do {
 584                         mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
 585                         tmp = readl(dsi->regs + DSI_INTSTA);
 586                 } while (tmp & DSI_BUSY);
 587
 588                 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
 589                 mtk_dsi_irq_data_set(dsi, status);
 590                 wake_up_interruptible(&dsi->irq_wait_queue);
 591         }
 592
 593         return IRQ_HANDLED;
 594 }
 595
 596 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
 597 {
 598         mtk_dsi_irq_data_clear(dsi, irq_flag);
 599         mtk_dsi_set_cmd_mode(dsi);
 600
 601         if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
 602                 DRM_ERROR("failed to switch cmd mode\n");
 603                 return -ETIME;
 604         } else {
 605                 return 0;
 606         }
 607 }
 608
 609 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 610 {
 611         struct device *dev = dsi->host.dev;
 612         int ret;
 613         u32 bit_per_pixel;
 614
 615         if (++dsi->refcount != 1)
 616                 return 0;
 617
 618         switch (dsi->format) {
 619         case MIPI_DSI_FMT_RGB565:
 620                 bit_per_pixel = 16;
 621                 break;
 622         case MIPI_DSI_FMT_RGB666_PACKED:
 623                 bit_per_pixel = 18;
 624                 break;
 625         case MIPI_DSI_FMT_RGB666:
 626         case MIPI_DSI_FMT_RGB888:
 627         default:
 628                 bit_per_pixel = 24;
 629                 break;
 630         }
 631
 632         dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
 633                                           dsi->lanes);
 634
 635         ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
 636         if (ret < 0) {
 637                 dev_err(dev, "Failed to set data rate: %d\n", ret);
 638                 goto err_refcount;
 639         }
 640
 641         phy_power_on(dsi->phy);
 642
 643         ret = clk_prepare_enable(dsi->engine_clk);
 644         if (ret < 0) {
 645                 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
 646                 goto err_phy_power_off;
 647         }
 648
 649         ret = clk_prepare_enable(dsi->digital_clk);
 650         if (ret < 0) {
 651                 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
 652                 goto err_disable_engine_clk;
 653         }
 654
 655         mtk_dsi_enable(dsi);
 656
 657         if (dsi->driver_data->has_shadow_ctl)
 658                 writel(FORCE_COMMIT | BYPASS_SHADOW,
 659                        dsi->regs + DSI_SHADOW_DEBUG);
 660
 661         mtk_dsi_reset_engine(dsi);
 662         mtk_dsi_phy_timconfig(dsi);
 663
 664         mtk_dsi_rxtx_control(dsi);
 665         usleep_range(30, 100);
 666         mtk_dsi_reset_dphy(dsi);
 667         mtk_dsi_ps_control_vact(dsi);
 668         mtk_dsi_set_vm_cmd(dsi);
 669         mtk_dsi_config_vdo_timing(dsi);
 670         mtk_dsi_set_interrupt_enable(dsi);
 671
 672         mtk_dsi_clk_ulp_mode_leave(dsi);
 673         mtk_dsi_lane0_ulp_mode_leave(dsi);
 674         mtk_dsi_clk_hs_mode(dsi, 0);
 675
 676         return 0;
 677 err_disable_engine_clk:
 678         clk_disable_unprepare(dsi->engine_clk);
 679 err_phy_power_off:
 680         phy_power_off(dsi->phy);
 681 err_refcount:
 682         dsi->refcount--;
 683         return ret;
 684 }
 685
 686 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 687 {
 688         if (WARN_ON(dsi->refcount == 0))
 689                 return;
 690
 691         if (--dsi->refcount != 0)
 692                 return;
 693
 694         /*
 695          * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
 696          * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
 697          * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
 698          * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
 699          * after dsi is fully set.
 700          */
 701         mtk_dsi_stop(dsi);
 702
 703         mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
 704         mtk_dsi_reset_engine(dsi);
 705         mtk_dsi_lane0_ulp_mode_enter(dsi);
 706         mtk_dsi_clk_ulp_mode_enter(dsi);
 707
 708         mtk_dsi_disable(dsi);
 709
 710         clk_disable_unprepare(dsi->engine_clk);
 711         clk_disable_unprepare(dsi->digital_clk);
 712
 713         phy_power_off(dsi->phy);
 714 }
 715
 716 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 717 {
 718         int ret;
 719
 720         if (dsi->enabled)
 721                 return;
 722
 723         ret = mtk_dsi_poweron(dsi);
 724         if (ret < 0) {
 725                 DRM_ERROR("failed to power on dsi\n");
 726                 return;
 727         }
 728
 729         mtk_dsi_set_mode(dsi);
 730         mtk_dsi_clk_hs_mode(dsi, 1);
 731
 732         mtk_dsi_start(dsi);
 733
 734         dsi->enabled = true;
 735 }
 736
 737 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
 738 {
 739         if (!dsi->enabled)
 740                 return;
 741
 742         mtk_dsi_poweroff(dsi);
 743
 744         dsi->enabled = false;
 745 }
 746
 747 static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,
 748                                  enum drm_bridge_attach_flags flags)
 749 {
 750         struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 751
 752         /* Attach the panel or bridge to the dsi bridge */
 753         return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
 754                                  &dsi->bridge, flags);
 755 }
 756
 757 static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,
 758                                     const struct drm_display_mode *mode,
 759                                     const struct drm_display_mode *adjusted)
 760 {
 761         struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 762
 763         drm_display_mode_to_videomode(adjusted, &dsi->vm);
 764 }
 765
 766 static void mtk_dsi_bridge_disable(struct drm_bridge *bridge)
 767 {
 768         struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 769
 770         mtk_output_dsi_disable(dsi);
 771 }
 772
 773 static void mtk_dsi_bridge_enable(struct drm_bridge *bridge)
 774 {
 775         struct mtk_dsi *dsi = bridge_to_dsi(bridge);
 776
 777         mtk_output_dsi_enable(dsi);
 778 }
 779
 780 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
 781         .attach = mtk_dsi_bridge_attach,
 782         .disable = mtk_dsi_bridge_disable,
 783         .enable = mtk_dsi_bridge_enable,
 784         .mode_set = mtk_dsi_bridge_mode_set,
 785 };
 786
 787 static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
 788 {
 789         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 790
 791         mtk_dsi_poweron(dsi);
 792 }
 793
 794 static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
 795 {
 796         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 797
 798         mtk_dsi_poweroff(dsi);
 799 }
 800
 801 static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
 802         .start = mtk_dsi_ddp_start,
 803         .stop = mtk_dsi_ddp_stop,
 804 };
 805
 806 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 807                                struct mipi_dsi_device *device)
 808 {
 809         struct mtk_dsi *dsi = host_to_dsi(host);
 810
 811         dsi->lanes = device->lanes;
 812         dsi->format = device->format;
 813         dsi->mode_flags = device->mode_flags;
 814
 815         return 0;
 816 }
 817
 818 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
 819 {
 820         int ret;
 821         u32 val;
 822
 823         ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
 824                                  4, 2000000);
 825         if (ret) {
 826                 DRM_WARN("polling dsi wait not busy timeout!\n");
 827
 828                 mtk_dsi_enable(dsi);
 829                 mtk_dsi_reset_engine(dsi);
 830         }
 831 }
 832
 833 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
 834 {
 835         switch (type) {
 836         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
 837         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
 838                 return 1;
 839         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
 840         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
 841                 return 2;
 842         case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
 843         case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
 844                 return read_data[1] + read_data[2] * 16;
 845         case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
 846                 DRM_INFO("type is 0x02, try again\n");
 847                 break;
 848         default:
 849                 DRM_INFO("type(0x%x) not recognized\n", type);
 850                 break;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
 857 {
 858         const char *tx_buf = msg->tx_buf;
 859         u8 config, cmdq_size, cmdq_off, type = msg->type;
 860         u32 reg_val, cmdq_mask, i;
 861         u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
 862
 863         if (MTK_DSI_HOST_IS_READ(type))
 864                 config = BTA;
 865         else
 866                 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
 867
 868         if (msg->tx_len > 2) {
 869                 cmdq_size = 1 + (msg->tx_len + 3) / 4;
 870                 cmdq_off = 4;
 871                 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
 872                 reg_val = (msg->tx_len << 16) | (type << 8) | config;
 873         } else {
 874                 cmdq_size = 1;
 875                 cmdq_off = 2;
 876                 cmdq_mask = CONFIG | DATA_ID;
 877                 reg_val = (type << 8) | config;
 878         }
 879
 880         for (i = 0; i < msg->tx_len; i++)
 881                 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
 882                              (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
 883                              tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
 884
 885         mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
 886         mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
 887 }
 888
 889 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
 890                                      const struct mipi_dsi_msg *msg, u8 flag)
 891 {
 892         mtk_dsi_wait_for_idle(dsi);
 893         mtk_dsi_irq_data_clear(dsi, flag);
 894         mtk_dsi_cmdq(dsi, msg);
 895         mtk_dsi_start(dsi);
 896
 897         if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
 898                 return -ETIME;
 899         else
 900                 return 0;
 901 }
 902
 903 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
 904                                      const struct mipi_dsi_msg *msg)
 905 {
 906         struct mtk_dsi *dsi = host_to_dsi(host);
 907         u32 recv_cnt, i;
 908         u8 read_data[16];
 909         void *src_addr;
 910         u8 irq_flag = CMD_DONE_INT_FLAG;
 911
 912         if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
 913                 DRM_ERROR("dsi engine is not command mode\n");
 914                 return -EINVAL;
 915         }
 916
 917         if (MTK_DSI_HOST_IS_READ(msg->type))
 918                 irq_flag |= LPRX_RD_RDY_INT_FLAG;
 919
 920         if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
 921                 return -ETIME;
 922
 923         if (!MTK_DSI_HOST_IS_READ(msg->type))
 924                 return 0;
 925
 926         if (!msg->rx_buf) {
 927                 DRM_ERROR("dsi receive buffer size may be NULL\n");
 928                 return -EINVAL;
 929         }
 930
 931         for (i = 0; i < 16; i++)
 932                 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
 933
 934         recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
 935
 936         if (recv_cnt > 2)
 937                 src_addr = &read_data[4];
 938         else
 939                 src_addr = &read_data[1];
 940
 941         if (recv_cnt > 10)
 942                 recv_cnt = 10;
 943
 944         if (recv_cnt > msg->rx_len)
 945                 recv_cnt = msg->rx_len;
 946
 947         if (recv_cnt)
 948                 memcpy(msg->rx_buf, src_addr, recv_cnt);
 949
 950         DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
 951                  recv_cnt, *((u8 *)(msg->tx_buf)));
 952
 953         return recv_cnt;
 954 }
 955
 956 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
 957         .attach = mtk_dsi_host_attach,
 958         .transfer = mtk_dsi_host_transfer,
 959 };
 960
 961 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
 962 {
 963         int ret;
 964
 965         ret = drm_simple_encoder_init(drm, &dsi->encoder,
 966                                       DRM_MODE_ENCODER_DSI);
 967         if (ret) {
 968                 DRM_ERROR("Failed to encoder init to drm\n");
 969                 return ret;
 970         }
 971
 972         dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp);
 973
 974         ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
 975                                 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 976         if (ret)
 977                 goto err_cleanup_encoder;
 978
 979         dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
 980         if (IS_ERR(dsi->connector)) {
 981                 DRM_ERROR("Unable to create bridge connector\n");
 982                 ret = PTR_ERR(dsi->connector);
 983                 goto err_cleanup_encoder;
 984         }
 985         drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
 986
 987         return 0;
 988
 989 err_cleanup_encoder:
 990         drm_encoder_cleanup(&dsi->encoder);
 991         return ret;
 992 }
 993
 994 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
 995 {
 996         int ret;
 997         struct drm_device *drm = data;
 998         struct mtk_dsi *dsi = dev_get_drvdata(dev);
 999
1000         ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1001         if (ret < 0) {
1002                 dev_err(dev, "Failed to register component %pOF: %d\n",
1003                         dev->of_node, ret);
1004                 return ret;
1005         }
1006
1007         ret = mtk_dsi_encoder_init(drm, dsi);
1008         if (ret)
1009                 goto err_unregister;
1010
1011         return 0;
1012
1013 err_unregister:
1014         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1015         return ret;
1016 }
1017
1018 static void mtk_dsi_unbind(struct device *dev, struct device *master,
1019                            void *data)
1020 {
1021         struct drm_device *drm = data;
1022         struct mtk_dsi *dsi = dev_get_drvdata(dev);
1023
1024         drm_encoder_cleanup(&dsi->encoder);
1025         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1026 }
1027
1028 static const struct component_ops mtk_dsi_component_ops = {
1029         .bind = mtk_dsi_bind,
1030         .unbind = mtk_dsi_unbind,
1031 };
1032
1033 static int mtk_dsi_probe(struct platform_device *pdev)
1034 {
1035         struct mtk_dsi *dsi;
1036         struct device *dev = &pdev->dev;
1037         struct drm_panel *panel;
1038         struct resource *regs;
1039         int irq_num;
1040         int comp_id;
1041         int ret;
1042
1043         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1044         if (!dsi)
1045                 return -ENOMEM;
1046
1047         dsi->host.ops = &mtk_dsi_ops;
1048         dsi->host.dev = dev;
1049         ret = mipi_dsi_host_register(&dsi->host);
1050         if (ret < 0) {
1051                 dev_err(dev, "failed to register DSI host: %d\n", ret);
1052                 return ret;
1053         }
1054
1055         ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1056                                           &panel, &dsi->next_bridge);
1057         if (ret)
1058                 goto err_unregister_host;
1059
1060         if (panel) {
1061                 dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel);
1062                 if (IS_ERR(dsi->next_bridge)) {
1063                         ret = PTR_ERR(dsi->next_bridge);
1064                         goto err_unregister_host;
1065                 }
1066         }
1067
1068         dsi->driver_data = of_device_get_match_data(dev);
1069
1070         dsi->engine_clk = devm_clk_get(dev, "engine");
1071         if (IS_ERR(dsi->engine_clk)) {
1072                 ret = PTR_ERR(dsi->engine_clk);
1073
1074                 if (ret != -EPROBE_DEFER)
1075                         dev_err(dev, "Failed to get engine clock: %d\n", ret);
1076                 goto err_unregister_host;
1077         }
1078
1079         dsi->digital_clk = devm_clk_get(dev, "digital");
1080         if (IS_ERR(dsi->digital_clk)) {
1081                 ret = PTR_ERR(dsi->digital_clk);
1082
1083                 if (ret != -EPROBE_DEFER)
1084                         dev_err(dev, "Failed to get digital clock: %d\n", ret);
1085                 goto err_unregister_host;
1086         }
1087
1088         dsi->hs_clk = devm_clk_get(dev, "hs");
1089         if (IS_ERR(dsi->hs_clk)) {
1090                 ret = PTR_ERR(dsi->hs_clk);
1091                 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1092                 goto err_unregister_host;
1093         }
1094
1095         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1096         dsi->regs = devm_ioremap_resource(dev, regs);
1097         if (IS_ERR(dsi->regs)) {
1098                 ret = PTR_ERR(dsi->regs);
1099                 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1100                 goto err_unregister_host;
1101         }
1102
1103         dsi->phy = devm_phy_get(dev, "dphy");
1104         if (IS_ERR(dsi->phy)) {
1105                 ret = PTR_ERR(dsi->phy);
1106                 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1107                 goto err_unregister_host;
1108         }
1109
1110         comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1111         if (comp_id < 0) {
1112                 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1113                 ret = comp_id;
1114                 goto err_unregister_host;
1115         }
1116
1117         ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1118                                 &mtk_dsi_funcs);
1119         if (ret) {
1120                 dev_err(dev, "Failed to initialize component: %d\n", ret);
1121                 goto err_unregister_host;
1122         }
1123
1124         irq_num = platform_get_irq(pdev, 0);
1125         if (irq_num < 0) {
1126                 dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num);
1127                 ret = irq_num;
1128                 goto err_unregister_host;
1129         }
1130
1131         irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
1132         ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1133                                IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1134         if (ret) {
1135                 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1136                 goto err_unregister_host;
1137         }
1138
1139         init_waitqueue_head(&dsi->irq_wait_queue);
1140
1141         platform_set_drvdata(pdev, dsi);
1142
1143         dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
1144         dsi->bridge.of_node = dev->of_node;
1145         dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1146
1147         drm_bridge_add(&dsi->bridge);
1148
1149         ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
1150         if (ret) {
1151                 dev_err(&pdev->dev, "failed to add component: %d\n", ret);
1152                 goto err_unregister_host;
1153         }
1154
1155         return 0;
1156
1157 err_unregister_host:
1158         mipi_dsi_host_unregister(&dsi->host);
1159         return ret;
1160 }
1161
1162 static int mtk_dsi_remove(struct platform_device *pdev)
1163 {
1164         struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1165
1166         mtk_output_dsi_disable(dsi);
1167         drm_bridge_remove(&dsi->bridge);
1168         component_del(&pdev->dev, &mtk_dsi_component_ops);
1169         mipi_dsi_host_unregister(&dsi->host);
1170
1171         return 0;
1172 }
1173
1174 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1175         .reg_cmdq_off = 0x200,
1176 };
1177
1178 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1179         .reg_cmdq_off = 0x180,
1180 };
1181
1182 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1183         .reg_cmdq_off = 0x200,
1184         .has_shadow_ctl = true,
1185         .has_size_ctl = true,
1186 };
1187
1188 static const struct of_device_id mtk_dsi_of_match[] = {
1189         { .compatible = "mediatek,mt2701-dsi",
1190           .data = &mt2701_dsi_driver_data },
1191         { .compatible = "mediatek,mt8173-dsi",
1192           .data = &mt8173_dsi_driver_data },
1193         { .compatible = "mediatek,mt8183-dsi",
1194           .data = &mt8183_dsi_driver_data },
1195         { },
1196 };
1197
1198 struct platform_driver mtk_dsi_driver = {
1199         .probe = mtk_dsi_probe,
1200         .remove = mtk_dsi_remove,
1201         .driver = {
1202                 .name = "mtk-dsi",
1203                 .of_match_table = mtk_dsi_of_match,
1204         },
1205 };