drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #ifndef __SMU_CMN_H__
  24 #define __SMU_CMN_H__
  25
  26 #include "amdgpu_smu.h"
  27
  28 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
  29 int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
  30                                      uint16_t msg, uint32_t param);
  31 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
  32                                     enum smu_message_type msg,
  33                                     uint32_t param,
  34                                     uint32_t *read_arg);
  35
  36 int smu_cmn_send_smc_msg(struct smu_context *smu,
  37                          enum smu_message_type msg,
  38                          uint32_t *read_arg);
  39
  40 int smu_cmn_wait_for_response(struct smu_context *smu);
  41
  42 int smu_cmn_to_asic_specific_index(struct smu_context *smu,
  43                                    enum smu_cmn2asic_mapping_type type,
  44                                    uint32_t index);
  45
  46 int smu_cmn_feature_is_supported(struct smu_context *smu,
  47                                  enum smu_feature_mask mask);
  48
  49 int smu_cmn_feature_is_enabled(struct smu_context *smu,
  50                                enum smu_feature_mask mask);
  51
  52 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
  53                                 enum smu_clk_type clk_type);
  54
  55 int smu_cmn_get_enabled_mask(struct smu_context *smu,
  56                              uint32_t *feature_mask,
  57                              uint32_t num);
  58
  59 int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
  60                                         uint32_t *feature_mask,
  61                                         uint32_t num);
  62
  63 uint64_t smu_cmn_get_indep_throttler_status(
  64                                         const unsigned long dep_status,
  65                                         const uint8_t *throttler_map);
  66
  67 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
  68                                         uint64_t feature_mask,
  69                                         bool enabled);
  70
  71 int smu_cmn_feature_set_enabled(struct smu_context *smu,
  72                                 enum smu_feature_mask mask,
  73                                 bool enable);
  74
  75 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
  76                                    char *buf);
  77
  78 int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
  79                                 uint64_t new_mask);
  80
  81 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
  82                                                 bool no_hw_disablement,
  83                                                 enum smu_feature_mask mask);
  84
  85 int smu_cmn_get_smc_version(struct smu_context *smu,
  86                             uint32_t *if_version,
  87                             uint32_t *smu_version);
  88
  89 int smu_cmn_update_table(struct smu_context *smu,
  90                          enum smu_table_id table_index,
  91                          int argument,
  92                          void *table_data,
  93                          bool drv2smu);
  94
  95 int smu_cmn_write_watermarks_table(struct smu_context *smu);
  96
  97 int smu_cmn_write_pptable(struct smu_context *smu);
  98
  99 int smu_cmn_get_metrics_table_locked(struct smu_context *smu,
 100                                      void *metrics_table,
 101                                      bool bypass_cache);
 102
 103 int smu_cmn_get_metrics_table(struct smu_context *smu,
 104                               void *metrics_table,
 105                               bool bypass_cache);
 106
 107 void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev);
 108
 109 int smu_cmn_set_mp1_state(struct smu_context *smu,
 110                           enum pp_mp1_state mp1_state);
 111
 112 #endif
 113 #endif