drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "amdgpu_amdkfd.h"
  24 #include "amd_shared.h"
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "amdgpu_dma_buf.h"
  29 #include <linux/module.h>
  30 #include <linux/dma-buf.h>
  31 #include "amdgpu_xgmi.h"
  32 #include <uapi/linux/kfd_ioctl.h>
  33
  34 /* Total memory size in system memory and all GPU VRAM. Used to
  35  * estimate worst case amount of memory to reserve for page tables
  36  */
  37 uint64_t amdgpu_amdkfd_total_mem_size;
  38
  39 static bool kfd_initialized;
  40
  41 int amdgpu_amdkfd_init(void)
  42 {
  43         struct sysinfo si;
  44         int ret;
  45
  46         si_meminfo(&si);
  47         amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
  48         amdgpu_amdkfd_total_mem_size *= si.mem_unit;
  49
  50         ret = kgd2kfd_init();
  51         amdgpu_amdkfd_gpuvm_init_mem_limits();
  52         kfd_initialized = !ret;
  53
  54         return ret;
  55 }
  56
  57 void amdgpu_amdkfd_fini(void)
  58 {
  59         if (kfd_initialized) {
  60                 kgd2kfd_exit();
  61                 kfd_initialized = false;
  62         }
  63 }
  64
  65 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
  66 {
  67         bool vf = amdgpu_sriov_vf(adev);
  68
  69         if (!kfd_initialized)
  70                 return;
  71
  72         adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
  73                                       adev->pdev, adev->asic_type, vf);
  74
  75         if (adev->kfd.dev)
  76                 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
  77 }
  78
  79 /**
  80  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
  81  *                                setup amdkfd
  82  *
  83  * @adev: amdgpu_device pointer
  84  * @aperture_base: output returning doorbell aperture base physical address
  85  * @aperture_size: output returning doorbell aperture size in bytes
  86  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
  87  *
  88  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
  89  * takes doorbells required for its own rings and reports the setup to amdkfd.
  90  * amdgpu reserved doorbells are at the start of the doorbell aperture.
  91  */
  92 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
  93                                          phys_addr_t *aperture_base,
  94                                          size_t *aperture_size,
  95                                          size_t *start_offset)
  96 {
  97         /*
  98          * The first num_doorbells are used by amdgpu.
  99          * amdkfd takes whatever's left in the aperture.
 100          */
 101         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 102                 *aperture_base = adev->doorbell.base;
 103                 *aperture_size = adev->doorbell.size;
 104                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 105         } else {
 106                 *aperture_base = 0;
 107                 *aperture_size = 0;
 108                 *start_offset = 0;
 109         }
 110 }
 111
 112 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 113 {
 114         int i;
 115         int last_valid_bit;
 116
 117         if (adev->kfd.dev) {
 118                 struct kgd2kfd_shared_resources gpu_resources = {
 119                         .compute_vmid_bitmap =
 120                                 ((1 << AMDGPU_NUM_VMID) - 1) -
 121                                 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
 122                         .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
 123                         .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
 124                         .gpuvm_size = min(adev->vm_manager.max_pfn
 125                                           << AMDGPU_GPU_PAGE_SHIFT,
 126                                           AMDGPU_GMC_HOLE_START),
 127                         .drm_render_minor = adev_to_drm(adev)->render->index,
 128                         .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
 129
 130                 };
 131
 132                 /* this is going to have a few of the MSBs set that we need to
 133                  * clear
 134                  */
 135                 bitmap_complement(gpu_resources.cp_queue_bitmap,
 136                                   adev->gfx.mec.queue_bitmap,
 137                                   KGD_MAX_QUEUES);
 138
 139                 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
 140                  * nbits is not compile time constant
 141                  */
 142                 last_valid_bit = 1 /* only first MEC can have compute queues */
 143                                 * adev->gfx.mec.num_pipe_per_mec
 144                                 * adev->gfx.mec.num_queue_per_pipe;
 145                 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
 146                         clear_bit(i, gpu_resources.cp_queue_bitmap);
 147
 148                 amdgpu_doorbell_get_kfd_info(adev,
 149                                 &gpu_resources.doorbell_physical_address,
 150                                 &gpu_resources.doorbell_aperture_size,
 151                                 &gpu_resources.doorbell_start_offset);
 152
 153                 /* Since SOC15, BIF starts to statically use the
 154                  * lower 12 bits of doorbell addresses for routing
 155                  * based on settings in registers like
 156                  * SDMA0_DOORBELL_RANGE etc..
 157                  * In order to route a doorbell to CP engine, the lower
 158                  * 12 bits of its address has to be outside the range
 159                  * set for SDMA, VCN, and IH blocks.
 160                  */
 161                 if (adev->asic_type >= CHIP_VEGA10) {
 162                         gpu_resources.non_cp_doorbells_start =
 163                                         adev->doorbell_index.first_non_cp;
 164                         gpu_resources.non_cp_doorbells_end =
 165                                         adev->doorbell_index.last_non_cp;
 166                 }
 167
 168                 kgd2kfd_device_init(adev->kfd.dev, adev_to_drm(adev), &gpu_resources);
 169         }
 170 }
 171
 172 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
 173 {
 174         if (adev->kfd.dev) {
 175                 kgd2kfd_device_exit(adev->kfd.dev);
 176                 adev->kfd.dev = NULL;
 177         }
 178 }
 179
 180 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 181                 const void *ih_ring_entry)
 182 {
 183         if (adev->kfd.dev)
 184                 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
 185 }
 186
 187 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
 188 {
 189         if (adev->kfd.dev)
 190                 kgd2kfd_suspend(adev->kfd.dev, run_pm);
 191 }
 192
 193 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
 194 {
 195         int r = 0;
 196
 197         if (adev->kfd.dev)
 198                 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
 199
 200         return r;
 201 }
 202
 203 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
 204 {
 205         int r = 0;
 206
 207         if (adev->kfd.dev)
 208                 r = kgd2kfd_pre_reset(adev->kfd.dev);
 209
 210         return r;
 211 }
 212
 213 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
 214 {
 215         int r = 0;
 216
 217         if (adev->kfd.dev)
 218                 r = kgd2kfd_post_reset(adev->kfd.dev);
 219
 220         return r;
 221 }
 222
 223 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
 224 {
 225         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 226
 227         if (amdgpu_device_should_recover_gpu(adev))
 228                 amdgpu_device_gpu_recover(adev, NULL);
 229 }
 230
 231 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
 232                                 void **mem_obj, uint64_t *gpu_addr,
 233                                 void **cpu_ptr, bool cp_mqd_gfx9)
 234 {
 235         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 236         struct amdgpu_bo *bo = NULL;
 237         struct amdgpu_bo_param bp;
 238         int r;
 239         void *cpu_ptr_tmp = NULL;
 240
 241         memset(&bp, 0, sizeof(bp));
 242         bp.size = size;
 243         bp.byte_align = PAGE_SIZE;
 244         bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 245         bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 246         bp.type = ttm_bo_type_kernel;
 247         bp.resv = NULL;
 248
 249         if (cp_mqd_gfx9)
 250                 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
 251
 252         r = amdgpu_bo_create(adev, &bp, &bo);
 253         if (r) {
 254                 dev_err(adev->dev,
 255                         "failed to allocate BO for amdkfd (%d)\n", r);
 256                 return r;
 257         }
 258
 259         /* map the buffer */
 260         r = amdgpu_bo_reserve(bo, true);
 261         if (r) {
 262                 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
 263                 goto allocate_mem_reserve_bo_failed;
 264         }
 265
 266         r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
 267         if (r) {
 268                 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
 269                 goto allocate_mem_pin_bo_failed;
 270         }
 271
 272         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 273         if (r) {
 274                 dev_err(adev->dev, "%p bind failed\n", bo);
 275                 goto allocate_mem_kmap_bo_failed;
 276         }
 277
 278         r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
 279         if (r) {
 280                 dev_err(adev->dev,
 281                         "(%d) failed to map bo to kernel for amdkfd\n", r);
 282                 goto allocate_mem_kmap_bo_failed;
 283         }
 284
 285         *mem_obj = bo;
 286         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 287         *cpu_ptr = cpu_ptr_tmp;
 288
 289         amdgpu_bo_unreserve(bo);
 290
 291         return 0;
 292
 293 allocate_mem_kmap_bo_failed:
 294         amdgpu_bo_unpin(bo);
 295 allocate_mem_pin_bo_failed:
 296         amdgpu_bo_unreserve(bo);
 297 allocate_mem_reserve_bo_failed:
 298         amdgpu_bo_unref(&bo);
 299
 300         return r;
 301 }
 302
 303 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
 304 {
 305         struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
 306
 307         amdgpu_bo_reserve(bo, true);
 308         amdgpu_bo_kunmap(bo);
 309         amdgpu_bo_unpin(bo);
 310         amdgpu_bo_unreserve(bo);
 311         amdgpu_bo_unref(&(bo));
 312 }
 313
 314 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
 315                                 void **mem_obj)
 316 {
 317         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 318         struct amdgpu_bo *bo = NULL;
 319         struct amdgpu_bo_param bp;
 320         int r;
 321
 322         memset(&bp, 0, sizeof(bp));
 323         bp.size = size;
 324         bp.byte_align = 1;
 325         bp.domain = AMDGPU_GEM_DOMAIN_GWS;
 326         bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 327         bp.type = ttm_bo_type_device;
 328         bp.resv = NULL;
 329
 330         r = amdgpu_bo_create(adev, &bp, &bo);
 331         if (r) {
 332                 dev_err(adev->dev,
 333                         "failed to allocate gws BO for amdkfd (%d)\n", r);
 334                 return r;
 335         }
 336
 337         *mem_obj = bo;
 338         return 0;
 339 }
 340
 341 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
 342 {
 343         struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
 344
 345         amdgpu_bo_unref(&bo);
 346 }
 347
 348 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
 349                                       enum kgd_engine_type type)
 350 {
 351         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 352
 353         switch (type) {
 354         case KGD_ENGINE_PFP:
 355                 return adev->gfx.pfp_fw_version;
 356
 357         case KGD_ENGINE_ME:
 358                 return adev->gfx.me_fw_version;
 359
 360         case KGD_ENGINE_CE:
 361                 return adev->gfx.ce_fw_version;
 362
 363         case KGD_ENGINE_MEC1:
 364                 return adev->gfx.mec_fw_version;
 365
 366         case KGD_ENGINE_MEC2:
 367                 return adev->gfx.mec2_fw_version;
 368
 369         case KGD_ENGINE_RLC:
 370                 return adev->gfx.rlc_fw_version;
 371
 372         case KGD_ENGINE_SDMA1:
 373                 return adev->sdma.instance[0].fw_version;
 374
 375         case KGD_ENGINE_SDMA2:
 376                 return adev->sdma.instance[1].fw_version;
 377
 378         default:
 379                 return 0;
 380         }
 381
 382         return 0;
 383 }
 384
 385 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
 386                                       struct kfd_local_mem_info *mem_info)
 387 {
 388         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 389
 390         memset(mem_info, 0, sizeof(*mem_info));
 391
 392         mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
 393         mem_info->local_mem_size_private = adev->gmc.real_vram_size -
 394                                                 adev->gmc.visible_vram_size;
 395
 396         mem_info->vram_width = adev->gmc.vram_width;
 397
 398         pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
 399                         &adev->gmc.aper_base,
 400                         mem_info->local_mem_size_public,
 401                         mem_info->local_mem_size_private);
 402
 403         if (amdgpu_sriov_vf(adev))
 404                 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
 405         else if (adev->pm.dpm_enabled) {
 406                 if (amdgpu_emu_mode == 1)
 407                         mem_info->mem_clk_max = 0;
 408                 else
 409                         mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
 410         } else
 411                 mem_info->mem_clk_max = 100;
 412 }
 413
 414 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
 415 {
 416         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 417
 418         if (adev->gfx.funcs->get_gpu_clock_counter)
 419                 return adev->gfx.funcs->get_gpu_clock_counter(adev);
 420         return 0;
 421 }
 422
 423 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 424 {
 425         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 426
 427         /* the sclk is in quantas of 10kHz */
 428         if (amdgpu_sriov_vf(adev))
 429                 return adev->clock.default_sclk / 100;
 430         else if (adev->pm.dpm_enabled)
 431                 return amdgpu_dpm_get_sclk(adev, false) / 100;
 432         else
 433                 return 100;
 434 }
 435
 436 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
 437 {
 438         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 439         struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
 440
 441         memset(cu_info, 0, sizeof(*cu_info));
 442         if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
 443                 return;
 444
 445         cu_info->cu_active_number = acu_info.number;
 446         cu_info->cu_ao_mask = acu_info.ao_cu_mask;
 447         memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
 448                sizeof(acu_info.bitmap));
 449         cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 450         cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 451         cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 452         cu_info->simd_per_cu = acu_info.simd_per_cu;
 453         cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
 454         cu_info->wave_front_size = acu_info.wave_front_size;
 455         cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
 456         cu_info->lds_size = acu_info.lds_size;
 457 }
 458
 459 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
 460                                   struct kgd_dev **dma_buf_kgd,
 461                                   uint64_t *bo_size, void *metadata_buffer,
 462                                   size_t buffer_size, uint32_t *metadata_size,
 463                                   uint32_t *flags)
 464 {
 465         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 466         struct dma_buf *dma_buf;
 467         struct drm_gem_object *obj;
 468         struct amdgpu_bo *bo;
 469         uint64_t metadata_flags;
 470         int r = -EINVAL;
 471
 472         dma_buf = dma_buf_get(dma_buf_fd);
 473         if (IS_ERR(dma_buf))
 474                 return PTR_ERR(dma_buf);
 475
 476         if (dma_buf->ops != &amdgpu_dmabuf_ops)
 477                 /* Can't handle non-graphics buffers */
 478                 goto out_put;
 479
 480         obj = dma_buf->priv;
 481         if (obj->dev->driver != adev_to_drm(adev)->driver)
 482                 /* Can't handle buffers from different drivers */
 483                 goto out_put;
 484
 485         adev = drm_to_adev(obj->dev);
 486         bo = gem_to_amdgpu_bo(obj);
 487         if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
 488                                     AMDGPU_GEM_DOMAIN_GTT)))
 489                 /* Only VRAM and GTT BOs are supported */
 490                 goto out_put;
 491
 492         r = 0;
 493         if (dma_buf_kgd)
 494                 *dma_buf_kgd = (struct kgd_dev *)adev;
 495         if (bo_size)
 496                 *bo_size = amdgpu_bo_size(bo);
 497         if (metadata_size)
 498                 *metadata_size = bo->metadata_size;
 499         if (metadata_buffer)
 500                 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
 501                                            metadata_size, &metadata_flags);
 502         if (flags) {
 503                 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
 504                                 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
 505                                 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
 506
 507                 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 508                         *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
 509         }
 510
 511 out_put:
 512         dma_buf_put(dma_buf);
 513         return r;
 514 }
 515
 516 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
 517 {
 518         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 519         struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 520
 521         return amdgpu_vram_mgr_usage(vram_man);
 522 }
 523
 524 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
 525 {
 526         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 527
 528         return adev->gmc.xgmi.hive_id;
 529 }
 530
 531 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd)
 532 {
 533         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 534
 535         return adev->unique_id;
 536 }
 537
 538 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
 539 {
 540         struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
 541         struct amdgpu_device *adev = (struct amdgpu_device *)dst;
 542         int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
 543
 544         if (ret < 0) {
 545                 DRM_ERROR("amdgpu: failed to get  xgmi hops count between node %d and %d. ret = %d\n",
 546                         adev->gmc.xgmi.physical_node_id,
 547                         peer_adev->gmc.xgmi.physical_node_id, ret);
 548                 ret = 0;
 549         }
 550         return  (uint8_t)ret;
 551 }
 552
 553 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
 554 {
 555         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 556
 557         return adev->rmmio_remap.bus_addr;
 558 }
 559
 560 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
 561 {
 562         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 563
 564         return adev->gds.gws_size;
 565 }
 566
 567 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
 568 {
 569         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 570
 571         return adev->rev_id;
 572 }
 573
 574 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd)
 575 {
 576         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 577
 578         return adev->gmc.noretry;
 579 }
 580
 581 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 582                                 uint32_t vmid, uint64_t gpu_addr,
 583                                 uint32_t *ib_cmd, uint32_t ib_len)
 584 {
 585         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 586         struct amdgpu_job *job;
 587         struct amdgpu_ib *ib;
 588         struct amdgpu_ring *ring;
 589         struct dma_fence *f = NULL;
 590         int ret;
 591
 592         switch (engine) {
 593         case KGD_ENGINE_MEC1:
 594                 ring = &adev->gfx.compute_ring[0];
 595                 break;
 596         case KGD_ENGINE_SDMA1:
 597                 ring = &adev->sdma.instance[0].ring;
 598                 break;
 599         case KGD_ENGINE_SDMA2:
 600                 ring = &adev->sdma.instance[1].ring;
 601                 break;
 602         default:
 603                 pr_err("Invalid engine in IB submission: %d\n", engine);
 604                 ret = -EINVAL;
 605                 goto err;
 606         }
 607
 608         ret = amdgpu_job_alloc(adev, 1, &job, NULL);
 609         if (ret)
 610                 goto err;
 611
 612         ib = &job->ibs[0];
 613         memset(ib, 0, sizeof(struct amdgpu_ib));
 614
 615         ib->gpu_addr = gpu_addr;
 616         ib->ptr = ib_cmd;
 617         ib->length_dw = ib_len;
 618         /* This works for NO_HWS. TODO: need to handle without knowing VMID */
 619         job->vmid = vmid;
 620
 621         ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
 622
 623         if (ret) {
 624                 DRM_ERROR("amdgpu: failed to schedule IB.\n");
 625                 goto err_ib_sched;
 626         }
 627
 628         ret = dma_fence_wait(f, false);
 629
 630 err_ib_sched:
 631         dma_fence_put(f);
 632         amdgpu_job_free(job);
 633 err:
 634         return ret;
 635 }
 636
 637 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
 638 {
 639         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 640
 641         /* Temp workaround to fix the soft hang observed in certain compute
 642          * applications if GFXOFF is enabled.
 643          */
 644         if (adev->asic_type == CHIP_SIENNA_CICHLID) {
 645                 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
 646                 amdgpu_gfx_off_ctrl(adev, idle);
 647         }
 648         amdgpu_dpm_switch_power_profile(adev,
 649                                         PP_SMC_POWER_PROFILE_COMPUTE,
 650                                         !idle);
 651 }
 652
 653 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
 654 {
 655         if (adev->kfd.dev)
 656                 return vmid >= adev->vm_manager.first_kfd_vmid;
 657
 658         return false;
 659 }
 660
 661 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
 662 {
 663         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 664
 665         if (adev->family == AMDGPU_FAMILY_AI) {
 666                 int i;
 667
 668                 for (i = 0; i < adev->num_vmhubs; i++)
 669                         amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
 670         } else {
 671                 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
 672         }
 673
 674         return 0;
 675 }
 676
 677 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid)
 678 {
 679         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 680         const uint32_t flush_type = 0;
 681         bool all_hub = false;
 682
 683         if (adev->family == AMDGPU_FAMILY_AI)
 684                 all_hub = true;
 685
 686         return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
 687 }
 688
 689 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
 690 {
 691         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 692
 693         return adev->have_atomics_support;
 694 }