drivers/gpu/drm/msm/msm_gpu.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <[email protected]>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "msm_gpu.h"
  19 #include "msm_gem.h"
  20 #include "msm_mmu.h"
  21 #include "msm_fence.h"
  22 #include "msm_gpu_trace.h"
  23 #include "adreno/adreno_gpu.h"
  24
  25 #include <generated/utsrelease.h>
  26 #include <linux/string_helpers.h>
  27 #include <linux/pm_opp.h>
  28 #include <linux/devfreq.h>
  29 #include <linux/devcoredump.h>
  30
  31 /*
  32  * Power Management:
  33  */
  34
  35 static int msm_devfreq_target(struct device *dev, unsigned long *freq,
  36                 u32 flags)
  37 {
  38         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  39         struct dev_pm_opp *opp;
  40
  41         opp = devfreq_recommended_opp(dev, freq, flags);
  42
  43         if (IS_ERR(opp))
  44                 return PTR_ERR(opp);
  45
  46         if (gpu->funcs->gpu_set_freq)
  47                 gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
  48         else
  49                 clk_set_rate(gpu->core_clk, *freq);
  50
  51         dev_pm_opp_put(opp);
  52
  53         return 0;
  54 }
  55
  56 static int msm_devfreq_get_dev_status(struct device *dev,
  57                 struct devfreq_dev_status *status)
  58 {
  59         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  60         ktime_t time;
  61
  62         if (gpu->funcs->gpu_get_freq)
  63                 status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
  64         else
  65                 status->current_frequency = clk_get_rate(gpu->core_clk);
  66
  67         status->busy_time = gpu->funcs->gpu_busy(gpu);
  68
  69         time = ktime_get();
  70         status->total_time = ktime_us_delta(time, gpu->devfreq.time);
  71         gpu->devfreq.time = time;
  72
  73         return 0;
  74 }
  75
  76 static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
  77 {
  78         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  79
  80         if (gpu->funcs->gpu_get_freq)
  81                 *freq = gpu->funcs->gpu_get_freq(gpu);
  82         else
  83                 *freq = clk_get_rate(gpu->core_clk);
  84
  85         return 0;
  86 }
  87
  88 static struct devfreq_dev_profile msm_devfreq_profile = {
  89         .polling_ms = 10,
  90         .target = msm_devfreq_target,
  91         .get_dev_status = msm_devfreq_get_dev_status,
  92         .get_cur_freq = msm_devfreq_get_cur_freq,
  93 };
  94
  95 static void msm_devfreq_init(struct msm_gpu *gpu)
  96 {
  97         /* We need target support to do devfreq */
  98         if (!gpu->funcs->gpu_busy)
  99                 return;
 100
 101         msm_devfreq_profile.initial_freq = gpu->fast_rate;
 102
 103         /*
 104          * Don't set the freq_table or max_state and let devfreq build the table
 105          * from OPP
 106          */
 107
 108         gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
 109                         &msm_devfreq_profile, "simple_ondemand", NULL);
 110
 111         if (IS_ERR(gpu->devfreq.devfreq)) {
 112                 DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
 113                 gpu->devfreq.devfreq = NULL;
 114         }
 115
 116         devfreq_suspend_device(gpu->devfreq.devfreq);
 117 }
 118
 119 static int enable_pwrrail(struct msm_gpu *gpu)
 120 {
 121         struct drm_device *dev = gpu->dev;
 122         int ret = 0;
 123
 124         if (gpu->gpu_reg) {
 125                 ret = regulator_enable(gpu->gpu_reg);
 126                 if (ret) {
 127                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
 128                         return ret;
 129                 }
 130         }
 131
 132         if (gpu->gpu_cx) {
 133                 ret = regulator_enable(gpu->gpu_cx);
 134                 if (ret) {
 135                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
 136                         return ret;
 137                 }
 138         }
 139
 140         return 0;
 141 }
 142
 143 static int disable_pwrrail(struct msm_gpu *gpu)
 144 {
 145         if (gpu->gpu_cx)
 146                 regulator_disable(gpu->gpu_cx);
 147         if (gpu->gpu_reg)
 148                 regulator_disable(gpu->gpu_reg);
 149         return 0;
 150 }
 151
 152 static int enable_clk(struct msm_gpu *gpu)
 153 {
 154         if (gpu->core_clk && gpu->fast_rate)
 155                 clk_set_rate(gpu->core_clk, gpu->fast_rate);
 156
 157         /* Set the RBBM timer rate to 19.2Mhz */
 158         if (gpu->rbbmtimer_clk)
 159                 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
 160
 161         return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
 162 }
 163
 164 static int disable_clk(struct msm_gpu *gpu)
 165 {
 166         clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
 167
 168         /*
 169          * Set the clock to a deliberately low rate. On older targets the clock
 170          * speed had to be non zero to avoid problems. On newer targets this
 171          * will be rounded down to zero anyway so it all works out.
 172          */
 173         if (gpu->core_clk)
 174                 clk_set_rate(gpu->core_clk, 27000000);
 175
 176         if (gpu->rbbmtimer_clk)
 177                 clk_set_rate(gpu->rbbmtimer_clk, 0);
 178
 179         return 0;
 180 }
 181
 182 static int enable_axi(struct msm_gpu *gpu)
 183 {
 184         if (gpu->ebi1_clk)
 185                 clk_prepare_enable(gpu->ebi1_clk);
 186         return 0;
 187 }
 188
 189 static int disable_axi(struct msm_gpu *gpu)
 190 {
 191         if (gpu->ebi1_clk)
 192                 clk_disable_unprepare(gpu->ebi1_clk);
 193         return 0;
 194 }
 195
 196 void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
 197 {
 198         gpu->devfreq.busy_cycles = 0;
 199         gpu->devfreq.time = ktime_get();
 200
 201         devfreq_resume_device(gpu->devfreq.devfreq);
 202 }
 203
 204 int msm_gpu_pm_resume(struct msm_gpu *gpu)
 205 {
 206         int ret;
 207
 208         DBG("%s", gpu->name);
 209
 210         ret = enable_pwrrail(gpu);
 211         if (ret)
 212                 return ret;
 213
 214         ret = enable_clk(gpu);
 215         if (ret)
 216                 return ret;
 217
 218         ret = enable_axi(gpu);
 219         if (ret)
 220                 return ret;
 221
 222         msm_gpu_resume_devfreq(gpu);
 223
 224         gpu->needs_hw_init = true;
 225
 226         return 0;
 227 }
 228
 229 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
 230 {
 231         int ret;
 232
 233         DBG("%s", gpu->name);
 234
 235         devfreq_suspend_device(gpu->devfreq.devfreq);
 236
 237         ret = disable_axi(gpu);
 238         if (ret)
 239                 return ret;
 240
 241         ret = disable_clk(gpu);
 242         if (ret)
 243                 return ret;
 244
 245         ret = disable_pwrrail(gpu);
 246         if (ret)
 247                 return ret;
 248
 249         return 0;
 250 }
 251
 252 int msm_gpu_hw_init(struct msm_gpu *gpu)
 253 {
 254         int ret;
 255
 256         WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
 257
 258         if (!gpu->needs_hw_init)
 259                 return 0;
 260
 261         disable_irq(gpu->irq);
 262         ret = gpu->funcs->hw_init(gpu);
 263         if (!ret)
 264                 gpu->needs_hw_init = false;
 265         enable_irq(gpu->irq);
 266
 267         return ret;
 268 }
 269
 270 #ifdef CONFIG_DEV_COREDUMP
 271 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
 272                 size_t count, void *data, size_t datalen)
 273 {
 274         struct msm_gpu *gpu = data;
 275         struct drm_print_iterator iter;
 276         struct drm_printer p;
 277         struct msm_gpu_state *state;
 278
 279         state = msm_gpu_crashstate_get(gpu);
 280         if (!state)
 281                 return 0;
 282
 283         iter.data = buffer;
 284         iter.offset = 0;
 285         iter.start = offset;
 286         iter.remain = count;
 287
 288         p = drm_coredump_printer(&iter);
 289
 290         drm_printf(&p, "---\n");
 291         drm_printf(&p, "kernel: " UTS_RELEASE "\n");
 292         drm_printf(&p, "module: " KBUILD_MODNAME "\n");
 293         drm_printf(&p, "time: %lld.%09ld\n",
 294                 state->time.tv_sec, state->time.tv_nsec);
 295         if (state->comm)
 296                 drm_printf(&p, "comm: %s\n", state->comm);
 297         if (state->cmd)
 298                 drm_printf(&p, "cmdline: %s\n", state->cmd);
 299
 300         gpu->funcs->show(gpu, state, &p);
 301
 302         msm_gpu_crashstate_put(gpu);
 303
 304         return count - iter.remain;
 305 }
 306
 307 static void msm_gpu_devcoredump_free(void *data)
 308 {
 309         struct msm_gpu *gpu = data;
 310
 311         msm_gpu_crashstate_put(gpu);
 312 }
 313
 314 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
 315                 struct msm_gem_object *obj, u64 iova, u32 flags)
 316 {
 317         struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
 318
 319         /* Don't record write only objects */
 320         state_bo->size = obj->base.size;
 321         state_bo->iova = iova;
 322
 323         /* Only store data for non imported buffer objects marked for read */
 324         if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
 325                 void *ptr;
 326
 327                 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
 328                 if (!state_bo->data)
 329                         goto out;
 330
 331                 ptr = msm_gem_get_vaddr_active(&obj->base);
 332                 if (IS_ERR(ptr)) {
 333                         kvfree(state_bo->data);
 334                         state_bo->data = NULL;
 335                         goto out;
 336                 }
 337
 338                 memcpy(state_bo->data, ptr, obj->base.size);
 339                 msm_gem_put_vaddr(&obj->base);
 340         }
 341 out:
 342         state->nr_bos++;
 343 }
 344
 345 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 346                 struct msm_gem_submit *submit, char *comm, char *cmd)
 347 {
 348         struct msm_gpu_state *state;
 349
 350         /* Check if the target supports capturing crash state */
 351         if (!gpu->funcs->gpu_state_get)
 352                 return;
 353
 354         /* Only save one crash state at a time */
 355         if (gpu->crashstate)
 356                 return;
 357
 358         state = gpu->funcs->gpu_state_get(gpu);
 359         if (IS_ERR_OR_NULL(state))
 360                 return;
 361
 362         /* Fill in the additional crash state information */
 363         state->comm = kstrdup(comm, GFP_KERNEL);
 364         state->cmd = kstrdup(cmd, GFP_KERNEL);
 365
 366         if (submit) {
 367                 int i;
 368
 369                 state->bos = kcalloc(submit->nr_cmds,
 370                         sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
 371
 372                 for (i = 0; state->bos && i < submit->nr_cmds; i++) {
 373                         int idx = submit->cmd[i].idx;
 374
 375                         msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
 376                                 submit->bos[idx].iova, submit->bos[idx].flags);
 377                 }
 378         }
 379
 380         /* Set the active crash state to be dumped on failure */
 381         gpu->crashstate = state;
 382
 383         /* FIXME: Release the crashstate if this errors out? */
 384         dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
 385                 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
 386 }
 387 #else
 388 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 389                 struct msm_gem_submit *submit, char *comm, char *cmd)
 390 {
 391 }
 392 #endif
 393
 394 /*
 395  * Hangcheck detection for locked gpu:
 396  */
 397
 398 static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 399                 uint32_t fence)
 400 {
 401         struct msm_gem_submit *submit;
 402
 403         list_for_each_entry(submit, &ring->submits, node) {
 404                 if (submit->seqno > fence)
 405                         break;
 406
 407                 msm_update_fence(submit->ring->fctx,
 408                         submit->fence->seqno);
 409         }
 410 }
 411
 412 static struct msm_gem_submit *
 413 find_submit(struct msm_ringbuffer *ring, uint32_t fence)
 414 {
 415         struct msm_gem_submit *submit;
 416
 417         WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex));
 418
 419         list_for_each_entry(submit, &ring->submits, node)
 420                 if (submit->seqno == fence)
 421                         return submit;
 422
 423         return NULL;
 424 }
 425
 426 static void retire_submits(struct msm_gpu *gpu);
 427
 428 static void recover_worker(struct work_struct *work)
 429 {
 430         struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
 431         struct drm_device *dev = gpu->dev;
 432         struct msm_drm_private *priv = dev->dev_private;
 433         struct msm_gem_submit *submit;
 434         struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 435         char *comm = NULL, *cmd = NULL;
 436         int i;
 437
 438         mutex_lock(&dev->struct_mutex);
 439
 440         DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
 441
 442         submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 443         if (submit) {
 444                 struct task_struct *task;
 445
 446                 /* Increment the fault counts */
 447                 gpu->global_faults++;
 448                 submit->queue->faults++;
 449
 450                 task = get_pid_task(submit->pid, PIDTYPE_PID);
 451                 if (task) {
 452                         comm = kstrdup(task->comm, GFP_KERNEL);
 453                         cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
 454                         put_task_struct(task);
 455                 }
 456
 457                 if (comm && cmd) {
 458                         DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
 459                                 gpu->name, comm, cmd);
 460
 461                         msm_rd_dump_submit(priv->hangrd, submit,
 462                                 "offending task: %s (%s)", comm, cmd);
 463                 } else
 464                         msm_rd_dump_submit(priv->hangrd, submit, NULL);
 465         }
 466
 467         /* Record the crash state */
 468         pm_runtime_get_sync(&gpu->pdev->dev);
 469         msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
 470         pm_runtime_put_sync(&gpu->pdev->dev);
 471
 472         kfree(cmd);
 473         kfree(comm);
 474
 475         /*
 476          * Update all the rings with the latest and greatest fence.. this
 477          * needs to happen after msm_rd_dump_submit() to ensure that the
 478          * bo's referenced by the offending submit are still around.
 479          */
 480         for (i = 0; i < gpu->nr_rings; i++) {
 481                 struct msm_ringbuffer *ring = gpu->rb[i];
 482
 483                 uint32_t fence = ring->memptrs->fence;
 484
 485                 /*
 486                  * For the current (faulting?) ring/submit advance the fence by
 487                  * one more to clear the faulting submit
 488                  */
 489                 if (ring == cur_ring)
 490                         fence++;
 491
 492                 update_fences(gpu, ring, fence);
 493         }
 494
 495         if (msm_gpu_active(gpu)) {
 496                 /* retire completed submits, plus the one that hung: */
 497                 retire_submits(gpu);
 498
 499                 pm_runtime_get_sync(&gpu->pdev->dev);
 500                 gpu->funcs->recover(gpu);
 501                 pm_runtime_put_sync(&gpu->pdev->dev);
 502
 503                 /*
 504                  * Replay all remaining submits starting with highest priority
 505                  * ring
 506                  */
 507                 for (i = 0; i < gpu->nr_rings; i++) {
 508                         struct msm_ringbuffer *ring = gpu->rb[i];
 509
 510                         list_for_each_entry(submit, &ring->submits, node)
 511                                 gpu->funcs->submit(gpu, submit, NULL);
 512                 }
 513         }
 514
 515         mutex_unlock(&dev->struct_mutex);
 516
 517         msm_gpu_retire(gpu);
 518 }
 519
 520 static void hangcheck_timer_reset(struct msm_gpu *gpu)
 521 {
 522         DBG("%s", gpu->name);
 523         mod_timer(&gpu->hangcheck_timer,
 524                         round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
 525 }
 526
 527 static void hangcheck_handler(struct timer_list *t)
 528 {
 529         struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
 530         struct drm_device *dev = gpu->dev;
 531         struct msm_drm_private *priv = dev->dev_private;
 532         struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
 533         uint32_t fence = ring->memptrs->fence;
 534
 535         if (fence != ring->hangcheck_fence) {
 536                 /* some progress has been made.. ya! */
 537                 ring->hangcheck_fence = fence;
 538         } else if (fence < ring->seqno) {
 539                 /* no progress and not done.. hung! */
 540                 ring->hangcheck_fence = fence;
 541                 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
 542                                 gpu->name, ring->id);
 543                 DRM_DEV_ERROR(dev->dev, "%s:     completed fence: %u\n",
 544                                 gpu->name, fence);
 545                 DRM_DEV_ERROR(dev->dev, "%s:     submitted fence: %u\n",
 546                                 gpu->name, ring->seqno);
 547
 548                 queue_work(priv->wq, &gpu->recover_work);
 549         }
 550
 551         /* if still more pending work, reset the hangcheck timer: */
 552         if (ring->seqno > ring->hangcheck_fence)
 553                 hangcheck_timer_reset(gpu);
 554
 555         /* workaround for missing irq: */
 556         queue_work(priv->wq, &gpu->retire_work);
 557 }
 558
 559 /*
 560  * Performance Counters:
 561  */
 562
 563 /* called under perf_lock */
 564 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
 565 {
 566         uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
 567         int i, n = min(ncntrs, gpu->num_perfcntrs);
 568
 569         /* read current values: */
 570         for (i = 0; i < gpu->num_perfcntrs; i++)
 571                 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
 572
 573         /* update cntrs: */
 574         for (i = 0; i < n; i++)
 575                 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
 576
 577         /* save current values: */
 578         for (i = 0; i < gpu->num_perfcntrs; i++)
 579                 gpu->last_cntrs[i] = current_cntrs[i];
 580
 581         return n;
 582 }
 583
 584 static void update_sw_cntrs(struct msm_gpu *gpu)
 585 {
 586         ktime_t time;
 587         uint32_t elapsed;
 588         unsigned long flags;
 589
 590         spin_lock_irqsave(&gpu->perf_lock, flags);
 591         if (!gpu->perfcntr_active)
 592                 goto out;
 593
 594         time = ktime_get();
 595         elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
 596
 597         gpu->totaltime += elapsed;
 598         if (gpu->last_sample.active)
 599                 gpu->activetime += elapsed;
 600
 601         gpu->last_sample.active = msm_gpu_active(gpu);
 602         gpu->last_sample.time = time;
 603
 604 out:
 605         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 606 }
 607
 608 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
 609 {
 610         unsigned long flags;
 611
 612         pm_runtime_get_sync(&gpu->pdev->dev);
 613
 614         spin_lock_irqsave(&gpu->perf_lock, flags);
 615         /* we could dynamically enable/disable perfcntr registers too.. */
 616         gpu->last_sample.active = msm_gpu_active(gpu);
 617         gpu->last_sample.time = ktime_get();
 618         gpu->activetime = gpu->totaltime = 0;
 619         gpu->perfcntr_active = true;
 620         update_hw_cntrs(gpu, 0, NULL);
 621         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 622 }
 623
 624 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
 625 {
 626         gpu->perfcntr_active = false;
 627         pm_runtime_put_sync(&gpu->pdev->dev);
 628 }
 629
 630 /* returns -errno or # of cntrs sampled */
 631 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 632                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
 633 {
 634         unsigned long flags;
 635         int ret;
 636
 637         spin_lock_irqsave(&gpu->perf_lock, flags);
 638
 639         if (!gpu->perfcntr_active) {
 640                 ret = -EINVAL;
 641                 goto out;
 642         }
 643
 644         *activetime = gpu->activetime;
 645         *totaltime = gpu->totaltime;
 646
 647         gpu->activetime = gpu->totaltime = 0;
 648
 649         ret = update_hw_cntrs(gpu, ncntrs, cntrs);
 650
 651 out:
 652         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 653
 654         return ret;
 655 }
 656
 657 /*
 658  * Cmdstream submission/retirement:
 659  */
 660
 661 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 662                 struct msm_gem_submit *submit)
 663 {
 664         int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 665         volatile struct msm_gpu_submit_stats *stats;
 666         u64 elapsed, clock = 0;
 667         int i;
 668
 669         stats = &ring->memptrs->stats[index];
 670         /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
 671         elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
 672         do_div(elapsed, 192);
 673
 674         /* Calculate the clock frequency from the number of CP cycles */
 675         if (elapsed) {
 676                 clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
 677                 do_div(clock, elapsed);
 678         }
 679
 680         trace_msm_gpu_submit_retired(submit, elapsed, clock,
 681                 stats->alwayson_start, stats->alwayson_end);
 682
 683         for (i = 0; i < submit->nr_bos; i++) {
 684                 struct msm_gem_object *msm_obj = submit->bos[i].obj;
 685                 /* move to inactive: */
 686                 msm_gem_move_to_inactive(&msm_obj->base);
 687                 msm_gem_unpin_iova(&msm_obj->base, gpu->aspace);
 688                 drm_gem_object_put(&msm_obj->base);
 689         }
 690
 691         pm_runtime_mark_last_busy(&gpu->pdev->dev);
 692         pm_runtime_put_autosuspend(&gpu->pdev->dev);
 693         msm_gem_submit_free(submit);
 694 }
 695
 696 static void retire_submits(struct msm_gpu *gpu)
 697 {
 698         struct drm_device *dev = gpu->dev;
 699         struct msm_gem_submit *submit, *tmp;
 700         int i;
 701
 702         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 703
 704         /* Retire the commits starting with highest priority */
 705         for (i = 0; i < gpu->nr_rings; i++) {
 706                 struct msm_ringbuffer *ring = gpu->rb[i];
 707
 708                 list_for_each_entry_safe(submit, tmp, &ring->submits, node) {
 709                         if (dma_fence_is_signaled(submit->fence))
 710                                 retire_submit(gpu, ring, submit);
 711                 }
 712         }
 713 }
 714
 715 static void retire_worker(struct work_struct *work)
 716 {
 717         struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
 718         struct drm_device *dev = gpu->dev;
 719         int i;
 720
 721         for (i = 0; i < gpu->nr_rings; i++)
 722                 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
 723
 724         mutex_lock(&dev->struct_mutex);
 725         retire_submits(gpu);
 726         mutex_unlock(&dev->struct_mutex);
 727 }
 728
 729 /* call from irq handler to schedule work to retire bo's */
 730 void msm_gpu_retire(struct msm_gpu *gpu)
 731 {
 732         struct msm_drm_private *priv = gpu->dev->dev_private;
 733         queue_work(priv->wq, &gpu->retire_work);
 734         update_sw_cntrs(gpu);
 735 }
 736
 737 /* add bo's to gpu's ring, and kick gpu: */
 738 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 739                 struct msm_file_private *ctx)
 740 {
 741         struct drm_device *dev = gpu->dev;
 742         struct msm_drm_private *priv = dev->dev_private;
 743         struct msm_ringbuffer *ring = submit->ring;
 744         int i;
 745
 746         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 747
 748         pm_runtime_get_sync(&gpu->pdev->dev);
 749
 750         msm_gpu_hw_init(gpu);
 751
 752         submit->seqno = ++ring->seqno;
 753
 754         list_add_tail(&submit->node, &ring->submits);
 755
 756         msm_rd_dump_submit(priv->rd, submit, NULL);
 757
 758         update_sw_cntrs(gpu);
 759
 760         for (i = 0; i < submit->nr_bos; i++) {
 761                 struct msm_gem_object *msm_obj = submit->bos[i].obj;
 762                 uint64_t iova;
 763
 764                 /* can't happen yet.. but when we add 2d support we'll have
 765                  * to deal w/ cross-ring synchronization:
 766                  */
 767                 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
 768
 769                 /* submit takes a reference to the bo and iova until retired: */
 770                 drm_gem_object_get(&msm_obj->base);
 771                 msm_gem_get_and_pin_iova(&msm_obj->base,
 772                                 submit->gpu->aspace, &iova);
 773
 774                 if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
 775                         msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
 776                 else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
 777                         msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
 778         }
 779
 780         gpu->funcs->submit(gpu, submit, ctx);
 781         priv->lastctx = ctx;
 782
 783         hangcheck_timer_reset(gpu);
 784 }
 785
 786 /*
 787  * Init/Cleanup:
 788  */
 789
 790 static irqreturn_t irq_handler(int irq, void *data)
 791 {
 792         struct msm_gpu *gpu = data;
 793         return gpu->funcs->irq(gpu);
 794 }
 795
 796 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
 797 {
 798         int ret = msm_clk_bulk_get(&pdev->dev, &gpu->grp_clks);
 799
 800         if (ret < 1) {
 801                 gpu->nr_clocks = 0;
 802                 return ret;
 803         }
 804
 805         gpu->nr_clocks = ret;
 806
 807         gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 808                 gpu->nr_clocks, "core");
 809
 810         gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 811                 gpu->nr_clocks, "rbbmtimer");
 812
 813         return 0;
 814 }
 815
 816 static struct msm_gem_address_space *
 817 msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev,
 818                 uint64_t va_start, uint64_t va_end)
 819 {
 820         struct msm_gem_address_space *aspace;
 821         int ret;
 822
 823         /*
 824          * Setup IOMMU.. eventually we will (I think) do this once per context
 825          * and have separate page tables per context.  For now, to keep things
 826          * simple and to get something working, just use a single address space:
 827          */
 828         if (!adreno_is_a2xx(to_adreno_gpu(gpu))) {
 829                 struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type);
 830                 if (!iommu)
 831                         return NULL;
 832
 833                 iommu->geometry.aperture_start = va_start;
 834                 iommu->geometry.aperture_end = va_end;
 835
 836                 DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name);
 837
 838                 aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu");
 839                 if (IS_ERR(aspace))
 840                         iommu_domain_free(iommu);
 841         } else {
 842                 aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu",
 843                         va_start, va_end);
 844         }
 845
 846         if (IS_ERR(aspace)) {
 847                 DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n",
 848                         PTR_ERR(aspace));
 849                 return ERR_CAST(aspace);
 850         }
 851
 852         ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0);
 853         if (ret) {
 854                 msm_gem_address_space_put(aspace);
 855                 return ERR_PTR(ret);
 856         }
 857
 858         return aspace;
 859 }
 860
 861 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 862                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 863                 const char *name, struct msm_gpu_config *config)
 864 {
 865         int i, ret, nr_rings = config->nr_rings;
 866         void *memptrs;
 867         uint64_t memptrs_iova;
 868
 869         if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
 870                 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
 871
 872         gpu->dev = drm;
 873         gpu->funcs = funcs;
 874         gpu->name = name;
 875
 876         INIT_LIST_HEAD(&gpu->active_list);
 877         INIT_WORK(&gpu->retire_work, retire_worker);
 878         INIT_WORK(&gpu->recover_work, recover_worker);
 879
 880
 881         timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
 882
 883         spin_lock_init(&gpu->perf_lock);
 884
 885
 886         /* Map registers: */
 887         gpu->mmio = msm_ioremap(pdev, config->ioname, name);
 888         if (IS_ERR(gpu->mmio)) {
 889                 ret = PTR_ERR(gpu->mmio);
 890                 goto fail;
 891         }
 892
 893         /* Get Interrupt: */
 894         gpu->irq = platform_get_irq(pdev, 0);
 895         if (gpu->irq < 0) {
 896                 ret = gpu->irq;
 897                 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
 898                 goto fail;
 899         }
 900
 901         ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
 902                         IRQF_TRIGGER_HIGH, gpu->name, gpu);
 903         if (ret) {
 904                 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
 905                 goto fail;
 906         }
 907
 908         ret = get_clocks(pdev, gpu);
 909         if (ret)
 910                 goto fail;
 911
 912         gpu->ebi1_clk = msm_clk_get(pdev, "bus");
 913         DBG("ebi1_clk: %p", gpu->ebi1_clk);
 914         if (IS_ERR(gpu->ebi1_clk))
 915                 gpu->ebi1_clk = NULL;
 916
 917         /* Acquire regulators: */
 918         gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
 919         DBG("gpu_reg: %p", gpu->gpu_reg);
 920         if (IS_ERR(gpu->gpu_reg))
 921                 gpu->gpu_reg = NULL;
 922
 923         gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
 924         DBG("gpu_cx: %p", gpu->gpu_cx);
 925         if (IS_ERR(gpu->gpu_cx))
 926                 gpu->gpu_cx = NULL;
 927
 928         gpu->pdev = pdev;
 929         platform_set_drvdata(pdev, gpu);
 930
 931         msm_devfreq_init(gpu);
 932
 933         gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
 934                 config->va_start, config->va_end);
 935
 936         if (gpu->aspace == NULL)
 937                 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
 938         else if (IS_ERR(gpu->aspace)) {
 939                 ret = PTR_ERR(gpu->aspace);
 940                 goto fail;
 941         }
 942
 943         memptrs = msm_gem_kernel_new(drm,
 944                 sizeof(struct msm_rbmemptrs) * nr_rings,
 945                 MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
 946                 &memptrs_iova);
 947
 948         if (IS_ERR(memptrs)) {
 949                 ret = PTR_ERR(memptrs);
 950                 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
 951                 goto fail;
 952         }
 953
 954         msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
 955
 956         if (nr_rings > ARRAY_SIZE(gpu->rb)) {
 957                 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
 958                         ARRAY_SIZE(gpu->rb));
 959                 nr_rings = ARRAY_SIZE(gpu->rb);
 960         }
 961
 962         /* Create ringbuffer(s): */
 963         for (i = 0; i < nr_rings; i++) {
 964                 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
 965
 966                 if (IS_ERR(gpu->rb[i])) {
 967                         ret = PTR_ERR(gpu->rb[i]);
 968                         DRM_DEV_ERROR(drm->dev,
 969                                 "could not create ringbuffer %d: %d\n", i, ret);
 970                         goto fail;
 971                 }
 972
 973                 memptrs += sizeof(struct msm_rbmemptrs);
 974                 memptrs_iova += sizeof(struct msm_rbmemptrs);
 975         }
 976
 977         gpu->nr_rings = nr_rings;
 978
 979         return 0;
 980
 981 fail:
 982         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
 983                 msm_ringbuffer_destroy(gpu->rb[i]);
 984                 gpu->rb[i] = NULL;
 985         }
 986
 987         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
 988
 989         platform_set_drvdata(pdev, NULL);
 990         return ret;
 991 }
 992
 993 void msm_gpu_cleanup(struct msm_gpu *gpu)
 994 {
 995         int i;
 996
 997         DBG("%s", gpu->name);
 998
 999         WARN_ON(!list_empty(&gpu->active_list));
1000
1001         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1002                 msm_ringbuffer_destroy(gpu->rb[i]);
1003                 gpu->rb[i] = NULL;
1004         }
1005
1006         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
1007
1008         if (!IS_ERR_OR_NULL(gpu->aspace)) {
1009                 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
1010                         NULL, 0);
1011                 msm_gem_address_space_put(gpu->aspace);
1012         }
1013 }