drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_sysfs_init(struct amdgpu_device *adev);
  49 static void psp_sysfs_fini(struct amdgpu_device *adev);
  50
  51 static int psp_load_smu_fw(struct psp_context *psp);
  52 static int psp_rap_terminate(struct psp_context *psp);
  53 static int psp_securedisplay_terminate(struct psp_context *psp);
  54
  55 static int psp_ring_init(struct psp_context *psp,
  56                          enum psp_ring_type ring_type)
  57 {
  58         int ret = 0;
  59         struct psp_ring *ring;
  60         struct amdgpu_device *adev = psp->adev;
  61
  62         ring = &psp->km_ring;
  63
  64         ring->ring_type = ring_type;
  65
  66         /* allocate 4k Page of Local Frame Buffer memory for ring */
  67         ring->ring_size = 0x1000;
  68         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  69                                       AMDGPU_GEM_DOMAIN_VRAM |
  70                                       AMDGPU_GEM_DOMAIN_GTT,
  71                                       &adev->firmware.rbuf,
  72                                       &ring->ring_mem_mc_addr,
  73                                       (void **)&ring->ring_mem);
  74         if (ret) {
  75                 ring->ring_size = 0;
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 /*
  83  * Due to DF Cstate management centralized to PMFW, the firmware
  84  * loading sequence will be updated as below:
  85  *   - Load KDB
  86  *   - Load SYS_DRV
  87  *   - Load tOS
  88  *   - Load PMFW
  89  *   - Setup TMR
  90  *   - Load other non-psp fw
  91  *   - Load ASD
  92  *   - Load XGMI/RAS/HDCP/DTM TA if any
  93  *
  94  * This new sequence is required for
  95  *   - Arcturus and onwards
  96  */
  97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  98 {
  99         struct amdgpu_device *adev = psp->adev;
 100
 101         if (amdgpu_sriov_vf(adev)) {
 102                 psp->pmfw_centralized_cstate_management = false;
 103                 return;
 104         }
 105
 106         switch (adev->ip_versions[MP0_HWIP][0]) {
 107         case IP_VERSION(11, 0, 0):
 108         case IP_VERSION(11, 0, 4):
 109         case IP_VERSION(11, 0, 5):
 110         case IP_VERSION(11, 0, 7):
 111         case IP_VERSION(11, 0, 9):
 112         case IP_VERSION(11, 0, 11):
 113         case IP_VERSION(11, 0, 12):
 114         case IP_VERSION(11, 0, 13):
 115         case IP_VERSION(13, 0, 0):
 116         case IP_VERSION(13, 0, 2):
 117         case IP_VERSION(13, 0, 7):
 118                 psp->pmfw_centralized_cstate_management = true;
 119                 break;
 120         default:
 121                 psp->pmfw_centralized_cstate_management = false;
 122                 break;
 123         }
 124 }
 125
 126 static int psp_init_sriov_microcode(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         char ucode_prefix[30];
 130         int ret = 0;
 131
 132         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 133
 134         switch (adev->ip_versions[MP0_HWIP][0]) {
 135         case IP_VERSION(9, 0, 0):
 136         case IP_VERSION(11, 0, 7):
 137         case IP_VERSION(11, 0, 9):
 138                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 139                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 140                 break;
 141         case IP_VERSION(13, 0, 2):
 142                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 143                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 144                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 145                 break;
 146         case IP_VERSION(13, 0, 0):
 147                 adev->virt.autoload_ucode_id = 0;
 148                 break;
 149         case IP_VERSION(13, 0, 10):
 150                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 151                 break;
 152         default:
 153                 return -EINVAL;
 154         }
 155         return ret;
 156 }
 157
 158 static int psp_early_init(void *handle)
 159 {
 160         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 161         struct psp_context *psp = &adev->psp;
 162
 163         switch (adev->ip_versions[MP0_HWIP][0]) {
 164         case IP_VERSION(9, 0, 0):
 165                 psp_v3_1_set_psp_funcs(psp);
 166                 psp->autoload_supported = false;
 167                 break;
 168         case IP_VERSION(10, 0, 0):
 169         case IP_VERSION(10, 0, 1):
 170                 psp_v10_0_set_psp_funcs(psp);
 171                 psp->autoload_supported = false;
 172                 break;
 173         case IP_VERSION(11, 0, 2):
 174         case IP_VERSION(11, 0, 4):
 175                 psp_v11_0_set_psp_funcs(psp);
 176                 psp->autoload_supported = false;
 177                 break;
 178         case IP_VERSION(11, 0, 0):
 179         case IP_VERSION(11, 0, 5):
 180         case IP_VERSION(11, 0, 9):
 181         case IP_VERSION(11, 0, 7):
 182         case IP_VERSION(11, 0, 11):
 183         case IP_VERSION(11, 5, 0):
 184         case IP_VERSION(11, 0, 12):
 185         case IP_VERSION(11, 0, 13):
 186                 psp_v11_0_set_psp_funcs(psp);
 187                 psp->autoload_supported = true;
 188                 break;
 189         case IP_VERSION(11, 0, 3):
 190         case IP_VERSION(12, 0, 1):
 191                 psp_v12_0_set_psp_funcs(psp);
 192                 break;
 193         case IP_VERSION(13, 0, 2):
 194                 psp_v13_0_set_psp_funcs(psp);
 195                 break;
 196         case IP_VERSION(13, 0, 1):
 197         case IP_VERSION(13, 0, 3):
 198         case IP_VERSION(13, 0, 5):
 199         case IP_VERSION(13, 0, 8):
 200         case IP_VERSION(13, 0, 10):
 201         case IP_VERSION(13, 0, 11):
 202                 psp_v13_0_set_psp_funcs(psp);
 203                 psp->autoload_supported = true;
 204                 break;
 205         case IP_VERSION(11, 0, 8):
 206                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 207                         psp_v11_0_8_set_psp_funcs(psp);
 208                         psp->autoload_supported = false;
 209                 }
 210                 break;
 211         case IP_VERSION(13, 0, 0):
 212         case IP_VERSION(13, 0, 7):
 213                 psp_v13_0_set_psp_funcs(psp);
 214                 psp->autoload_supported = true;
 215                 break;
 216         case IP_VERSION(13, 0, 4):
 217                 psp_v13_0_4_set_psp_funcs(psp);
 218                 psp->autoload_supported = true;
 219                 break;
 220         default:
 221                 return -EINVAL;
 222         }
 223
 224         psp->adev = adev;
 225
 226         psp_check_pmfw_centralized_cstate_management(psp);
 227
 228         if (amdgpu_sriov_vf(adev))
 229                 return psp_init_sriov_microcode(psp);
 230         else
 231                 return psp_init_microcode(psp);
 232 }
 233
 234 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 235 {
 236         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 237                               &mem_ctx->shared_buf);
 238         mem_ctx->shared_bo = NULL;
 239 }
 240
 241 static void psp_free_shared_bufs(struct psp_context *psp)
 242 {
 243         void *tmr_buf;
 244         void **pptr;
 245
 246         /* free TMR memory buffer */
 247         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 248         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 249         psp->tmr_bo = NULL;
 250
 251         /* free xgmi shared memory */
 252         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 253
 254         /* free ras shared memory */
 255         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 256
 257         /* free hdcp shared memory */
 258         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 259
 260         /* free dtm shared memory */
 261         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 262
 263         /* free rap shared memory */
 264         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 265
 266         /* free securedisplay shared memory */
 267         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 268
 269
 270 }
 271
 272 static void psp_memory_training_fini(struct psp_context *psp)
 273 {
 274         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 275
 276         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 277         kfree(ctx->sys_cache);
 278         ctx->sys_cache = NULL;
 279 }
 280
 281 static int psp_memory_training_init(struct psp_context *psp)
 282 {
 283         int ret;
 284         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 285
 286         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 287                 DRM_DEBUG("memory training is not supported!\n");
 288                 return 0;
 289         }
 290
 291         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 292         if (ctx->sys_cache == NULL) {
 293                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 294                 ret = -ENOMEM;
 295                 goto Err_out;
 296         }
 297
 298         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 299                   ctx->train_data_size,
 300                   ctx->p2c_train_data_offset,
 301                   ctx->c2p_train_data_offset);
 302         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 303         return 0;
 304
 305 Err_out:
 306         psp_memory_training_fini(psp);
 307         return ret;
 308 }
 309
 310 /*
 311  * Helper funciton to query psp runtime database entry
 312  *
 313  * @adev: amdgpu_device pointer
 314  * @entry_type: the type of psp runtime database entry
 315  * @db_entry: runtime database entry pointer
 316  *
 317  * Return false if runtime database doesn't exit or entry is invalid
 318  * or true if the specific database entry is found, and copy to @db_entry
 319  */
 320 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 321                                      enum psp_runtime_entry_type entry_type,
 322                                      void *db_entry)
 323 {
 324         uint64_t db_header_pos, db_dir_pos;
 325         struct psp_runtime_data_header db_header = {0};
 326         struct psp_runtime_data_directory db_dir = {0};
 327         bool ret = false;
 328         int i;
 329
 330         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 331         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 332
 333         /* read runtime db header from vram */
 334         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 335                         sizeof(struct psp_runtime_data_header), false);
 336
 337         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 338                 /* runtime db doesn't exist, exit */
 339                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 340                 return false;
 341         }
 342
 343         /* read runtime database entry from vram */
 344         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 345                         sizeof(struct psp_runtime_data_directory), false);
 346
 347         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 348                 /* invalid db entry count, exit */
 349                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 350                 return false;
 351         }
 352
 353         /* look up for requested entry type */
 354         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 355                 if (db_dir.entry_list[i].entry_type == entry_type) {
 356                         switch (entry_type) {
 357                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 358                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 359                                         /* invalid db entry size */
 360                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 361                                         return false;
 362                                 }
 363                                 /* read runtime database entry */
 364                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 365                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 366                                 ret = true;
 367                                 break;
 368                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 369                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 370                                         /* invalid db entry size */
 371                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 372                                         return false;
 373                                 }
 374                                 /* read runtime database entry */
 375                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 376                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 377                                 ret = true;
 378                                 break;
 379                         default:
 380                                 ret = false;
 381                                 break;
 382                         }
 383                 }
 384         }
 385
 386         return ret;
 387 }
 388
 389 static int psp_sw_init(void *handle)
 390 {
 391         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 392         struct psp_context *psp = &adev->psp;
 393         int ret;
 394         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 395         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 396         struct psp_runtime_scpm_entry scpm_entry;
 397
 398         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 399         if (!psp->cmd) {
 400                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 401                 ret = -ENOMEM;
 402         }
 403
 404         adev->psp.xgmi_context.supports_extended_data =
 405                 !adev->gmc.xgmi.connected_to_cpu &&
 406                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 407
 408         memset(&scpm_entry, 0, sizeof(scpm_entry));
 409         if ((psp_get_runtime_db_entry(adev,
 410                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 411                                 &scpm_entry)) &&
 412             (SCPM_DISABLE != scpm_entry.scpm_status)) {
 413                 adev->scpm_enabled = true;
 414                 adev->scpm_status = scpm_entry.scpm_status;
 415         } else {
 416                 adev->scpm_enabled = false;
 417                 adev->scpm_status = SCPM_DISABLE;
 418         }
 419
 420         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 421
 422         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 423         if (psp_get_runtime_db_entry(adev,
 424                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 425                                 &boot_cfg_entry)) {
 426                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 427                 if ((psp->boot_cfg_bitmask) &
 428                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 429                         /* If psp runtime database exists, then
 430                          * only enable two stage memory training
 431                          * when TWO_STAGE_DRAM_TRAINING bit is set
 432                          * in runtime database */
 433                         mem_training_ctx->enable_mem_training = true;
 434                 }
 435
 436         } else {
 437                 /* If psp runtime database doesn't exist or
 438                  * is invalid, force enable two stage memory
 439                  * training */
 440                 mem_training_ctx->enable_mem_training = true;
 441         }
 442
 443         if (mem_training_ctx->enable_mem_training) {
 444                 ret = psp_memory_training_init(psp);
 445                 if (ret) {
 446                         DRM_ERROR("Failed to initialize memory training!\n");
 447                         return ret;
 448                 }
 449
 450                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 451                 if (ret) {
 452                         DRM_ERROR("Failed to process memory training!\n");
 453                         return ret;
 454                 }
 455         }
 456
 457         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 458             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 459                 ret= psp_sysfs_init(adev);
 460                 if (ret) {
 461                         return ret;
 462                 }
 463         }
 464
 465         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 466                                       amdgpu_sriov_vf(adev) ?
 467                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 468                                       &psp->fw_pri_bo,
 469                                       &psp->fw_pri_mc_addr,
 470                                       &psp->fw_pri_buf);
 471         if (ret)
 472                 return ret;
 473
 474         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 475                                       AMDGPU_GEM_DOMAIN_VRAM,
 476                                       &psp->fence_buf_bo,
 477                                       &psp->fence_buf_mc_addr,
 478                                       &psp->fence_buf);
 479         if (ret)
 480                 goto failed1;
 481
 482         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 483                                       AMDGPU_GEM_DOMAIN_VRAM,
 484                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 485                                       (void **)&psp->cmd_buf_mem);
 486         if (ret)
 487                 goto failed2;
 488
 489         return 0;
 490
 491 failed2:
 492         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 493                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 494 failed1:
 495         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 496                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 497         return ret;
 498 }
 499
 500 static int psp_sw_fini(void *handle)
 501 {
 502         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 503         struct psp_context *psp = &adev->psp;
 504         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 505
 506         psp_memory_training_fini(psp);
 507
 508         amdgpu_ucode_release(&psp->sos_fw);
 509         amdgpu_ucode_release(&psp->asd_fw);
 510         amdgpu_ucode_release(&psp->ta_fw);
 511         amdgpu_ucode_release(&psp->cap_fw);
 512         amdgpu_ucode_release(&psp->toc_fw);
 513
 514         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 515             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 516                 psp_sysfs_fini(adev);
 517
 518         kfree(cmd);
 519         cmd = NULL;
 520
 521         if (psp->km_ring.ring_mem)
 522                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 523                                       &psp->km_ring.ring_mem_mc_addr,
 524                                       (void **)&psp->km_ring.ring_mem);
 525
 526         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 527                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 528         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 529                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 530         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 531                               (void **)&psp->cmd_buf_mem);
 532
 533         return 0;
 534 }
 535
 536 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 537                  uint32_t reg_val, uint32_t mask, bool check_changed)
 538 {
 539         uint32_t val;
 540         int i;
 541         struct amdgpu_device *adev = psp->adev;
 542
 543         if (psp->adev->no_hw_access)
 544                 return 0;
 545
 546         for (i = 0; i < adev->usec_timeout; i++) {
 547                 val = RREG32(reg_index);
 548                 if (check_changed) {
 549                         if (val != reg_val)
 550                                 return 0;
 551                 } else {
 552                         if ((val & mask) == reg_val)
 553                                 return 0;
 554                 }
 555                 udelay(1);
 556         }
 557
 558         return -ETIME;
 559 }
 560
 561 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 562 {
 563         switch (cmd_id) {
 564         case GFX_CMD_ID_LOAD_TA:
 565                 return "LOAD_TA";
 566         case GFX_CMD_ID_UNLOAD_TA:
 567                 return "UNLOAD_TA";
 568         case GFX_CMD_ID_INVOKE_CMD:
 569                 return "INVOKE_CMD";
 570         case GFX_CMD_ID_LOAD_ASD:
 571                 return "LOAD_ASD";
 572         case GFX_CMD_ID_SETUP_TMR:
 573                 return "SETUP_TMR";
 574         case GFX_CMD_ID_LOAD_IP_FW:
 575                 return "LOAD_IP_FW";
 576         case GFX_CMD_ID_DESTROY_TMR:
 577                 return "DESTROY_TMR";
 578         case GFX_CMD_ID_SAVE_RESTORE:
 579                 return "SAVE_RESTORE_IP_FW";
 580         case GFX_CMD_ID_SETUP_VMR:
 581                 return "SETUP_VMR";
 582         case GFX_CMD_ID_DESTROY_VMR:
 583                 return "DESTROY_VMR";
 584         case GFX_CMD_ID_PROG_REG:
 585                 return "PROG_REG";
 586         case GFX_CMD_ID_GET_FW_ATTESTATION:
 587                 return "GET_FW_ATTESTATION";
 588         case GFX_CMD_ID_LOAD_TOC:
 589                 return "ID_LOAD_TOC";
 590         case GFX_CMD_ID_AUTOLOAD_RLC:
 591                 return "AUTOLOAD_RLC";
 592         case GFX_CMD_ID_BOOT_CFG:
 593                 return "BOOT_CFG";
 594         default:
 595                 return "UNKNOWN CMD";
 596         }
 597 }
 598
 599 static int
 600 psp_cmd_submit_buf(struct psp_context *psp,
 601                    struct amdgpu_firmware_info *ucode,
 602                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 603 {
 604         int ret;
 605         int index;
 606         int timeout = 20000;
 607         bool ras_intr = false;
 608         bool skip_unsupport = false;
 609
 610         if (psp->adev->no_hw_access)
 611                 return 0;
 612
 613         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 614
 615         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 616
 617         index = atomic_inc_return(&psp->fence_value);
 618         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 619         if (ret) {
 620                 atomic_dec(&psp->fence_value);
 621                 goto exit;
 622         }
 623
 624         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 625         while (*((unsigned int *)psp->fence_buf) != index) {
 626                 if (--timeout == 0)
 627                         break;
 628                 /*
 629                  * Shouldn't wait for timeout when err_event_athub occurs,
 630                  * because gpu reset thread triggered and lock resource should
 631                  * be released for psp resume sequence.
 632                  */
 633                 ras_intr = amdgpu_ras_intr_triggered();
 634                 if (ras_intr)
 635                         break;
 636                 usleep_range(10, 100);
 637                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 638         }
 639
 640         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 641         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 642                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 643
 644         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 645
 646         /* In some cases, psp response status is not 0 even there is no
 647          * problem while the command is submitted. Some version of PSP FW
 648          * doesn't write 0 to that field.
 649          * So here we would like to only print a warning instead of an error
 650          * during psp initialization to avoid breaking hw_init and it doesn't
 651          * return -EINVAL.
 652          */
 653         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 654                 if (ucode)
 655                         DRM_WARN("failed to load ucode %s(0x%X) ",
 656                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 657                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 658                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 659                          psp->cmd_buf_mem->resp.status);
 660                 /* If any firmware (including CAP) load fails under SRIOV, it should
 661                  * return failure to stop the VF from initializing.
 662                  * Also return failure in case of timeout
 663                  */
 664                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 665                         ret = -EINVAL;
 666                         goto exit;
 667                 }
 668         }
 669
 670         if (ucode) {
 671                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 672                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 673         }
 674
 675 exit:
 676         return ret;
 677 }
 678
 679 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 680 {
 681         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 682
 683         mutex_lock(&psp->mutex);
 684
 685         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 686
 687         return cmd;
 688 }
 689
 690 static void release_psp_cmd_buf(struct psp_context *psp)
 691 {
 692         mutex_unlock(&psp->mutex);
 693 }
 694
 695 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 696                                  struct psp_gfx_cmd_resp *cmd,
 697                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 698 {
 699         struct amdgpu_device *adev = psp->adev;
 700         uint32_t size = amdgpu_bo_size(tmr_bo);
 701         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 702
 703         if (amdgpu_sriov_vf(psp->adev))
 704                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 705         else
 706                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 707         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 708         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 709         cmd->cmd.cmd_setup_tmr.buf_size = size;
 710         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 711         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 712         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 713 }
 714
 715 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 716                                       uint64_t pri_buf_mc, uint32_t size)
 717 {
 718         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 719         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 720         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 721         cmd->cmd.cmd_load_toc.toc_size = size;
 722 }
 723
 724 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 725 static int psp_load_toc(struct psp_context *psp,
 726                         uint32_t *tmr_size)
 727 {
 728         int ret;
 729         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 730
 731         /* Copy toc to psp firmware private buffer */
 732         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 733
 734         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 735
 736         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 737                                  psp->fence_buf_mc_addr);
 738         if (!ret)
 739                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 740
 741         release_psp_cmd_buf(psp);
 742
 743         return ret;
 744 }
 745
 746 /* Set up Trusted Memory Region */
 747 static int psp_tmr_init(struct psp_context *psp)
 748 {
 749         int ret = 0;
 750         int tmr_size;
 751         void *tmr_buf;
 752         void **pptr;
 753
 754         /*
 755          * According to HW engineer, they prefer the TMR address be "naturally
 756          * aligned" , e.g. the start address be an integer divide of TMR size.
 757          *
 758          * Note: this memory need be reserved till the driver
 759          * uninitializes.
 760          */
 761         tmr_size = PSP_TMR_SIZE(psp->adev);
 762
 763         /* For ASICs support RLC autoload, psp will parse the toc
 764          * and calculate the total size of TMR needed */
 765         if (!amdgpu_sriov_vf(psp->adev) &&
 766             psp->toc.start_addr &&
 767             psp->toc.size_bytes &&
 768             psp->fw_pri_buf) {
 769                 ret = psp_load_toc(psp, &tmr_size);
 770                 if (ret) {
 771                         DRM_ERROR("Failed to load toc\n");
 772                         return ret;
 773                 }
 774         }
 775
 776         if (!psp->tmr_bo) {
 777                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 778                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 779                                               PSP_TMR_ALIGNMENT,
 780                                               AMDGPU_HAS_VRAM(psp->adev) ?
 781                                               AMDGPU_GEM_DOMAIN_VRAM :
 782                                               AMDGPU_GEM_DOMAIN_GTT,
 783                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 784                                               pptr);
 785         }
 786
 787         return ret;
 788 }
 789
 790 static bool psp_skip_tmr(struct psp_context *psp)
 791 {
 792         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 793         case IP_VERSION(11, 0, 9):
 794         case IP_VERSION(11, 0, 7):
 795         case IP_VERSION(13, 0, 2):
 796         case IP_VERSION(13, 0, 10):
 797                 return true;
 798         default:
 799                 return false;
 800         }
 801 }
 802
 803 static int psp_tmr_load(struct psp_context *psp)
 804 {
 805         int ret;
 806         struct psp_gfx_cmd_resp *cmd;
 807
 808         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 809          * Already set up by host driver.
 810          */
 811         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 812                 return 0;
 813
 814         cmd = acquire_psp_cmd_buf(psp);
 815
 816         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 817         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 818                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 819
 820         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 821                                  psp->fence_buf_mc_addr);
 822
 823         release_psp_cmd_buf(psp);
 824
 825         return ret;
 826 }
 827
 828 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 829                                         struct psp_gfx_cmd_resp *cmd)
 830 {
 831         if (amdgpu_sriov_vf(psp->adev))
 832                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 833         else
 834                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 835 }
 836
 837 static int psp_tmr_unload(struct psp_context *psp)
 838 {
 839         int ret;
 840         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 841
 842         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 843         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 844
 845         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 846                                  psp->fence_buf_mc_addr);
 847
 848         release_psp_cmd_buf(psp);
 849
 850         return ret;
 851 }
 852
 853 static int psp_tmr_terminate(struct psp_context *psp)
 854 {
 855         return psp_tmr_unload(psp);
 856 }
 857
 858 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 859                                         uint64_t *output_ptr)
 860 {
 861         int ret;
 862         struct psp_gfx_cmd_resp *cmd;
 863
 864         if (!output_ptr)
 865                 return -EINVAL;
 866
 867         if (amdgpu_sriov_vf(psp->adev))
 868                 return 0;
 869
 870         cmd = acquire_psp_cmd_buf(psp);
 871
 872         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 873
 874         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 875                                  psp->fence_buf_mc_addr);
 876
 877         if (!ret) {
 878                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 879                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 880         }
 881
 882         release_psp_cmd_buf(psp);
 883
 884         return ret;
 885 }
 886
 887 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 888 {
 889         struct psp_context *psp = &adev->psp;
 890         struct psp_gfx_cmd_resp *cmd;
 891         int ret;
 892
 893         if (amdgpu_sriov_vf(adev))
 894                 return 0;
 895
 896         cmd = acquire_psp_cmd_buf(psp);
 897
 898         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 899         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 900
 901         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 902         if (!ret) {
 903                 *boot_cfg =
 904                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 905         }
 906
 907         release_psp_cmd_buf(psp);
 908
 909         return ret;
 910 }
 911
 912 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 913 {
 914         int ret;
 915         struct psp_context *psp = &adev->psp;
 916         struct psp_gfx_cmd_resp *cmd;
 917
 918         if (amdgpu_sriov_vf(adev))
 919                 return 0;
 920
 921         cmd = acquire_psp_cmd_buf(psp);
 922
 923         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 924         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 925         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 926         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 927
 928         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 929
 930         release_psp_cmd_buf(psp);
 931
 932         return ret;
 933 }
 934
 935 static int psp_rl_load(struct amdgpu_device *adev)
 936 {
 937         int ret;
 938         struct psp_context *psp = &adev->psp;
 939         struct psp_gfx_cmd_resp *cmd;
 940
 941         if (!is_psp_fw_valid(psp->rl))
 942                 return 0;
 943
 944         cmd = acquire_psp_cmd_buf(psp);
 945
 946         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 947         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 948
 949         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 950         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 951         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 952         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 953         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 954
 955         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 956
 957         release_psp_cmd_buf(psp);
 958
 959         return ret;
 960 }
 961
 962 static int psp_asd_initialize(struct psp_context *psp)
 963 {
 964         int ret;
 965
 966         /* If PSP version doesn't match ASD version, asd loading will be failed.
 967          * add workaround to bypass it for sriov now.
 968          * TODO: add version check to make it common
 969          */
 970         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
 971                 return 0;
 972
 973         psp->asd_context.mem_context.shared_mc_addr  = 0;
 974         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
 975         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
 976
 977         ret = psp_ta_load(psp, &psp->asd_context);
 978         if (!ret)
 979                 psp->asd_context.initialized = true;
 980
 981         return ret;
 982 }
 983
 984 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 985                                        uint32_t session_id)
 986 {
 987         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 988         cmd->cmd.cmd_unload_ta.session_id = session_id;
 989 }
 990
 991 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
 992 {
 993         int ret;
 994         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 995
 996         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
 997
 998         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 999
1000         context->resp_status = cmd->resp.status;
1001
1002         release_psp_cmd_buf(psp);
1003
1004         return ret;
1005 }
1006
1007 static int psp_asd_terminate(struct psp_context *psp)
1008 {
1009         int ret;
1010
1011         if (amdgpu_sriov_vf(psp->adev))
1012                 return 0;
1013
1014         if (!psp->asd_context.initialized)
1015                 return 0;
1016
1017         ret = psp_ta_unload(psp, &psp->asd_context);
1018         if (!ret)
1019                 psp->asd_context.initialized = false;
1020
1021         return ret;
1022 }
1023
1024 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1025                 uint32_t id, uint32_t value)
1026 {
1027         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1028         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1029         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1030 }
1031
1032 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1033                 uint32_t value)
1034 {
1035         struct psp_gfx_cmd_resp *cmd;
1036         int ret = 0;
1037
1038         if (reg >= PSP_REG_LAST)
1039                 return -EINVAL;
1040
1041         cmd = acquire_psp_cmd_buf(psp);
1042
1043         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1044         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1045         if (ret)
1046                 DRM_ERROR("PSP failed to program reg id %d", reg);
1047
1048         release_psp_cmd_buf(psp);
1049
1050         return ret;
1051 }
1052
1053 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1054                                      uint64_t ta_bin_mc,
1055                                      struct ta_context *context)
1056 {
1057         cmd->cmd_id                             = context->ta_load_type;
1058         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1059         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1060         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1061
1062         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1063                 lower_32_bits(context->mem_context.shared_mc_addr);
1064         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1065                 upper_32_bits(context->mem_context.shared_mc_addr);
1066         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1067 }
1068
1069 int psp_ta_init_shared_buf(struct psp_context *psp,
1070                                   struct ta_mem_context *mem_ctx)
1071 {
1072         /*
1073         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1074         * physical) for ta to host memory
1075         */
1076         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1077                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1078                                       AMDGPU_GEM_DOMAIN_GTT,
1079                                       &mem_ctx->shared_bo,
1080                                       &mem_ctx->shared_mc_addr,
1081                                       &mem_ctx->shared_buf);
1082 }
1083
1084 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1085                                        uint32_t ta_cmd_id,
1086                                        uint32_t session_id)
1087 {
1088         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1089         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1090         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1091 }
1092
1093 int psp_ta_invoke(struct psp_context *psp,
1094                   uint32_t ta_cmd_id,
1095                   struct ta_context *context)
1096 {
1097         int ret;
1098         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1099
1100         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1101
1102         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1103                                  psp->fence_buf_mc_addr);
1104
1105         context->resp_status = cmd->resp.status;
1106
1107         release_psp_cmd_buf(psp);
1108
1109         return ret;
1110 }
1111
1112 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1113 {
1114         int ret;
1115         struct psp_gfx_cmd_resp *cmd;
1116
1117         cmd = acquire_psp_cmd_buf(psp);
1118
1119         psp_copy_fw(psp, context->bin_desc.start_addr,
1120                     context->bin_desc.size_bytes);
1121
1122         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1123
1124         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1125                                  psp->fence_buf_mc_addr);
1126
1127         context->resp_status = cmd->resp.status;
1128
1129         if (!ret) {
1130                 context->session_id = cmd->resp.session_id;
1131         }
1132
1133         release_psp_cmd_buf(psp);
1134
1135         return ret;
1136 }
1137
1138 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1139 {
1140         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1141 }
1142
1143 int psp_xgmi_terminate(struct psp_context *psp)
1144 {
1145         int ret;
1146         struct amdgpu_device *adev = psp->adev;
1147
1148         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1149         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1150             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1151              adev->gmc.xgmi.connected_to_cpu))
1152                 return 0;
1153
1154         if (!psp->xgmi_context.context.initialized)
1155                 return 0;
1156
1157         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1158
1159         psp->xgmi_context.context.initialized = false;
1160
1161         return ret;
1162 }
1163
1164 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1165 {
1166         struct ta_xgmi_shared_memory *xgmi_cmd;
1167         int ret;
1168
1169         if (!psp->ta_fw ||
1170             !psp->xgmi_context.context.bin_desc.size_bytes ||
1171             !psp->xgmi_context.context.bin_desc.start_addr)
1172                 return -ENOENT;
1173
1174         if (!load_ta)
1175                 goto invoke;
1176
1177         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1178         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1179
1180         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1181                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1182                 if (ret)
1183                         return ret;
1184         }
1185
1186         /* Load XGMI TA */
1187         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1188         if (!ret)
1189                 psp->xgmi_context.context.initialized = true;
1190         else
1191                 return ret;
1192
1193 invoke:
1194         /* Initialize XGMI session */
1195         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1196         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1197         xgmi_cmd->flag_extend_link_record = set_extended_data;
1198         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1199
1200         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1201
1202         return ret;
1203 }
1204
1205 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1206 {
1207         struct ta_xgmi_shared_memory *xgmi_cmd;
1208         int ret;
1209
1210         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1211         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1212
1213         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1214
1215         /* Invoke xgmi ta to get hive id */
1216         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1217         if (ret)
1218                 return ret;
1219
1220         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1221
1222         return 0;
1223 }
1224
1225 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1226 {
1227         struct ta_xgmi_shared_memory *xgmi_cmd;
1228         int ret;
1229
1230         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1231         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1232
1233         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1234
1235         /* Invoke xgmi ta to get the node id */
1236         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1237         if (ret)
1238                 return ret;
1239
1240         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1241
1242         return 0;
1243 }
1244
1245 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1246 {
1247         return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1248                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1249 }
1250
1251 /*
1252  * Chips that support extended topology information require the driver to
1253  * reflect topology information in the opposite direction.  This is
1254  * because the TA has already exceeded its link record limit and if the
1255  * TA holds bi-directional information, the driver would have to do
1256  * multiple fetches instead of just two.
1257  */
1258 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1259                                         struct psp_xgmi_node_info node_info)
1260 {
1261         struct amdgpu_device *mirror_adev;
1262         struct amdgpu_hive_info *hive;
1263         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1264         uint64_t dst_node_id = node_info.node_id;
1265         uint8_t dst_num_hops = node_info.num_hops;
1266         uint8_t dst_num_links = node_info.num_links;
1267
1268         hive = amdgpu_get_xgmi_hive(psp->adev);
1269         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1270                 struct psp_xgmi_topology_info *mirror_top_info;
1271                 int j;
1272
1273                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1274                         continue;
1275
1276                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1277                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1278                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1279                                 continue;
1280
1281                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1282                         /*
1283                          * prevent 0 num_links value re-reflection since reflection
1284                          * criteria is based on num_hops (direct or indirect).
1285                          *
1286                          */
1287                         if (dst_num_links)
1288                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1289
1290                         break;
1291                 }
1292
1293                 break;
1294         }
1295
1296         amdgpu_put_xgmi_hive(hive);
1297 }
1298
1299 int psp_xgmi_get_topology_info(struct psp_context *psp,
1300                                int number_devices,
1301                                struct psp_xgmi_topology_info *topology,
1302                                bool get_extended_data)
1303 {
1304         struct ta_xgmi_shared_memory *xgmi_cmd;
1305         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1306         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1307         int i;
1308         int ret;
1309
1310         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1311                 return -EINVAL;
1312
1313         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1314         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1315         xgmi_cmd->flag_extend_link_record = get_extended_data;
1316
1317         /* Fill in the shared memory with topology information as input */
1318         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1319         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1320         topology_info_input->num_nodes = number_devices;
1321
1322         for (i = 0; i < topology_info_input->num_nodes; i++) {
1323                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1324                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1325                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1326                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1327         }
1328
1329         /* Invoke xgmi ta to get the topology information */
1330         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1331         if (ret)
1332                 return ret;
1333
1334         /* Read the output topology information from the shared memory */
1335         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1336         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1337         for (i = 0; i < topology->num_nodes; i++) {
1338                 /* extended data will either be 0 or equal to non-extended data */
1339                 if (topology_info_output->nodes[i].num_hops)
1340                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1341
1342                 /* non-extended data gets everything here so no need to update */
1343                 if (!get_extended_data) {
1344                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1345                         topology->nodes[i].is_sharing_enabled =
1346                                         topology_info_output->nodes[i].is_sharing_enabled;
1347                         topology->nodes[i].sdma_engine =
1348                                         topology_info_output->nodes[i].sdma_engine;
1349                 }
1350
1351         }
1352
1353         /* Invoke xgmi ta again to get the link information */
1354         if (psp_xgmi_peer_link_info_supported(psp)) {
1355                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1356
1357                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1358
1359                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1360
1361                 if (ret)
1362                         return ret;
1363
1364                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1365                 for (i = 0; i < topology->num_nodes; i++) {
1366                         /* accumulate num_links on extended data */
1367                         topology->nodes[i].num_links = get_extended_data ?
1368                                         topology->nodes[i].num_links +
1369                                                         link_info_output->nodes[i].num_links :
1370                                         link_info_output->nodes[i].num_links;
1371
1372                         /* reflect the topology information for bi-directionality */
1373                         if (psp->xgmi_context.supports_extended_data &&
1374                                         get_extended_data && topology->nodes[i].num_hops)
1375                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1376                 }
1377         }
1378
1379         return 0;
1380 }
1381
1382 int psp_xgmi_set_topology_info(struct psp_context *psp,
1383                                int number_devices,
1384                                struct psp_xgmi_topology_info *topology)
1385 {
1386         struct ta_xgmi_shared_memory *xgmi_cmd;
1387         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1388         int i;
1389
1390         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1391                 return -EINVAL;
1392
1393         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1394         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1395
1396         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1397         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1398         topology_info_input->num_nodes = number_devices;
1399
1400         for (i = 0; i < topology_info_input->num_nodes; i++) {
1401                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1402                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1403                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1404                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1405         }
1406
1407         /* Invoke xgmi ta to set topology information */
1408         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1409 }
1410
1411 // ras begin
1412 static void psp_ras_ta_check_status(struct psp_context *psp)
1413 {
1414         struct ta_ras_shared_memory *ras_cmd =
1415                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1416
1417         switch (ras_cmd->ras_status) {
1418         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1419                 dev_warn(psp->adev->dev,
1420                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1421                 break;
1422         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1423                 dev_warn(psp->adev->dev,
1424                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1425                 break;
1426         case TA_RAS_STATUS__SUCCESS:
1427                 break;
1428         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1429                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1430                         dev_warn(psp->adev->dev,
1431                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1432                 break;
1433         default:
1434                 dev_warn(psp->adev->dev,
1435                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1436                 break;
1437         }
1438 }
1439
1440 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1441 {
1442         struct ta_ras_shared_memory *ras_cmd;
1443         int ret;
1444
1445         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1446
1447         /*
1448          * TODO: bypass the loading in sriov for now
1449          */
1450         if (amdgpu_sriov_vf(psp->adev))
1451                 return 0;
1452
1453         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1454
1455         if (amdgpu_ras_intr_triggered())
1456                 return ret;
1457
1458         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1459         {
1460                 DRM_WARN("RAS: Unsupported Interface");
1461                 return -EINVAL;
1462         }
1463
1464         if (!ret) {
1465                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1466                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1467
1468                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1469                 }
1470                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1471                         dev_warn(psp->adev->dev,
1472                                  "RAS internal register access blocked\n");
1473
1474                 psp_ras_ta_check_status(psp);
1475         }
1476
1477         return ret;
1478 }
1479
1480 int psp_ras_enable_features(struct psp_context *psp,
1481                 union ta_ras_cmd_input *info, bool enable)
1482 {
1483         struct ta_ras_shared_memory *ras_cmd;
1484         int ret;
1485
1486         if (!psp->ras_context.context.initialized)
1487                 return -EINVAL;
1488
1489         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1490         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1491
1492         if (enable)
1493                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1494         else
1495                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1496
1497         ras_cmd->ras_in_message = *info;
1498
1499         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1500         if (ret)
1501                 return -EINVAL;
1502
1503         return 0;
1504 }
1505
1506 int psp_ras_terminate(struct psp_context *psp)
1507 {
1508         int ret;
1509
1510         /*
1511          * TODO: bypass the terminate in sriov for now
1512          */
1513         if (amdgpu_sriov_vf(psp->adev))
1514                 return 0;
1515
1516         if (!psp->ras_context.context.initialized)
1517                 return 0;
1518
1519         ret = psp_ta_unload(psp, &psp->ras_context.context);
1520
1521         psp->ras_context.context.initialized = false;
1522
1523         return ret;
1524 }
1525
1526 int psp_ras_initialize(struct psp_context *psp)
1527 {
1528         int ret;
1529         uint32_t boot_cfg = 0xFF;
1530         struct amdgpu_device *adev = psp->adev;
1531         struct ta_ras_shared_memory *ras_cmd;
1532
1533         /*
1534          * TODO: bypass the initialize in sriov for now
1535          */
1536         if (amdgpu_sriov_vf(adev))
1537                 return 0;
1538
1539         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1540             !adev->psp.ras_context.context.bin_desc.start_addr) {
1541                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1542                 return 0;
1543         }
1544
1545         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1546                 /* query GECC enablement status from boot config
1547                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1548                  */
1549                 ret = psp_boot_config_get(adev, &boot_cfg);
1550                 if (ret)
1551                         dev_warn(adev->dev, "PSP get boot config failed\n");
1552
1553                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1554                         if (!boot_cfg) {
1555                                 dev_info(adev->dev, "GECC is disabled\n");
1556                         } else {
1557                                 /* disable GECC in next boot cycle if ras is
1558                                  * disabled by module parameter amdgpu_ras_enable
1559                                  * and/or amdgpu_ras_mask, or boot_config_get call
1560                                  * is failed
1561                                  */
1562                                 ret = psp_boot_config_set(adev, 0);
1563                                 if (ret)
1564                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1565                                 else
1566                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1567                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1568                         }
1569                 } else {
1570                         if (1 == boot_cfg) {
1571                                 dev_info(adev->dev, "GECC is enabled\n");
1572                         } else {
1573                                 /* enable GECC in next boot cycle if it is disabled
1574                                  * in boot config, or force enable GECC if failed to
1575                                  * get boot configuration
1576                                  */
1577                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1578                                 if (ret)
1579                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1580                                 else
1581                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1582                         }
1583                 }
1584         }
1585
1586         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1587         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1588
1589         if (!psp->ras_context.context.mem_context.shared_buf) {
1590                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1591                 if (ret)
1592                         return ret;
1593         }
1594
1595         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1596         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1597
1598         if (amdgpu_ras_is_poison_mode_supported(adev))
1599                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1600         if (!adev->gmc.xgmi.connected_to_cpu)
1601                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1602
1603         ret = psp_ta_load(psp, &psp->ras_context.context);
1604
1605         if (!ret && !ras_cmd->ras_status)
1606                 psp->ras_context.context.initialized = true;
1607         else {
1608                 if (ras_cmd->ras_status)
1609                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1610
1611                 /* fail to load RAS TA */
1612                 psp->ras_context.context.initialized = false;
1613         }
1614
1615         return ret;
1616 }
1617
1618 int psp_ras_trigger_error(struct psp_context *psp,
1619                           struct ta_ras_trigger_error_input *info)
1620 {
1621         struct ta_ras_shared_memory *ras_cmd;
1622         int ret;
1623
1624         if (!psp->ras_context.context.initialized)
1625                 return -EINVAL;
1626
1627         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1628         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1629
1630         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1631         ras_cmd->ras_in_message.trigger_error = *info;
1632
1633         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1634         if (ret)
1635                 return -EINVAL;
1636
1637         /* If err_event_athub occurs error inject was successful, however
1638            return status from TA is no long reliable */
1639         if (amdgpu_ras_intr_triggered())
1640                 return 0;
1641
1642         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1643                 return -EACCES;
1644         else if (ras_cmd->ras_status)
1645                 return -EINVAL;
1646
1647         return 0;
1648 }
1649 // ras end
1650
1651 // HDCP start
1652 static int psp_hdcp_initialize(struct psp_context *psp)
1653 {
1654         int ret;
1655
1656         /*
1657          * TODO: bypass the initialize in sriov for now
1658          */
1659         if (amdgpu_sriov_vf(psp->adev))
1660                 return 0;
1661
1662         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1663             !psp->hdcp_context.context.bin_desc.start_addr) {
1664                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1665                 return 0;
1666         }
1667
1668         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1669         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1670
1671         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1672                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1673                 if (ret)
1674                         return ret;
1675         }
1676
1677         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1678         if (!ret) {
1679                 psp->hdcp_context.context.initialized = true;
1680                 mutex_init(&psp->hdcp_context.mutex);
1681         }
1682
1683         return ret;
1684 }
1685
1686 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1687 {
1688         /*
1689          * TODO: bypass the loading in sriov for now
1690          */
1691         if (amdgpu_sriov_vf(psp->adev))
1692                 return 0;
1693
1694         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1695 }
1696
1697 static int psp_hdcp_terminate(struct psp_context *psp)
1698 {
1699         int ret;
1700
1701         /*
1702          * TODO: bypass the terminate in sriov for now
1703          */
1704         if (amdgpu_sriov_vf(psp->adev))
1705                 return 0;
1706
1707         if (!psp->hdcp_context.context.initialized)
1708                 return 0;
1709
1710         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1711
1712         psp->hdcp_context.context.initialized = false;
1713
1714         return ret;
1715 }
1716 // HDCP end
1717
1718 // DTM start
1719 static int psp_dtm_initialize(struct psp_context *psp)
1720 {
1721         int ret;
1722
1723         /*
1724          * TODO: bypass the initialize in sriov for now
1725          */
1726         if (amdgpu_sriov_vf(psp->adev))
1727                 return 0;
1728
1729         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1730             !psp->dtm_context.context.bin_desc.start_addr) {
1731                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1732                 return 0;
1733         }
1734
1735         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1736         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1737
1738         if (!psp->dtm_context.context.mem_context.shared_buf) {
1739                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1740                 if (ret)
1741                         return ret;
1742         }
1743
1744         ret = psp_ta_load(psp, &psp->dtm_context.context);
1745         if (!ret) {
1746                 psp->dtm_context.context.initialized = true;
1747                 mutex_init(&psp->dtm_context.mutex);
1748         }
1749
1750         return ret;
1751 }
1752
1753 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1754 {
1755         /*
1756          * TODO: bypass the loading in sriov for now
1757          */
1758         if (amdgpu_sriov_vf(psp->adev))
1759                 return 0;
1760
1761         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1762 }
1763
1764 static int psp_dtm_terminate(struct psp_context *psp)
1765 {
1766         int ret;
1767
1768         /*
1769          * TODO: bypass the terminate in sriov for now
1770          */
1771         if (amdgpu_sriov_vf(psp->adev))
1772                 return 0;
1773
1774         if (!psp->dtm_context.context.initialized)
1775                 return 0;
1776
1777         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1778
1779         psp->dtm_context.context.initialized = false;
1780
1781         return ret;
1782 }
1783 // DTM end
1784
1785 // RAP start
1786 static int psp_rap_initialize(struct psp_context *psp)
1787 {
1788         int ret;
1789         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1790
1791         /*
1792          * TODO: bypass the initialize in sriov for now
1793          */
1794         if (amdgpu_sriov_vf(psp->adev))
1795                 return 0;
1796
1797         if (!psp->rap_context.context.bin_desc.size_bytes ||
1798             !psp->rap_context.context.bin_desc.start_addr) {
1799                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1800                 return 0;
1801         }
1802
1803         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1804         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1805
1806         if (!psp->rap_context.context.mem_context.shared_buf) {
1807                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1808                 if (ret)
1809                         return ret;
1810         }
1811
1812         ret = psp_ta_load(psp, &psp->rap_context.context);
1813         if (!ret) {
1814                 psp->rap_context.context.initialized = true;
1815                 mutex_init(&psp->rap_context.mutex);
1816         } else
1817                 return ret;
1818
1819         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1820         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1821                 psp_rap_terminate(psp);
1822                 /* free rap shared memory */
1823                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1824
1825                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1826                          ret, status);
1827
1828                 return ret;
1829         }
1830
1831         return 0;
1832 }
1833
1834 static int psp_rap_terminate(struct psp_context *psp)
1835 {
1836         int ret;
1837
1838         if (!psp->rap_context.context.initialized)
1839                 return 0;
1840
1841         ret = psp_ta_unload(psp, &psp->rap_context.context);
1842
1843         psp->rap_context.context.initialized = false;
1844
1845         return ret;
1846 }
1847
1848 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1849 {
1850         struct ta_rap_shared_memory *rap_cmd;
1851         int ret = 0;
1852
1853         if (!psp->rap_context.context.initialized)
1854                 return 0;
1855
1856         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1857             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1858                 return -EINVAL;
1859
1860         mutex_lock(&psp->rap_context.mutex);
1861
1862         rap_cmd = (struct ta_rap_shared_memory *)
1863                   psp->rap_context.context.mem_context.shared_buf;
1864         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1865
1866         rap_cmd->cmd_id = ta_cmd_id;
1867         rap_cmd->validation_method_id = METHOD_A;
1868
1869         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1870         if (ret)
1871                 goto out_unlock;
1872
1873         if (status)
1874                 *status = rap_cmd->rap_status;
1875
1876 out_unlock:
1877         mutex_unlock(&psp->rap_context.mutex);
1878
1879         return ret;
1880 }
1881 // RAP end
1882
1883 /* securedisplay start */
1884 static int psp_securedisplay_initialize(struct psp_context *psp)
1885 {
1886         int ret;
1887         struct ta_securedisplay_cmd *securedisplay_cmd;
1888
1889         /*
1890          * TODO: bypass the initialize in sriov for now
1891          */
1892         if (amdgpu_sriov_vf(psp->adev))
1893                 return 0;
1894
1895         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1896             !psp->securedisplay_context.context.bin_desc.start_addr) {
1897                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1898                 return 0;
1899         }
1900
1901         psp->securedisplay_context.context.mem_context.shared_mem_size =
1902                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1903         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1904
1905         if (!psp->securedisplay_context.context.initialized) {
1906                 ret = psp_ta_init_shared_buf(psp,
1907                                              &psp->securedisplay_context.context.mem_context);
1908                 if (ret)
1909                         return ret;
1910         }
1911
1912         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1913         if (!ret) {
1914                 psp->securedisplay_context.context.initialized = true;
1915                 mutex_init(&psp->securedisplay_context.mutex);
1916         } else
1917                 return ret;
1918
1919         mutex_lock(&psp->securedisplay_context.mutex);
1920
1921         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1922                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1923
1924         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1925
1926         mutex_unlock(&psp->securedisplay_context.mutex);
1927
1928         if (ret) {
1929                 psp_securedisplay_terminate(psp);
1930                 /* free securedisplay shared memory */
1931                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1932                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1933                 return -EINVAL;
1934         }
1935
1936         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1937                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1938                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1939                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1940         }
1941
1942         return 0;
1943 }
1944
1945 static int psp_securedisplay_terminate(struct psp_context *psp)
1946 {
1947         int ret;
1948
1949         /*
1950          * TODO:bypass the terminate in sriov for now
1951          */
1952         if (amdgpu_sriov_vf(psp->adev))
1953                 return 0;
1954
1955         if (!psp->securedisplay_context.context.initialized)
1956                 return 0;
1957
1958         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1959
1960         psp->securedisplay_context.context.initialized = false;
1961
1962         return ret;
1963 }
1964
1965 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1966 {
1967         int ret;
1968
1969         if (!psp->securedisplay_context.context.initialized)
1970                 return -EINVAL;
1971
1972         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1973             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1974                 return -EINVAL;
1975
1976         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
1977
1978         return ret;
1979 }
1980 /* SECUREDISPLAY end */
1981
1982 static int psp_hw_start(struct psp_context *psp)
1983 {
1984         struct amdgpu_device *adev = psp->adev;
1985         int ret;
1986
1987         if (!amdgpu_sriov_vf(adev)) {
1988                 if ((is_psp_fw_valid(psp->kdb)) &&
1989                     (psp->funcs->bootloader_load_kdb != NULL)) {
1990                         ret = psp_bootloader_load_kdb(psp);
1991                         if (ret) {
1992                                 DRM_ERROR("PSP load kdb failed!\n");
1993                                 return ret;
1994                         }
1995                 }
1996
1997                 if ((is_psp_fw_valid(psp->spl)) &&
1998                     (psp->funcs->bootloader_load_spl != NULL)) {
1999                         ret = psp_bootloader_load_spl(psp);
2000                         if (ret) {
2001                                 DRM_ERROR("PSP load spl failed!\n");
2002                                 return ret;
2003                         }
2004                 }
2005
2006                 if ((is_psp_fw_valid(psp->sys)) &&
2007                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2008                         ret = psp_bootloader_load_sysdrv(psp);
2009                         if (ret) {
2010                                 DRM_ERROR("PSP load sys drv failed!\n");
2011                                 return ret;
2012                         }
2013                 }
2014
2015                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2016                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2017                         ret = psp_bootloader_load_soc_drv(psp);
2018                         if (ret) {
2019                                 DRM_ERROR("PSP load soc drv failed!\n");
2020                                 return ret;
2021                         }
2022                 }
2023
2024                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2025                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2026                         ret = psp_bootloader_load_intf_drv(psp);
2027                         if (ret) {
2028                                 DRM_ERROR("PSP load intf drv failed!\n");
2029                                 return ret;
2030                         }
2031                 }
2032
2033                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2034                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2035                         ret = psp_bootloader_load_dbg_drv(psp);
2036                         if (ret) {
2037                                 DRM_ERROR("PSP load dbg drv failed!\n");
2038                                 return ret;
2039                         }
2040                 }
2041
2042                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2043                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2044                         ret = psp_bootloader_load_ras_drv(psp);
2045                         if (ret) {
2046                                 DRM_ERROR("PSP load ras_drv failed!\n");
2047                                 return ret;
2048                         }
2049                 }
2050
2051                 if ((is_psp_fw_valid(psp->sos)) &&
2052                     (psp->funcs->bootloader_load_sos != NULL)) {
2053                         ret = psp_bootloader_load_sos(psp);
2054                         if (ret) {
2055                                 DRM_ERROR("PSP load sos failed!\n");
2056                                 return ret;
2057                         }
2058                 }
2059         }
2060
2061         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2062         if (ret) {
2063                 DRM_ERROR("PSP create ring failed!\n");
2064                 return ret;
2065         }
2066
2067         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2068                 goto skip_pin_bo;
2069
2070         ret = psp_tmr_init(psp);
2071         if (ret) {
2072                 DRM_ERROR("PSP tmr init failed!\n");
2073                 return ret;
2074         }
2075
2076 skip_pin_bo:
2077         /*
2078          * For ASICs with DF Cstate management centralized
2079          * to PMFW, TMR setup should be performed after PMFW
2080          * loaded and before other non-psp firmware loaded.
2081          */
2082         if (psp->pmfw_centralized_cstate_management) {
2083                 ret = psp_load_smu_fw(psp);
2084                 if (ret)
2085                         return ret;
2086         }
2087
2088         ret = psp_tmr_load(psp);
2089         if (ret) {
2090                 DRM_ERROR("PSP load tmr failed!\n");
2091                 return ret;
2092         }
2093
2094         return 0;
2095 }
2096
2097 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2098                            enum psp_gfx_fw_type *type)
2099 {
2100         switch (ucode->ucode_id) {
2101         case AMDGPU_UCODE_ID_CAP:
2102                 *type = GFX_FW_TYPE_CAP;
2103                 break;
2104         case AMDGPU_UCODE_ID_SDMA0:
2105                 *type = GFX_FW_TYPE_SDMA0;
2106                 break;
2107         case AMDGPU_UCODE_ID_SDMA1:
2108                 *type = GFX_FW_TYPE_SDMA1;
2109                 break;
2110         case AMDGPU_UCODE_ID_SDMA2:
2111                 *type = GFX_FW_TYPE_SDMA2;
2112                 break;
2113         case AMDGPU_UCODE_ID_SDMA3:
2114                 *type = GFX_FW_TYPE_SDMA3;
2115                 break;
2116         case AMDGPU_UCODE_ID_SDMA4:
2117                 *type = GFX_FW_TYPE_SDMA4;
2118                 break;
2119         case AMDGPU_UCODE_ID_SDMA5:
2120                 *type = GFX_FW_TYPE_SDMA5;
2121                 break;
2122         case AMDGPU_UCODE_ID_SDMA6:
2123                 *type = GFX_FW_TYPE_SDMA6;
2124                 break;
2125         case AMDGPU_UCODE_ID_SDMA7:
2126                 *type = GFX_FW_TYPE_SDMA7;
2127                 break;
2128         case AMDGPU_UCODE_ID_CP_MES:
2129                 *type = GFX_FW_TYPE_CP_MES;
2130                 break;
2131         case AMDGPU_UCODE_ID_CP_MES_DATA:
2132                 *type = GFX_FW_TYPE_MES_STACK;
2133                 break;
2134         case AMDGPU_UCODE_ID_CP_MES1:
2135                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2136                 break;
2137         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2138                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2139                 break;
2140         case AMDGPU_UCODE_ID_CP_CE:
2141                 *type = GFX_FW_TYPE_CP_CE;
2142                 break;
2143         case AMDGPU_UCODE_ID_CP_PFP:
2144                 *type = GFX_FW_TYPE_CP_PFP;
2145                 break;
2146         case AMDGPU_UCODE_ID_CP_ME:
2147                 *type = GFX_FW_TYPE_CP_ME;
2148                 break;
2149         case AMDGPU_UCODE_ID_CP_MEC1:
2150                 *type = GFX_FW_TYPE_CP_MEC;
2151                 break;
2152         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2153                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2154                 break;
2155         case AMDGPU_UCODE_ID_CP_MEC2:
2156                 *type = GFX_FW_TYPE_CP_MEC;
2157                 break;
2158         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2159                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2160                 break;
2161         case AMDGPU_UCODE_ID_RLC_P:
2162                 *type = GFX_FW_TYPE_RLC_P;
2163                 break;
2164         case AMDGPU_UCODE_ID_RLC_V:
2165                 *type = GFX_FW_TYPE_RLC_V;
2166                 break;
2167         case AMDGPU_UCODE_ID_RLC_G:
2168                 *type = GFX_FW_TYPE_RLC_G;
2169                 break;
2170         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2171                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2172                 break;
2173         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2174                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2175                 break;
2176         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2177                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2178                 break;
2179         case AMDGPU_UCODE_ID_RLC_IRAM:
2180                 *type = GFX_FW_TYPE_RLC_IRAM;
2181                 break;
2182         case AMDGPU_UCODE_ID_RLC_DRAM:
2183                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2184                 break;
2185         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2186                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2187                 break;
2188         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2189                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2190                 break;
2191         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2192                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2193                 break;
2194         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2195                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2196                 break;
2197         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2198                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2199                 break;
2200         case AMDGPU_UCODE_ID_SMC:
2201                 *type = GFX_FW_TYPE_SMU;
2202                 break;
2203         case AMDGPU_UCODE_ID_PPTABLE:
2204                 *type = GFX_FW_TYPE_PPTABLE;
2205                 break;
2206         case AMDGPU_UCODE_ID_UVD:
2207                 *type = GFX_FW_TYPE_UVD;
2208                 break;
2209         case AMDGPU_UCODE_ID_UVD1:
2210                 *type = GFX_FW_TYPE_UVD1;
2211                 break;
2212         case AMDGPU_UCODE_ID_VCE:
2213                 *type = GFX_FW_TYPE_VCE;
2214                 break;
2215         case AMDGPU_UCODE_ID_VCN:
2216                 *type = GFX_FW_TYPE_VCN;
2217                 break;
2218         case AMDGPU_UCODE_ID_VCN1:
2219                 *type = GFX_FW_TYPE_VCN1;
2220                 break;
2221         case AMDGPU_UCODE_ID_DMCU_ERAM:
2222                 *type = GFX_FW_TYPE_DMCU_ERAM;
2223                 break;
2224         case AMDGPU_UCODE_ID_DMCU_INTV:
2225                 *type = GFX_FW_TYPE_DMCU_ISR;
2226                 break;
2227         case AMDGPU_UCODE_ID_VCN0_RAM:
2228                 *type = GFX_FW_TYPE_VCN0_RAM;
2229                 break;
2230         case AMDGPU_UCODE_ID_VCN1_RAM:
2231                 *type = GFX_FW_TYPE_VCN1_RAM;
2232                 break;
2233         case AMDGPU_UCODE_ID_DMCUB:
2234                 *type = GFX_FW_TYPE_DMUB;
2235                 break;
2236         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2237                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2238                 break;
2239         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2240                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2241                 break;
2242         case AMDGPU_UCODE_ID_IMU_I:
2243                 *type = GFX_FW_TYPE_IMU_I;
2244                 break;
2245         case AMDGPU_UCODE_ID_IMU_D:
2246                 *type = GFX_FW_TYPE_IMU_D;
2247                 break;
2248         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2249                 *type = GFX_FW_TYPE_RS64_PFP;
2250                 break;
2251         case AMDGPU_UCODE_ID_CP_RS64_ME:
2252                 *type = GFX_FW_TYPE_RS64_ME;
2253                 break;
2254         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2255                 *type = GFX_FW_TYPE_RS64_MEC;
2256                 break;
2257         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2258                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2259                 break;
2260         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2261                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2262                 break;
2263         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2264                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2265                 break;
2266         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2267                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2268                 break;
2269         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2270                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2271                 break;
2272         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2273                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2274                 break;
2275         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2276                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2277                 break;
2278         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2279                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2280                 break;
2281         case AMDGPU_UCODE_ID_MAXIMUM:
2282         default:
2283                 return -EINVAL;
2284         }
2285
2286         return 0;
2287 }
2288
2289 static void psp_print_fw_hdr(struct psp_context *psp,
2290                              struct amdgpu_firmware_info *ucode)
2291 {
2292         struct amdgpu_device *adev = psp->adev;
2293         struct common_firmware_header *hdr;
2294
2295         switch (ucode->ucode_id) {
2296         case AMDGPU_UCODE_ID_SDMA0:
2297         case AMDGPU_UCODE_ID_SDMA1:
2298         case AMDGPU_UCODE_ID_SDMA2:
2299         case AMDGPU_UCODE_ID_SDMA3:
2300         case AMDGPU_UCODE_ID_SDMA4:
2301         case AMDGPU_UCODE_ID_SDMA5:
2302         case AMDGPU_UCODE_ID_SDMA6:
2303         case AMDGPU_UCODE_ID_SDMA7:
2304                 hdr = (struct common_firmware_header *)
2305                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2306                 amdgpu_ucode_print_sdma_hdr(hdr);
2307                 break;
2308         case AMDGPU_UCODE_ID_CP_CE:
2309                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2310                 amdgpu_ucode_print_gfx_hdr(hdr);
2311                 break;
2312         case AMDGPU_UCODE_ID_CP_PFP:
2313                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2314                 amdgpu_ucode_print_gfx_hdr(hdr);
2315                 break;
2316         case AMDGPU_UCODE_ID_CP_ME:
2317                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2318                 amdgpu_ucode_print_gfx_hdr(hdr);
2319                 break;
2320         case AMDGPU_UCODE_ID_CP_MEC1:
2321                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2322                 amdgpu_ucode_print_gfx_hdr(hdr);
2323                 break;
2324         case AMDGPU_UCODE_ID_RLC_G:
2325                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2326                 amdgpu_ucode_print_rlc_hdr(hdr);
2327                 break;
2328         case AMDGPU_UCODE_ID_SMC:
2329                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2330                 amdgpu_ucode_print_smc_hdr(hdr);
2331                 break;
2332         default:
2333                 break;
2334         }
2335 }
2336
2337 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2338                                        struct psp_gfx_cmd_resp *cmd)
2339 {
2340         int ret;
2341         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2342
2343         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2344         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2345         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2346         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2347
2348         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2349         if (ret)
2350                 DRM_ERROR("Unknown firmware type\n");
2351
2352         return ret;
2353 }
2354
2355 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2356                                   struct amdgpu_firmware_info *ucode)
2357 {
2358         int ret = 0;
2359         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2360
2361         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2362         if (!ret) {
2363                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2364                                          psp->fence_buf_mc_addr);
2365         }
2366
2367         release_psp_cmd_buf(psp);
2368
2369         return ret;
2370 }
2371
2372 static int psp_load_smu_fw(struct psp_context *psp)
2373 {
2374         int ret;
2375         struct amdgpu_device *adev = psp->adev;
2376         struct amdgpu_firmware_info *ucode =
2377                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2378         struct amdgpu_ras *ras = psp->ras_context.ras;
2379
2380         /*
2381          * Skip SMU FW reloading in case of using BACO for runpm only,
2382          * as SMU is always alive.
2383          */
2384         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2385                 return 0;
2386
2387         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2388                 return 0;
2389
2390         if ((amdgpu_in_reset(adev) &&
2391              ras && adev->ras_enabled &&
2392              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2393               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2394                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2395                 if (ret) {
2396                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2397                 }
2398         }
2399
2400         ret = psp_execute_non_psp_fw_load(psp, ucode);
2401
2402         if (ret)
2403                 DRM_ERROR("PSP load smu failed!\n");
2404
2405         return ret;
2406 }
2407
2408 static bool fw_load_skip_check(struct psp_context *psp,
2409                                struct amdgpu_firmware_info *ucode)
2410 {
2411         if (!ucode->fw || !ucode->ucode_size)
2412                 return true;
2413
2414         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2415             (psp_smu_reload_quirk(psp) ||
2416              psp->autoload_supported ||
2417              psp->pmfw_centralized_cstate_management))
2418                 return true;
2419
2420         if (amdgpu_sriov_vf(psp->adev) &&
2421             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2422                 return true;
2423
2424         if (psp->autoload_supported &&
2425             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2426              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2427                 /* skip mec JT when autoload is enabled */
2428                 return true;
2429
2430         return false;
2431 }
2432
2433 int psp_load_fw_list(struct psp_context *psp,
2434                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2435 {
2436         int ret = 0, i;
2437         struct amdgpu_firmware_info *ucode;
2438
2439         for (i = 0; i < ucode_count; ++i) {
2440                 ucode = ucode_list[i];
2441                 psp_print_fw_hdr(psp, ucode);
2442                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2443                 if (ret)
2444                         return ret;
2445         }
2446         return ret;
2447 }
2448
2449 static int psp_load_non_psp_fw(struct psp_context *psp)
2450 {
2451         int i, ret;
2452         struct amdgpu_firmware_info *ucode;
2453         struct amdgpu_device *adev = psp->adev;
2454
2455         if (psp->autoload_supported &&
2456             !psp->pmfw_centralized_cstate_management) {
2457                 ret = psp_load_smu_fw(psp);
2458                 if (ret)
2459                         return ret;
2460         }
2461
2462         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2463                 ucode = &adev->firmware.ucode[i];
2464
2465                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2466                     !fw_load_skip_check(psp, ucode)) {
2467                         ret = psp_load_smu_fw(psp);
2468                         if (ret)
2469                                 return ret;
2470                         continue;
2471                 }
2472
2473                 if (fw_load_skip_check(psp, ucode))
2474                         continue;
2475
2476                 if (psp->autoload_supported &&
2477                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2478                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2479                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2480                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2481                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2482                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2483                         /* PSP only receive one SDMA fw for sienna_cichlid,
2484                          * as all four sdma fw are same */
2485                         continue;
2486
2487                 psp_print_fw_hdr(psp, ucode);
2488
2489                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2490                 if (ret)
2491                         return ret;
2492
2493                 /* Start rlc autoload after psp recieved all the gfx firmware */
2494                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2495                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2496                         ret = psp_rlc_autoload_start(psp);
2497                         if (ret) {
2498                                 DRM_ERROR("Failed to start rlc autoload\n");
2499                                 return ret;
2500                         }
2501                 }
2502         }
2503
2504         return 0;
2505 }
2506
2507 static int psp_load_fw(struct amdgpu_device *adev)
2508 {
2509         int ret;
2510         struct psp_context *psp = &adev->psp;
2511
2512         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2513                 /* should not destroy ring, only stop */
2514                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2515         } else {
2516                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2517
2518                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2519                 if (ret) {
2520                         DRM_ERROR("PSP ring init failed!\n");
2521                         goto failed;
2522                 }
2523         }
2524
2525         ret = psp_hw_start(psp);
2526         if (ret)
2527                 goto failed;
2528
2529         ret = psp_load_non_psp_fw(psp);
2530         if (ret)
2531                 goto failed1;
2532
2533         ret = psp_asd_initialize(psp);
2534         if (ret) {
2535                 DRM_ERROR("PSP load asd failed!\n");
2536                 goto failed1;
2537         }
2538
2539         ret = psp_rl_load(adev);
2540         if (ret) {
2541                 DRM_ERROR("PSP load RL failed!\n");
2542                 goto failed1;
2543         }
2544
2545         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2546                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2547                         ret = psp_xgmi_initialize(psp, false, true);
2548                         /* Warning the XGMI seesion initialize failure
2549                         * Instead of stop driver initialization
2550                         */
2551                         if (ret)
2552                                 dev_err(psp->adev->dev,
2553                                         "XGMI: Failed to initialize XGMI session\n");
2554                 }
2555         }
2556
2557         if (psp->ta_fw) {
2558                 ret = psp_ras_initialize(psp);
2559                 if (ret)
2560                         dev_err(psp->adev->dev,
2561                                         "RAS: Failed to initialize RAS\n");
2562
2563                 ret = psp_hdcp_initialize(psp);
2564                 if (ret)
2565                         dev_err(psp->adev->dev,
2566                                 "HDCP: Failed to initialize HDCP\n");
2567
2568                 ret = psp_dtm_initialize(psp);
2569                 if (ret)
2570                         dev_err(psp->adev->dev,
2571                                 "DTM: Failed to initialize DTM\n");
2572
2573                 ret = psp_rap_initialize(psp);
2574                 if (ret)
2575                         dev_err(psp->adev->dev,
2576                                 "RAP: Failed to initialize RAP\n");
2577
2578                 ret = psp_securedisplay_initialize(psp);
2579                 if (ret)
2580                         dev_err(psp->adev->dev,
2581                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2582         }
2583
2584         return 0;
2585
2586 failed1:
2587         psp_free_shared_bufs(psp);
2588 failed:
2589         /*
2590          * all cleanup jobs (xgmi terminate, ras terminate,
2591          * ring destroy, cmd/fence/fw buffers destory,
2592          * psp->cmd destory) are delayed to psp_hw_fini
2593          */
2594         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2595         return ret;
2596 }
2597
2598 static int psp_hw_init(void *handle)
2599 {
2600         int ret;
2601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2602
2603         mutex_lock(&adev->firmware.mutex);
2604         /*
2605          * This sequence is just used on hw_init only once, no need on
2606          * resume.
2607          */
2608         ret = amdgpu_ucode_init_bo(adev);
2609         if (ret)
2610                 goto failed;
2611
2612         ret = psp_load_fw(adev);
2613         if (ret) {
2614                 DRM_ERROR("PSP firmware loading failed\n");
2615                 goto failed;
2616         }
2617
2618         mutex_unlock(&adev->firmware.mutex);
2619         return 0;
2620
2621 failed:
2622         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2623         mutex_unlock(&adev->firmware.mutex);
2624         return -EINVAL;
2625 }
2626
2627 static int psp_hw_fini(void *handle)
2628 {
2629         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2630         struct psp_context *psp = &adev->psp;
2631
2632         if (psp->ta_fw) {
2633                 psp_ras_terminate(psp);
2634                 psp_securedisplay_terminate(psp);
2635                 psp_rap_terminate(psp);
2636                 psp_dtm_terminate(psp);
2637                 psp_hdcp_terminate(psp);
2638
2639                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2640                         psp_xgmi_terminate(psp);
2641         }
2642
2643         psp_asd_terminate(psp);
2644         psp_tmr_terminate(psp);
2645
2646         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2647
2648         psp_free_shared_bufs(psp);
2649
2650         return 0;
2651 }
2652
2653 static int psp_suspend(void *handle)
2654 {
2655         int ret = 0;
2656         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2657         struct psp_context *psp = &adev->psp;
2658
2659         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2660             psp->xgmi_context.context.initialized) {
2661                 ret = psp_xgmi_terminate(psp);
2662                 if (ret) {
2663                         DRM_ERROR("Failed to terminate xgmi ta\n");
2664                         goto out;
2665                 }
2666         }
2667
2668         if (psp->ta_fw) {
2669                 ret = psp_ras_terminate(psp);
2670                 if (ret) {
2671                         DRM_ERROR("Failed to terminate ras ta\n");
2672                         goto out;
2673                 }
2674                 ret = psp_hdcp_terminate(psp);
2675                 if (ret) {
2676                         DRM_ERROR("Failed to terminate hdcp ta\n");
2677                         goto out;
2678                 }
2679                 ret = psp_dtm_terminate(psp);
2680                 if (ret) {
2681                         DRM_ERROR("Failed to terminate dtm ta\n");
2682                         goto out;
2683                 }
2684                 ret = psp_rap_terminate(psp);
2685                 if (ret) {
2686                         DRM_ERROR("Failed to terminate rap ta\n");
2687                         goto out;
2688                 }
2689                 ret = psp_securedisplay_terminate(psp);
2690                 if (ret) {
2691                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2692                         goto out;
2693                 }
2694         }
2695
2696         ret = psp_asd_terminate(psp);
2697         if (ret) {
2698                 DRM_ERROR("Failed to terminate asd\n");
2699                 goto out;
2700         }
2701
2702         ret = psp_tmr_terminate(psp);
2703         if (ret) {
2704                 DRM_ERROR("Failed to terminate tmr\n");
2705                 goto out;
2706         }
2707
2708         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2709         if (ret) {
2710                 DRM_ERROR("PSP ring stop failed\n");
2711         }
2712
2713 out:
2714         return ret;
2715 }
2716
2717 static int psp_resume(void *handle)
2718 {
2719         int ret;
2720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2721         struct psp_context *psp = &adev->psp;
2722
2723         DRM_INFO("PSP is resuming...\n");
2724
2725         if (psp->mem_train_ctx.enable_mem_training) {
2726                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2727                 if (ret) {
2728                         DRM_ERROR("Failed to process memory training!\n");
2729                         return ret;
2730                 }
2731         }
2732
2733         mutex_lock(&adev->firmware.mutex);
2734
2735         ret = psp_hw_start(psp);
2736         if (ret)
2737                 goto failed;
2738
2739         ret = psp_load_non_psp_fw(psp);
2740         if (ret)
2741                 goto failed;
2742
2743         ret = psp_asd_initialize(psp);
2744         if (ret) {
2745                 DRM_ERROR("PSP load asd failed!\n");
2746                 goto failed;
2747         }
2748
2749         ret = psp_rl_load(adev);
2750         if (ret) {
2751                 dev_err(adev->dev, "PSP load RL failed!\n");
2752                 goto failed;
2753         }
2754
2755         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2756                 ret = psp_xgmi_initialize(psp, false, true);
2757                 /* Warning the XGMI seesion initialize failure
2758                  * Instead of stop driver initialization
2759                  */
2760                 if (ret)
2761                         dev_err(psp->adev->dev,
2762                                 "XGMI: Failed to initialize XGMI session\n");
2763         }
2764
2765         if (psp->ta_fw) {
2766                 ret = psp_ras_initialize(psp);
2767                 if (ret)
2768                         dev_err(psp->adev->dev,
2769                                         "RAS: Failed to initialize RAS\n");
2770
2771                 ret = psp_hdcp_initialize(psp);
2772                 if (ret)
2773                         dev_err(psp->adev->dev,
2774                                 "HDCP: Failed to initialize HDCP\n");
2775
2776                 ret = psp_dtm_initialize(psp);
2777                 if (ret)
2778                         dev_err(psp->adev->dev,
2779                                 "DTM: Failed to initialize DTM\n");
2780
2781                 ret = psp_rap_initialize(psp);
2782                 if (ret)
2783                         dev_err(psp->adev->dev,
2784                                 "RAP: Failed to initialize RAP\n");
2785
2786                 ret = psp_securedisplay_initialize(psp);
2787                 if (ret)
2788                         dev_err(psp->adev->dev,
2789                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2790         }
2791
2792         mutex_unlock(&adev->firmware.mutex);
2793
2794         return 0;
2795
2796 failed:
2797         DRM_ERROR("PSP resume failed\n");
2798         mutex_unlock(&adev->firmware.mutex);
2799         return ret;
2800 }
2801
2802 int psp_gpu_reset(struct amdgpu_device *adev)
2803 {
2804         int ret;
2805
2806         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2807                 return 0;
2808
2809         mutex_lock(&adev->psp.mutex);
2810         ret = psp_mode1_reset(&adev->psp);
2811         mutex_unlock(&adev->psp.mutex);
2812
2813         return ret;
2814 }
2815
2816 int psp_rlc_autoload_start(struct psp_context *psp)
2817 {
2818         int ret;
2819         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2820
2821         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2822
2823         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2824                                  psp->fence_buf_mc_addr);
2825
2826         release_psp_cmd_buf(psp);
2827
2828         return ret;
2829 }
2830
2831 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2832                         uint64_t cmd_gpu_addr, int cmd_size)
2833 {
2834         struct amdgpu_firmware_info ucode = {0};
2835
2836         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2837                 AMDGPU_UCODE_ID_VCN0_RAM;
2838         ucode.mc_addr = cmd_gpu_addr;
2839         ucode.ucode_size = cmd_size;
2840
2841         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2842 }
2843
2844 int psp_ring_cmd_submit(struct psp_context *psp,
2845                         uint64_t cmd_buf_mc_addr,
2846                         uint64_t fence_mc_addr,
2847                         int index)
2848 {
2849         unsigned int psp_write_ptr_reg = 0;
2850         struct psp_gfx_rb_frame *write_frame;
2851         struct psp_ring *ring = &psp->km_ring;
2852         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2853         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2854                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2855         struct amdgpu_device *adev = psp->adev;
2856         uint32_t ring_size_dw = ring->ring_size / 4;
2857         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2858
2859         /* KM (GPCOM) prepare write pointer */
2860         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2861
2862         /* Update KM RB frame pointer to new frame */
2863         /* write_frame ptr increments by size of rb_frame in bytes */
2864         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2865         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2866                 write_frame = ring_buffer_start;
2867         else
2868                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2869         /* Check invalid write_frame ptr address */
2870         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2871                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2872                           ring_buffer_start, ring_buffer_end, write_frame);
2873                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2874                 return -EINVAL;
2875         }
2876
2877         /* Initialize KM RB frame */
2878         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2879
2880         /* Update KM RB frame */
2881         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2882         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2883         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2884         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2885         write_frame->fence_value = index;
2886         amdgpu_device_flush_hdp(adev, NULL);
2887
2888         /* Update the write Pointer in DWORDs */
2889         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2890         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2891         return 0;
2892 }
2893
2894 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2895 {
2896         struct amdgpu_device *adev = psp->adev;
2897         char fw_name[PSP_FW_NAME_LEN];
2898         const struct psp_firmware_header_v1_0 *asd_hdr;
2899         int err = 0;
2900
2901         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2902         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
2903         if (err)
2904                 goto out;
2905
2906         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2907         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2908         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2909         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2910         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2911                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2912         return 0;
2913 out:
2914         amdgpu_ucode_release(&adev->psp.asd_fw);
2915         return err;
2916 }
2917
2918 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
2919 {
2920         struct amdgpu_device *adev = psp->adev;
2921         char fw_name[PSP_FW_NAME_LEN];
2922         const struct psp_firmware_header_v1_0 *toc_hdr;
2923         int err = 0;
2924
2925         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2926         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
2927         if (err)
2928                 goto out;
2929
2930         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2931         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2932         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2933         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2934         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2935                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2936         return 0;
2937 out:
2938         amdgpu_ucode_release(&adev->psp.toc_fw);
2939         return err;
2940 }
2941
2942 static int parse_sos_bin_descriptor(struct psp_context *psp,
2943                                    const struct psp_fw_bin_desc *desc,
2944                                    const struct psp_firmware_header_v2_0 *sos_hdr)
2945 {
2946         uint8_t *ucode_start_addr  = NULL;
2947
2948         if (!psp || !desc || !sos_hdr)
2949                 return -EINVAL;
2950
2951         ucode_start_addr  = (uint8_t *)sos_hdr +
2952                             le32_to_cpu(desc->offset_bytes) +
2953                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2954
2955         switch (desc->fw_type) {
2956         case PSP_FW_TYPE_PSP_SOS:
2957                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
2958                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
2959                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
2960                 psp->sos.start_addr        = ucode_start_addr;
2961                 break;
2962         case PSP_FW_TYPE_PSP_SYS_DRV:
2963                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
2964                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
2965                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
2966                 psp->sys.start_addr        = ucode_start_addr;
2967                 break;
2968         case PSP_FW_TYPE_PSP_KDB:
2969                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
2970                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
2971                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
2972                 psp->kdb.start_addr        = ucode_start_addr;
2973                 break;
2974         case PSP_FW_TYPE_PSP_TOC:
2975                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
2976                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
2977                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
2978                 psp->toc.start_addr        = ucode_start_addr;
2979                 break;
2980         case PSP_FW_TYPE_PSP_SPL:
2981                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
2982                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
2983                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
2984                 psp->spl.start_addr        = ucode_start_addr;
2985                 break;
2986         case PSP_FW_TYPE_PSP_RL:
2987                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
2988                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
2989                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
2990                 psp->rl.start_addr         = ucode_start_addr;
2991                 break;
2992         case PSP_FW_TYPE_PSP_SOC_DRV:
2993                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
2994                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
2995                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
2996                 psp->soc_drv.start_addr         = ucode_start_addr;
2997                 break;
2998         case PSP_FW_TYPE_PSP_INTF_DRV:
2999                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3000                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3001                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3002                 psp->intf_drv.start_addr        = ucode_start_addr;
3003                 break;
3004         case PSP_FW_TYPE_PSP_DBG_DRV:
3005                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3006                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3007                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3008                 psp->dbg_drv.start_addr         = ucode_start_addr;
3009                 break;
3010         case PSP_FW_TYPE_PSP_RAS_DRV:
3011                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3012                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3013                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3014                 psp->ras_drv.start_addr         = ucode_start_addr;
3015                 break;
3016         default:
3017                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3018                 break;
3019         }
3020
3021         return 0;
3022 }
3023
3024 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3025 {
3026         const struct psp_firmware_header_v1_0 *sos_hdr;
3027         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3028         uint8_t *ucode_array_start_addr;
3029
3030         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3031         ucode_array_start_addr = (uint8_t *)sos_hdr +
3032                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3033
3034         if (adev->gmc.xgmi.connected_to_cpu ||
3035             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3036                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3037                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3038
3039                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3040                 adev->psp.sys.start_addr = ucode_array_start_addr;
3041
3042                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3043                 adev->psp.sos.start_addr = ucode_array_start_addr +
3044                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3045         } else {
3046                 /* Load alternate PSP SOS FW */
3047                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3048
3049                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3050                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3051
3052                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3053                 adev->psp.sys.start_addr = ucode_array_start_addr +
3054                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3055
3056                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3057                 adev->psp.sos.start_addr = ucode_array_start_addr +
3058                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3059         }
3060
3061         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3062                 dev_warn(adev->dev, "PSP SOS FW not available");
3063                 return -EINVAL;
3064         }
3065
3066         return 0;
3067 }
3068
3069 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3070 {
3071         struct amdgpu_device *adev = psp->adev;
3072         char fw_name[PSP_FW_NAME_LEN];
3073         const struct psp_firmware_header_v1_0 *sos_hdr;
3074         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3075         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3076         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3077         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3078         int err = 0;
3079         uint8_t *ucode_array_start_addr;
3080         int fw_index = 0;
3081
3082         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3083         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3084         if (err)
3085                 goto out;
3086
3087         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3088         ucode_array_start_addr = (uint8_t *)sos_hdr +
3089                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3090         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3091
3092         switch (sos_hdr->header.header_version_major) {
3093         case 1:
3094                 err = psp_init_sos_base_fw(adev);
3095                 if (err)
3096                         goto out;
3097
3098                 if (sos_hdr->header.header_version_minor == 1) {
3099                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3100                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3101                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3102                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3103                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3104                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3105                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3106                 }
3107                 if (sos_hdr->header.header_version_minor == 2) {
3108                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3109                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3110                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3111                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3112                 }
3113                 if (sos_hdr->header.header_version_minor == 3) {
3114                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3115                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3116                         adev->psp.toc.start_addr = ucode_array_start_addr +
3117                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3118                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3119                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3120                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3121                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3122                         adev->psp.spl.start_addr = ucode_array_start_addr +
3123                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3124                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3125                         adev->psp.rl.start_addr = ucode_array_start_addr +
3126                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3127                 }
3128                 break;
3129         case 2:
3130                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3131
3132                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3133                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3134                         err = -EINVAL;
3135                         goto out;
3136                 }
3137
3138                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3139                         err = parse_sos_bin_descriptor(psp,
3140                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3141                                                        sos_hdr_v2_0);
3142                         if (err)
3143                                 goto out;
3144                 }
3145                 break;
3146         default:
3147                 dev_err(adev->dev,
3148                         "unsupported psp sos firmware\n");
3149                 err = -EINVAL;
3150                 goto out;
3151         }
3152
3153         return 0;
3154 out:
3155         amdgpu_ucode_release(&adev->psp.sos_fw);
3156
3157         return err;
3158 }
3159
3160 static int parse_ta_bin_descriptor(struct psp_context *psp,
3161                                    const struct psp_fw_bin_desc *desc,
3162                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3163 {
3164         uint8_t *ucode_start_addr  = NULL;
3165
3166         if (!psp || !desc || !ta_hdr)
3167                 return -EINVAL;
3168
3169         ucode_start_addr  = (uint8_t *)ta_hdr +
3170                             le32_to_cpu(desc->offset_bytes) +
3171                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3172
3173         switch (desc->fw_type) {
3174         case TA_FW_TYPE_PSP_ASD:
3175                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3176                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3177                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3178                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3179                 break;
3180         case TA_FW_TYPE_PSP_XGMI:
3181                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3182                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3183                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3184                 break;
3185         case TA_FW_TYPE_PSP_RAS:
3186                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3187                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3188                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3189                 break;
3190         case TA_FW_TYPE_PSP_HDCP:
3191                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3192                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3193                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3194                 break;
3195         case TA_FW_TYPE_PSP_DTM:
3196                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3197                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3198                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3199                 break;
3200         case TA_FW_TYPE_PSP_RAP:
3201                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3202                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3203                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3204                 break;
3205         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3206                 psp->securedisplay_context.context.bin_desc.fw_version =
3207                         le32_to_cpu(desc->fw_version);
3208                 psp->securedisplay_context.context.bin_desc.size_bytes =
3209                         le32_to_cpu(desc->size_bytes);
3210                 psp->securedisplay_context.context.bin_desc.start_addr =
3211                         ucode_start_addr;
3212                 break;
3213         default:
3214                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3215                 break;
3216         }
3217
3218         return 0;
3219 }
3220
3221 static int parse_ta_v1_microcode(struct psp_context *psp)
3222 {
3223         const struct ta_firmware_header_v1_0 *ta_hdr;
3224         struct amdgpu_device *adev = psp->adev;
3225
3226         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3227
3228         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3229                 return -EINVAL;
3230
3231         adev->psp.xgmi_context.context.bin_desc.fw_version =
3232                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3233         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3234                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3235         adev->psp.xgmi_context.context.bin_desc.start_addr =
3236                 (uint8_t *)ta_hdr +
3237                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3238
3239         adev->psp.ras_context.context.bin_desc.fw_version =
3240                 le32_to_cpu(ta_hdr->ras.fw_version);
3241         adev->psp.ras_context.context.bin_desc.size_bytes =
3242                 le32_to_cpu(ta_hdr->ras.size_bytes);
3243         adev->psp.ras_context.context.bin_desc.start_addr =
3244                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3245                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3246
3247         adev->psp.hdcp_context.context.bin_desc.fw_version =
3248                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3249         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3250                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3251         adev->psp.hdcp_context.context.bin_desc.start_addr =
3252                 (uint8_t *)ta_hdr +
3253                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3254
3255         adev->psp.dtm_context.context.bin_desc.fw_version =
3256                 le32_to_cpu(ta_hdr->dtm.fw_version);
3257         adev->psp.dtm_context.context.bin_desc.size_bytes =
3258                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3259         adev->psp.dtm_context.context.bin_desc.start_addr =
3260                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3261                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3262
3263         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3264                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3265         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3266                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3267         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3268                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3269                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3270
3271         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3272
3273         return 0;
3274 }
3275
3276 static int parse_ta_v2_microcode(struct psp_context *psp)
3277 {
3278         const struct ta_firmware_header_v2_0 *ta_hdr;
3279         struct amdgpu_device *adev = psp->adev;
3280         int err = 0;
3281         int ta_index = 0;
3282
3283         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3284
3285         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3286                 return -EINVAL;
3287
3288         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3289                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3290                 return -EINVAL;
3291         }
3292
3293         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3294                 err = parse_ta_bin_descriptor(psp,
3295                                               &ta_hdr->ta_fw_bin[ta_index],
3296                                               ta_hdr);
3297                 if (err)
3298                         return err;
3299         }
3300
3301         return 0;
3302 }
3303
3304 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3305 {
3306         const struct common_firmware_header *hdr;
3307         struct amdgpu_device *adev = psp->adev;
3308         char fw_name[PSP_FW_NAME_LEN];
3309         int err;
3310
3311         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3312         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3313         if (err)
3314                 return err;
3315
3316         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3317         switch (le16_to_cpu(hdr->header_version_major)) {
3318         case 1:
3319                 err = parse_ta_v1_microcode(psp);
3320                 break;
3321         case 2:
3322                 err = parse_ta_v2_microcode(psp);
3323                 break;
3324         default:
3325                 dev_err(adev->dev, "unsupported TA header version\n");
3326                 err = -EINVAL;
3327         }
3328
3329         if (err)
3330                 amdgpu_ucode_release(&adev->psp.ta_fw);
3331
3332         return err;
3333 }
3334
3335 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3336 {
3337         struct amdgpu_device *adev = psp->adev;
3338         char fw_name[PSP_FW_NAME_LEN];
3339         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3340         struct amdgpu_firmware_info *info = NULL;
3341         int err = 0;
3342
3343         if (!amdgpu_sriov_vf(adev)) {
3344                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3345                 return -EINVAL;
3346         }
3347
3348         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3349         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3350         if (err) {
3351                 if (err == -ENODEV) {
3352                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3353                         err = 0;
3354                         goto out;
3355                 }
3356                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3357         }
3358
3359         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3360         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3361         info->fw = adev->psp.cap_fw;
3362         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3363                 adev->psp.cap_fw->data;
3364         adev->firmware.fw_size += ALIGN(
3365                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3366         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3367         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3368         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3369
3370         return 0;
3371
3372 out:
3373         amdgpu_ucode_release(&adev->psp.cap_fw);
3374         return err;
3375 }
3376
3377 static int psp_set_clockgating_state(void *handle,
3378                                      enum amd_clockgating_state state)
3379 {
3380         return 0;
3381 }
3382
3383 static int psp_set_powergating_state(void *handle,
3384                                      enum amd_powergating_state state)
3385 {
3386         return 0;
3387 }
3388
3389 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3390                                          struct device_attribute *attr,
3391                                          char *buf)
3392 {
3393         struct drm_device *ddev = dev_get_drvdata(dev);
3394         struct amdgpu_device *adev = drm_to_adev(ddev);
3395         uint32_t fw_ver;
3396         int ret;
3397
3398         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3399                 DRM_INFO("PSP block is not ready yet.");
3400                 return -EBUSY;
3401         }
3402
3403         mutex_lock(&adev->psp.mutex);
3404         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3405         mutex_unlock(&adev->psp.mutex);
3406
3407         if (ret) {
3408                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3409                 return ret;
3410         }
3411
3412         return sysfs_emit(buf, "%x\n", fw_ver);
3413 }
3414
3415 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3416                                                        struct device_attribute *attr,
3417                                                        const char *buf,
3418                                                        size_t count)
3419 {
3420         struct drm_device *ddev = dev_get_drvdata(dev);
3421         struct amdgpu_device *adev = drm_to_adev(ddev);
3422         int ret, idx;
3423         char fw_name[100];
3424         const struct firmware *usbc_pd_fw;
3425         struct amdgpu_bo *fw_buf_bo = NULL;
3426         uint64_t fw_pri_mc_addr;
3427         void *fw_pri_cpu_addr;
3428
3429         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3430                 DRM_INFO("PSP block is not ready yet.");
3431                 return -EBUSY;
3432         }
3433
3434         if (!drm_dev_enter(ddev, &idx))
3435                 return -ENODEV;
3436
3437         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3438         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3439         if (ret)
3440                 goto fail;
3441
3442         /* LFB address which is aligned to 1MB boundary per PSP request */
3443         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3444                                       AMDGPU_GEM_DOMAIN_VRAM |
3445                                       AMDGPU_GEM_DOMAIN_GTT,
3446                                       &fw_buf_bo, &fw_pri_mc_addr,
3447                                       &fw_pri_cpu_addr);
3448         if (ret)
3449                 goto rel_buf;
3450
3451         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3452
3453         mutex_lock(&adev->psp.mutex);
3454         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3455         mutex_unlock(&adev->psp.mutex);
3456
3457         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3458
3459 rel_buf:
3460         release_firmware(usbc_pd_fw);
3461 fail:
3462         if (ret) {
3463                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3464                 count = ret;
3465         }
3466
3467         drm_dev_exit(idx);
3468         return count;
3469 }
3470
3471 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3472 {
3473         int idx;
3474
3475         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3476                 return;
3477
3478         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3479         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3480
3481         drm_dev_exit(idx);
3482 }
3483
3484 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3485                    psp_usbc_pd_fw_sysfs_read,
3486                    psp_usbc_pd_fw_sysfs_write);
3487
3488 int is_psp_fw_valid(struct psp_bin_desc bin)
3489 {
3490         return bin.size_bytes;
3491 }
3492
3493 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3494                                         struct bin_attribute *bin_attr,
3495                                         char *buffer, loff_t pos, size_t count)
3496 {
3497         struct device *dev = kobj_to_dev(kobj);
3498         struct drm_device *ddev = dev_get_drvdata(dev);
3499         struct amdgpu_device *adev = drm_to_adev(ddev);
3500
3501         adev->psp.vbflash_done = false;
3502
3503         /* Safeguard against memory drain */
3504         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3505                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3506                 kvfree(adev->psp.vbflash_tmp_buf);
3507                 adev->psp.vbflash_tmp_buf = NULL;
3508                 adev->psp.vbflash_image_size = 0;
3509                 return -ENOMEM;
3510         }
3511
3512         /* TODO Just allocate max for now and optimize to realloc later if needed */
3513         if (!adev->psp.vbflash_tmp_buf) {
3514                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3515                 if (!adev->psp.vbflash_tmp_buf)
3516                         return -ENOMEM;
3517         }
3518
3519         mutex_lock(&adev->psp.mutex);
3520         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3521         adev->psp.vbflash_image_size += count;
3522         mutex_unlock(&adev->psp.mutex);
3523
3524         dev_info(adev->dev, "VBIOS flash write PSP done");
3525
3526         return count;
3527 }
3528
3529 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3530                                        struct bin_attribute *bin_attr, char *buffer,
3531                                        loff_t pos, size_t count)
3532 {
3533         struct device *dev = kobj_to_dev(kobj);
3534         struct drm_device *ddev = dev_get_drvdata(dev);
3535         struct amdgpu_device *adev = drm_to_adev(ddev);
3536         struct amdgpu_bo *fw_buf_bo = NULL;
3537         uint64_t fw_pri_mc_addr;
3538         void *fw_pri_cpu_addr;
3539         int ret;
3540
3541         dev_info(adev->dev, "VBIOS flash to PSP started");
3542
3543         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3544                                         AMDGPU_GPU_PAGE_SIZE,
3545                                         AMDGPU_GEM_DOMAIN_VRAM,
3546                                         &fw_buf_bo,
3547                                         &fw_pri_mc_addr,
3548                                         &fw_pri_cpu_addr);
3549         if (ret)
3550                 goto rel_buf;
3551
3552         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3553
3554         mutex_lock(&adev->psp.mutex);
3555         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3556         mutex_unlock(&adev->psp.mutex);
3557
3558         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3559
3560 rel_buf:
3561         kvfree(adev->psp.vbflash_tmp_buf);
3562         adev->psp.vbflash_tmp_buf = NULL;
3563         adev->psp.vbflash_image_size = 0;
3564
3565         if (ret) {
3566                 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3567                 return ret;
3568         }
3569
3570         dev_info(adev->dev, "VBIOS flash to PSP done");
3571         return 0;
3572 }
3573
3574 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3575                                          struct device_attribute *attr,
3576                                          char *buf)
3577 {
3578         struct drm_device *ddev = dev_get_drvdata(dev);
3579         struct amdgpu_device *adev = drm_to_adev(ddev);
3580         uint32_t vbflash_status;
3581
3582         vbflash_status = psp_vbflash_status(&adev->psp);
3583         if (!adev->psp.vbflash_done)
3584                 vbflash_status = 0;
3585         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3586                 vbflash_status = 1;
3587
3588         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3589 }
3590
3591 static const struct bin_attribute psp_vbflash_bin_attr = {
3592         .attr = {.name = "psp_vbflash", .mode = 0664},
3593         .size = 0,
3594         .write = amdgpu_psp_vbflash_write,
3595         .read = amdgpu_psp_vbflash_read,
3596 };
3597
3598 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3599
3600 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3601 {
3602         int ret = 0;
3603         struct psp_context *psp = &adev->psp;
3604
3605         if (amdgpu_sriov_vf(adev))
3606                 return -EINVAL;
3607
3608         switch (adev->ip_versions[MP0_HWIP][0]) {
3609         case IP_VERSION(13, 0, 0):
3610         case IP_VERSION(13, 0, 7):
3611                 if (!psp->adev) {
3612                         psp->adev = adev;
3613                         psp_v13_0_set_psp_funcs(psp);
3614                 }
3615                 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3616                 if (ret)
3617                         dev_err(adev->dev, "Failed to create device file psp_vbflash");
3618                 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3619                 if (ret)
3620                         dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3621                 return ret;
3622         default:
3623                 return 0;
3624         }
3625 }
3626
3627 const struct amd_ip_funcs psp_ip_funcs = {
3628         .name = "psp",
3629         .early_init = psp_early_init,
3630         .late_init = NULL,
3631         .sw_init = psp_sw_init,
3632         .sw_fini = psp_sw_fini,
3633         .hw_init = psp_hw_init,
3634         .hw_fini = psp_hw_fini,
3635         .suspend = psp_suspend,
3636         .resume = psp_resume,
3637         .is_idle = NULL,
3638         .check_soft_reset = NULL,
3639         .wait_for_idle = NULL,
3640         .soft_reset = NULL,
3641         .set_clockgating_state = psp_set_clockgating_state,
3642         .set_powergating_state = psp_set_powergating_state,
3643 };
3644
3645 static int psp_sysfs_init(struct amdgpu_device *adev)
3646 {
3647         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3648
3649         if (ret)
3650                 DRM_ERROR("Failed to create USBC PD FW control file!");
3651
3652         return ret;
3653 }
3654
3655 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3656 {
3657         sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3658         device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3659 }
3660
3661 static void psp_sysfs_fini(struct amdgpu_device *adev)
3662 {
3663         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3664 }
3665
3666 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3667 {
3668         .type = AMD_IP_BLOCK_TYPE_PSP,
3669         .major = 3,
3670         .minor = 1,
3671         .rev = 0,
3672         .funcs = &psp_ip_funcs,
3673 };
3674
3675 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3676 {
3677         .type = AMD_IP_BLOCK_TYPE_PSP,
3678         .major = 10,
3679         .minor = 0,
3680         .rev = 0,
3681         .funcs = &psp_ip_funcs,
3682 };
3683
3684 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3685 {
3686         .type = AMD_IP_BLOCK_TYPE_PSP,
3687         .major = 11,
3688         .minor = 0,
3689         .rev = 0,
3690         .funcs = &psp_ip_funcs,
3691 };
3692
3693 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3694         .type = AMD_IP_BLOCK_TYPE_PSP,
3695         .major = 11,
3696         .minor = 0,
3697         .rev = 8,
3698         .funcs = &psp_ip_funcs,
3699 };
3700
3701 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3702 {
3703         .type = AMD_IP_BLOCK_TYPE_PSP,
3704         .major = 12,
3705         .minor = 0,
3706         .rev = 0,
3707         .funcs = &psp_ip_funcs,
3708 };
3709
3710 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3711         .type = AMD_IP_BLOCK_TYPE_PSP,
3712         .major = 13,
3713         .minor = 0,
3714         .rev = 0,
3715         .funcs = &psp_ip_funcs,
3716 };
3717
3718 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3719         .type = AMD_IP_BLOCK_TYPE_PSP,
3720         .major = 13,
3721         .minor = 0,
3722         .rev = 4,
3723         .funcs = &psp_ip_funcs,
3724 };