drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "nbio_v4_3.h"
  38 #include "atom.h"
  39 #include "amdgpu_reset.h"
  40
  41 #ifdef CONFIG_X86_MCE_AMD
  42 #include <asm/mce.h>
  43
  44 static bool notifier_registered;
  45 #endif
  46 static const char *RAS_FS_NAME = "ras";
  47
  48 const char *ras_error_string[] = {
  49         "none",
  50         "parity",
  51         "single_correctable",
  52         "multi_uncorrectable",
  53         "poison",
  54 };
  55
  56 const char *ras_block_string[] = {
  57         "umc",
  58         "sdma",
  59         "gfx",
  60         "mmhub",
  61         "athub",
  62         "pcie_bif",
  63         "hdp",
  64         "xgmi_wafl",
  65         "df",
  66         "smn",
  67         "sem",
  68         "mp0",
  69         "mp1",
  70         "fuse",
  71         "mca",
  72         "vcn",
  73         "jpeg",
  74 };
  75
  76 const char *ras_mca_block_string[] = {
  77         "mca_mp0",
  78         "mca_mp1",
  79         "mca_mpio",
  80         "mca_iohc",
  81 };
  82
  83 struct amdgpu_ras_block_list {
  84         /* ras block link */
  85         struct list_head node;
  86
  87         struct amdgpu_ras_block_object *ras_obj;
  88 };
  89
  90 const char *get_ras_block_str(struct ras_common_if *ras_block)
  91 {
  92         if (!ras_block)
  93                 return "NULL";
  94
  95         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  96                 return "OUT OF RANGE";
  97
  98         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
  99                 return ras_mca_block_string[ras_block->sub_block_index];
 100
 101         return ras_block_string[ras_block->block];
 102 }
 103
 104 #define ras_block_str(_BLOCK_) \
 105         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 106
 107 #define ras_err_str(i) (ras_error_string[ffs(i)])
 108
 109 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 110
 111 /* inject address is 52 bits */
 112 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 113
 114 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 115 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 116
 117 enum amdgpu_ras_retire_page_reservation {
 118         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 119         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 120         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 121 };
 122
 123 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 124
 125 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 126                                 uint64_t addr);
 127 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 128                                 uint64_t addr);
 129 #ifdef CONFIG_X86_MCE_AMD
 130 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 131 struct mce_notifier_adev_list {
 132         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 133         int num_gpu;
 134 };
 135 static struct mce_notifier_adev_list mce_adev_list;
 136 #endif
 137
 138 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 139 {
 140         if (adev && amdgpu_ras_get_context(adev))
 141                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 142 }
 143
 144 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 145 {
 146         if (adev && amdgpu_ras_get_context(adev))
 147                 return amdgpu_ras_get_context(adev)->error_query_ready;
 148
 149         return false;
 150 }
 151
 152 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 153 {
 154         struct ras_err_data err_data = {0, 0, 0, NULL};
 155         struct eeprom_table_record err_rec;
 156
 157         if ((address >= adev->gmc.mc_vram_size) ||
 158             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 159                 dev_warn(adev->dev,
 160                          "RAS WARN: input address 0x%llx is invalid.\n",
 161                          address);
 162                 return -EINVAL;
 163         }
 164
 165         if (amdgpu_ras_check_bad_page(adev, address)) {
 166                 dev_warn(adev->dev,
 167                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 168                          address);
 169                 return 0;
 170         }
 171
 172         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 173         err_data.err_addr = &err_rec;
 174         amdgpu_umc_fill_error_record(&err_data, address,
 175                         (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
 176
 177         if (amdgpu_bad_page_threshold != 0) {
 178                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 179                                          err_data.err_addr_cnt);
 180                 amdgpu_ras_save_bad_pages(adev, NULL);
 181         }
 182
 183         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 184         dev_warn(adev->dev, "Clear EEPROM:\n");
 185         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 186
 187         return 0;
 188 }
 189
 190 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 191                                         size_t size, loff_t *pos)
 192 {
 193         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 194         struct ras_query_if info = {
 195                 .head = obj->head,
 196         };
 197         ssize_t s;
 198         char val[128];
 199
 200         if (amdgpu_ras_query_error_status(obj->adev, &info))
 201                 return -EINVAL;
 202
 203         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 204         if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
 205             obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
 206                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 207                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 208         }
 209
 210         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 211                         "ue", info.ue_count,
 212                         "ce", info.ce_count);
 213         if (*pos >= s)
 214                 return 0;
 215
 216         s -= *pos;
 217         s = min_t(u64, s, size);
 218
 219
 220         if (copy_to_user(buf, &val[*pos], s))
 221                 return -EINVAL;
 222
 223         *pos += s;
 224
 225         return s;
 226 }
 227
 228 static const struct file_operations amdgpu_ras_debugfs_ops = {
 229         .owner = THIS_MODULE,
 230         .read = amdgpu_ras_debugfs_read,
 231         .write = NULL,
 232         .llseek = default_llseek
 233 };
 234
 235 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 236 {
 237         int i;
 238
 239         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 240                 *block_id = i;
 241                 if (strcmp(name, ras_block_string[i]) == 0)
 242                         return 0;
 243         }
 244         return -EINVAL;
 245 }
 246
 247 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 248                 const char __user *buf, size_t size,
 249                 loff_t *pos, struct ras_debug_if *data)
 250 {
 251         ssize_t s = min_t(u64, 64, size);
 252         char str[65];
 253         char block_name[33];
 254         char err[9] = "ue";
 255         int op = -1;
 256         int block_id;
 257         uint32_t sub_block;
 258         u64 address, value;
 259         /* default value is 0 if the mask is not set by user */
 260         u32 instance_mask = 0;
 261
 262         if (*pos)
 263                 return -EINVAL;
 264         *pos = size;
 265
 266         memset(str, 0, sizeof(str));
 267         memset(data, 0, sizeof(*data));
 268
 269         if (copy_from_user(str, buf, s))
 270                 return -EINVAL;
 271
 272         if (sscanf(str, "disable %32s", block_name) == 1)
 273                 op = 0;
 274         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 275                 op = 1;
 276         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 277                 op = 2;
 278         else if (strstr(str, "retire_page") != NULL)
 279                 op = 3;
 280         else if (str[0] && str[1] && str[2] && str[3])
 281                 /* ascii string, but commands are not matched. */
 282                 return -EINVAL;
 283
 284         if (op != -1) {
 285                 if (op == 3) {
 286                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 287                             sscanf(str, "%*s %llu", &address) != 1)
 288                                 return -EINVAL;
 289
 290                         data->op = op;
 291                         data->inject.address = address;
 292
 293                         return 0;
 294                 }
 295
 296                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 297                         return -EINVAL;
 298
 299                 data->head.block = block_id;
 300                 /* only ue and ce errors are supported */
 301                 if (!memcmp("ue", err, 2))
 302                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 303                 else if (!memcmp("ce", err, 2))
 304                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 305                 else
 306                         return -EINVAL;
 307
 308                 data->op = op;
 309
 310                 if (op == 2) {
 311                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 312                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 313                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 314                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 315                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 316                                    &sub_block, &address, &value) != 3 &&
 317                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 318                                    &sub_block, &address, &value) != 3)
 319                                 return -EINVAL;
 320                         data->head.sub_block_index = sub_block;
 321                         data->inject.address = address;
 322                         data->inject.value = value;
 323                         data->inject.instance_mask = instance_mask;
 324                 }
 325         } else {
 326                 if (size < sizeof(*data))
 327                         return -EINVAL;
 328
 329                 if (copy_from_user(data, buf, sizeof(*data)))
 330                         return -EINVAL;
 331         }
 332
 333         return 0;
 334 }
 335
 336 /**
 337  * DOC: AMDGPU RAS debugfs control interface
 338  *
 339  * The control interface accepts struct ras_debug_if which has two members.
 340  *
 341  * First member: ras_debug_if::head or ras_debug_if::inject.
 342  *
 343  * head is used to indicate which IP block will be under control.
 344  *
 345  * head has four members, they are block, type, sub_block_index, name.
 346  * block: which IP will be under control.
 347  * type: what kind of error will be enabled/disabled/injected.
 348  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 349  * name: the name of IP.
 350  *
 351  * inject has three more members than head, they are address, value and mask.
 352  * As their names indicate, inject operation will write the
 353  * value to the address.
 354  *
 355  * The second member: struct ras_debug_if::op.
 356  * It has three kinds of operations.
 357  *
 358  * - 0: disable RAS on the block. Take ::head as its data.
 359  * - 1: enable RAS on the block. Take ::head as its data.
 360  * - 2: inject errors on the block. Take ::inject as its data.
 361  *
 362  * How to use the interface?
 363  *
 364  * In a program
 365  *
 366  * Copy the struct ras_debug_if in your code and initialize it.
 367  * Write the struct to the control interface.
 368  *
 369  * From shell
 370  *
 371  * .. code-block:: bash
 372  *
 373  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 374  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 375  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 376  *
 377  * Where N, is the card which you want to affect.
 378  *
 379  * "disable" requires only the block.
 380  * "enable" requires the block and error type.
 381  * "inject" requires the block, error type, address, and value.
 382  *
 383  * The block is one of: umc, sdma, gfx, etc.
 384  *      see ras_block_string[] for details
 385  *
 386  * The error type is one of: ue, ce, where,
 387  *      ue is multi-uncorrectable
 388  *      ce is single-correctable
 389  *
 390  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 391  * The address and value are hexadecimal numbers, leading 0x is optional.
 392  * The mask means instance mask, is optional, default value is 0x1.
 393  *
 394  * For instance,
 395  *
 396  * .. code-block:: bash
 397  *
 398  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 399  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 400  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 401  *
 402  * How to check the result of the operation?
 403  *
 404  * To check disable/enable, see "ras" features at,
 405  * /sys/class/drm/card[0/1/2...]/device/ras/features
 406  *
 407  * To check inject, see the corresponding error count at,
 408  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 409  *
 410  * .. note::
 411  *      Operations are only allowed on blocks which are supported.
 412  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 413  *      to see which blocks support RAS on a particular asic.
 414  *
 415  */
 416 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 417                                              const char __user *buf,
 418                                              size_t size, loff_t *pos)
 419 {
 420         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 421         struct ras_debug_if data;
 422         int ret = 0;
 423
 424         if (!amdgpu_ras_get_error_query_ready(adev)) {
 425                 dev_warn(adev->dev, "RAS WARN: error injection "
 426                                 "currently inaccessible\n");
 427                 return size;
 428         }
 429
 430         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 431         if (ret)
 432                 return ret;
 433
 434         if (data.op == 3) {
 435                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 436                 if (!ret)
 437                         return size;
 438                 else
 439                         return ret;
 440         }
 441
 442         if (!amdgpu_ras_is_supported(adev, data.head.block))
 443                 return -EINVAL;
 444
 445         switch (data.op) {
 446         case 0:
 447                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 448                 break;
 449         case 1:
 450                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 451                 break;
 452         case 2:
 453                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 454                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 455                         dev_warn(adev->dev, "RAS WARN: input address "
 456                                         "0x%llx is invalid.",
 457                                         data.inject.address);
 458                         ret = -EINVAL;
 459                         break;
 460                 }
 461
 462                 /* umc ce/ue error injection for a bad page is not allowed */
 463                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 464                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 465                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 466                                  "already been marked as bad!\n",
 467                                  data.inject.address);
 468                         break;
 469                 }
 470
 471                 /* data.inject.address is offset instead of absolute gpu address */
 472                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 473                 break;
 474         default:
 475                 ret = -EINVAL;
 476                 break;
 477         }
 478
 479         if (ret)
 480                 return ret;
 481
 482         return size;
 483 }
 484
 485 /**
 486  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 487  *
 488  * Some boards contain an EEPROM which is used to persistently store a list of
 489  * bad pages which experiences ECC errors in vram.  This interface provides
 490  * a way to reset the EEPROM, e.g., after testing error injection.
 491  *
 492  * Usage:
 493  *
 494  * .. code-block:: bash
 495  *
 496  *      echo 1 > ../ras/ras_eeprom_reset
 497  *
 498  * will reset EEPROM table to 0 entries.
 499  *
 500  */
 501 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 502                                                const char __user *buf,
 503                                                size_t size, loff_t *pos)
 504 {
 505         struct amdgpu_device *adev =
 506                 (struct amdgpu_device *)file_inode(f)->i_private;
 507         int ret;
 508
 509         ret = amdgpu_ras_eeprom_reset_table(
 510                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 511
 512         if (!ret) {
 513                 /* Something was written to EEPROM.
 514                  */
 515                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 516                 return size;
 517         } else {
 518                 return ret;
 519         }
 520 }
 521
 522 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 523         .owner = THIS_MODULE,
 524         .read = NULL,
 525         .write = amdgpu_ras_debugfs_ctrl_write,
 526         .llseek = default_llseek
 527 };
 528
 529 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 530         .owner = THIS_MODULE,
 531         .read = NULL,
 532         .write = amdgpu_ras_debugfs_eeprom_write,
 533         .llseek = default_llseek
 534 };
 535
 536 /**
 537  * DOC: AMDGPU RAS sysfs Error Count Interface
 538  *
 539  * It allows the user to read the error count for each IP block on the gpu through
 540  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 541  *
 542  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 543  * (ce) error counts.
 544  *
 545  * The format of one line is below,
 546  *
 547  * [ce|ue]: count
 548  *
 549  * Example:
 550  *
 551  * .. code-block:: bash
 552  *
 553  *      ue: 0
 554  *      ce: 1
 555  *
 556  */
 557 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 558                 struct device_attribute *attr, char *buf)
 559 {
 560         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 561         struct ras_query_if info = {
 562                 .head = obj->head,
 563         };
 564
 565         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 566                 return sysfs_emit(buf, "Query currently inaccessible\n");
 567
 568         if (amdgpu_ras_query_error_status(obj->adev, &info))
 569                 return -EINVAL;
 570
 571         if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
 572             obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
 573                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 574                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 575         }
 576
 577         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 578                           "ce", info.ce_count);
 579 }
 580
 581 /* obj begin */
 582
 583 #define get_obj(obj) do { (obj)->use++; } while (0)
 584 #define alive_obj(obj) ((obj)->use)
 585
 586 static inline void put_obj(struct ras_manager *obj)
 587 {
 588         if (obj && (--obj->use == 0))
 589                 list_del(&obj->node);
 590         if (obj && (obj->use < 0))
 591                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 592 }
 593
 594 /* make one obj and return it. */
 595 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 596                 struct ras_common_if *head)
 597 {
 598         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 599         struct ras_manager *obj;
 600
 601         if (!adev->ras_enabled || !con)
 602                 return NULL;
 603
 604         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 605                 return NULL;
 606
 607         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 608                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 609                         return NULL;
 610
 611                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 612         } else
 613                 obj = &con->objs[head->block];
 614
 615         /* already exist. return obj? */
 616         if (alive_obj(obj))
 617                 return NULL;
 618
 619         obj->head = *head;
 620         obj->adev = adev;
 621         list_add(&obj->node, &con->head);
 622         get_obj(obj);
 623
 624         return obj;
 625 }
 626
 627 /* return an obj equal to head, or the first when head is NULL */
 628 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 629                 struct ras_common_if *head)
 630 {
 631         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 632         struct ras_manager *obj;
 633         int i;
 634
 635         if (!adev->ras_enabled || !con)
 636                 return NULL;
 637
 638         if (head) {
 639                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 640                         return NULL;
 641
 642                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 643                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 644                                 return NULL;
 645
 646                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 647                 } else
 648                         obj = &con->objs[head->block];
 649
 650                 if (alive_obj(obj))
 651                         return obj;
 652         } else {
 653                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 654                         obj = &con->objs[i];
 655                         if (alive_obj(obj))
 656                                 return obj;
 657                 }
 658         }
 659
 660         return NULL;
 661 }
 662 /* obj end */
 663
 664 /* feature ctl begin */
 665 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 666                                          struct ras_common_if *head)
 667 {
 668         return adev->ras_hw_enabled & BIT(head->block);
 669 }
 670
 671 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 672                 struct ras_common_if *head)
 673 {
 674         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 675
 676         return con->features & BIT(head->block);
 677 }
 678
 679 /*
 680  * if obj is not created, then create one.
 681  * set feature enable flag.
 682  */
 683 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 684                 struct ras_common_if *head, int enable)
 685 {
 686         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 687         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 688
 689         /* If hardware does not support ras, then do not create obj.
 690          * But if hardware support ras, we can create the obj.
 691          * Ras framework checks con->hw_supported to see if it need do
 692          * corresponding initialization.
 693          * IP checks con->support to see if it need disable ras.
 694          */
 695         if (!amdgpu_ras_is_feature_allowed(adev, head))
 696                 return 0;
 697
 698         if (enable) {
 699                 if (!obj) {
 700                         obj = amdgpu_ras_create_obj(adev, head);
 701                         if (!obj)
 702                                 return -EINVAL;
 703                 } else {
 704                         /* In case we create obj somewhere else */
 705                         get_obj(obj);
 706                 }
 707                 con->features |= BIT(head->block);
 708         } else {
 709                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 710                         con->features &= ~BIT(head->block);
 711                         put_obj(obj);
 712                 }
 713         }
 714
 715         return 0;
 716 }
 717
 718 static int amdgpu_ras_check_feature_allowed(struct amdgpu_device *adev,
 719                 struct ras_common_if *head)
 720 {
 721         if (amdgpu_ras_is_feature_allowed(adev, head) ||
 722                 amdgpu_ras_is_poison_mode_supported(adev))
 723                 return 1;
 724         else
 725                 return 0;
 726 }
 727
 728 /* wrapper of psp_ras_enable_features */
 729 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 730                 struct ras_common_if *head, bool enable)
 731 {
 732         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 733         union ta_ras_cmd_input *info;
 734         int ret = 0;
 735
 736         if (!con)
 737                 return -EINVAL;
 738
 739         if (head->block == AMDGPU_RAS_BLOCK__GFX) {
 740                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 741                 if (!info)
 742                         return -ENOMEM;
 743
 744                 if (!enable) {
 745                         info->disable_features = (struct ta_ras_disable_features_input) {
 746                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 747                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 748                         };
 749                 } else {
 750                         info->enable_features = (struct ta_ras_enable_features_input) {
 751                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 752                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 753                         };
 754                 }
 755         }
 756
 757         /* Do not enable if it is not allowed. */
 758         if (enable && !amdgpu_ras_check_feature_allowed(adev, head))
 759                 goto out;
 760
 761         /* Only enable ras feature operation handle on host side */
 762         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 763                 !amdgpu_sriov_vf(adev) &&
 764                 !amdgpu_ras_intr_triggered()) {
 765                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 766                 if (ret) {
 767                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 768                                 enable ? "enable":"disable",
 769                                 get_ras_block_str(head),
 770                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 771                         goto out;
 772                 }
 773         }
 774
 775         /* setup the obj */
 776         __amdgpu_ras_feature_enable(adev, head, enable);
 777 out:
 778         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 779                 kfree(info);
 780         return ret;
 781 }
 782
 783 /* Only used in device probe stage and called only once. */
 784 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 785                 struct ras_common_if *head, bool enable)
 786 {
 787         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 788         int ret;
 789
 790         if (!con)
 791                 return -EINVAL;
 792
 793         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 794                 if (enable) {
 795                         /* There is no harm to issue a ras TA cmd regardless of
 796                          * the currecnt ras state.
 797                          * If current state == target state, it will do nothing
 798                          * But sometimes it requests driver to reset and repost
 799                          * with error code -EAGAIN.
 800                          */
 801                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 802                         /* With old ras TA, we might fail to enable ras.
 803                          * Log it and just setup the object.
 804                          * TODO need remove this WA in the future.
 805                          */
 806                         if (ret == -EINVAL) {
 807                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 808                                 if (!ret)
 809                                         dev_info(adev->dev,
 810                                                 "RAS INFO: %s setup object\n",
 811                                                 get_ras_block_str(head));
 812                         }
 813                 } else {
 814                         /* setup the object then issue a ras TA disable cmd.*/
 815                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 816                         if (ret)
 817                                 return ret;
 818
 819                         /* gfx block ras dsiable cmd must send to ras-ta */
 820                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 821                                 con->features |= BIT(head->block);
 822
 823                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 824
 825                         /* clean gfx block ras features flag */
 826                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 827                                 con->features &= ~BIT(head->block);
 828                 }
 829         } else
 830                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 831
 832         return ret;
 833 }
 834
 835 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 836                 bool bypass)
 837 {
 838         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 839         struct ras_manager *obj, *tmp;
 840
 841         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 842                 /* bypass psp.
 843                  * aka just release the obj and corresponding flags
 844                  */
 845                 if (bypass) {
 846                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 847                                 break;
 848                 } else {
 849                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 850                                 break;
 851                 }
 852         }
 853
 854         return con->features;
 855 }
 856
 857 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 858                 bool bypass)
 859 {
 860         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 861         int i;
 862         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 863
 864         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 865                 struct ras_common_if head = {
 866                         .block = i,
 867                         .type = default_ras_type,
 868                         .sub_block_index = 0,
 869                 };
 870
 871                 if (i == AMDGPU_RAS_BLOCK__MCA)
 872                         continue;
 873
 874                 if (bypass) {
 875                         /*
 876                          * bypass psp. vbios enable ras for us.
 877                          * so just create the obj
 878                          */
 879                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 880                                 break;
 881                 } else {
 882                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 883                                 break;
 884                 }
 885         }
 886
 887         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 888                 struct ras_common_if head = {
 889                         .block = AMDGPU_RAS_BLOCK__MCA,
 890                         .type = default_ras_type,
 891                         .sub_block_index = i,
 892                 };
 893
 894                 if (bypass) {
 895                         /*
 896                          * bypass psp. vbios enable ras for us.
 897                          * so just create the obj
 898                          */
 899                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 900                                 break;
 901                 } else {
 902                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 903                                 break;
 904                 }
 905         }
 906
 907         return con->features;
 908 }
 909 /* feature ctl end */
 910
 911 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 912                 enum amdgpu_ras_block block)
 913 {
 914         if (!block_obj)
 915                 return -EINVAL;
 916
 917         if (block_obj->ras_comm.block == block)
 918                 return 0;
 919
 920         return -EINVAL;
 921 }
 922
 923 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 924                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 925 {
 926         struct amdgpu_ras_block_list *node, *tmp;
 927         struct amdgpu_ras_block_object *obj;
 928
 929         if (block >= AMDGPU_RAS_BLOCK__LAST)
 930                 return NULL;
 931
 932         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 933                 if (!node->ras_obj) {
 934                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 935                         continue;
 936                 }
 937
 938                 obj = node->ras_obj;
 939                 if (obj->ras_block_match) {
 940                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 941                                 return obj;
 942                 } else {
 943                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 944                                 return obj;
 945                 }
 946         }
 947
 948         return NULL;
 949 }
 950
 951 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
 952 {
 953         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 954         int ret = 0;
 955
 956         /*
 957          * choosing right query method according to
 958          * whether smu support query error information
 959          */
 960         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
 961         if (ret == -EOPNOTSUPP) {
 962                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
 963                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
 964                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 965
 966                 /* umc query_ras_error_address is also responsible for clearing
 967                  * error status
 968                  */
 969                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
 970                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
 971                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
 972         } else if (!ret) {
 973                 if (adev->umc.ras &&
 974                         adev->umc.ras->ecc_info_query_ras_error_count)
 975                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
 976
 977                 if (adev->umc.ras &&
 978                         adev->umc.ras->ecc_info_query_ras_error_address)
 979                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
 980         }
 981 }
 982
 983 /* query/inject/cure begin */
 984 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 985                                   struct ras_query_if *info)
 986 {
 987         struct amdgpu_ras_block_object *block_obj = NULL;
 988         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 989         struct ras_err_data err_data = {0, 0, 0, NULL};
 990
 991         if (!obj)
 992                 return -EINVAL;
 993
 994         if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
 995                 amdgpu_ras_get_ecc_info(adev, &err_data);
 996         } else {
 997                 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
 998                 if (!block_obj || !block_obj->hw_ops)   {
 999                         dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1000                                      get_ras_block_str(&info->head));
1001                         return -EINVAL;
1002                 }
1003
1004                 if (block_obj->hw_ops->query_ras_error_count)
1005                         block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1006
1007                 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1008                     (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1009                     (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1010                                 if (block_obj->hw_ops->query_ras_error_status)
1011                                         block_obj->hw_ops->query_ras_error_status(adev);
1012                         }
1013         }
1014
1015         obj->err_data.ue_count += err_data.ue_count;
1016         obj->err_data.ce_count += err_data.ce_count;
1017
1018         info->ue_count = obj->err_data.ue_count;
1019         info->ce_count = obj->err_data.ce_count;
1020
1021         if (err_data.ce_count) {
1022                 if (adev->smuio.funcs &&
1023                     adev->smuio.funcs->get_socket_id &&
1024                     adev->smuio.funcs->get_die_id) {
1025                         dev_info(adev->dev, "socket: %d, die: %d "
1026                                         "%ld correctable hardware errors "
1027                                         "detected in %s block, no user "
1028                                         "action is needed.\n",
1029                                         adev->smuio.funcs->get_socket_id(adev),
1030                                         adev->smuio.funcs->get_die_id(adev),
1031                                         obj->err_data.ce_count,
1032                                         get_ras_block_str(&info->head));
1033                 } else {
1034                         dev_info(adev->dev, "%ld correctable hardware errors "
1035                                         "detected in %s block, no user "
1036                                         "action is needed.\n",
1037                                         obj->err_data.ce_count,
1038                                         get_ras_block_str(&info->head));
1039                 }
1040         }
1041         if (err_data.ue_count) {
1042                 if (adev->smuio.funcs &&
1043                     adev->smuio.funcs->get_socket_id &&
1044                     adev->smuio.funcs->get_die_id) {
1045                         dev_info(adev->dev, "socket: %d, die: %d "
1046                                         "%ld uncorrectable hardware errors "
1047                                         "detected in %s block\n",
1048                                         adev->smuio.funcs->get_socket_id(adev),
1049                                         adev->smuio.funcs->get_die_id(adev),
1050                                         obj->err_data.ue_count,
1051                                         get_ras_block_str(&info->head));
1052                 } else {
1053                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1054                                         "detected in %s block\n",
1055                                         obj->err_data.ue_count,
1056                                         get_ras_block_str(&info->head));
1057                 }
1058         }
1059
1060         return 0;
1061 }
1062
1063 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1064                 enum amdgpu_ras_block block)
1065 {
1066         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1067
1068         if (!amdgpu_ras_is_supported(adev, block))
1069                 return -EINVAL;
1070
1071         if (!block_obj || !block_obj->hw_ops)   {
1072                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1073                              ras_block_str(block));
1074                 return -EINVAL;
1075         }
1076
1077         if (block_obj->hw_ops->reset_ras_error_count)
1078                 block_obj->hw_ops->reset_ras_error_count(adev);
1079
1080         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1081             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1082                 if (block_obj->hw_ops->reset_ras_error_status)
1083                         block_obj->hw_ops->reset_ras_error_status(adev);
1084         }
1085
1086         return 0;
1087 }
1088
1089 /* wrapper of psp_ras_trigger_error */
1090 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1091                 struct ras_inject_if *info)
1092 {
1093         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1094         struct ta_ras_trigger_error_input block_info = {
1095                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1096                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1097                 .sub_block_index = info->head.sub_block_index,
1098                 .address = info->address,
1099                 .value = info->value,
1100         };
1101         int ret = -EINVAL;
1102         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1103                                                         info->head.block,
1104                                                         info->head.sub_block_index);
1105
1106         /* inject on guest isn't allowed, return success directly */
1107         if (amdgpu_sriov_vf(adev))
1108                 return 0;
1109
1110         if (!obj)
1111                 return -EINVAL;
1112
1113         if (!block_obj || !block_obj->hw_ops)   {
1114                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1115                              get_ras_block_str(&info->head));
1116                 return -EINVAL;
1117         }
1118
1119         /* Calculate XGMI relative offset */
1120         if (adev->gmc.xgmi.num_physical_nodes > 1) {
1121                 block_info.address =
1122                         amdgpu_xgmi_get_relative_phy_addr(adev,
1123                                                           block_info.address);
1124         }
1125
1126         if (info->head.block == AMDGPU_RAS_BLOCK__GFX) {
1127                 if (block_obj->hw_ops->ras_error_inject)
1128                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1129         } else {
1130                 /* If defined special ras_error_inject(e.g: xgmi), implement special ras_error_inject */
1131                 if (block_obj->hw_ops->ras_error_inject)
1132                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1133                                                 info->instance_mask);
1134                 else  /*If not defined .ras_error_inject, use default ras_error_inject*/
1135                         ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1136         }
1137
1138         if (ret)
1139                 dev_err(adev->dev, "ras inject %s failed %d\n",
1140                         get_ras_block_str(&info->head), ret);
1141
1142         return ret;
1143 }
1144
1145 /**
1146  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1147  * @adev: pointer to AMD GPU device
1148  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1149  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1150  * @query_info: pointer to ras_query_if
1151  *
1152  * Return 0 for query success or do nothing, otherwise return an error
1153  * on failures
1154  */
1155 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1156                                                unsigned long *ce_count,
1157                                                unsigned long *ue_count,
1158                                                struct ras_query_if *query_info)
1159 {
1160         int ret;
1161
1162         if (!query_info)
1163                 /* do nothing if query_info is not specified */
1164                 return 0;
1165
1166         ret = amdgpu_ras_query_error_status(adev, query_info);
1167         if (ret)
1168                 return ret;
1169
1170         *ce_count += query_info->ce_count;
1171         *ue_count += query_info->ue_count;
1172
1173         /* some hardware/IP supports read to clear
1174          * no need to explictly reset the err status after the query call */
1175         if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1176             adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1177                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1178                         dev_warn(adev->dev,
1179                                  "Failed to reset error counter and error status\n");
1180         }
1181
1182         return 0;
1183 }
1184
1185 /**
1186  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1187  * @adev: pointer to AMD GPU device
1188  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1189  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1190  * errors.
1191  * @query_info: pointer to ras_query_if if the query request is only for
1192  * specific ip block; if info is NULL, then the qurey request is for
1193  * all the ip blocks that support query ras error counters/status
1194  *
1195  * If set, @ce_count or @ue_count, count and return the corresponding
1196  * error counts in those integer pointers. Return 0 if the device
1197  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1198  */
1199 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1200                                  unsigned long *ce_count,
1201                                  unsigned long *ue_count,
1202                                  struct ras_query_if *query_info)
1203 {
1204         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1205         struct ras_manager *obj;
1206         unsigned long ce, ue;
1207         int ret;
1208
1209         if (!adev->ras_enabled || !con)
1210                 return -EOPNOTSUPP;
1211
1212         /* Don't count since no reporting.
1213          */
1214         if (!ce_count && !ue_count)
1215                 return 0;
1216
1217         ce = 0;
1218         ue = 0;
1219         if (!query_info) {
1220                 /* query all the ip blocks that support ras query interface */
1221                 list_for_each_entry(obj, &con->head, node) {
1222                         struct ras_query_if info = {
1223                                 .head = obj->head,
1224                         };
1225
1226                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1227                 }
1228         } else {
1229                 /* query specific ip block */
1230                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1231         }
1232
1233         if (ret)
1234                 return ret;
1235
1236         if (ce_count)
1237                 *ce_count = ce;
1238
1239         if (ue_count)
1240                 *ue_count = ue;
1241
1242         return 0;
1243 }
1244 /* query/inject/cure end */
1245
1246
1247 /* sysfs begin */
1248
1249 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1250                 struct ras_badpage **bps, unsigned int *count);
1251
1252 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1253 {
1254         switch (flags) {
1255         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1256                 return "R";
1257         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1258                 return "P";
1259         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1260         default:
1261                 return "F";
1262         }
1263 }
1264
1265 /**
1266  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1267  *
1268  * It allows user to read the bad pages of vram on the gpu through
1269  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1270  *
1271  * It outputs multiple lines, and each line stands for one gpu page.
1272  *
1273  * The format of one line is below,
1274  * gpu pfn : gpu page size : flags
1275  *
1276  * gpu pfn and gpu page size are printed in hex format.
1277  * flags can be one of below character,
1278  *
1279  * R: reserved, this gpu page is reserved and not able to use.
1280  *
1281  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1282  * in next window of page_reserve.
1283  *
1284  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1285  *
1286  * Examples:
1287  *
1288  * .. code-block:: bash
1289  *
1290  *      0x00000001 : 0x00001000 : R
1291  *      0x00000002 : 0x00001000 : P
1292  *
1293  */
1294
1295 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1296                 struct kobject *kobj, struct bin_attribute *attr,
1297                 char *buf, loff_t ppos, size_t count)
1298 {
1299         struct amdgpu_ras *con =
1300                 container_of(attr, struct amdgpu_ras, badpages_attr);
1301         struct amdgpu_device *adev = con->adev;
1302         const unsigned int element_size =
1303                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1304         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1305         unsigned int end = div64_ul(ppos + count - 1, element_size);
1306         ssize_t s = 0;
1307         struct ras_badpage *bps = NULL;
1308         unsigned int bps_count = 0;
1309
1310         memset(buf, 0, count);
1311
1312         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1313                 return 0;
1314
1315         for (; start < end && start < bps_count; start++)
1316                 s += scnprintf(&buf[s], element_size + 1,
1317                                 "0x%08x : 0x%08x : %1s\n",
1318                                 bps[start].bp,
1319                                 bps[start].size,
1320                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1321
1322         kfree(bps);
1323
1324         return s;
1325 }
1326
1327 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1328                 struct device_attribute *attr, char *buf)
1329 {
1330         struct amdgpu_ras *con =
1331                 container_of(attr, struct amdgpu_ras, features_attr);
1332
1333         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1334 }
1335
1336 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1337 {
1338         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1339
1340         sysfs_remove_file_from_group(&adev->dev->kobj,
1341                                 &con->badpages_attr.attr,
1342                                 RAS_FS_NAME);
1343 }
1344
1345 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1346 {
1347         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1348         struct attribute *attrs[] = {
1349                 &con->features_attr.attr,
1350                 NULL
1351         };
1352         struct attribute_group group = {
1353                 .name = RAS_FS_NAME,
1354                 .attrs = attrs,
1355         };
1356
1357         sysfs_remove_group(&adev->dev->kobj, &group);
1358
1359         return 0;
1360 }
1361
1362 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1363                 struct ras_common_if *head)
1364 {
1365         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1366
1367         if (!obj || obj->attr_inuse)
1368                 return -EINVAL;
1369
1370         get_obj(obj);
1371
1372         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1373                 "%s_err_count", head->name);
1374
1375         obj->sysfs_attr = (struct device_attribute){
1376                 .attr = {
1377                         .name = obj->fs_data.sysfs_name,
1378                         .mode = S_IRUGO,
1379                 },
1380                         .show = amdgpu_ras_sysfs_read,
1381         };
1382         sysfs_attr_init(&obj->sysfs_attr.attr);
1383
1384         if (sysfs_add_file_to_group(&adev->dev->kobj,
1385                                 &obj->sysfs_attr.attr,
1386                                 RAS_FS_NAME)) {
1387                 put_obj(obj);
1388                 return -EINVAL;
1389         }
1390
1391         obj->attr_inuse = 1;
1392
1393         return 0;
1394 }
1395
1396 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1397                 struct ras_common_if *head)
1398 {
1399         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1400
1401         if (!obj || !obj->attr_inuse)
1402                 return -EINVAL;
1403
1404         sysfs_remove_file_from_group(&adev->dev->kobj,
1405                                 &obj->sysfs_attr.attr,
1406                                 RAS_FS_NAME);
1407         obj->attr_inuse = 0;
1408         put_obj(obj);
1409
1410         return 0;
1411 }
1412
1413 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1414 {
1415         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1416         struct ras_manager *obj, *tmp;
1417
1418         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1419                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1420         }
1421
1422         if (amdgpu_bad_page_threshold != 0)
1423                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1424
1425         amdgpu_ras_sysfs_remove_feature_node(adev);
1426
1427         return 0;
1428 }
1429 /* sysfs end */
1430
1431 /**
1432  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1433  *
1434  * Normally when there is an uncorrectable error, the driver will reset
1435  * the GPU to recover.  However, in the event of an unrecoverable error,
1436  * the driver provides an interface to reboot the system automatically
1437  * in that event.
1438  *
1439  * The following file in debugfs provides that interface:
1440  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1441  *
1442  * Usage:
1443  *
1444  * .. code-block:: bash
1445  *
1446  *      echo true > .../ras/auto_reboot
1447  *
1448  */
1449 /* debugfs begin */
1450 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1451 {
1452         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1453         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1454         struct dentry     *dir;
1455
1456         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1457         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1458                             &amdgpu_ras_debugfs_ctrl_ops);
1459         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1460                             &amdgpu_ras_debugfs_eeprom_ops);
1461         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1462                            &con->bad_page_cnt_threshold);
1463         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1464         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1465         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1466                             &amdgpu_ras_debugfs_eeprom_size_ops);
1467         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1468                                                        S_IRUGO, dir, adev,
1469                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1470         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1471
1472         /*
1473          * After one uncorrectable error happens, usually GPU recovery will
1474          * be scheduled. But due to the known problem in GPU recovery failing
1475          * to bring GPU back, below interface provides one direct way to
1476          * user to reboot system automatically in such case within
1477          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1478          * will never be called.
1479          */
1480         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1481
1482         /*
1483          * User could set this not to clean up hardware's error count register
1484          * of RAS IPs during ras recovery.
1485          */
1486         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1487                             &con->disable_ras_err_cnt_harvest);
1488         return dir;
1489 }
1490
1491 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1492                                       struct ras_fs_if *head,
1493                                       struct dentry *dir)
1494 {
1495         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1496
1497         if (!obj || !dir)
1498                 return;
1499
1500         get_obj(obj);
1501
1502         memcpy(obj->fs_data.debugfs_name,
1503                         head->debugfs_name,
1504                         sizeof(obj->fs_data.debugfs_name));
1505
1506         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1507                             obj, &amdgpu_ras_debugfs_ops);
1508 }
1509
1510 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1511 {
1512         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1513         struct dentry *dir;
1514         struct ras_manager *obj;
1515         struct ras_fs_if fs_info;
1516
1517         /*
1518          * it won't be called in resume path, no need to check
1519          * suspend and gpu reset status
1520          */
1521         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1522                 return;
1523
1524         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1525
1526         list_for_each_entry(obj, &con->head, node) {
1527                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1528                         (obj->attr_inuse == 1)) {
1529                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1530                                         get_ras_block_str(&obj->head));
1531                         fs_info.head = obj->head;
1532                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1533                 }
1534         }
1535 }
1536
1537 /* debugfs end */
1538
1539 /* ras fs */
1540 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1541                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1542 static DEVICE_ATTR(features, S_IRUGO,
1543                 amdgpu_ras_sysfs_features_read, NULL);
1544 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1545 {
1546         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1547         struct attribute_group group = {
1548                 .name = RAS_FS_NAME,
1549         };
1550         struct attribute *attrs[] = {
1551                 &con->features_attr.attr,
1552                 NULL
1553         };
1554         struct bin_attribute *bin_attrs[] = {
1555                 NULL,
1556                 NULL,
1557         };
1558         int r;
1559
1560         /* add features entry */
1561         con->features_attr = dev_attr_features;
1562         group.attrs = attrs;
1563         sysfs_attr_init(attrs[0]);
1564
1565         if (amdgpu_bad_page_threshold != 0) {
1566                 /* add bad_page_features entry */
1567                 bin_attr_gpu_vram_bad_pages.private = NULL;
1568                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1569                 bin_attrs[0] = &con->badpages_attr;
1570                 group.bin_attrs = bin_attrs;
1571                 sysfs_bin_attr_init(bin_attrs[0]);
1572         }
1573
1574         r = sysfs_create_group(&adev->dev->kobj, &group);
1575         if (r)
1576                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1577
1578         return 0;
1579 }
1580
1581 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1582 {
1583         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1584         struct ras_manager *con_obj, *ip_obj, *tmp;
1585
1586         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1587                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1588                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1589                         if (ip_obj)
1590                                 put_obj(ip_obj);
1591                 }
1592         }
1593
1594         amdgpu_ras_sysfs_remove_all(adev);
1595         return 0;
1596 }
1597 /* ras fs end */
1598
1599 /* ih begin */
1600
1601 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1602  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1603  * register to check whether the interrupt is triggered or not, and properly
1604  * ack the interrupt if it is there
1605  */
1606 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1607 {
1608         /* Fatal error events are handled on host side */
1609         if (amdgpu_sriov_vf(adev))
1610                 return;
1611
1612         if (adev->nbio.ras &&
1613             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1614                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1615
1616         if (adev->nbio.ras &&
1617             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1618                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1619 }
1620
1621 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1622                                 struct amdgpu_iv_entry *entry)
1623 {
1624         bool poison_stat = false;
1625         struct amdgpu_device *adev = obj->adev;
1626         struct amdgpu_ras_block_object *block_obj =
1627                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1628
1629         if (!block_obj)
1630                 return;
1631
1632         /* both query_poison_status and handle_poison_consumption are optional,
1633          * but at least one of them should be implemented if we need poison
1634          * consumption handler
1635          */
1636         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1637                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1638                 if (!poison_stat) {
1639                         /* Not poison consumption interrupt, no need to handle it */
1640                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1641                                         block_obj->ras_comm.name);
1642
1643                         return;
1644                 }
1645         }
1646
1647         if (!adev->gmc.xgmi.connected_to_cpu)
1648                 amdgpu_umc_poison_handler(adev, false);
1649
1650         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1651                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1652
1653         /* gpu reset is fallback for failed and default cases */
1654         if (poison_stat) {
1655                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1656                                 block_obj->ras_comm.name);
1657                 amdgpu_ras_reset_gpu(adev);
1658         } else {
1659                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1660         }
1661 }
1662
1663 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1664                                 struct amdgpu_iv_entry *entry)
1665 {
1666         dev_info(obj->adev->dev,
1667                 "Poison is created, no user action is needed.\n");
1668 }
1669
1670 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1671                                 struct amdgpu_iv_entry *entry)
1672 {
1673         struct ras_ih_data *data = &obj->ih_data;
1674         struct ras_err_data err_data = {0, 0, 0, NULL};
1675         int ret;
1676
1677         if (!data->cb)
1678                 return;
1679
1680         /* Let IP handle its data, maybe we need get the output
1681          * from the callback to update the error type/count, etc
1682          */
1683         ret = data->cb(obj->adev, &err_data, entry);
1684         /* ue will trigger an interrupt, and in that case
1685          * we need do a reset to recovery the whole system.
1686          * But leave IP do that recovery, here we just dispatch
1687          * the error.
1688          */
1689         if (ret == AMDGPU_RAS_SUCCESS) {
1690                 /* these counts could be left as 0 if
1691                  * some blocks do not count error number
1692                  */
1693                 obj->err_data.ue_count += err_data.ue_count;
1694                 obj->err_data.ce_count += err_data.ce_count;
1695         }
1696 }
1697
1698 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1699 {
1700         struct ras_ih_data *data = &obj->ih_data;
1701         struct amdgpu_iv_entry entry;
1702
1703         while (data->rptr != data->wptr) {
1704                 rmb();
1705                 memcpy(&entry, &data->ring[data->rptr],
1706                                 data->element_size);
1707
1708                 wmb();
1709                 data->rptr = (data->aligned_element_size +
1710                                 data->rptr) % data->ring_size;
1711
1712                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1713                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1714                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1715                         else
1716                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1717                 } else {
1718                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1719                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1720                         else
1721                                 dev_warn(obj->adev->dev,
1722                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1723                 }
1724         }
1725 }
1726
1727 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1728 {
1729         struct ras_ih_data *data =
1730                 container_of(work, struct ras_ih_data, ih_work);
1731         struct ras_manager *obj =
1732                 container_of(data, struct ras_manager, ih_data);
1733
1734         amdgpu_ras_interrupt_handler(obj);
1735 }
1736
1737 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1738                 struct ras_dispatch_if *info)
1739 {
1740         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1741         struct ras_ih_data *data = &obj->ih_data;
1742
1743         if (!obj)
1744                 return -EINVAL;
1745
1746         if (data->inuse == 0)
1747                 return 0;
1748
1749         /* Might be overflow... */
1750         memcpy(&data->ring[data->wptr], info->entry,
1751                         data->element_size);
1752
1753         wmb();
1754         data->wptr = (data->aligned_element_size +
1755                         data->wptr) % data->ring_size;
1756
1757         schedule_work(&data->ih_work);
1758
1759         return 0;
1760 }
1761
1762 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1763                 struct ras_common_if *head)
1764 {
1765         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1766         struct ras_ih_data *data;
1767
1768         if (!obj)
1769                 return -EINVAL;
1770
1771         data = &obj->ih_data;
1772         if (data->inuse == 0)
1773                 return 0;
1774
1775         cancel_work_sync(&data->ih_work);
1776
1777         kfree(data->ring);
1778         memset(data, 0, sizeof(*data));
1779         put_obj(obj);
1780
1781         return 0;
1782 }
1783
1784 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1785                 struct ras_common_if *head)
1786 {
1787         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1788         struct ras_ih_data *data;
1789         struct amdgpu_ras_block_object *ras_obj;
1790
1791         if (!obj) {
1792                 /* in case we registe the IH before enable ras feature */
1793                 obj = amdgpu_ras_create_obj(adev, head);
1794                 if (!obj)
1795                         return -EINVAL;
1796         } else
1797                 get_obj(obj);
1798
1799         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1800
1801         data = &obj->ih_data;
1802         /* add the callback.etc */
1803         *data = (struct ras_ih_data) {
1804                 .inuse = 0,
1805                 .cb = ras_obj->ras_cb,
1806                 .element_size = sizeof(struct amdgpu_iv_entry),
1807                 .rptr = 0,
1808                 .wptr = 0,
1809         };
1810
1811         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1812
1813         data->aligned_element_size = ALIGN(data->element_size, 8);
1814         /* the ring can store 64 iv entries. */
1815         data->ring_size = 64 * data->aligned_element_size;
1816         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1817         if (!data->ring) {
1818                 put_obj(obj);
1819                 return -ENOMEM;
1820         }
1821
1822         /* IH is ready */
1823         data->inuse = 1;
1824
1825         return 0;
1826 }
1827
1828 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1829 {
1830         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1831         struct ras_manager *obj, *tmp;
1832
1833         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1834                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
1835         }
1836
1837         return 0;
1838 }
1839 /* ih end */
1840
1841 /* traversal all IPs except NBIO to query error counter */
1842 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1843 {
1844         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1845         struct ras_manager *obj;
1846
1847         if (!adev->ras_enabled || !con)
1848                 return;
1849
1850         list_for_each_entry(obj, &con->head, node) {
1851                 struct ras_query_if info = {
1852                         .head = obj->head,
1853                 };
1854
1855                 /*
1856                  * PCIE_BIF IP has one different isr by ras controller
1857                  * interrupt, the specific ras counter query will be
1858                  * done in that isr. So skip such block from common
1859                  * sync flood interrupt isr calling.
1860                  */
1861                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1862                         continue;
1863
1864                 /*
1865                  * this is a workaround for aldebaran, skip send msg to
1866                  * smu to get ecc_info table due to smu handle get ecc
1867                  * info table failed temporarily.
1868                  * should be removed until smu fix handle ecc_info table.
1869                  */
1870                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1871                         (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1872                         continue;
1873
1874                 amdgpu_ras_query_error_status(adev, &info);
1875
1876                 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1877                     adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
1878                     adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
1879                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
1880                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
1881                 }
1882         }
1883 }
1884
1885 /* Parse RdRspStatus and WrRspStatus */
1886 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1887                                           struct ras_query_if *info)
1888 {
1889         struct amdgpu_ras_block_object *block_obj;
1890         /*
1891          * Only two block need to query read/write
1892          * RspStatus at current state
1893          */
1894         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1895                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
1896                 return;
1897
1898         block_obj = amdgpu_ras_get_ras_block(adev,
1899                                         info->head.block,
1900                                         info->head.sub_block_index);
1901
1902         if (!block_obj || !block_obj->hw_ops) {
1903                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1904                              get_ras_block_str(&info->head));
1905                 return;
1906         }
1907
1908         if (block_obj->hw_ops->query_ras_error_status)
1909                 block_obj->hw_ops->query_ras_error_status(adev);
1910
1911 }
1912
1913 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1914 {
1915         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1916         struct ras_manager *obj;
1917
1918         if (!adev->ras_enabled || !con)
1919                 return;
1920
1921         list_for_each_entry(obj, &con->head, node) {
1922                 struct ras_query_if info = {
1923                         .head = obj->head,
1924                 };
1925
1926                 amdgpu_ras_error_status_query(adev, &info);
1927         }
1928 }
1929
1930 /* recovery begin */
1931
1932 /* return 0 on success.
1933  * caller need free bps.
1934  */
1935 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1936                 struct ras_badpage **bps, unsigned int *count)
1937 {
1938         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1939         struct ras_err_handler_data *data;
1940         int i = 0;
1941         int ret = 0, status;
1942
1943         if (!con || !con->eh_data || !bps || !count)
1944                 return -EINVAL;
1945
1946         mutex_lock(&con->recovery_lock);
1947         data = con->eh_data;
1948         if (!data || data->count == 0) {
1949                 *bps = NULL;
1950                 ret = -EINVAL;
1951                 goto out;
1952         }
1953
1954         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1955         if (!*bps) {
1956                 ret = -ENOMEM;
1957                 goto out;
1958         }
1959
1960         for (; i < data->count; i++) {
1961                 (*bps)[i] = (struct ras_badpage){
1962                         .bp = data->bps[i].retired_page,
1963                         .size = AMDGPU_GPU_PAGE_SIZE,
1964                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1965                 };
1966                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
1967                                 data->bps[i].retired_page);
1968                 if (status == -EBUSY)
1969                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1970                 else if (status == -ENOENT)
1971                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1972         }
1973
1974         *count = data->count;
1975 out:
1976         mutex_unlock(&con->recovery_lock);
1977         return ret;
1978 }
1979
1980 static void amdgpu_ras_do_recovery(struct work_struct *work)
1981 {
1982         struct amdgpu_ras *ras =
1983                 container_of(work, struct amdgpu_ras, recovery_work);
1984         struct amdgpu_device *remote_adev = NULL;
1985         struct amdgpu_device *adev = ras->adev;
1986         struct list_head device_list, *device_list_handle =  NULL;
1987
1988         if (!ras->disable_ras_err_cnt_harvest) {
1989                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1990
1991                 /* Build list of devices to query RAS related errors */
1992                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1993                         device_list_handle = &hive->device_list;
1994                 } else {
1995                         INIT_LIST_HEAD(&device_list);
1996                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1997                         device_list_handle = &device_list;
1998                 }
1999
2000                 list_for_each_entry(remote_adev,
2001                                 device_list_handle, gmc.xgmi.head) {
2002                         amdgpu_ras_query_err_status(remote_adev);
2003                         amdgpu_ras_log_on_err_counter(remote_adev);
2004                 }
2005
2006                 amdgpu_put_xgmi_hive(hive);
2007         }
2008
2009         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2010                 struct amdgpu_reset_context reset_context;
2011                 memset(&reset_context, 0, sizeof(reset_context));
2012
2013                 reset_context.method = AMD_RESET_METHOD_NONE;
2014                 reset_context.reset_req_dev = adev;
2015
2016                 /* Perform full reset in fatal error mode */
2017                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2018                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2019                 else
2020                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2021
2022                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2023         }
2024         atomic_set(&ras->in_recovery, 0);
2025 }
2026
2027 /* alloc/realloc bps array */
2028 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2029                 struct ras_err_handler_data *data, int pages)
2030 {
2031         unsigned int old_space = data->count + data->space_left;
2032         unsigned int new_space = old_space + pages;
2033         unsigned int align_space = ALIGN(new_space, 512);
2034         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2035
2036         if (!bps) {
2037                 return -ENOMEM;
2038         }
2039
2040         if (data->bps) {
2041                 memcpy(bps, data->bps,
2042                                 data->count * sizeof(*data->bps));
2043                 kfree(data->bps);
2044         }
2045
2046         data->bps = bps;
2047         data->space_left += align_space - old_space;
2048         return 0;
2049 }
2050
2051 /* it deal with vram only. */
2052 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2053                 struct eeprom_table_record *bps, int pages)
2054 {
2055         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2056         struct ras_err_handler_data *data;
2057         int ret = 0;
2058         uint32_t i;
2059
2060         if (!con || !con->eh_data || !bps || pages <= 0)
2061                 return 0;
2062
2063         mutex_lock(&con->recovery_lock);
2064         data = con->eh_data;
2065         if (!data)
2066                 goto out;
2067
2068         for (i = 0; i < pages; i++) {
2069                 if (amdgpu_ras_check_bad_page_unlock(con,
2070                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2071                         continue;
2072
2073                 if (!data->space_left &&
2074                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2075                         ret = -ENOMEM;
2076                         goto out;
2077                 }
2078
2079                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2080                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2081                         AMDGPU_GPU_PAGE_SIZE);
2082
2083                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2084                 data->count++;
2085                 data->space_left--;
2086         }
2087 out:
2088         mutex_unlock(&con->recovery_lock);
2089
2090         return ret;
2091 }
2092
2093 /*
2094  * write error record array to eeprom, the function should be
2095  * protected by recovery_lock
2096  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2097  */
2098 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2099                 unsigned long *new_cnt)
2100 {
2101         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2102         struct ras_err_handler_data *data;
2103         struct amdgpu_ras_eeprom_control *control;
2104         int save_count;
2105
2106         if (!con || !con->eh_data) {
2107                 if (new_cnt)
2108                         *new_cnt = 0;
2109
2110                 return 0;
2111         }
2112
2113         mutex_lock(&con->recovery_lock);
2114         control = &con->eeprom_control;
2115         data = con->eh_data;
2116         save_count = data->count - control->ras_num_recs;
2117         mutex_unlock(&con->recovery_lock);
2118
2119         if (new_cnt)
2120                 *new_cnt = save_count / adev->umc.retire_unit;
2121
2122         /* only new entries are saved */
2123         if (save_count > 0) {
2124                 if (amdgpu_ras_eeprom_append(control,
2125                                              &data->bps[control->ras_num_recs],
2126                                              save_count)) {
2127                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2128                         return -EIO;
2129                 }
2130
2131                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2132         }
2133
2134         return 0;
2135 }
2136
2137 /*
2138  * read error record array in eeprom and reserve enough space for
2139  * storing new bad pages
2140  */
2141 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2142 {
2143         struct amdgpu_ras_eeprom_control *control =
2144                 &adev->psp.ras_context.ras->eeprom_control;
2145         struct eeprom_table_record *bps;
2146         int ret;
2147
2148         /* no bad page record, skip eeprom access */
2149         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2150                 return 0;
2151
2152         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2153         if (!bps)
2154                 return -ENOMEM;
2155
2156         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2157         if (ret)
2158                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2159         else
2160                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2161
2162         kfree(bps);
2163         return ret;
2164 }
2165
2166 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2167                                 uint64_t addr)
2168 {
2169         struct ras_err_handler_data *data = con->eh_data;
2170         int i;
2171
2172         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2173         for (i = 0; i < data->count; i++)
2174                 if (addr == data->bps[i].retired_page)
2175                         return true;
2176
2177         return false;
2178 }
2179
2180 /*
2181  * check if an address belongs to bad page
2182  *
2183  * Note: this check is only for umc block
2184  */
2185 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2186                                 uint64_t addr)
2187 {
2188         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2189         bool ret = false;
2190
2191         if (!con || !con->eh_data)
2192                 return ret;
2193
2194         mutex_lock(&con->recovery_lock);
2195         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2196         mutex_unlock(&con->recovery_lock);
2197         return ret;
2198 }
2199
2200 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2201                                           uint32_t max_count)
2202 {
2203         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2204
2205         /*
2206          * Justification of value bad_page_cnt_threshold in ras structure
2207          *
2208          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2209          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2210          * scenarios accordingly.
2211          *
2212          * Bad page retirement enablement:
2213          *    - If amdgpu_bad_page_threshold = -2,
2214          *      bad_page_cnt_threshold = typical value by formula.
2215          *
2216          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2217          *      max record length in eeprom, use it directly.
2218          *
2219          * Bad page retirement disablement:
2220          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2221          *      functionality is disabled, and bad_page_cnt_threshold will
2222          *      take no effect.
2223          */
2224
2225         if (amdgpu_bad_page_threshold < 0) {
2226                 u64 val = adev->gmc.mc_vram_size;
2227
2228                 do_div(val, RAS_BAD_PAGE_COVER);
2229                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2230                                                   max_count);
2231         } else {
2232                 con->bad_page_cnt_threshold = min_t(int, max_count,
2233                                                     amdgpu_bad_page_threshold);
2234         }
2235 }
2236
2237 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2238 {
2239         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2240         struct ras_err_handler_data **data;
2241         u32  max_eeprom_records_count = 0;
2242         bool exc_err_limit = false;
2243         int ret;
2244
2245         if (!con || amdgpu_sriov_vf(adev))
2246                 return 0;
2247
2248         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2249          * supports RAS and debugfs is enabled, but when
2250          * adev->ras_enabled is unset, i.e. when "ras_enable"
2251          * module parameter is set to 0.
2252          */
2253         con->adev = adev;
2254
2255         if (!adev->ras_enabled)
2256                 return 0;
2257
2258         data = &con->eh_data;
2259         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2260         if (!*data) {
2261                 ret = -ENOMEM;
2262                 goto out;
2263         }
2264
2265         mutex_init(&con->recovery_lock);
2266         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2267         atomic_set(&con->in_recovery, 0);
2268         con->eeprom_control.bad_channel_bitmap = 0;
2269
2270         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
2271         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2272
2273         /* Todo: During test the SMU might fail to read the eeprom through I2C
2274          * when the GPU is pending on XGMI reset during probe time
2275          * (Mostly after second bus reset), skip it now
2276          */
2277         if (adev->gmc.xgmi.pending_reset)
2278                 return 0;
2279         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2280         /*
2281          * This calling fails when exc_err_limit is true or
2282          * ret != 0.
2283          */
2284         if (exc_err_limit || ret)
2285                 goto free;
2286
2287         if (con->eeprom_control.ras_num_recs) {
2288                 ret = amdgpu_ras_load_bad_pages(adev);
2289                 if (ret)
2290                         goto free;
2291
2292                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2293
2294                 if (con->update_channel_flag == true) {
2295                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2296                         con->update_channel_flag = false;
2297                 }
2298         }
2299
2300 #ifdef CONFIG_X86_MCE_AMD
2301         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2302             (adev->gmc.xgmi.connected_to_cpu))
2303                 amdgpu_register_bad_pages_mca_notifier(adev);
2304 #endif
2305         return 0;
2306
2307 free:
2308         kfree((*data)->bps);
2309         kfree(*data);
2310         con->eh_data = NULL;
2311 out:
2312         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2313
2314         /*
2315          * Except error threshold exceeding case, other failure cases in this
2316          * function would not fail amdgpu driver init.
2317          */
2318         if (!exc_err_limit)
2319                 ret = 0;
2320         else
2321                 ret = -EINVAL;
2322
2323         return ret;
2324 }
2325
2326 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2327 {
2328         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2329         struct ras_err_handler_data *data = con->eh_data;
2330
2331         /* recovery_init failed to init it, fini is useless */
2332         if (!data)
2333                 return 0;
2334
2335         cancel_work_sync(&con->recovery_work);
2336
2337         mutex_lock(&con->recovery_lock);
2338         con->eh_data = NULL;
2339         kfree(data->bps);
2340         kfree(data);
2341         mutex_unlock(&con->recovery_lock);
2342
2343         return 0;
2344 }
2345 /* recovery end */
2346
2347 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2348 {
2349         if (amdgpu_sriov_vf(adev)) {
2350                 switch (adev->ip_versions[MP0_HWIP][0]) {
2351                 case IP_VERSION(13, 0, 2):
2352                         return true;
2353                 default:
2354                         return false;
2355                 }
2356         }
2357
2358         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2359                 switch (adev->ip_versions[MP0_HWIP][0]) {
2360                 case IP_VERSION(13, 0, 0):
2361                 case IP_VERSION(13, 0, 10):
2362                         return true;
2363                 default:
2364                         return false;
2365                 }
2366         }
2367
2368         return adev->asic_type == CHIP_VEGA10 ||
2369                 adev->asic_type == CHIP_VEGA20 ||
2370                 adev->asic_type == CHIP_ARCTURUS ||
2371                 adev->asic_type == CHIP_ALDEBARAN ||
2372                 adev->asic_type == CHIP_SIENNA_CICHLID;
2373 }
2374
2375 /*
2376  * this is workaround for vega20 workstation sku,
2377  * force enable gfx ras, ignore vbios gfx ras flag
2378  * due to GC EDC can not write
2379  */
2380 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2381 {
2382         struct atom_context *ctx = adev->mode_info.atom_context;
2383
2384         if (!ctx)
2385                 return;
2386
2387         if (strnstr(ctx->vbios_version, "D16406",
2388                     sizeof(ctx->vbios_version)) ||
2389                 strnstr(ctx->vbios_version, "D36002",
2390                         sizeof(ctx->vbios_version)))
2391                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2392 }
2393
2394 /*
2395  * check hardware's ras ability which will be saved in hw_supported.
2396  * if hardware does not support ras, we can skip some ras initializtion and
2397  * forbid some ras operations from IP.
2398  * if software itself, say boot parameter, limit the ras ability. We still
2399  * need allow IP do some limited operations, like disable. In such case,
2400  * we have to initialize ras as normal. but need check if operation is
2401  * allowed or not in each function.
2402  */
2403 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2404 {
2405         adev->ras_hw_enabled = adev->ras_enabled = 0;
2406
2407         if (!adev->is_atom_fw ||
2408             !amdgpu_ras_asic_supported(adev))
2409                 return;
2410
2411         if (!adev->gmc.xgmi.connected_to_cpu) {
2412                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2413                         dev_info(adev->dev, "MEM ECC is active.\n");
2414                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2415                                                    1 << AMDGPU_RAS_BLOCK__DF);
2416                 } else {
2417                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2418                 }
2419
2420                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2421                         dev_info(adev->dev, "SRAM ECC is active.\n");
2422                         if (!amdgpu_sriov_vf(adev))
2423                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2424                                                             1 << AMDGPU_RAS_BLOCK__DF);
2425                         else
2426                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2427                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2428                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2429
2430                         /* VCN/JPEG RAS can be supported on both bare metal and
2431                          * SRIOV environment
2432                          */
2433                         if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) ||
2434                             adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0))
2435                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2436                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2437                         else
2438                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2439                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2440
2441                         /*
2442                          * XGMI RAS is not supported if xgmi num physical nodes
2443                          * is zero
2444                          */
2445                         if (!adev->gmc.xgmi.num_physical_nodes)
2446                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2447                 } else {
2448                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2449                 }
2450         } else {
2451                 /* driver only manages a few IP blocks RAS feature
2452                  * when GPU is connected cpu through XGMI */
2453                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2454                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2455                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2456         }
2457
2458         amdgpu_ras_get_quirks(adev);
2459
2460         /* hw_supported needs to be aligned with RAS block mask. */
2461         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2462
2463         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2464                 adev->ras_hw_enabled & amdgpu_ras_mask;
2465 }
2466
2467 static void amdgpu_ras_counte_dw(struct work_struct *work)
2468 {
2469         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2470                                               ras_counte_delay_work.work);
2471         struct amdgpu_device *adev = con->adev;
2472         struct drm_device *dev = adev_to_drm(adev);
2473         unsigned long ce_count, ue_count;
2474         int res;
2475
2476         res = pm_runtime_get_sync(dev->dev);
2477         if (res < 0)
2478                 goto Out;
2479
2480         /* Cache new values.
2481          */
2482         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2483                 atomic_set(&con->ras_ce_count, ce_count);
2484                 atomic_set(&con->ras_ue_count, ue_count);
2485         }
2486
2487         pm_runtime_mark_last_busy(dev->dev);
2488 Out:
2489         pm_runtime_put_autosuspend(dev->dev);
2490 }
2491
2492 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2493 {
2494         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2495         bool df_poison, umc_poison;
2496
2497         /* poison setting is useless on SRIOV guest */
2498         if (amdgpu_sriov_vf(adev) || !con)
2499                 return;
2500
2501         /* Init poison supported flag, the default value is false */
2502         if (adev->gmc.xgmi.connected_to_cpu) {
2503                 /* enabled by default when GPU is connected to CPU */
2504                 con->poison_supported = true;
2505         } else if (adev->df.funcs &&
2506             adev->df.funcs->query_ras_poison_mode &&
2507             adev->umc.ras &&
2508             adev->umc.ras->query_ras_poison_mode) {
2509                 df_poison =
2510                         adev->df.funcs->query_ras_poison_mode(adev);
2511                 umc_poison =
2512                         adev->umc.ras->query_ras_poison_mode(adev);
2513
2514                 /* Only poison is set in both DF and UMC, we can support it */
2515                 if (df_poison && umc_poison)
2516                         con->poison_supported = true;
2517                 else if (df_poison != umc_poison)
2518                         dev_warn(adev->dev,
2519                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2520                                 df_poison, umc_poison);
2521         }
2522 }
2523
2524 int amdgpu_ras_init(struct amdgpu_device *adev)
2525 {
2526         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2527         int r;
2528
2529         if (con)
2530                 return 0;
2531
2532         con = kmalloc(sizeof(struct amdgpu_ras) +
2533                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2534                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2535                         GFP_KERNEL|__GFP_ZERO);
2536         if (!con)
2537                 return -ENOMEM;
2538
2539         con->adev = adev;
2540         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2541         atomic_set(&con->ras_ce_count, 0);
2542         atomic_set(&con->ras_ue_count, 0);
2543
2544         con->objs = (struct ras_manager *)(con + 1);
2545
2546         amdgpu_ras_set_context(adev, con);
2547
2548         amdgpu_ras_check_supported(adev);
2549
2550         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2551                 /* set gfx block ras context feature for VEGA20 Gaming
2552                  * send ras disable cmd to ras ta during ras late init.
2553                  */
2554                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2555                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2556
2557                         return 0;
2558                 }
2559
2560                 r = 0;
2561                 goto release_con;
2562         }
2563
2564         con->update_channel_flag = false;
2565         con->features = 0;
2566         INIT_LIST_HEAD(&con->head);
2567         /* Might need get this flag from vbios. */
2568         con->flags = RAS_DEFAULT_FLAGS;
2569
2570         /* initialize nbio ras function ahead of any other
2571          * ras functions so hardware fatal error interrupt
2572          * can be enabled as early as possible */
2573         switch (adev->ip_versions[NBIO_HWIP][0]) {
2574         case IP_VERSION(7, 4, 0):
2575         case IP_VERSION(7, 4, 1):
2576         case IP_VERSION(7, 4, 4):
2577                 if (!adev->gmc.xgmi.connected_to_cpu)
2578                         adev->nbio.ras = &nbio_v7_4_ras;
2579                 break;
2580         case IP_VERSION(4, 3, 0):
2581                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2582                         /* unlike other generation of nbio ras,
2583                          * nbio v4_3 only support fatal error interrupt
2584                          * to inform software that DF is freezed due to
2585                          * system fatal error event. driver should not
2586                          * enable nbio ras in such case. Instead,
2587                          * check DF RAS */
2588                         adev->nbio.ras = &nbio_v4_3_ras;
2589                 break;
2590         default:
2591                 /* nbio ras is not available */
2592                 break;
2593         }
2594
2595         /* nbio ras block needs to be enabled ahead of other ras blocks
2596          * to handle fatal error */
2597         r = amdgpu_nbio_ras_sw_init(adev);
2598         if (r)
2599                 return r;
2600
2601         if (adev->nbio.ras &&
2602             adev->nbio.ras->init_ras_controller_interrupt) {
2603                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2604                 if (r)
2605                         goto release_con;
2606         }
2607
2608         if (adev->nbio.ras &&
2609             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2610                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2611                 if (r)
2612                         goto release_con;
2613         }
2614
2615         amdgpu_ras_query_poison_mode(adev);
2616
2617         if (amdgpu_ras_fs_init(adev)) {
2618                 r = -EINVAL;
2619                 goto release_con;
2620         }
2621
2622         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2623                  "hardware ability[%x] ras_mask[%x]\n",
2624                  adev->ras_hw_enabled, adev->ras_enabled);
2625
2626         return 0;
2627 release_con:
2628         amdgpu_ras_set_context(adev, NULL);
2629         kfree(con);
2630
2631         return r;
2632 }
2633
2634 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2635 {
2636         if (adev->gmc.xgmi.connected_to_cpu ||
2637             adev->gmc.is_app_apu)
2638                 return 1;
2639         return 0;
2640 }
2641
2642 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2643                                         struct ras_common_if *ras_block)
2644 {
2645         struct ras_query_if info = {
2646                 .head = *ras_block,
2647         };
2648
2649         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2650                 return 0;
2651
2652         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2653                 DRM_WARN("RAS init harvest failure");
2654
2655         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2656                 DRM_WARN("RAS init harvest reset failure");
2657
2658         return 0;
2659 }
2660
2661 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2662 {
2663        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2664
2665        if (!con)
2666                return false;
2667
2668        return con->poison_supported;
2669 }
2670
2671 /* helper function to handle common stuff in ip late init phase */
2672 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2673                          struct ras_common_if *ras_block)
2674 {
2675         struct amdgpu_ras_block_object *ras_obj = NULL;
2676         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2677         struct ras_query_if *query_info;
2678         unsigned long ue_count, ce_count;
2679         int r;
2680
2681         /* disable RAS feature per IP block if it is not supported */
2682         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2683                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2684                 return 0;
2685         }
2686
2687         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2688         if (r) {
2689                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2690                         /* in resume phase, if fail to enable ras,
2691                          * clean up all ras fs nodes, and disable ras */
2692                         goto cleanup;
2693                 } else
2694                         return r;
2695         }
2696
2697         /* check for errors on warm reset edc persisant supported ASIC */
2698         amdgpu_persistent_edc_harvesting(adev, ras_block);
2699
2700         /* in resume phase, no need to create ras fs node */
2701         if (adev->in_suspend || amdgpu_in_reset(adev))
2702                 return 0;
2703
2704         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2705         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2706             (ras_obj->hw_ops->query_poison_status ||
2707             ras_obj->hw_ops->handle_poison_consumption))) {
2708                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
2709                 if (r)
2710                         goto cleanup;
2711         }
2712
2713         r = amdgpu_ras_sysfs_create(adev, ras_block);
2714         if (r)
2715                 goto interrupt;
2716
2717         /* Those are the cached values at init.
2718          */
2719         query_info = kzalloc(sizeof(struct ras_query_if), GFP_KERNEL);
2720         if (!query_info)
2721                 return -ENOMEM;
2722         memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
2723
2724         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2725                 atomic_set(&con->ras_ce_count, ce_count);
2726                 atomic_set(&con->ras_ue_count, ue_count);
2727         }
2728
2729         kfree(query_info);
2730         return 0;
2731
2732 interrupt:
2733         if (ras_obj->ras_cb)
2734                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2735 cleanup:
2736         amdgpu_ras_feature_enable(adev, ras_block, 0);
2737         return r;
2738 }
2739
2740 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2741                          struct ras_common_if *ras_block)
2742 {
2743         return amdgpu_ras_block_late_init(adev, ras_block);
2744 }
2745
2746 /* helper function to remove ras fs node and interrupt handler */
2747 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2748                           struct ras_common_if *ras_block)
2749 {
2750         struct amdgpu_ras_block_object *ras_obj;
2751         if (!ras_block)
2752                 return;
2753
2754         amdgpu_ras_sysfs_remove(adev, ras_block);
2755
2756         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2757         if (ras_obj->ras_cb)
2758                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2759 }
2760
2761 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2762                           struct ras_common_if *ras_block)
2763 {
2764         return amdgpu_ras_block_late_fini(adev, ras_block);
2765 }
2766
2767 /* do some init work after IP late init as dependence.
2768  * and it runs in resume/gpu reset/booting up cases.
2769  */
2770 void amdgpu_ras_resume(struct amdgpu_device *adev)
2771 {
2772         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2773         struct ras_manager *obj, *tmp;
2774
2775         if (!adev->ras_enabled || !con) {
2776                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2777                 amdgpu_release_ras_context(adev);
2778
2779                 return;
2780         }
2781
2782         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2783                 /* Set up all other IPs which are not implemented. There is a
2784                  * tricky thing that IP's actual ras error type should be
2785                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2786                  * ERROR_NONE make sense anyway.
2787                  */
2788                 amdgpu_ras_enable_all_features(adev, 1);
2789
2790                 /* We enable ras on all hw_supported block, but as boot
2791                  * parameter might disable some of them and one or more IP has
2792                  * not implemented yet. So we disable them on behalf.
2793                  */
2794                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2795                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2796                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2797                                 /* there should be no any reference. */
2798                                 WARN_ON(alive_obj(obj));
2799                         }
2800                 }
2801         }
2802 }
2803
2804 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2805 {
2806         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2807
2808         if (!adev->ras_enabled || !con)
2809                 return;
2810
2811         amdgpu_ras_disable_all_features(adev, 0);
2812         /* Make sure all ras objects are disabled. */
2813         if (con->features)
2814                 amdgpu_ras_disable_all_features(adev, 1);
2815 }
2816
2817 int amdgpu_ras_late_init(struct amdgpu_device *adev)
2818 {
2819         struct amdgpu_ras_block_list *node, *tmp;
2820         struct amdgpu_ras_block_object *obj;
2821         int r;
2822
2823         /* Guest side doesn't need init ras feature */
2824         if (amdgpu_sriov_vf(adev))
2825                 return 0;
2826
2827         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2828                 if (!node->ras_obj) {
2829                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2830                         continue;
2831                 }
2832
2833                 obj = node->ras_obj;
2834                 if (obj->ras_late_init) {
2835                         r = obj->ras_late_init(adev, &obj->ras_comm);
2836                         if (r) {
2837                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2838                                         obj->ras_comm.name, r);
2839                                 return r;
2840                         }
2841                 } else
2842                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
2843         }
2844
2845         return 0;
2846 }
2847
2848 /* do some fini work before IP fini as dependence */
2849 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2850 {
2851         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2852
2853         if (!adev->ras_enabled || !con)
2854                 return 0;
2855
2856
2857         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2858         if (con->features)
2859                 amdgpu_ras_disable_all_features(adev, 0);
2860         amdgpu_ras_recovery_fini(adev);
2861         return 0;
2862 }
2863
2864 int amdgpu_ras_fini(struct amdgpu_device *adev)
2865 {
2866         struct amdgpu_ras_block_list *ras_node, *tmp;
2867         struct amdgpu_ras_block_object *obj = NULL;
2868         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2869
2870         if (!adev->ras_enabled || !con)
2871                 return 0;
2872
2873         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2874                 if (ras_node->ras_obj) {
2875                         obj = ras_node->ras_obj;
2876                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2877                             obj->ras_fini)
2878                                 obj->ras_fini(adev, &obj->ras_comm);
2879                         else
2880                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
2881                 }
2882
2883                 /* Clear ras blocks from ras_list and free ras block list node */
2884                 list_del(&ras_node->node);
2885                 kfree(ras_node);
2886         }
2887
2888         amdgpu_ras_fs_fini(adev);
2889         amdgpu_ras_interrupt_remove_all(adev);
2890
2891         WARN(con->features, "Feature mask is not cleared");
2892
2893         if (con->features)
2894                 amdgpu_ras_disable_all_features(adev, 1);
2895
2896         cancel_delayed_work_sync(&con->ras_counte_delay_work);
2897
2898         amdgpu_ras_set_context(adev, NULL);
2899         kfree(con);
2900
2901         return 0;
2902 }
2903
2904 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2905 {
2906         amdgpu_ras_check_supported(adev);
2907         if (!adev->ras_hw_enabled)
2908                 return;
2909
2910         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2911                 dev_info(adev->dev, "uncorrectable hardware error"
2912                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2913
2914                 amdgpu_ras_reset_gpu(adev);
2915         }
2916 }
2917
2918 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2919 {
2920         if (adev->asic_type == CHIP_VEGA20 &&
2921             adev->pm.fw_version <= 0x283400) {
2922                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2923                                 amdgpu_ras_intr_triggered();
2924         }
2925
2926         return false;
2927 }
2928
2929 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2930 {
2931         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2932
2933         if (!con)
2934                 return;
2935
2936         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2937                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2938                 amdgpu_ras_set_context(adev, NULL);
2939                 kfree(con);
2940         }
2941 }
2942
2943 #ifdef CONFIG_X86_MCE_AMD
2944 static struct amdgpu_device *find_adev(uint32_t node_id)
2945 {
2946         int i;
2947         struct amdgpu_device *adev = NULL;
2948
2949         for (i = 0; i < mce_adev_list.num_gpu; i++) {
2950                 adev = mce_adev_list.devs[i];
2951
2952                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
2953                     adev->gmc.xgmi.physical_node_id == node_id)
2954                         break;
2955                 adev = NULL;
2956         }
2957
2958         return adev;
2959 }
2960
2961 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
2962 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
2963 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
2964 #define GPU_ID_OFFSET           8
2965
2966 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
2967                                     unsigned long val, void *data)
2968 {
2969         struct mce *m = (struct mce *)data;
2970         struct amdgpu_device *adev = NULL;
2971         uint32_t gpu_id = 0;
2972         uint32_t umc_inst = 0, ch_inst = 0;
2973
2974         /*
2975          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
2976          * and error occurred in DramECC (Extended error code = 0) then only
2977          * process the error, else bail out.
2978          */
2979         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
2980                     (XEC(m->status, 0x3f) == 0x0)))
2981                 return NOTIFY_DONE;
2982
2983         /*
2984          * If it is correctable error, return.
2985          */
2986         if (mce_is_correctable(m))
2987                 return NOTIFY_OK;
2988
2989         /*
2990          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
2991          */
2992         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
2993
2994         adev = find_adev(gpu_id);
2995         if (!adev) {
2996                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
2997                                                                 gpu_id);
2998                 return NOTIFY_DONE;
2999         }
3000
3001         /*
3002          * If it is uncorrectable error, then find out UMC instance and
3003          * channel index.
3004          */
3005         umc_inst = GET_UMC_INST(m->ipid);
3006         ch_inst = GET_CHAN_INDEX(m->ipid);
3007
3008         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3009                              umc_inst, ch_inst);
3010
3011         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3012                 return NOTIFY_OK;
3013         else
3014                 return NOTIFY_DONE;
3015 }
3016
3017 static struct notifier_block amdgpu_bad_page_nb = {
3018         .notifier_call  = amdgpu_bad_page_notifier,
3019         .priority       = MCE_PRIO_UC,
3020 };
3021
3022 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3023 {
3024         /*
3025          * Add the adev to the mce_adev_list.
3026          * During mode2 reset, amdgpu device is temporarily
3027          * removed from the mgpu_info list which can cause
3028          * page retirement to fail.
3029          * Use this list instead of mgpu_info to find the amdgpu
3030          * device on which the UMC error was reported.
3031          */
3032         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3033
3034         /*
3035          * Register the x86 notifier only once
3036          * with MCE subsystem.
3037          */
3038         if (notifier_registered == false) {
3039                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3040                 notifier_registered = true;
3041         }
3042 }
3043 #endif
3044
3045 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3046 {
3047         if (!adev)
3048                 return NULL;
3049
3050         return adev->psp.ras_context.ras;
3051 }
3052
3053 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3054 {
3055         if (!adev)
3056                 return -EINVAL;
3057
3058         adev->psp.ras_context.ras = ras_con;
3059         return 0;
3060 }
3061
3062 /* check if ras is supported on block, say, sdma, gfx */
3063 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3064                 unsigned int block)
3065 {
3066         int ret = 0;
3067         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3068
3069         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3070                 return 0;
3071
3072         ret = ras && (adev->ras_enabled & (1 << block));
3073
3074         /* For the special asic with mem ecc enabled but sram ecc
3075          * not enabled, even if the ras block is not supported on
3076          * .ras_enabled, if the asic supports poison mode and the
3077          * ras block has ras configuration, it can be considered
3078          * that the ras block supports ras function.
3079          */
3080         if (!ret &&
3081             amdgpu_ras_is_poison_mode_supported(adev) &&
3082             amdgpu_ras_get_ras_block(adev, block, 0))
3083                 ret = 1;
3084
3085         return ret;
3086 }
3087
3088 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3089 {
3090         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3091
3092         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3093                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3094         return 0;
3095 }
3096
3097
3098 /* Register each ip ras block into amdgpu ras */
3099 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3100                 struct amdgpu_ras_block_object *ras_block_obj)
3101 {
3102         struct amdgpu_ras_block_list *ras_node;
3103         if (!adev || !ras_block_obj)
3104                 return -EINVAL;
3105
3106         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3107         if (!ras_node)
3108                 return -ENOMEM;
3109
3110         INIT_LIST_HEAD(&ras_node->node);
3111         ras_node->ras_obj = ras_block_obj;
3112         list_add_tail(&ras_node->node, &adev->ras_list);
3113
3114         return 0;
3115 }
3116
3117 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3118 {
3119         if (!err_type_name)
3120                 return;
3121
3122         switch (err_type) {
3123         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3124                 sprintf(err_type_name, "correctable");
3125                 break;
3126         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3127                 sprintf(err_type_name, "uncorrectable");
3128                 break;
3129         default:
3130                 sprintf(err_type_name, "unknown");
3131                 break;
3132         }
3133 }
3134
3135 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3136                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3137                                          uint32_t instance,
3138                                          uint32_t *memory_id)
3139 {
3140         uint32_t err_status_lo_data, err_status_lo_offset;
3141
3142         if (!reg_entry)
3143                 return false;
3144
3145         err_status_lo_offset =
3146                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3147                                             reg_entry->seg_lo, reg_entry->reg_lo);
3148         err_status_lo_data = RREG32(err_status_lo_offset);
3149
3150         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3151             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3152                 return false;
3153
3154         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3155
3156         return true;
3157 }
3158
3159 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3160                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3161                                        uint32_t instance,
3162                                        unsigned long *err_cnt)
3163 {
3164         uint32_t err_status_hi_data, err_status_hi_offset;
3165
3166         if (!reg_entry)
3167                 return false;
3168
3169         err_status_hi_offset =
3170                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3171                                             reg_entry->seg_hi, reg_entry->reg_hi);
3172         err_status_hi_data = RREG32(err_status_hi_offset);
3173
3174         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3175             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3176                 /* keep the check here in case we need to refer to the result later */
3177                 dev_dbg(adev->dev, "Invalid err_info field\n");
3178
3179         /* read err count */
3180         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3181
3182         return true;
3183 }
3184
3185 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3186                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3187                                            uint32_t reg_list_size,
3188                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3189                                            uint32_t mem_list_size,
3190                                            uint32_t instance,
3191                                            uint32_t err_type,
3192                                            unsigned long *err_count)
3193 {
3194         uint32_t memory_id;
3195         unsigned long err_cnt;
3196         char err_type_name[16];
3197         uint32_t i, j;
3198
3199         for (i = 0; i < reg_list_size; i++) {
3200                 /* query memory_id from err_status_lo */
3201                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3202                                                          instance, &memory_id))
3203                         continue;
3204
3205                 /* query err_cnt from err_status_hi */
3206                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3207                                                        instance, &err_cnt) ||
3208                     !err_cnt)
3209                         continue;
3210
3211                 *err_count += err_cnt;
3212
3213                 /* log the errors */
3214                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3215                 if (!mem_list) {
3216                         /* memory_list is not supported */
3217                         dev_info(adev->dev,
3218                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3219                                  err_cnt, err_type_name,
3220                                  reg_list[i].block_name,
3221                                  instance, memory_id);
3222                 } else {
3223                         for (j = 0; j < mem_list_size; j++) {
3224                                 if (memory_id == mem_list[j].memory_id) {
3225                                         dev_info(adev->dev,
3226                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3227                                                  err_cnt, err_type_name,
3228                                                  reg_list[i].block_name,
3229                                                  instance, mem_list[j].name);
3230                                         break;
3231                                 }
3232                         }
3233                 }
3234         }
3235 }
3236
3237 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3238                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3239                                            uint32_t reg_list_size,
3240                                            uint32_t instance)
3241 {
3242         uint32_t err_status_lo_offset, err_status_hi_offset;
3243         uint32_t i;
3244
3245         for (i = 0; i < reg_list_size; i++) {
3246                 err_status_lo_offset =
3247                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3248                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3249                 err_status_hi_offset =
3250                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3251                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3252                 WREG32(err_status_lo_offset, 0);
3253                 WREG32(err_status_hi_offset, 0);
3254         }
3255 }