drivers/gpu/drm/i915/display/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <[email protected]>
  24  */
  25
  26 #include <linux/dmi.h>
  27 #include <linux/slab.h>
  28
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_crtc.h>
  31 #include <drm/drm_edid.h>
  32 #include <drm/drm_mipi_dsi.h>
  33
  34 #include "i915_drv.h"
  35 #include "i915_reg.h"
  36 #include "intel_atomic.h"
  37 #include "intel_backlight.h"
  38 #include "intel_connector.h"
  39 #include "intel_crtc.h"
  40 #include "intel_de.h"
  41 #include "intel_display_types.h"
  42 #include "intel_dsi.h"
  43 #include "intel_dsi_vbt.h"
  44 #include "intel_fifo_underrun.h"
  45 #include "intel_panel.h"
  46 #include "skl_scaler.h"
  47 #include "vlv_dsi.h"
  48 #include "vlv_dsi_pll.h"
  49 #include "vlv_dsi_regs.h"
  50 #include "vlv_sideband.h"
  51
  52 /* return pixels in terms of txbyteclkhs */
  53 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  54                        u16 burst_mode_ratio)
  55 {
  56         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  57                                          8 * 100), lane_count);
  58 }
  59
  60 /* return pixels equvalent to txbyteclkhs */
  61 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  62                         u16 burst_mode_ratio)
  63 {
  64         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  65                                                 (bpp * burst_mode_ratio));
  66 }
  67
  68 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  69 {
  70         /* It just so happens the VBT matches register contents. */
  71         switch (fmt) {
  72         case VID_MODE_FORMAT_RGB888:
  73                 return MIPI_DSI_FMT_RGB888;
  74         case VID_MODE_FORMAT_RGB666:
  75                 return MIPI_DSI_FMT_RGB666;
  76         case VID_MODE_FORMAT_RGB666_PACKED:
  77                 return MIPI_DSI_FMT_RGB666_PACKED;
  78         case VID_MODE_FORMAT_RGB565:
  79                 return MIPI_DSI_FMT_RGB565;
  80         default:
  81                 MISSING_CASE(fmt);
  82                 return MIPI_DSI_FMT_RGB666;
  83         }
  84 }
  85
  86 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  87 {
  88         struct drm_encoder *encoder = &intel_dsi->base.base;
  89         struct drm_device *dev = encoder->dev;
  90         struct drm_i915_private *dev_priv = to_i915(dev);
  91         u32 mask;
  92
  93         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  94                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  95
  96         if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
  97                                   mask, 100))
  98                 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
  99 }
 100
 101 static void write_data(struct drm_i915_private *dev_priv,
 102                        i915_reg_t reg,
 103                        const u8 *data, u32 len)
 104 {
 105         u32 i, j;
 106
 107         for (i = 0; i < len; i += 4) {
 108                 u32 val = 0;
 109
 110                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 111                         val |= *data++ << 8 * j;
 112
 113                 intel_de_write(dev_priv, reg, val);
 114         }
 115 }
 116
 117 static void read_data(struct drm_i915_private *dev_priv,
 118                       i915_reg_t reg,
 119                       u8 *data, u32 len)
 120 {
 121         u32 i, j;
 122
 123         for (i = 0; i < len; i += 4) {
 124                 u32 val = intel_de_read(dev_priv, reg);
 125
 126                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 127                         *data++ = val >> 8 * j;
 128         }
 129 }
 130
 131 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 132                                        const struct mipi_dsi_msg *msg)
 133 {
 134         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 135         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 136         struct drm_i915_private *dev_priv = to_i915(dev);
 137         enum port port = intel_dsi_host->port;
 138         struct mipi_dsi_packet packet;
 139         ssize_t ret;
 140         const u8 *header;
 141         i915_reg_t data_reg, ctrl_reg;
 142         u32 data_mask, ctrl_mask;
 143
 144         ret = mipi_dsi_create_packet(&packet, msg);
 145         if (ret < 0)
 146                 return ret;
 147
 148         header = packet.header;
 149
 150         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 151                 data_reg = MIPI_LP_GEN_DATA(port);
 152                 data_mask = LP_DATA_FIFO_FULL;
 153                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 154                 ctrl_mask = LP_CTRL_FIFO_FULL;
 155         } else {
 156                 data_reg = MIPI_HS_GEN_DATA(port);
 157                 data_mask = HS_DATA_FIFO_FULL;
 158                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 159                 ctrl_mask = HS_CTRL_FIFO_FULL;
 160         }
 161
 162         /* note: this is never true for reads */
 163         if (packet.payload_length) {
 164                 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 165                                             data_mask, 50))
 166                         drm_err(&dev_priv->drm,
 167                                 "Timeout waiting for HS/LP DATA FIFO !full\n");
 168
 169                 write_data(dev_priv, data_reg, packet.payload,
 170                            packet.payload_length);
 171         }
 172
 173         if (msg->rx_len) {
 174                 intel_de_write(dev_priv, MIPI_INTR_STAT(port),
 175                                GEN_READ_DATA_AVAIL);
 176         }
 177
 178         if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
 179                                     ctrl_mask, 50)) {
 180                 drm_err(&dev_priv->drm,
 181                         "Timeout waiting for HS/LP CTRL FIFO !full\n");
 182         }
 183
 184         intel_de_write(dev_priv, ctrl_reg,
 185                        header[2] << 16 | header[1] << 8 | header[0]);
 186
 187         /* ->rx_len is set only for reads */
 188         if (msg->rx_len) {
 189                 data_mask = GEN_READ_DATA_AVAIL;
 190                 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
 191                                           data_mask, 50))
 192                         drm_err(&dev_priv->drm,
 193                                 "Timeout waiting for read data.\n");
 194
 195                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 196         }
 197
 198         /* XXX: fix for reads and writes */
 199         return 4 + packet.payload_length;
 200 }
 201
 202 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 203                                  struct mipi_dsi_device *dsi)
 204 {
 205         return 0;
 206 }
 207
 208 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 209                                  struct mipi_dsi_device *dsi)
 210 {
 211         return 0;
 212 }
 213
 214 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 215         .attach = intel_dsi_host_attach,
 216         .detach = intel_dsi_host_detach,
 217         .transfer = intel_dsi_host_transfer,
 218 };
 219
 220 /*
 221  * send a video mode command
 222  *
 223  * XXX: commands with data in MIPI_DPI_DATA?
 224  */
 225 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 226                         enum port port)
 227 {
 228         struct drm_encoder *encoder = &intel_dsi->base.base;
 229         struct drm_device *dev = encoder->dev;
 230         struct drm_i915_private *dev_priv = to_i915(dev);
 231         u32 mask;
 232
 233         /* XXX: pipe, hs */
 234         if (hs)
 235                 cmd &= ~DPI_LP_MODE;
 236         else
 237                 cmd |= DPI_LP_MODE;
 238
 239         /* clear bit */
 240         intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 241
 242         /* XXX: old code skips write if control unchanged */
 243         if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
 244                 drm_dbg_kms(&dev_priv->drm,
 245                             "Same special packet %02x twice in a row.\n", cmd);
 246
 247         intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
 248
 249         mask = SPL_PKT_SENT_INTERRUPT;
 250         if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
 251                 drm_err(&dev_priv->drm,
 252                         "Video mode command 0x%08x send failed.\n", cmd);
 253
 254         return 0;
 255 }
 256
 257 static void band_gap_reset(struct drm_i915_private *dev_priv)
 258 {
 259         vlv_flisdsi_get(dev_priv);
 260
 261         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 262         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 263         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 264         udelay(150);
 265         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 266         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 267
 268         vlv_flisdsi_put(dev_priv);
 269 }
 270
 271 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 272                                     struct intel_crtc_state *pipe_config,
 273                                     struct drm_connector_state *conn_state)
 274 {
 275         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 276         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 277                                                    base);
 278         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 279         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 280         int ret;
 281
 282         drm_dbg_kms(&dev_priv->drm, "\n");
 283         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 284         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 285
 286         ret = intel_panel_compute_config(intel_connector, adjusted_mode);
 287         if (ret)
 288                 return ret;
 289
 290         ret = intel_panel_fitting(pipe_config, conn_state);
 291         if (ret)
 292                 return ret;
 293
 294         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 295                 return -EINVAL;
 296
 297         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 298         adjusted_mode->flags = 0;
 299
 300         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 301                 pipe_config->pipe_bpp = 24;
 302         else
 303                 pipe_config->pipe_bpp = 18;
 304
 305         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 306                 /* Enable Frame time stamp based scanline reporting */
 307                 pipe_config->mode_flags |=
 308                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 309
 310                 /* Dual link goes to DSI transcoder A. */
 311                 if (intel_dsi->ports == BIT(PORT_C))
 312                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 313                 else
 314                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 315
 316                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 317                 if (ret)
 318                         return -EINVAL;
 319         } else {
 320                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 321                 if (ret)
 322                         return -EINVAL;
 323         }
 324
 325         pipe_config->clock_set = true;
 326
 327         return 0;
 328 }
 329
 330 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 331 {
 332         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 333         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 334         enum port port;
 335         bool cold_boot = false;
 336
 337         /* Set the MIPI mode
 338          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 339          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 340          */
 341         for_each_dsi_port(port, intel_dsi->ports)
 342                 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE);
 343
 344         /* Put the IO into reset */
 345         intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
 346
 347         /* Program LP Wake */
 348         for_each_dsi_port(port, intel_dsi->ports) {
 349                 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 350                 intel_de_rmw(dev_priv, MIPI_CTRL(port),
 351                              GLK_LP_WAKE, (tmp & DEVICE_READY) ? GLK_LP_WAKE : 0);
 352         }
 353
 354         /* Wait for Pwr ACK */
 355         for_each_dsi_port(port, intel_dsi->ports) {
 356                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 357                                           GLK_MIPIIO_PORT_POWERED, 20))
 358                         drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
 359         }
 360
 361         /* Check for cold boot scenario */
 362         for_each_dsi_port(port, intel_dsi->ports) {
 363                 cold_boot |=
 364                         !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY);
 365         }
 366
 367         return cold_boot;
 368 }
 369
 370 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 371 {
 372         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 373         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 374         enum port port;
 375
 376         /* Wait for MIPI PHY status bit to set */
 377         for_each_dsi_port(port, intel_dsi->ports) {
 378                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 379                                           GLK_PHY_STATUS_PORT_READY, 20))
 380                         drm_err(&dev_priv->drm, "PHY is not ON\n");
 381         }
 382
 383         /* Get IO out of reset */
 384         intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED);
 385
 386         /* Get IO out of Low power state*/
 387         for_each_dsi_port(port, intel_dsi->ports) {
 388                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 389                         intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 390                                      ULPS_STATE_MASK, DEVICE_READY);
 391                         usleep_range(10, 15);
 392                 } else {
 393                         /* Enter ULPS */
 394                         intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 395                                      ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
 396
 397                         /* Wait for ULPS active */
 398                         if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 399                                                     GLK_ULPS_NOT_ACTIVE, 20))
 400                                 drm_err(&dev_priv->drm, "ULPS not active\n");
 401
 402                         /* Exit ULPS */
 403                         intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 404                                      ULPS_STATE_MASK, ULPS_STATE_EXIT | DEVICE_READY);
 405
 406                         /* Enter Normal Mode */
 407                         intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 408                                      ULPS_STATE_MASK,
 409                                      ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 410
 411                         intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0);
 412                 }
 413         }
 414
 415         /* Wait for Stop state */
 416         for_each_dsi_port(port, intel_dsi->ports) {
 417                 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
 418                                           GLK_DATA_LANE_STOP_STATE, 20))
 419                         drm_err(&dev_priv->drm,
 420                                 "Date lane not in STOP state\n");
 421         }
 422
 423         /* Wait for AFE LATCH */
 424         for_each_dsi_port(port, intel_dsi->ports) {
 425                 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
 426                                           AFE_LATCHOUT, 20))
 427                         drm_err(&dev_priv->drm,
 428                                 "D-PHY not entering LP-11 state\n");
 429         }
 430 }
 431
 432 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 433 {
 434         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 435         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 436         enum port port;
 437         u32 val;
 438
 439         drm_dbg_kms(&dev_priv->drm, "\n");
 440
 441         /* Enable MIPI PHY transparent latch */
 442         for_each_dsi_port(port, intel_dsi->ports) {
 443                 intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD);
 444                 usleep_range(2000, 2500);
 445         }
 446
 447         /* Clear ULPS and set device ready */
 448         for_each_dsi_port(port, intel_dsi->ports) {
 449                 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
 450                 val &= ~ULPS_STATE_MASK;
 451                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 452                 usleep_range(2000, 2500);
 453                 val |= DEVICE_READY;
 454                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val);
 455         }
 456 }
 457
 458 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 459 {
 460         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 461         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 462         enum port port;
 463
 464         drm_dbg_kms(&dev_priv->drm, "\n");
 465
 466         vlv_flisdsi_get(dev_priv);
 467         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 468          * needed everytime after power gate */
 469         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 470         vlv_flisdsi_put(dev_priv);
 471
 472         /* bandgap reset is needed after everytime we do power gate */
 473         band_gap_reset(dev_priv);
 474
 475         for_each_dsi_port(port, intel_dsi->ports) {
 476
 477                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 478                                ULPS_STATE_ENTER);
 479                 usleep_range(2500, 3000);
 480
 481                 /* Enable MIPI PHY transparent latch
 482                  * Common bit for both MIPI Port A & MIPI Port C
 483                  * No similar bit in MIPI Port C reg
 484                  */
 485                 intel_de_rmw(dev_priv, MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD);
 486                 usleep_range(1000, 1500);
 487
 488                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 489                                ULPS_STATE_EXIT);
 490                 usleep_range(2500, 3000);
 491
 492                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 493                                DEVICE_READY);
 494                 usleep_range(2500, 3000);
 495         }
 496 }
 497
 498 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 499 {
 500         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 501
 502         if (IS_GEMINILAKE(dev_priv))
 503                 glk_dsi_device_ready(encoder);
 504         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 505                 bxt_dsi_device_ready(encoder);
 506         else
 507                 vlv_dsi_device_ready(encoder);
 508 }
 509
 510 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 511 {
 512         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 513         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 514         enum port port;
 515
 516         /* Enter ULPS */
 517         for_each_dsi_port(port, intel_dsi->ports)
 518                 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port),
 519                              ULPS_STATE_MASK, ULPS_STATE_ENTER | DEVICE_READY);
 520
 521         /* Wait for MIPI PHY status bit to unset */
 522         for_each_dsi_port(port, intel_dsi->ports) {
 523                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 524                                             GLK_PHY_STATUS_PORT_READY, 20))
 525                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 526         }
 527
 528         /* Wait for Pwr ACK bit to unset */
 529         for_each_dsi_port(port, intel_dsi->ports) {
 530                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 531                                             GLK_MIPIIO_PORT_POWERED, 20))
 532                         drm_err(&dev_priv->drm,
 533                                 "MIPI IO Port is not powergated\n");
 534         }
 535 }
 536
 537 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 538 {
 539         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 540         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 541         enum port port;
 542
 543         /* Put the IO into reset */
 544         intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0);
 545
 546         /* Wait for MIPI PHY status bit to unset */
 547         for_each_dsi_port(port, intel_dsi->ports) {
 548                 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
 549                                             GLK_PHY_STATUS_PORT_READY, 20))
 550                         drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
 551         }
 552
 553         /* Clear MIPI mode */
 554         for_each_dsi_port(port, intel_dsi->ports)
 555                 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_ENABLE, 0);
 556 }
 557
 558 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 559 {
 560         glk_dsi_enter_low_power_mode(encoder);
 561         glk_dsi_disable_mipi_io(encoder);
 562 }
 563
 564 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 565 {
 566         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 567         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 568         enum port port;
 569
 570         drm_dbg_kms(&dev_priv->drm, "\n");
 571         for_each_dsi_port(port, intel_dsi->ports) {
 572                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 573                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 574                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 575
 576                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 577                                DEVICE_READY | ULPS_STATE_ENTER);
 578                 usleep_range(2000, 2500);
 579
 580                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 581                                DEVICE_READY | ULPS_STATE_EXIT);
 582                 usleep_range(2000, 2500);
 583
 584                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port),
 585                                DEVICE_READY | ULPS_STATE_ENTER);
 586                 usleep_range(2000, 2500);
 587
 588                 /*
 589                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 590                  * Port A only. MIPI Port C has no similar bit for checking.
 591                  */
 592                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || port == PORT_A) &&
 593                     intel_de_wait_for_clear(dev_priv, port_ctrl,
 594                                             AFE_LATCHOUT, 30))
 595                         drm_err(&dev_priv->drm, "DSI LP not going Low\n");
 596
 597                 /* Disable MIPI PHY transparent latch */
 598                 intel_de_rmw(dev_priv, port_ctrl, LP_OUTPUT_HOLD, 0);
 599                 usleep_range(1000, 1500);
 600
 601                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00);
 602                 usleep_range(2000, 2500);
 603         }
 604 }
 605
 606 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 607                                   const struct intel_crtc_state *crtc_state)
 608 {
 609         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 610         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 611         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 612         enum port port;
 613
 614         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 615                 u32 temp = intel_dsi->pixel_overlap;
 616
 617                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 618                         for_each_dsi_port(port, intel_dsi->ports)
 619                                 intel_de_rmw(dev_priv, MIPI_CTRL(port),
 620                                              BXT_PIXEL_OVERLAP_CNT_MASK,
 621                                              temp << BXT_PIXEL_OVERLAP_CNT_SHIFT);
 622                 } else {
 623                         intel_de_rmw(dev_priv, VLV_CHICKEN_3,
 624                                      PIXEL_OVERLAP_CNT_MASK,
 625                                      temp << PIXEL_OVERLAP_CNT_SHIFT);
 626                 }
 627         }
 628
 629         for_each_dsi_port(port, intel_dsi->ports) {
 630                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 631                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 632                 u32 temp;
 633
 634                 temp = intel_de_read(dev_priv, port_ctrl);
 635
 636                 temp &= ~LANE_CONFIGURATION_MASK;
 637                 temp &= ~DUAL_LINK_MODE_MASK;
 638
 639                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 640                         temp |= (intel_dsi->dual_link - 1)
 641                                                 << DUAL_LINK_MODE_SHIFT;
 642                         if (IS_BROXTON(dev_priv))
 643                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 644                         else
 645                                 temp |= crtc->pipe ?
 646                                         LANE_CONFIGURATION_DUAL_LINK_B :
 647                                         LANE_CONFIGURATION_DUAL_LINK_A;
 648                 }
 649
 650                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 651                         temp |= DITHERING_ENABLE;
 652
 653                 /* assert ip_tg_enable signal */
 654                 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE);
 655                 intel_de_posting_read(dev_priv, port_ctrl);
 656         }
 657 }
 658
 659 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 660 {
 661         struct drm_device *dev = encoder->base.dev;
 662         struct drm_i915_private *dev_priv = to_i915(dev);
 663         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 664         enum port port;
 665
 666         for_each_dsi_port(port, intel_dsi->ports) {
 667                 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 668                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 669
 670                 /* de-assert ip_tg_enable signal */
 671                 intel_de_rmw(dev_priv, port_ctrl, DPI_ENABLE, 0);
 672                 intel_de_posting_read(dev_priv, port_ctrl);
 673         }
 674 }
 675 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 676                               const struct intel_crtc_state *pipe_config);
 677 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 678
 679 /*
 680  * Panel enable/disable sequences from the VBT spec.
 681  *
 682  * Note the spec has AssertReset / DeassertReset swapped from their
 683  * usual naming. We use the normal names to avoid confusion (so below
 684  * they are swapped compared to the spec).
 685  *
 686  * Steps starting with MIPI refer to VBT sequences, note that for v2
 687  * VBTs several steps which have a VBT in v2 are expected to be handled
 688  * directly by the driver, by directly driving gpios for example.
 689  *
 690  * v2 video mode seq         v3 video mode seq         command mode seq
 691  * - power on                - MIPIPanelPowerOn        - power on
 692  * - wait t1+t2                                        - wait t1+t2
 693  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 694  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 695  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 696  *                                                     - MIPITearOn
 697  *                                                     - MIPIDisplayOn
 698  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 699  * - MIPIDisplayOn           - MIPIDisplayOn
 700  * - wait t5                                           - wait t5
 701  * - backlight on            - MIPIBacklightOn         - backlight on
 702  * ...                       ...                       ... issue mem cmds ...
 703  * - backlight off           - MIPIBacklightOff        - backlight off
 704  * - wait t6                                           - wait t6
 705  * - MIPIDisplayOff
 706  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 707  *                                                     - MIPITearOff
 708  *                           - MIPIDisplayOff          - MIPIDisplayOff
 709  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 710  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 711  * - wait t3                                           - wait t3
 712  * - power off               - MIPIPanelPowerOff       - power off
 713  * - wait t4                                           - wait t4
 714  */
 715
 716 /*
 717  * DSI port enable has to be done before pipe and plane enable, so we do it in
 718  * the pre_enable hook instead of the enable hook.
 719  */
 720 static void intel_dsi_pre_enable(struct intel_atomic_state *state,
 721                                  struct intel_encoder *encoder,
 722                                  const struct intel_crtc_state *pipe_config,
 723                                  const struct drm_connector_state *conn_state)
 724 {
 725         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 726         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 727         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 728         enum pipe pipe = crtc->pipe;
 729         enum port port;
 730         bool glk_cold_boot = false;
 731
 732         drm_dbg_kms(&dev_priv->drm, "\n");
 733
 734         intel_dsi_wait_panel_power_cycle(intel_dsi);
 735
 736         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 737
 738         /*
 739          * The BIOS may leave the PLL in a wonky state where it doesn't
 740          * lock. It needs to be fully powered down to fix it.
 741          */
 742         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 743                 bxt_dsi_pll_disable(encoder);
 744                 bxt_dsi_pll_enable(encoder, pipe_config);
 745         } else {
 746                 vlv_dsi_pll_disable(encoder);
 747                 vlv_dsi_pll_enable(encoder, pipe_config);
 748         }
 749
 750         if (IS_BROXTON(dev_priv)) {
 751                 /* Add MIPI IO reset programming for modeset */
 752                 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, MIPIO_RST_CTRL);
 753
 754                 /* Power up DSI regulator */
 755                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 756                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 757         }
 758
 759         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 760                 /* Disable DPOunit clock gating, can stall pipe */
 761                 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
 762                              0, DPOUNIT_CLOCK_GATE_DISABLE);
 763         }
 764
 765         if (!IS_GEMINILAKE(dev_priv))
 766                 intel_dsi_prepare(encoder, pipe_config);
 767
 768         /* Give the panel time to power-on and then deassert its reset */
 769         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 770         msleep(intel_dsi->panel_on_delay);
 771         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 772
 773         if (IS_GEMINILAKE(dev_priv)) {
 774                 glk_cold_boot = glk_dsi_enable_io(encoder);
 775
 776                 /* Prepare port in cold boot(s3/s4) scenario */
 777                 if (glk_cold_boot)
 778                         intel_dsi_prepare(encoder, pipe_config);
 779         }
 780
 781         /* Put device in ready state (LP-11) */
 782         intel_dsi_device_ready(encoder);
 783
 784         /* Prepare port in normal boot scenario */
 785         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 786                 intel_dsi_prepare(encoder, pipe_config);
 787
 788         /* Send initialization commands in LP mode */
 789         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 790
 791         /*
 792          * Enable port in pre-enable phase itself because as per hw team
 793          * recommendation, port should be enabled before plane & pipe
 794          */
 795         if (is_cmd_mode(intel_dsi)) {
 796                 for_each_dsi_port(port, intel_dsi->ports)
 797                         intel_de_write(dev_priv,
 798                                        MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 799                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 800                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 801         } else {
 802                 msleep(20); /* XXX */
 803                 for_each_dsi_port(port, intel_dsi->ports)
 804                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 805                 msleep(100);
 806
 807                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 808
 809                 intel_dsi_port_enable(encoder, pipe_config);
 810         }
 811
 812         intel_backlight_enable(pipe_config, conn_state);
 813         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 814 }
 815
 816 static void bxt_dsi_enable(struct intel_atomic_state *state,
 817                            struct intel_encoder *encoder,
 818                            const struct intel_crtc_state *crtc_state,
 819                            const struct drm_connector_state *conn_state)
 820 {
 821         intel_crtc_vblank_on(crtc_state);
 822 }
 823
 824 /*
 825  * DSI port disable has to be done after pipe and plane disable, so we do it in
 826  * the post_disable hook.
 827  */
 828 static void intel_dsi_disable(struct intel_atomic_state *state,
 829                               struct intel_encoder *encoder,
 830                               const struct intel_crtc_state *old_crtc_state,
 831                               const struct drm_connector_state *old_conn_state)
 832 {
 833         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 834         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 835         enum port port;
 836
 837         drm_dbg_kms(&i915->drm, "\n");
 838
 839         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 840         intel_backlight_disable(old_conn_state);
 841
 842         /*
 843          * According to the spec we should send SHUTDOWN before
 844          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 845          * has shown that the v3 sequence works for v2 VBTs too
 846          */
 847         if (is_vid_mode(intel_dsi)) {
 848                 /* Send Shutdown command to the panel in LP mode */
 849                 for_each_dsi_port(port, intel_dsi->ports)
 850                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 851                 msleep(10);
 852         }
 853 }
 854
 855 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 856 {
 857         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 858
 859         if (IS_GEMINILAKE(dev_priv))
 860                 glk_dsi_clear_device_ready(encoder);
 861         else
 862                 vlv_dsi_clear_device_ready(encoder);
 863 }
 864
 865 static void intel_dsi_post_disable(struct intel_atomic_state *state,
 866                                    struct intel_encoder *encoder,
 867                                    const struct intel_crtc_state *old_crtc_state,
 868                                    const struct drm_connector_state *old_conn_state)
 869 {
 870         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 871         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 872         enum port port;
 873
 874         drm_dbg_kms(&dev_priv->drm, "\n");
 875
 876         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 877                 intel_crtc_vblank_off(old_crtc_state);
 878
 879                 skl_scaler_disable(old_crtc_state);
 880         }
 881
 882         if (is_vid_mode(intel_dsi)) {
 883                 for_each_dsi_port(port, intel_dsi->ports)
 884                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 885
 886                 intel_dsi_port_disable(encoder);
 887                 usleep_range(2000, 5000);
 888         }
 889
 890         intel_dsi_unprepare(encoder);
 891
 892         /*
 893          * if disable packets are sent before sending shutdown packet then in
 894          * some next enable sequence send turn on packet error is observed
 895          */
 896         if (is_cmd_mode(intel_dsi))
 897                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 898         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 899
 900         /* Transition to LP-00 */
 901         intel_dsi_clear_device_ready(encoder);
 902
 903         if (IS_BROXTON(dev_priv)) {
 904                 /* Power down DSI regulator to save power */
 905                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 906                 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL,
 907                                HS_IO_CTRL_SELECT);
 908
 909                 /* Add MIPI IO reset programming for modeset */
 910                 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, MIPIO_RST_CTRL, 0);
 911         }
 912
 913         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 914                 bxt_dsi_pll_disable(encoder);
 915         } else {
 916                 vlv_dsi_pll_disable(encoder);
 917
 918                 intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv),
 919                              DPOUNIT_CLOCK_GATE_DISABLE, 0);
 920         }
 921
 922         /* Assert reset */
 923         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 924
 925         msleep(intel_dsi->panel_off_delay);
 926         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 927
 928         intel_dsi->panel_power_off_time = ktime_get_boottime();
 929 }
 930
 931 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 932                                    enum pipe *pipe)
 933 {
 934         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 935         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 936         intel_wakeref_t wakeref;
 937         enum port port;
 938         bool active = false;
 939
 940         drm_dbg_kms(&dev_priv->drm, "\n");
 941
 942         wakeref = intel_display_power_get_if_enabled(dev_priv,
 943                                                      encoder->power_domain);
 944         if (!wakeref)
 945                 return false;
 946
 947         /*
 948          * On Broxton the PLL needs to be enabled with a valid divider
 949          * configuration, otherwise accessing DSI registers will hang the
 950          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 951          */
 952         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
 953             !bxt_dsi_pll_is_enabled(dev_priv))
 954                 goto out_put_power;
 955
 956         /* XXX: this only works for one DSI output */
 957         for_each_dsi_port(port, intel_dsi->ports) {
 958                 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) ?
 959                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 960                 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE;
 961
 962                 /*
 963                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 964                  * bit in port C control register does not get set. As a
 965                  * workaround, check pipe B conf instead.
 966                  */
 967                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 968                     port == PORT_C)
 969                         enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
 970
 971                 /* Try command mode if video mode not enabled */
 972                 if (!enabled) {
 973                         u32 tmp = intel_de_read(dev_priv,
 974                                                 MIPI_DSI_FUNC_PRG(port));
 975                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
 976                 }
 977
 978                 if (!enabled)
 979                         continue;
 980
 981                 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY))
 982                         continue;
 983
 984                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 985                         u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
 986                         tmp &= BXT_PIPE_SELECT_MASK;
 987                         tmp >>= BXT_PIPE_SELECT_SHIFT;
 988
 989                         if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C))
 990                                 continue;
 991
 992                         *pipe = tmp;
 993                 } else {
 994                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
 995                 }
 996
 997                 active = true;
 998                 break;
 999         }
1000
1001 out_put_power:
1002         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1003
1004         return active;
1005 }
1006
1007 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1008                                     struct intel_crtc_state *pipe_config)
1009 {
1010         struct drm_device *dev = encoder->base.dev;
1011         struct drm_i915_private *dev_priv = to_i915(dev);
1012         struct drm_display_mode *adjusted_mode =
1013                                         &pipe_config->hw.adjusted_mode;
1014         struct drm_display_mode *adjusted_mode_sw;
1015         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1016         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1017         unsigned int lane_count = intel_dsi->lane_count;
1018         unsigned int bpp, fmt;
1019         enum port port;
1020         u16 hactive, hfp, hsync, hbp, vfp, vsync;
1021         u16 hfp_sw, hsync_sw, hbp_sw;
1022         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1023                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1024
1025         /* FIXME: hw readout should not depend on SW state */
1026         adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1027
1028         /*
1029          * Atleast one port is active as encoder->get_config called only if
1030          * encoder->get_hw_state() returns true.
1031          */
1032         for_each_dsi_port(port, intel_dsi->ports) {
1033                 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1034                         break;
1035         }
1036
1037         fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1038         bpp = mipi_dsi_pixel_format_to_bpp(
1039                         pixel_format_from_register_bits(fmt));
1040
1041         pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1042
1043         /* Enable Frame time stamo based scanline reporting */
1044         pipe_config->mode_flags |=
1045                 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1046
1047         /* In terms of pixels */
1048         adjusted_mode->crtc_hdisplay =
1049                                 intel_de_read(dev_priv,
1050                                               BXT_MIPI_TRANS_HACTIVE(port));
1051         adjusted_mode->crtc_vdisplay =
1052                                 intel_de_read(dev_priv,
1053                                               BXT_MIPI_TRANS_VACTIVE(port));
1054         adjusted_mode->crtc_vtotal =
1055                                 intel_de_read(dev_priv,
1056                                               BXT_MIPI_TRANS_VTOTAL(port));
1057
1058         hactive = adjusted_mode->crtc_hdisplay;
1059         hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port));
1060
1061         /*
1062          * Meaningful for video mode non-burst sync pulse mode only,
1063          * can be zero for non-burst sync events and burst modes
1064          */
1065         hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port));
1066         hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port));
1067
1068         /* harizontal values are in terms of high speed byte clock */
1069         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1070                                                 intel_dsi->burst_mode_ratio);
1071         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1072                                                 intel_dsi->burst_mode_ratio);
1073         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1074                                                 intel_dsi->burst_mode_ratio);
1075
1076         if (intel_dsi->dual_link) {
1077                 hfp *= 2;
1078                 hsync *= 2;
1079                 hbp *= 2;
1080         }
1081
1082         /* vertical values are in terms of lines */
1083         vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port));
1084         vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port));
1085
1086         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1087         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1088         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1089         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1090         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1091
1092         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1093         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1094         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1095         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1096
1097         /*
1098          * In BXT DSI there is no regs programmed with few horizontal timings
1099          * in Pixels but txbyteclkhs.. So retrieval process adds some
1100          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1101          * Actually here for the given adjusted_mode, we are calculating the
1102          * value programmed to the port and then back to the horizontal timing
1103          * param in pixels. This is the expected value, including roundup errors
1104          * And if that is same as retrieved value from port, then
1105          * (HW state) adjusted_mode's horizontal timings are corrected to
1106          * match with SW state to nullify the errors.
1107          */
1108         /* Calculating the value programmed to the Port register */
1109         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1110                                         adjusted_mode_sw->crtc_hdisplay;
1111         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1112                                         adjusted_mode_sw->crtc_hsync_start;
1113         hbp_sw = adjusted_mode_sw->crtc_htotal -
1114                                         adjusted_mode_sw->crtc_hsync_end;
1115
1116         if (intel_dsi->dual_link) {
1117                 hfp_sw /= 2;
1118                 hsync_sw /= 2;
1119                 hbp_sw /= 2;
1120         }
1121
1122         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1123                                                 intel_dsi->burst_mode_ratio);
1124         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1125                             intel_dsi->burst_mode_ratio);
1126         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1127                                                 intel_dsi->burst_mode_ratio);
1128
1129         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1130         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1131                                                 intel_dsi->burst_mode_ratio);
1132         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1133                                                 intel_dsi->burst_mode_ratio);
1134         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1135                                                 intel_dsi->burst_mode_ratio);
1136
1137         if (intel_dsi->dual_link) {
1138                 hfp_sw *= 2;
1139                 hsync_sw *= 2;
1140                 hbp_sw *= 2;
1141         }
1142
1143         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1144                                                         hsync_sw + hbp_sw;
1145         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1146         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1147         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1148         crtc_hblank_end_sw = crtc_htotal_sw;
1149
1150         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1151                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1152
1153         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1154                 adjusted_mode->crtc_hsync_start =
1155                                         adjusted_mode_sw->crtc_hsync_start;
1156
1157         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1158                 adjusted_mode->crtc_hsync_end =
1159                                         adjusted_mode_sw->crtc_hsync_end;
1160
1161         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1162                 adjusted_mode->crtc_hblank_start =
1163                                         adjusted_mode_sw->crtc_hblank_start;
1164
1165         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1166                 adjusted_mode->crtc_hblank_end =
1167                                         adjusted_mode_sw->crtc_hblank_end;
1168 }
1169
1170 static void intel_dsi_get_config(struct intel_encoder *encoder,
1171                                  struct intel_crtc_state *pipe_config)
1172 {
1173         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1174         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1175         u32 pclk;
1176
1177         drm_dbg_kms(&dev_priv->drm, "\n");
1178
1179         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1180
1181         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1182                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1183                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1184         } else {
1185                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1186         }
1187
1188         pipe_config->port_clock = pclk;
1189
1190         /* FIXME definitely not right for burst/cmd mode/pixel overlap */
1191         pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1192         if (intel_dsi->dual_link)
1193                 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1194 }
1195
1196 /* return txclkesc cycles in terms of divider and duration in us */
1197 static u16 txclkesc(u32 divider, unsigned int us)
1198 {
1199         switch (divider) {
1200         case ESCAPE_CLOCK_DIVIDER_1:
1201         default:
1202                 return 20 * us;
1203         case ESCAPE_CLOCK_DIVIDER_2:
1204                 return 10 * us;
1205         case ESCAPE_CLOCK_DIVIDER_4:
1206                 return 5 * us;
1207         }
1208 }
1209
1210 static void set_dsi_timings(struct drm_encoder *encoder,
1211                             const struct drm_display_mode *adjusted_mode)
1212 {
1213         struct drm_device *dev = encoder->dev;
1214         struct drm_i915_private *dev_priv = to_i915(dev);
1215         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1216         enum port port;
1217         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1218         unsigned int lane_count = intel_dsi->lane_count;
1219
1220         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1221
1222         hactive = adjusted_mode->crtc_hdisplay;
1223         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1224         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1225         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1226
1227         if (intel_dsi->dual_link) {
1228                 hactive /= 2;
1229                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1230                         hactive += intel_dsi->pixel_overlap;
1231                 hfp /= 2;
1232                 hsync /= 2;
1233                 hbp /= 2;
1234         }
1235
1236         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1237         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1238         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1239
1240         /* horizontal values are in terms of high speed byte clock */
1241         hactive = txbyteclkhs(hactive, bpp, lane_count,
1242                               intel_dsi->burst_mode_ratio);
1243         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1244         hsync = txbyteclkhs(hsync, bpp, lane_count,
1245                             intel_dsi->burst_mode_ratio);
1246         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1247
1248         for_each_dsi_port(port, intel_dsi->ports) {
1249                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1250                         /*
1251                          * Program hdisplay and vdisplay on MIPI transcoder.
1252                          * This is different from calculated hactive and
1253                          * vactive, as they are calculated per channel basis,
1254                          * whereas these values should be based on resolution.
1255                          */
1256                         intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port),
1257                                        adjusted_mode->crtc_hdisplay);
1258                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port),
1259                                        adjusted_mode->crtc_vdisplay);
1260                         intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port),
1261                                        adjusted_mode->crtc_vtotal);
1262                 }
1263
1264                 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port),
1265                                hactive);
1266                 intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp);
1267
1268                 /* meaningful for video mode non-burst sync pulse mode only,
1269                  * can be zero for non-burst sync events and burst modes */
1270                 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port),
1271                                hsync);
1272                 intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp);
1273
1274                 /* vertical values are in terms of lines */
1275                 intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp);
1276                 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port),
1277                                vsync);
1278                 intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp);
1279         }
1280 }
1281
1282 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1283 {
1284         switch (fmt) {
1285         case MIPI_DSI_FMT_RGB888:
1286                 return VID_MODE_FORMAT_RGB888;
1287         case MIPI_DSI_FMT_RGB666:
1288                 return VID_MODE_FORMAT_RGB666;
1289         case MIPI_DSI_FMT_RGB666_PACKED:
1290                 return VID_MODE_FORMAT_RGB666_PACKED;
1291         case MIPI_DSI_FMT_RGB565:
1292                 return VID_MODE_FORMAT_RGB565;
1293         default:
1294                 MISSING_CASE(fmt);
1295                 return VID_MODE_FORMAT_RGB666;
1296         }
1297 }
1298
1299 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1300                               const struct intel_crtc_state *pipe_config)
1301 {
1302         struct drm_encoder *encoder = &intel_encoder->base;
1303         struct drm_device *dev = encoder->dev;
1304         struct drm_i915_private *dev_priv = to_i915(dev);
1305         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1306         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1307         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1308         enum port port;
1309         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1310         u32 val, tmp;
1311         u16 mode_hdisplay;
1312
1313         drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe));
1314
1315         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1316
1317         if (intel_dsi->dual_link) {
1318                 mode_hdisplay /= 2;
1319                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1320                         mode_hdisplay += intel_dsi->pixel_overlap;
1321         }
1322
1323         for_each_dsi_port(port, intel_dsi->ports) {
1324                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1325                         /*
1326                          * escape clock divider, 20MHz, shared for A and C.
1327                          * device ready must be off when doing this! txclkesc?
1328                          */
1329                         tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A));
1330                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1331                         intel_de_write(dev_priv, MIPI_CTRL(PORT_A),
1332                                        tmp | ESCAPE_CLOCK_DIVIDER_1);
1333
1334                         /* read request priority is per pipe */
1335                         tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
1336                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1337                         intel_de_write(dev_priv, MIPI_CTRL(port),
1338                                        tmp | READ_REQUEST_PRIORITY_HIGH);
1339                 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1340                         enum pipe pipe = crtc->pipe;
1341
1342                         intel_de_rmw(dev_priv, MIPI_CTRL(port),
1343                                      BXT_PIPE_SELECT_MASK, BXT_PIPE_SELECT(pipe));
1344                 }
1345
1346                 /* XXX: why here, why like this? handling in irq handler?! */
1347                 intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff);
1348                 intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff);
1349
1350                 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port),
1351                                intel_dsi->dphy_reg);
1352
1353                 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port),
1354                                adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1355         }
1356
1357         set_dsi_timings(encoder, adjusted_mode);
1358
1359         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1360         if (is_cmd_mode(intel_dsi)) {
1361                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1362                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1363         } else {
1364                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1365                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1366         }
1367
1368         tmp = 0;
1369         if (intel_dsi->eotp_pkt == 0)
1370                 tmp |= EOT_DISABLE;
1371         if (intel_dsi->clock_stop)
1372                 tmp |= CLOCKSTOP;
1373
1374         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1375                 tmp |= BXT_DPHY_DEFEATURE_EN;
1376                 if (!is_cmd_mode(intel_dsi))
1377                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1378         }
1379
1380         for_each_dsi_port(port, intel_dsi->ports) {
1381                 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val);
1382
1383                 /* timeouts for recovery. one frame IIUC. if counter expires,
1384                  * EOT and stop state. */
1385
1386                 /*
1387                  * In burst mode, value greater than one DPI line Time in byte
1388                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1389                  * said value is recommended.
1390                  *
1391                  * In non-burst mode, Value greater than one DPI frame time in
1392                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1393                  * said value is recommended.
1394                  *
1395                  * In DBI only mode, value greater than one DBI frame time in
1396                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1397                  * said value is recommended.
1398                  */
1399
1400                 if (is_vid_mode(intel_dsi) &&
1401                         intel_dsi->video_mode == BURST_MODE) {
1402                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1403                                        txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1404                 } else {
1405                         intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port),
1406                                        txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1407                 }
1408                 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port),
1409                                intel_dsi->lp_rx_timeout);
1410                 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port),
1411                                intel_dsi->turn_arnd_val);
1412                 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port),
1413                                intel_dsi->rst_timer_val);
1414
1415                 /* dphy stuff */
1416
1417                 /* in terms of low power clock */
1418                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1419                                txclkesc(intel_dsi->escape_clk_div, 100));
1420
1421                 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1422                     !intel_dsi->dual_link) {
1423                         /*
1424                          * BXT spec says write MIPI_INIT_COUNT for
1425                          * both the ports, even if only one is
1426                          * getting used. So write the other port
1427                          * if not in dual link mode.
1428                          */
1429                         intel_de_write(dev_priv,
1430                                        MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A),
1431                                        intel_dsi->init_count);
1432                 }
1433
1434                 /* recovery disables */
1435                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp);
1436
1437                 /* in terms of low power clock */
1438                 intel_de_write(dev_priv, MIPI_INIT_COUNT(port),
1439                                intel_dsi->init_count);
1440
1441                 /* in terms of txbyteclkhs. actual high to low switch +
1442                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1443                  *
1444                  * XXX: write MIPI_STOP_STATE_STALL?
1445                  */
1446                 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port),
1447                                intel_dsi->hs_to_lp_count);
1448
1449                 /* XXX: low power clock equivalence in terms of byte clock.
1450                  * the number of byte clocks occupied in one low power clock.
1451                  * based on txbyteclkhs and txclkesc.
1452                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1453                  * ) / 105.???
1454                  */
1455                 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port),
1456                                intel_dsi->lp_byte_clk);
1457
1458                 if (IS_GEMINILAKE(dev_priv)) {
1459                         intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port),
1460                                        intel_dsi->lp_byte_clk);
1461                         /* Shadow of DPHY reg */
1462                         intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port),
1463                                        intel_dsi->dphy_reg);
1464                 }
1465
1466                 /* the bw essential for transmitting 16 long packets containing
1467                  * 252 bytes meant for dcs write memory command is programmed in
1468                  * this register in terms of byte clocks. based on dsi transfer
1469                  * rate and the number of lanes configured the time taken to
1470                  * transmit 16 long packets in a dsi stream varies. */
1471                 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port),
1472                                intel_dsi->bw_timer);
1473
1474                 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1475                                intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1476
1477                 if (is_vid_mode(intel_dsi)) {
1478                         u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;
1479
1480                         /*
1481                          * Some panels might have resolution which is not a
1482                          * multiple of 64 like 1366 x 768. Enable RANDOM
1483                          * resolution support for such panels by default.
1484                          */
1485                         fmt |= RANDOM_DPI_DISPLAY_RESOLUTION;
1486
1487                         switch (intel_dsi->video_mode) {
1488                         default:
1489                                 MISSING_CASE(intel_dsi->video_mode);
1490                                 fallthrough;
1491                         case NON_BURST_SYNC_EVENTS:
1492                                 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS;
1493                                 break;
1494                         case NON_BURST_SYNC_PULSE:
1495                                 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE;
1496                                 break;
1497                         case BURST_MODE:
1498                                 fmt |= VIDEO_MODE_BURST;
1499                                 break;
1500                         }
1501
1502                         intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), fmt);
1503                 }
1504         }
1505 }
1506
1507 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1508 {
1509         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1510         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1511         enum port port;
1512
1513         if (IS_GEMINILAKE(dev_priv))
1514                 return;
1515
1516         for_each_dsi_port(port, intel_dsi->ports) {
1517                 /* Panel commands can be sent when clock is in LP11 */
1518                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0);
1519
1520                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1521                         bxt_dsi_reset_clocks(encoder, port);
1522                 else
1523                         vlv_dsi_reset_clocks(encoder, port);
1524                 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP);
1525
1526                 intel_de_rmw(dev_priv, MIPI_DSI_FUNC_PRG(port), VID_MODE_FORMAT_MASK, 0);
1527
1528                 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1);
1529         }
1530 }
1531
1532 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1533 {
1534         struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder));
1535
1536         intel_dsi_vbt_gpio_cleanup(intel_dsi);
1537         intel_encoder_destroy(encoder);
1538 }
1539
1540 static const struct drm_encoder_funcs intel_dsi_funcs = {
1541         .destroy = intel_dsi_encoder_destroy,
1542 };
1543
1544 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1545         .get_modes = intel_dsi_get_modes,
1546         .mode_valid = intel_dsi_mode_valid,
1547         .atomic_check = intel_digital_connector_atomic_check,
1548 };
1549
1550 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1551         .detect = intel_panel_detect,
1552         .late_register = intel_connector_register,
1553         .early_unregister = intel_connector_unregister,
1554         .destroy = intel_connector_destroy,
1555         .fill_modes = drm_helper_probe_single_connector_modes,
1556         .atomic_get_property = intel_digital_connector_atomic_get_property,
1557         .atomic_set_property = intel_digital_connector_atomic_set_property,
1558         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1559         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1560 };
1561
1562 static void vlv_dsi_add_properties(struct intel_connector *connector)
1563 {
1564         const struct drm_display_mode *fixed_mode =
1565                 intel_panel_preferred_fixed_mode(connector);
1566
1567         intel_attach_scaling_mode_property(&connector->base);
1568
1569         drm_connector_set_panel_orientation_with_quirk(&connector->base,
1570                                                        intel_dsi_get_panel_orientation(connector),
1571                                                        fixed_mode->hdisplay,
1572                                                        fixed_mode->vdisplay);
1573 }
1574
1575 #define NS_KHZ_RATIO            1000000
1576
1577 #define PREPARE_CNT_MAX         0x3F
1578 #define EXIT_ZERO_CNT_MAX       0x3F
1579 #define CLK_ZERO_CNT_MAX        0xFF
1580 #define TRAIL_CNT_MAX           0x1F
1581
1582 static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1583 {
1584         struct drm_device *dev = intel_dsi->base.base.dev;
1585         struct drm_i915_private *dev_priv = to_i915(dev);
1586         struct intel_connector *connector = intel_dsi->attached_connector;
1587         struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1588         u32 tlpx_ns, extra_byte_count, tlpx_ui;
1589         u32 ui_num, ui_den;
1590         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1591         u32 ths_prepare_ns, tclk_trail_ns;
1592         u32 tclk_prepare_clkzero, ths_prepare_hszero;
1593         u32 lp_to_hs_switch, hs_to_lp_switch;
1594         u32 mul;
1595
1596         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1597
1598         switch (intel_dsi->lane_count) {
1599         case 1:
1600         case 2:
1601                 extra_byte_count = 2;
1602                 break;
1603         case 3:
1604                 extra_byte_count = 4;
1605                 break;
1606         case 4:
1607         default:
1608                 extra_byte_count = 3;
1609                 break;
1610         }
1611
1612         /* in Kbps */
1613         ui_num = NS_KHZ_RATIO;
1614         ui_den = intel_dsi_bitrate(intel_dsi);
1615
1616         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1617         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1618
1619         /*
1620          * B060
1621          * LP byte clock = TLPX/ (8UI)
1622          */
1623         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
1624
1625         /* DDR clock period = 2 * UI
1626          * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1627          * UI(nsec) = 10^6 / bitrate
1628          * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1629          * DDR clock count  = ns_value / DDR clock period
1630          *
1631          * For GEMINILAKE dphy_param_reg will be programmed in terms of
1632          * HS byte clock count for other platform in HS ddr clock count
1633          */
1634         mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1635         ths_prepare_ns = max(mipi_config->ths_prepare,
1636                              mipi_config->tclk_prepare);
1637
1638         /* prepare count */
1639         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
1640
1641         if (prepare_cnt > PREPARE_CNT_MAX) {
1642                 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1643                             prepare_cnt);
1644                 prepare_cnt = PREPARE_CNT_MAX;
1645         }
1646
1647         /* exit zero count */
1648         exit_zero_cnt = DIV_ROUND_UP(
1649                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
1650                                 ui_num * mul
1651                                 );
1652
1653         /*
1654          * Exit zero is unified val ths_zero and ths_exit
1655          * minimum value for ths_exit = 110ns
1656          * min (exit_zero_cnt * 2) = 110/UI
1657          * exit_zero_cnt = 55/UI
1658          */
1659         if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1660                 exit_zero_cnt += 1;
1661
1662         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
1663                 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1664                             exit_zero_cnt);
1665                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
1666         }
1667
1668         /* clk zero count */
1669         clk_zero_cnt = DIV_ROUND_UP(
1670                                 (tclk_prepare_clkzero - ths_prepare_ns)
1671                                 * ui_den, ui_num * mul);
1672
1673         if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
1674                 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1675                             clk_zero_cnt);
1676                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
1677         }
1678
1679         /* trail count */
1680         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1681         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
1682
1683         if (trail_cnt > TRAIL_CNT_MAX) {
1684                 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1685                             trail_cnt);
1686                 trail_cnt = TRAIL_CNT_MAX;
1687         }
1688
1689         /* B080 */
1690         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1691                                                 clk_zero_cnt << 8 | prepare_cnt;
1692
1693         /*
1694          * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1695          *                                      mul + 10UI + Extra Byte Count
1696          *
1697          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1698          * Extra Byte Count is calculated according to number of lanes.
1699          * High Low Switch Count is the Max of LP to HS and
1700          * HS to LP switch count
1701          *
1702          */
1703         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
1704
1705         /* B044 */
1706         /* FIXME:
1707          * The comment above does not match with the code */
1708         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +
1709                                                 exit_zero_cnt * mul + 10, 8);
1710
1711         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
1712
1713         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
1714         intel_dsi->hs_to_lp_count += extra_byte_count;
1715
1716         /* B088 */
1717         /* LP -> HS for clock lanes
1718          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1719          *                                              extra byte count
1720          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1721          *                                      2(in UI) + extra byte count
1722          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1723          *                                      8 + extra byte count
1724          */
1725         intel_dsi->clk_lp_to_hs_count =
1726                 DIV_ROUND_UP(
1727                         4 * tlpx_ui + prepare_cnt * 2 +
1728                         clk_zero_cnt * 2,
1729                         8);
1730
1731         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1732
1733         /* HS->LP for Clock Lanes
1734          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1735          *                                              Extra byte count
1736          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1737          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1738          *                                              Extra byte count
1739          */
1740         intel_dsi->clk_hs_to_lp_count =
1741                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
1742                         8);
1743         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1744
1745         intel_dsi_log_params(intel_dsi);
1746 }
1747
1748 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
1749
1750 /*
1751  * Vtotal is wrong on the Asus TF103C leading to the last line of the display
1752  * being shown as the first line. The factory installed Android has a hardcoded
1753  * modeline, causing it to not suffer from this BIOS bug.
1754  *
1755  * Original mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa
1756  * Fixed    mode: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa
1757  *
1758  * https://gitlab.freedesktop.org/drm/intel/-/issues/9381
1759  */
1760 static void vlv_dsi_asus_tf103c_mode_fixup(struct intel_dsi *intel_dsi)
1761 {
1762         /* Cast away the const as we want to fixup the mode */
1763         struct drm_display_mode *fixed_mode = (struct drm_display_mode *)
1764                 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1765
1766         if (fixed_mode->vtotal == 820)
1767                 fixed_mode->vtotal -= 4;
1768 }
1769
1770 /*
1771  * On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems:
1772  * 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7
1773  *    which under Linux become bus 0 - 6. And the MIPI sequence reference
1774  *    to bus 3 is indented for I2C3 which is bus 2 under Linux.
1775  *
1776  *    Note mipi_exec_i2c() cannot just subtract 1 from the bus
1777  *    given in the I2C MIPI sequence element. Since on other
1778  *    devices the I2C bus-numbers used in the MIPI sequences do
1779  *    actually start at 0.
1780  *
1781  * 2. width_/height_mm contain a bogus 192mm x 120mm size. This is
1782  *    especially a problem on the 8" 830 version which uses a 10:16
1783  *    portrait screen where as the bogus size is 16:10.
1784  *
1785  * https://gitlab.freedesktop.org/drm/intel/-/issues/9379
1786  */
1787 static void vlv_dsi_lenovo_yoga_tab2_size_fixup(struct intel_dsi *intel_dsi)
1788 {
1789         const struct drm_display_mode *fixed_mode =
1790                 intel_panel_preferred_fixed_mode(intel_dsi->attached_connector);
1791         struct drm_display_info *info = &intel_dsi->attached_connector->base.display_info;
1792
1793         intel_dsi->i2c_bus_num = 2;
1794
1795         /*
1796          * The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830
1797          * uses a 1200x1920 portrait screen.
1798          */
1799         if (fixed_mode->hdisplay == 1920) {
1800                 info->width_mm = 216;
1801                 info->height_mm = 135;
1802         } else {
1803                 info->width_mm = 107;
1804                 info->height_mm = 171;
1805         }
1806 }
1807
1808 /*
1809  * On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 problems:
1810  * 1. i2c_acpi_find_adapter() picks the wrong adapter causing mipi_exec_i2c()
1811  *    to not work. Fix this by setting i2c_bus_num.
1812  * 2. There is no backlight off MIPI sequence, causing the backlight to stay on.
1813  *    Add a backlight off sequence mirroring the existing backlight on sequence.
1814  *
1815  * https://gitlab.freedesktop.org/drm/intel/-/issues/9380
1816  */
1817 static void vlv_dsi_lenovo_yoga_tab3_backlight_fixup(struct intel_dsi *intel_dsi)
1818 {
1819         static const u8 backlight_off_sequence[16] = {
1820                 /* Header Seq-id 7, length after header 11 bytes */
1821                 0x07, 0x0b, 0x00, 0x00, 0x00,
1822                 /* MIPI_SEQ_ELEM_I2C bus 0 addr 0x2c reg 0x00 data-len 1 data 0x00 */
1823                 0x04, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x01, 0x00,
1824                 /* MIPI_SEQ_ELEM_END */
1825                 0x00
1826         };
1827         struct intel_connector *connector = intel_dsi->attached_connector;
1828
1829         intel_dsi->i2c_bus_num = 0;
1830         connector->panel.vbt.dsi.sequence[MIPI_SEQ_BACKLIGHT_OFF] = backlight_off_sequence;
1831 }
1832
1833 static const struct dmi_system_id vlv_dsi_dmi_quirk_table[] = {
1834         {
1835                 /* Asus Transformer Pad TF103C */
1836                 .matches = {
1837                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
1838                         DMI_MATCH(DMI_PRODUCT_NAME, "TF103C"),
1839                 },
1840                 .driver_data = (void *)vlv_dsi_asus_tf103c_mode_fixup,
1841         },
1842         {
1843                 /*
1844                  * Lenovo Yoga Tablet 2 830F/L or 1050F/L (The 8" and 10"
1845                  * Lenovo Yoga Tablet 2 use the same mainboard)
1846                  */
1847                 .matches = {
1848                         DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp."),
1849                         DMI_MATCH(DMI_PRODUCT_NAME, "VALLEYVIEW C0 PLATFORM"),
1850                         DMI_MATCH(DMI_BOARD_NAME, "BYT-T FFD8"),
1851                         /* Partial match on beginning of BIOS version */
1852                         DMI_MATCH(DMI_BIOS_VERSION, "BLADE_21"),
1853                 },
1854                 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab2_size_fixup,
1855         },
1856         {
1857                 /* Lenovo Yoga Tab 3 Pro YT3-X90F */
1858                 .matches = {
1859                         DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"),
1860                         DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"),
1861                         DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"),
1862                 },
1863                 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup,
1864         },
1865         { }
1866 };
1867
1868 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1869 {
1870         struct intel_dsi *intel_dsi;
1871         struct intel_encoder *intel_encoder;
1872         struct drm_encoder *encoder;
1873         struct intel_connector *intel_connector;
1874         struct drm_connector *connector;
1875         struct drm_display_mode *current_mode;
1876         const struct dmi_system_id *dmi_id;
1877         enum port port;
1878         enum pipe pipe;
1879
1880         drm_dbg_kms(&dev_priv->drm, "\n");
1881
1882         /* There is no detection method for MIPI so rely on VBT */
1883         if (!intel_bios_is_dsi_present(dev_priv, &port))
1884                 return;
1885
1886         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1887                 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1888         else
1889                 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1890
1891         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1892         if (!intel_dsi)
1893                 return;
1894
1895         intel_connector = intel_connector_alloc();
1896         if (!intel_connector) {
1897                 kfree(intel_dsi);
1898                 return;
1899         }
1900
1901         intel_encoder = &intel_dsi->base;
1902         encoder = &intel_encoder->base;
1903         intel_dsi->attached_connector = intel_connector;
1904
1905         connector = &intel_connector->base;
1906
1907         drm_encoder_init(&dev_priv->drm, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1908                          "DSI %c", port_name(port));
1909
1910         intel_encoder->compute_config = intel_dsi_compute_config;
1911         intel_encoder->pre_enable = intel_dsi_pre_enable;
1912         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1913                 intel_encoder->enable = bxt_dsi_enable;
1914         intel_encoder->disable = intel_dsi_disable;
1915         intel_encoder->post_disable = intel_dsi_post_disable;
1916         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1917         intel_encoder->get_config = intel_dsi_get_config;
1918         intel_encoder->update_pipe = intel_backlight_update;
1919         intel_encoder->shutdown = intel_dsi_shutdown;
1920
1921         intel_connector->get_hw_state = intel_connector_get_hw_state;
1922
1923         intel_encoder->port = port;
1924         intel_encoder->type = INTEL_OUTPUT_DSI;
1925         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1926         intel_encoder->cloneable = 0;
1927
1928         /*
1929          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1930          * port C. BXT isn't limited like this.
1931          */
1932         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1933                 intel_encoder->pipe_mask = ~0;
1934         else if (port == PORT_A)
1935                 intel_encoder->pipe_mask = BIT(PIPE_A);
1936         else
1937                 intel_encoder->pipe_mask = BIT(PIPE_B);
1938
1939         intel_dsi->panel_power_off_time = ktime_get_boottime();
1940
1941         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, NULL);
1942
1943         if (intel_connector->panel.vbt.dsi.config->dual_link)
1944                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1945         else
1946                 intel_dsi->ports = BIT(port);
1947
1948         if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1949                 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1950
1951         if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1952                 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1953
1954         /* Create a DSI host (and a device) for each port. */
1955         for_each_dsi_port(port, intel_dsi->ports) {
1956                 struct intel_dsi_host *host;
1957
1958                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1959                                            port);
1960                 if (!host)
1961                         goto err;
1962
1963                 intel_dsi->dsi_hosts[port] = host;
1964         }
1965
1966         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1967                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
1968                 goto err;
1969         }
1970
1971         /* Use clock read-back from current hw-state for fastboot */
1972         current_mode = intel_encoder_current_mode(intel_encoder);
1973         if (current_mode) {
1974                 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1975                             intel_dsi->pclk, current_mode->clock);
1976                 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1977                                             current_mode->clock)) {
1978                         drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1979                         intel_dsi->pclk = current_mode->clock;
1980                 }
1981
1982                 kfree(current_mode);
1983         }
1984
1985         vlv_dphy_param_init(intel_dsi);
1986
1987         intel_dsi_vbt_gpio_init(intel_dsi,
1988                                 intel_dsi_get_hw_state(intel_encoder, &pipe));
1989
1990         drm_connector_init(&dev_priv->drm, connector, &intel_dsi_connector_funcs,
1991                            DRM_MODE_CONNECTOR_DSI);
1992
1993         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1994
1995         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1996
1997         intel_connector_attach_encoder(intel_connector, intel_encoder);
1998
1999         mutex_lock(&dev_priv->drm.mode_config.mutex);
2000         intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
2001         mutex_unlock(&dev_priv->drm.mode_config.mutex);
2002
2003         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2004                 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
2005                 goto err_cleanup_connector;
2006         }
2007
2008         dmi_id = dmi_first_match(vlv_dsi_dmi_quirk_table);
2009         if (dmi_id) {
2010                 vlv_dsi_dmi_quirk_func quirk_func =
2011                         (vlv_dsi_dmi_quirk_func)dmi_id->driver_data;
2012
2013                 quirk_func(intel_dsi);
2014         }
2015
2016         intel_panel_init(intel_connector, NULL);
2017
2018         intel_backlight_setup(intel_connector, INVALID_PIPE);
2019
2020         vlv_dsi_add_properties(intel_connector);
2021
2022         return;
2023
2024 err_cleanup_connector:
2025         drm_connector_cleanup(&intel_connector->base);
2026 err:
2027         drm_encoder_cleanup(&intel_encoder->base);
2028         kfree(intel_dsi);
2029         kfree(intel_connector);
2030 }