drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dma-resv.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_dp_helper.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_damage_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44
  45 #include "gem/i915_gem_lmem.h"
  46 #include "gem/i915_gem_object.h"
  47
  48 #include "g4x_dp.h"
  49 #include "g4x_hdmi.h"
  50 #include "hsw_ips.h"
  51 #include "i915_drv.h"
  52 #include "i915_reg.h"
  53 #include "i915_utils.h"
  54 #include "i9xx_plane.h"
  55 #include "i9xx_wm.h"
  56 #include "intel_atomic.h"
  57 #include "intel_atomic_plane.h"
  58 #include "intel_audio.h"
  59 #include "intel_bw.h"
  60 #include "intel_cdclk.h"
  61 #include "intel_clock_gating.h"
  62 #include "intel_color.h"
  63 #include "intel_crt.h"
  64 #include "intel_crtc.h"
  65 #include "intel_crtc_state_dump.h"
  66 #include "intel_ddi.h"
  67 #include "intel_de.h"
  68 #include "intel_display_driver.h"
  69 #include "intel_display_power.h"
  70 #include "intel_display_types.h"
  71 #include "intel_dmc.h"
  72 #include "intel_dp.h"
  73 #include "intel_dp_link_training.h"
  74 #include "intel_dp_mst.h"
  75 #include "intel_dpio_phy.h"
  76 #include "intel_dpll.h"
  77 #include "intel_dpll_mgr.h"
  78 #include "intel_dpt.h"
  79 #include "intel_drrs.h"
  80 #include "intel_dsb.h"
  81 #include "intel_dsi.h"
  82 #include "intel_dvo.h"
  83 #include "intel_fb.h"
  84 #include "intel_fbc.h"
  85 #include "intel_fbdev.h"
  86 #include "intel_fdi.h"
  87 #include "intel_fifo_underrun.h"
  88 #include "intel_frontbuffer.h"
  89 #include "intel_hdmi.h"
  90 #include "intel_hotplug.h"
  91 #include "intel_link_bw.h"
  92 #include "intel_lvds.h"
  93 #include "intel_lvds_regs.h"
  94 #include "intel_modeset_setup.h"
  95 #include "intel_modeset_verify.h"
  96 #include "intel_overlay.h"
  97 #include "intel_panel.h"
  98 #include "intel_pch_display.h"
  99 #include "intel_pch_refclk.h"
 100 #include "intel_pcode.h"
 101 #include "intel_pipe_crc.h"
 102 #include "intel_plane_initial.h"
 103 #include "intel_pmdemand.h"
 104 #include "intel_pps.h"
 105 #include "intel_psr.h"
 106 #include "intel_sdvo.h"
 107 #include "intel_snps_phy.h"
 108 #include "intel_tc.h"
 109 #include "intel_tv.h"
 110 #include "intel_vblank.h"
 111 #include "intel_vdsc.h"
 112 #include "intel_vdsc_regs.h"
 113 #include "intel_vga.h"
 114 #include "intel_vrr.h"
 115 #include "intel_wm.h"
 116 #include "skl_scaler.h"
 117 #include "skl_universal_plane.h"
 118 #include "skl_watermark.h"
 119 #include "vlv_dsi.h"
 120 #include "vlv_dsi_pll.h"
 121 #include "vlv_dsi_regs.h"
 122 #include "vlv_sideband.h"
 123
 124 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 125 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 126 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 127 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
 128
 129 /* returns HPLL frequency in kHz */
 130 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 131 {
 132         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 133
 134         /* Obtain SKU information */
 135         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 136                 CCK_FUSE_HPLL_FREQ_MASK;
 137
 138         return vco_freq[hpll_freq] * 1000;
 139 }
 140
 141 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 142                       const char *name, u32 reg, int ref_freq)
 143 {
 144         u32 val;
 145         int divider;
 146
 147         val = vlv_cck_read(dev_priv, reg);
 148         divider = val & CCK_FREQUENCY_VALUES;
 149
 150         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 151                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 152                  "%s change in progress\n", name);
 153
 154         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 155 }
 156
 157 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 158                            const char *name, u32 reg)
 159 {
 160         int hpll;
 161
 162         vlv_cck_get(dev_priv);
 163
 164         if (dev_priv->hpll_freq == 0)
 165                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 166
 167         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 168
 169         vlv_cck_put(dev_priv);
 170
 171         return hpll;
 172 }
 173
 174 void intel_update_czclk(struct drm_i915_private *dev_priv)
 175 {
 176         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 177                 return;
 178
 179         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 180                                                       CCK_CZ_CLOCK_CONTROL);
 181
 182         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 183                 dev_priv->czclk_freq);
 184 }
 185
 186 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 187 {
 188         return (crtc_state->active_planes &
 189                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 190 }
 191
 192 /* WA Display #0827: Gen9:all */
 193 static void
 194 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 195 {
 196         if (enable)
 197                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 198                              0, DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 199         else
 200                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 201                              DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0);
 202 }
 203
 204 /* Wa_2006604312:icl,ehl */
 205 static void
 206 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 207                        bool enable)
 208 {
 209         if (enable)
 210                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS);
 211         else
 212                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0);
 213 }
 214
 215 /* Wa_1604331009:icl,jsl,ehl */
 216 static void
 217 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 218                        bool enable)
 219 {
 220         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
 221                      enable ? CURSOR_GATING_DIS : 0);
 222 }
 223
 224 static bool
 225 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 226 {
 227         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 228 }
 229
 230 bool
 231 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 232 {
 233         return crtc_state->sync_mode_slaves_mask != 0;
 234 }
 235
 236 bool
 237 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 238 {
 239         return is_trans_port_sync_master(crtc_state) ||
 240                 is_trans_port_sync_slave(crtc_state);
 241 }
 242
 243 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 244 {
 245         return ffs(crtc_state->bigjoiner_pipes) - 1;
 246 }
 247
 248 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 249 {
 250         if (crtc_state->bigjoiner_pipes)
 251                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 252         else
 253                 return 0;
 254 }
 255
 256 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 257 {
 258         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 259
 260         return crtc_state->bigjoiner_pipes &&
 261                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 262 }
 263
 264 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 265 {
 266         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 267
 268         return crtc_state->bigjoiner_pipes &&
 269                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 270 }
 271
 272 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 273 {
 274         return hweight8(crtc_state->bigjoiner_pipes);
 275 }
 276
 277 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 278 {
 279         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 280
 281         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 282                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 283         else
 284                 return to_intel_crtc(crtc_state->uapi.crtc);
 285 }
 286
 287 static void
 288 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 289 {
 290         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 291         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 292
 293         if (DISPLAY_VER(dev_priv) >= 4) {
 294                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 295
 296                 /* Wait for the Pipe State to go off */
 297                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
 298                                             TRANSCONF_STATE_ENABLE, 100))
 299                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 300         } else {
 301                 intel_wait_for_pipe_scanline_stopped(crtc);
 302         }
 303 }
 304
 305 void assert_transcoder(struct drm_i915_private *dev_priv,
 306                        enum transcoder cpu_transcoder, bool state)
 307 {
 308         bool cur_state;
 309         enum intel_display_power_domain power_domain;
 310         intel_wakeref_t wakeref;
 311
 312         /* we keep both pipes enabled on 830 */
 313         if (IS_I830(dev_priv))
 314                 state = true;
 315
 316         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 317         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 318         if (wakeref) {
 319                 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 320                 cur_state = !!(val & TRANSCONF_ENABLE);
 321
 322                 intel_display_power_put(dev_priv, power_domain, wakeref);
 323         } else {
 324                 cur_state = false;
 325         }
 326
 327         I915_STATE_WARN(dev_priv, cur_state != state,
 328                         "transcoder %s assertion failure (expected %s, current %s)\n",
 329                         transcoder_name(cpu_transcoder), str_on_off(state),
 330                         str_on_off(cur_state));
 331 }
 332
 333 static void assert_plane(struct intel_plane *plane, bool state)
 334 {
 335         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 336         enum pipe pipe;
 337         bool cur_state;
 338
 339         cur_state = plane->get_hw_state(plane, &pipe);
 340
 341         I915_STATE_WARN(i915, cur_state != state,
 342                         "%s assertion failure (expected %s, current %s)\n",
 343                         plane->base.name, str_on_off(state),
 344                         str_on_off(cur_state));
 345 }
 346
 347 #define assert_plane_enabled(p) assert_plane(p, true)
 348 #define assert_plane_disabled(p) assert_plane(p, false)
 349
 350 static void assert_planes_disabled(struct intel_crtc *crtc)
 351 {
 352         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 353         struct intel_plane *plane;
 354
 355         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 356                 assert_plane_disabled(plane);
 357 }
 358
 359 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 360                          struct intel_digital_port *dig_port,
 361                          unsigned int expected_mask)
 362 {
 363         u32 port_mask;
 364         i915_reg_t dpll_reg;
 365
 366         switch (dig_port->base.port) {
 367         default:
 368                 MISSING_CASE(dig_port->base.port);
 369                 fallthrough;
 370         case PORT_B:
 371                 port_mask = DPLL_PORTB_READY_MASK;
 372                 dpll_reg = DPLL(0);
 373                 break;
 374         case PORT_C:
 375                 port_mask = DPLL_PORTC_READY_MASK;
 376                 dpll_reg = DPLL(0);
 377                 expected_mask <<= 4;
 378                 break;
 379         case PORT_D:
 380                 port_mask = DPLL_PORTD_READY_MASK;
 381                 dpll_reg = DPIO_PHY_STATUS;
 382                 break;
 383         }
 384
 385         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 386                                        port_mask, expected_mask, 1000))
 387                 drm_WARN(&dev_priv->drm, 1,
 388                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 389                          dig_port->base.base.base.id, dig_port->base.base.name,
 390                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 391                          expected_mask);
 392 }
 393
 394 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 395 {
 396         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 397         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 398         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 399         enum pipe pipe = crtc->pipe;
 400         i915_reg_t reg;
 401         u32 val;
 402
 403         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 404
 405         assert_planes_disabled(crtc);
 406
 407         /*
 408          * A pipe without a PLL won't actually be able to drive bits from
 409          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 410          * need the check.
 411          */
 412         if (HAS_GMCH(dev_priv)) {
 413                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 414                         assert_dsi_pll_enabled(dev_priv);
 415                 else
 416                         assert_pll_enabled(dev_priv, pipe);
 417         } else {
 418                 if (new_crtc_state->has_pch_encoder) {
 419                         /* if driving the PCH, we need FDI enabled */
 420                         assert_fdi_rx_pll_enabled(dev_priv,
 421                                                   intel_crtc_pch_transcoder(crtc));
 422                         assert_fdi_tx_pll_enabled(dev_priv,
 423                                                   (enum pipe) cpu_transcoder);
 424                 }
 425                 /* FIXME: assert CPU port conditions for SNB+ */
 426         }
 427
 428         /* Wa_22012358565:adl-p */
 429         if (DISPLAY_VER(dev_priv) == 13)
 430                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 431                              0, PIPE_ARB_USE_PROG_SLOTS);
 432
 433         reg = TRANSCONF(cpu_transcoder);
 434         val = intel_de_read(dev_priv, reg);
 435         if (val & TRANSCONF_ENABLE) {
 436                 /* we keep both pipes enabled on 830 */
 437                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 438                 return;
 439         }
 440
 441         intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE);
 442         intel_de_posting_read(dev_priv, reg);
 443
 444         /*
 445          * Until the pipe starts PIPEDSL reads will return a stale value,
 446          * which causes an apparent vblank timestamp jump when PIPEDSL
 447          * resets to its proper value. That also messes up the frame count
 448          * when it's derived from the timestamps. So let's wait for the
 449          * pipe to start properly before we call drm_crtc_vblank_on()
 450          */
 451         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 452                 intel_wait_for_pipe_scanline_moving(crtc);
 453 }
 454
 455 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 456 {
 457         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 458         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 459         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 460         enum pipe pipe = crtc->pipe;
 461         i915_reg_t reg;
 462         u32 val;
 463
 464         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 465
 466         /*
 467          * Make sure planes won't keep trying to pump pixels to us,
 468          * or we might hang the display.
 469          */
 470         assert_planes_disabled(crtc);
 471
 472         reg = TRANSCONF(cpu_transcoder);
 473         val = intel_de_read(dev_priv, reg);
 474         if ((val & TRANSCONF_ENABLE) == 0)
 475                 return;
 476
 477         /*
 478          * Double wide has implications for planes
 479          * so best keep it disabled when not needed.
 480          */
 481         if (old_crtc_state->double_wide)
 482                 val &= ~TRANSCONF_DOUBLE_WIDE;
 483
 484         /* Don't disable pipe or pipe PLLs if needed */
 485         if (!IS_I830(dev_priv))
 486                 val &= ~TRANSCONF_ENABLE;
 487
 488         if (DISPLAY_VER(dev_priv) >= 14)
 489                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
 490                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 491         else if (DISPLAY_VER(dev_priv) >= 12)
 492                 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
 493                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 494
 495         intel_de_write(dev_priv, reg, val);
 496         if ((val & TRANSCONF_ENABLE) == 0)
 497                 intel_wait_for_pipe_off(old_crtc_state);
 498 }
 499
 500 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 501 {
 502         unsigned int size = 0;
 503         int i;
 504
 505         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 506                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 507
 508         return size;
 509 }
 510
 511 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 512 {
 513         unsigned int size = 0;
 514         int i;
 515
 516         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 517                 unsigned int plane_size;
 518
 519                 if (rem_info->plane[i].linear)
 520                         plane_size = rem_info->plane[i].size;
 521                 else
 522                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 523
 524                 if (plane_size == 0)
 525                         continue;
 526
 527                 if (rem_info->plane_alignment)
 528                         size = ALIGN(size, rem_info->plane_alignment);
 529
 530                 size += plane_size;
 531         }
 532
 533         return size;
 534 }
 535
 536 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 537 {
 538         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 539         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 540
 541         return DISPLAY_VER(dev_priv) < 4 ||
 542                 (plane->fbc &&
 543                  plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
 544 }
 545
 546 /*
 547  * Convert the x/y offsets into a linear offset.
 548  * Only valid with 0/180 degree rotation, which is fine since linear
 549  * offset is only used with linear buffers on pre-hsw and tiled buffers
 550  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 551  */
 552 u32 intel_fb_xy_to_linear(int x, int y,
 553                           const struct intel_plane_state *state,
 554                           int color_plane)
 555 {
 556         const struct drm_framebuffer *fb = state->hw.fb;
 557         unsigned int cpp = fb->format->cpp[color_plane];
 558         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 559
 560         return y * pitch + x * cpp;
 561 }
 562
 563 /*
 564  * Add the x/y offsets derived from fb->offsets[] to the user
 565  * specified plane src x/y offsets. The resulting x/y offsets
 566  * specify the start of scanout from the beginning of the gtt mapping.
 567  */
 568 void intel_add_fb_offsets(int *x, int *y,
 569                           const struct intel_plane_state *state,
 570                           int color_plane)
 571
 572 {
 573         *x += state->view.color_plane[color_plane].x;
 574         *y += state->view.color_plane[color_plane].y;
 575 }
 576
 577 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 578                               u32 pixel_format, u64 modifier)
 579 {
 580         struct intel_crtc *crtc;
 581         struct intel_plane *plane;
 582
 583         if (!HAS_DISPLAY(dev_priv))
 584                 return 0;
 585
 586         /*
 587          * We assume the primary plane for pipe A has
 588          * the highest stride limits of them all,
 589          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 590          */
 591         crtc = intel_first_crtc(dev_priv);
 592         if (!crtc)
 593                 return 0;
 594
 595         plane = to_intel_plane(crtc->base.primary);
 596
 597         return plane->max_stride(plane, pixel_format, modifier,
 598                                  DRM_MODE_ROTATE_0);
 599 }
 600
 601 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 602                              struct intel_plane_state *plane_state,
 603                              bool visible)
 604 {
 605         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 606
 607         plane_state->uapi.visible = visible;
 608
 609         if (visible)
 610                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 611         else
 612                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 613 }
 614
 615 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 616 {
 617         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 618         struct drm_plane *plane;
 619
 620         /*
 621          * Active_planes aliases if multiple "primary" or cursor planes
 622          * have been used on the same (or wrong) pipe. plane_mask uses
 623          * unique ids, hence we can use that to reconstruct active_planes.
 624          */
 625         crtc_state->enabled_planes = 0;
 626         crtc_state->active_planes = 0;
 627
 628         drm_for_each_plane_mask(plane, &dev_priv->drm,
 629                                 crtc_state->uapi.plane_mask) {
 630                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 631                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 632         }
 633 }
 634
 635 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 636                                   struct intel_plane *plane)
 637 {
 638         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 639         struct intel_crtc_state *crtc_state =
 640                 to_intel_crtc_state(crtc->base.state);
 641         struct intel_plane_state *plane_state =
 642                 to_intel_plane_state(plane->base.state);
 643
 644         drm_dbg_kms(&dev_priv->drm,
 645                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 646                     plane->base.base.id, plane->base.name,
 647                     crtc->base.base.id, crtc->base.name);
 648
 649         intel_set_plane_visible(crtc_state, plane_state, false);
 650         intel_plane_fixup_bitmasks(crtc_state);
 651         crtc_state->data_rate[plane->id] = 0;
 652         crtc_state->data_rate_y[plane->id] = 0;
 653         crtc_state->rel_data_rate[plane->id] = 0;
 654         crtc_state->rel_data_rate_y[plane->id] = 0;
 655         crtc_state->min_cdclk[plane->id] = 0;
 656
 657         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 658             hsw_ips_disable(crtc_state)) {
 659                 crtc_state->ips_enabled = false;
 660                 intel_crtc_wait_for_next_vblank(crtc);
 661         }
 662
 663         /*
 664          * Vblank time updates from the shadow to live plane control register
 665          * are blocked if the memory self-refresh mode is active at that
 666          * moment. So to make sure the plane gets truly disabled, disable
 667          * first the self-refresh mode. The self-refresh enable bit in turn
 668          * will be checked/applied by the HW only at the next frame start
 669          * event which is after the vblank start event, so we need to have a
 670          * wait-for-vblank between disabling the plane and the pipe.
 671          */
 672         if (HAS_GMCH(dev_priv) &&
 673             intel_set_memory_cxsr(dev_priv, false))
 674                 intel_crtc_wait_for_next_vblank(crtc);
 675
 676         /*
 677          * Gen2 reports pipe underruns whenever all planes are disabled.
 678          * So disable underrun reporting before all the planes get disabled.
 679          */
 680         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 681                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 682
 683         intel_plane_disable_arm(plane, crtc_state);
 684         intel_crtc_wait_for_next_vblank(crtc);
 685 }
 686
 687 unsigned int
 688 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 689 {
 690         int x = 0, y = 0;
 691
 692         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 693                                           plane_state->view.color_plane[0].offset, 0);
 694
 695         return y;
 696 }
 697
 698 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 699 {
 700         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 701         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 702         enum pipe pipe = crtc->pipe;
 703         u32 tmp;
 704
 705         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 706
 707         /*
 708          * Display WA #1153: icl
 709          * enable hardware to bypass the alpha math
 710          * and rounding for per-pixel values 00 and 0xff
 711          */
 712         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 713         /*
 714          * Display WA # 1605353570: icl
 715          * Set the pixel rounding bit to 1 for allowing
 716          * passthrough of Frame buffer pixels unmodified
 717          * across pipe
 718          */
 719         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 720
 721         /*
 722          * Underrun recovery must always be disabled on display 13+.
 723          * DG2 chicken bit meaning is inverted compared to other platforms.
 724          */
 725         if (IS_DG2(dev_priv))
 726                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
 727         else if (DISPLAY_VER(dev_priv) >= 13)
 728                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 729
 730         /* Wa_14010547955:dg2 */
 731         if (IS_DG2(dev_priv))
 732                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
 733
 734         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 735 }
 736
 737 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
 738 {
 739         struct drm_crtc *crtc;
 740         bool cleanup_done;
 741
 742         drm_for_each_crtc(crtc, &dev_priv->drm) {
 743                 struct drm_crtc_commit *commit;
 744                 spin_lock(&crtc->commit_lock);
 745                 commit = list_first_entry_or_null(&crtc->commit_list,
 746                                                   struct drm_crtc_commit, commit_entry);
 747                 cleanup_done = commit ?
 748                         try_wait_for_completion(&commit->cleanup_done) : true;
 749                 spin_unlock(&crtc->commit_lock);
 750
 751                 if (cleanup_done)
 752                         continue;
 753
 754                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
 755
 756                 return true;
 757         }
 758
 759         return false;
 760 }
 761
 762 /*
 763  * Finds the encoder associated with the given CRTC. This can only be
 764  * used when we know that the CRTC isn't feeding multiple encoders!
 765  */
 766 struct intel_encoder *
 767 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 768                            const struct intel_crtc_state *crtc_state)
 769 {
 770         const struct drm_connector_state *connector_state;
 771         const struct drm_connector *connector;
 772         struct intel_encoder *encoder = NULL;
 773         struct intel_crtc *master_crtc;
 774         int num_encoders = 0;
 775         int i;
 776
 777         master_crtc = intel_master_crtc(crtc_state);
 778
 779         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 780                 if (connector_state->crtc != &master_crtc->base)
 781                         continue;
 782
 783                 encoder = to_intel_encoder(connector_state->best_encoder);
 784                 num_encoders++;
 785         }
 786
 787         drm_WARN(state->base.dev, num_encoders != 1,
 788                  "%d encoders for pipe %c\n",
 789                  num_encoders, pipe_name(master_crtc->pipe));
 790
 791         return encoder;
 792 }
 793
 794 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 795 {
 796         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 797         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 798         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
 799         enum pipe pipe = crtc->pipe;
 800         int width = drm_rect_width(dst);
 801         int height = drm_rect_height(dst);
 802         int x = dst->x1;
 803         int y = dst->y1;
 804
 805         if (!crtc_state->pch_pfit.enabled)
 806                 return;
 807
 808         /* Force use of hard-coded filter coefficients
 809          * as some pre-programmed values are broken,
 810          * e.g. x201.
 811          */
 812         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
 813                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 814                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
 815         else
 816                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 817                                   PF_FILTER_MED_3x3);
 818         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
 819                           PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
 820         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
 821                           PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
 822 }
 823
 824 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 825 {
 826         if (crtc->overlay)
 827                 (void) intel_overlay_switch_off(crtc->overlay);
 828
 829         /* Let userspace switch the overlay on again. In most cases userspace
 830          * has to recompute where to put it anyway.
 831          */
 832 }
 833
 834 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 835 {
 836         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 837
 838         if (!crtc_state->nv12_planes)
 839                 return false;
 840
 841         /* WA Display #0827: Gen9:all */
 842         if (DISPLAY_VER(dev_priv) == 9)
 843                 return true;
 844
 845         return false;
 846 }
 847
 848 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 849 {
 850         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 851
 852         /* Wa_2006604312:icl,ehl */
 853         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
 854                 return true;
 855
 856         return false;
 857 }
 858
 859 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
 860 {
 861         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 862
 863         /* Wa_1604331009:icl,jsl,ehl */
 864         if (is_hdr_mode(crtc_state) &&
 865             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
 866             DISPLAY_VER(dev_priv) == 11)
 867                 return true;
 868
 869         return false;
 870 }
 871
 872 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
 873                                     enum pipe pipe, bool enable)
 874 {
 875         if (DISPLAY_VER(i915) == 9) {
 876                 /*
 877                  * "Plane N strech max must be programmed to 11b (x1)
 878                  *  when Async flips are enabled on that plane."
 879                  */
 880                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 881                              SKL_PLANE1_STRETCH_MAX_MASK,
 882                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
 883         } else {
 884                 /* Also needed on HSW/BDW albeit undocumented */
 885                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 886                              HSW_PRI_STRETCH_MAX_MASK,
 887                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
 888         }
 889 }
 890
 891 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
 892 {
 893         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 894
 895         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
 896                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
 897 }
 898
 899 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
 900         ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
 901          (new_crtc_state)->feature)
 902 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
 903         ((old_crtc_state)->feature && \
 904          (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
 905
 906 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 907                             const struct intel_crtc_state *new_crtc_state)
 908 {
 909         return is_enabling(active_planes, old_crtc_state, new_crtc_state);
 910 }
 911
 912 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
 913                              const struct intel_crtc_state *new_crtc_state)
 914 {
 915         return is_disabling(active_planes, old_crtc_state, new_crtc_state);
 916 }
 917
 918 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 919                                const struct intel_crtc_state *new_crtc_state)
 920 {
 921         return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
 922                 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
 923                 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
 924                 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
 925                 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
 926 }
 927
 928 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 929                          const struct intel_crtc_state *new_crtc_state)
 930 {
 931         return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
 932                 (new_crtc_state->vrr.enable &&
 933                  (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
 934                   vrr_params_changed(old_crtc_state, new_crtc_state)));
 935 }
 936
 937 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
 938                           const struct intel_crtc_state *new_crtc_state)
 939 {
 940         return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
 941                 (old_crtc_state->vrr.enable &&
 942                  (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
 943                   vrr_params_changed(old_crtc_state, new_crtc_state)));
 944 }
 945
 946 #undef is_disabling
 947 #undef is_enabling
 948
 949 static void intel_post_plane_update(struct intel_atomic_state *state,
 950                                     struct intel_crtc *crtc)
 951 {
 952         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 953         const struct intel_crtc_state *old_crtc_state =
 954                 intel_atomic_get_old_crtc_state(state, crtc);
 955         const struct intel_crtc_state *new_crtc_state =
 956                 intel_atomic_get_new_crtc_state(state, crtc);
 957         enum pipe pipe = crtc->pipe;
 958
 959         intel_psr_post_plane_update(state, crtc);
 960
 961         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 962
 963         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 964                 intel_update_watermarks(dev_priv);
 965
 966         intel_fbc_post_update(state, crtc);
 967
 968         if (needs_async_flip_vtd_wa(old_crtc_state) &&
 969             !needs_async_flip_vtd_wa(new_crtc_state))
 970                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
 971
 972         if (needs_nv12_wa(old_crtc_state) &&
 973             !needs_nv12_wa(new_crtc_state))
 974                 skl_wa_827(dev_priv, pipe, false);
 975
 976         if (needs_scalerclk_wa(old_crtc_state) &&
 977             !needs_scalerclk_wa(new_crtc_state))
 978                 icl_wa_scalerclkgating(dev_priv, pipe, false);
 979
 980         if (needs_cursorclk_wa(old_crtc_state) &&
 981             !needs_cursorclk_wa(new_crtc_state))
 982                 icl_wa_cursorclkgating(dev_priv, pipe, false);
 983
 984         if (intel_crtc_needs_color_update(new_crtc_state))
 985                 intel_color_post_update(new_crtc_state);
 986 }
 987
 988 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
 989                                         struct intel_crtc *crtc)
 990 {
 991         const struct intel_crtc_state *crtc_state =
 992                 intel_atomic_get_new_crtc_state(state, crtc);
 993         u8 update_planes = crtc_state->update_planes;
 994         const struct intel_plane_state __maybe_unused *plane_state;
 995         struct intel_plane *plane;
 996         int i;
 997
 998         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 999                 if (plane->pipe == crtc->pipe &&
1000                     update_planes & BIT(plane->id))
1001                         plane->enable_flip_done(plane);
1002         }
1003 }
1004
1005 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1006                                          struct intel_crtc *crtc)
1007 {
1008         const struct intel_crtc_state *crtc_state =
1009                 intel_atomic_get_new_crtc_state(state, crtc);
1010         u8 update_planes = crtc_state->update_planes;
1011         const struct intel_plane_state __maybe_unused *plane_state;
1012         struct intel_plane *plane;
1013         int i;
1014
1015         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1016                 if (plane->pipe == crtc->pipe &&
1017                     update_planes & BIT(plane->id))
1018                         plane->disable_flip_done(plane);
1019         }
1020 }
1021
1022 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1023                                              struct intel_crtc *crtc)
1024 {
1025         const struct intel_crtc_state *old_crtc_state =
1026                 intel_atomic_get_old_crtc_state(state, crtc);
1027         const struct intel_crtc_state *new_crtc_state =
1028                 intel_atomic_get_new_crtc_state(state, crtc);
1029         u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1030                                        ~new_crtc_state->async_flip_planes;
1031         const struct intel_plane_state *old_plane_state;
1032         struct intel_plane *plane;
1033         bool need_vbl_wait = false;
1034         int i;
1035
1036         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1037                 if (plane->need_async_flip_disable_wa &&
1038                     plane->pipe == crtc->pipe &&
1039                     disable_async_flip_planes & BIT(plane->id)) {
1040                         /*
1041                          * Apart from the async flip bit we want to
1042                          * preserve the old state for the plane.
1043                          */
1044                         plane->async_flip(plane, old_crtc_state,
1045                                           old_plane_state, false);
1046                         need_vbl_wait = true;
1047                 }
1048         }
1049
1050         if (need_vbl_wait)
1051                 intel_crtc_wait_for_next_vblank(crtc);
1052 }
1053
1054 static void intel_pre_plane_update(struct intel_atomic_state *state,
1055                                    struct intel_crtc *crtc)
1056 {
1057         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1058         const struct intel_crtc_state *old_crtc_state =
1059                 intel_atomic_get_old_crtc_state(state, crtc);
1060         const struct intel_crtc_state *new_crtc_state =
1061                 intel_atomic_get_new_crtc_state(state, crtc);
1062         enum pipe pipe = crtc->pipe;
1063
1064         if (vrr_disabling(old_crtc_state, new_crtc_state)) {
1065                 intel_vrr_disable(old_crtc_state);
1066                 intel_crtc_update_active_timings(old_crtc_state, false);
1067         }
1068
1069         intel_drrs_deactivate(old_crtc_state);
1070
1071         intel_psr_pre_plane_update(state, crtc);
1072
1073         if (hsw_ips_pre_update(state, crtc))
1074                 intel_crtc_wait_for_next_vblank(crtc);
1075
1076         if (intel_fbc_pre_update(state, crtc))
1077                 intel_crtc_wait_for_next_vblank(crtc);
1078
1079         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1080             needs_async_flip_vtd_wa(new_crtc_state))
1081                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1082
1083         /* Display WA 827 */
1084         if (!needs_nv12_wa(old_crtc_state) &&
1085             needs_nv12_wa(new_crtc_state))
1086                 skl_wa_827(dev_priv, pipe, true);
1087
1088         /* Wa_2006604312:icl,ehl */
1089         if (!needs_scalerclk_wa(old_crtc_state) &&
1090             needs_scalerclk_wa(new_crtc_state))
1091                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1092
1093         /* Wa_1604331009:icl,jsl,ehl */
1094         if (!needs_cursorclk_wa(old_crtc_state) &&
1095             needs_cursorclk_wa(new_crtc_state))
1096                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1097
1098         /*
1099          * Vblank time updates from the shadow to live plane control register
1100          * are blocked if the memory self-refresh mode is active at that
1101          * moment. So to make sure the plane gets truly disabled, disable
1102          * first the self-refresh mode. The self-refresh enable bit in turn
1103          * will be checked/applied by the HW only at the next frame start
1104          * event which is after the vblank start event, so we need to have a
1105          * wait-for-vblank between disabling the plane and the pipe.
1106          */
1107         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1108             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1109                 intel_crtc_wait_for_next_vblank(crtc);
1110
1111         /*
1112          * IVB workaround: must disable low power watermarks for at least
1113          * one frame before enabling scaling.  LP watermarks can be re-enabled
1114          * when scaling is disabled.
1115          *
1116          * WaCxSRDisabledForSpriteScaling:ivb
1117          */
1118         if (old_crtc_state->hw.active &&
1119             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1120                 intel_crtc_wait_for_next_vblank(crtc);
1121
1122         /*
1123          * If we're doing a modeset we don't need to do any
1124          * pre-vblank watermark programming here.
1125          */
1126         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1127                 /*
1128                  * For platforms that support atomic watermarks, program the
1129                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1130                  * will be the intermediate values that are safe for both pre- and
1131                  * post- vblank; when vblank happens, the 'active' values will be set
1132                  * to the final 'target' values and we'll do this again to get the
1133                  * optimal watermarks.  For gen9+ platforms, the values we program here
1134                  * will be the final target values which will get automatically latched
1135                  * at vblank time; no further programming will be necessary.
1136                  *
1137                  * If a platform hasn't been transitioned to atomic watermarks yet,
1138                  * we'll continue to update watermarks the old way, if flags tell
1139                  * us to.
1140                  */
1141                 if (!intel_initial_watermarks(state, crtc))
1142                         if (new_crtc_state->update_wm_pre)
1143                                 intel_update_watermarks(dev_priv);
1144         }
1145
1146         /*
1147          * Gen2 reports pipe underruns whenever all planes are disabled.
1148          * So disable underrun reporting before all the planes get disabled.
1149          *
1150          * We do this after .initial_watermarks() so that we have a
1151          * chance of catching underruns with the intermediate watermarks
1152          * vs. the old plane configuration.
1153          */
1154         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1155                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1156
1157         /*
1158          * WA for platforms where async address update enable bit
1159          * is double buffered and only latched at start of vblank.
1160          */
1161         if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1162                 intel_crtc_async_flip_disable_wa(state, crtc);
1163 }
1164
1165 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1166                                       struct intel_crtc *crtc)
1167 {
1168         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1169         const struct intel_crtc_state *new_crtc_state =
1170                 intel_atomic_get_new_crtc_state(state, crtc);
1171         unsigned int update_mask = new_crtc_state->update_planes;
1172         const struct intel_plane_state *old_plane_state;
1173         struct intel_plane *plane;
1174         unsigned fb_bits = 0;
1175         int i;
1176
1177         intel_crtc_dpms_overlay_disable(crtc);
1178
1179         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1180                 if (crtc->pipe != plane->pipe ||
1181                     !(update_mask & BIT(plane->id)))
1182                         continue;
1183
1184                 intel_plane_disable_arm(plane, new_crtc_state);
1185
1186                 if (old_plane_state->uapi.visible)
1187                         fb_bits |= plane->frontbuffer_bit;
1188         }
1189
1190         intel_frontbuffer_flip(dev_priv, fb_bits);
1191 }
1192
1193 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1194 {
1195         struct drm_i915_private *i915 = to_i915(state->base.dev);
1196         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1197         struct intel_crtc *crtc;
1198         int i;
1199
1200         /*
1201          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1202          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1203          */
1204         if (i915->display.dpll.mgr) {
1205                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1206                         if (intel_crtc_needs_modeset(new_crtc_state))
1207                                 continue;
1208
1209                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1210                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1211                 }
1212         }
1213 }
1214
1215 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1216                                           struct intel_crtc *crtc)
1217 {
1218         const struct intel_crtc_state *crtc_state =
1219                 intel_atomic_get_new_crtc_state(state, crtc);
1220         const struct drm_connector_state *conn_state;
1221         struct drm_connector *conn;
1222         int i;
1223
1224         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1225                 struct intel_encoder *encoder =
1226                         to_intel_encoder(conn_state->best_encoder);
1227
1228                 if (conn_state->crtc != &crtc->base)
1229                         continue;
1230
1231                 if (encoder->pre_pll_enable)
1232                         encoder->pre_pll_enable(state, encoder,
1233                                                 crtc_state, conn_state);
1234         }
1235 }
1236
1237 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1238                                       struct intel_crtc *crtc)
1239 {
1240         const struct intel_crtc_state *crtc_state =
1241                 intel_atomic_get_new_crtc_state(state, crtc);
1242         const struct drm_connector_state *conn_state;
1243         struct drm_connector *conn;
1244         int i;
1245
1246         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1247                 struct intel_encoder *encoder =
1248                         to_intel_encoder(conn_state->best_encoder);
1249
1250                 if (conn_state->crtc != &crtc->base)
1251                         continue;
1252
1253                 if (encoder->pre_enable)
1254                         encoder->pre_enable(state, encoder,
1255                                             crtc_state, conn_state);
1256         }
1257 }
1258
1259 static void intel_encoders_enable(struct intel_atomic_state *state,
1260                                   struct intel_crtc *crtc)
1261 {
1262         const struct intel_crtc_state *crtc_state =
1263                 intel_atomic_get_new_crtc_state(state, crtc);
1264         const struct drm_connector_state *conn_state;
1265         struct drm_connector *conn;
1266         int i;
1267
1268         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1269                 struct intel_encoder *encoder =
1270                         to_intel_encoder(conn_state->best_encoder);
1271
1272                 if (conn_state->crtc != &crtc->base)
1273                         continue;
1274
1275                 if (encoder->enable)
1276                         encoder->enable(state, encoder,
1277                                         crtc_state, conn_state);
1278                 intel_opregion_notify_encoder(encoder, true);
1279         }
1280 }
1281
1282 static void intel_encoders_disable(struct intel_atomic_state *state,
1283                                    struct intel_crtc *crtc)
1284 {
1285         const struct intel_crtc_state *old_crtc_state =
1286                 intel_atomic_get_old_crtc_state(state, crtc);
1287         const struct drm_connector_state *old_conn_state;
1288         struct drm_connector *conn;
1289         int i;
1290
1291         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1292                 struct intel_encoder *encoder =
1293                         to_intel_encoder(old_conn_state->best_encoder);
1294
1295                 if (old_conn_state->crtc != &crtc->base)
1296                         continue;
1297
1298                 intel_opregion_notify_encoder(encoder, false);
1299                 if (encoder->disable)
1300                         encoder->disable(state, encoder,
1301                                          old_crtc_state, old_conn_state);
1302         }
1303 }
1304
1305 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1306                                         struct intel_crtc *crtc)
1307 {
1308         const struct intel_crtc_state *old_crtc_state =
1309                 intel_atomic_get_old_crtc_state(state, crtc);
1310         const struct drm_connector_state *old_conn_state;
1311         struct drm_connector *conn;
1312         int i;
1313
1314         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1315                 struct intel_encoder *encoder =
1316                         to_intel_encoder(old_conn_state->best_encoder);
1317
1318                 if (old_conn_state->crtc != &crtc->base)
1319                         continue;
1320
1321                 if (encoder->post_disable)
1322                         encoder->post_disable(state, encoder,
1323                                               old_crtc_state, old_conn_state);
1324         }
1325 }
1326
1327 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1328                                             struct intel_crtc *crtc)
1329 {
1330         const struct intel_crtc_state *old_crtc_state =
1331                 intel_atomic_get_old_crtc_state(state, crtc);
1332         const struct drm_connector_state *old_conn_state;
1333         struct drm_connector *conn;
1334         int i;
1335
1336         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1337                 struct intel_encoder *encoder =
1338                         to_intel_encoder(old_conn_state->best_encoder);
1339
1340                 if (old_conn_state->crtc != &crtc->base)
1341                         continue;
1342
1343                 if (encoder->post_pll_disable)
1344                         encoder->post_pll_disable(state, encoder,
1345                                                   old_crtc_state, old_conn_state);
1346         }
1347 }
1348
1349 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1350                                        struct intel_crtc *crtc)
1351 {
1352         const struct intel_crtc_state *crtc_state =
1353                 intel_atomic_get_new_crtc_state(state, crtc);
1354         const struct drm_connector_state *conn_state;
1355         struct drm_connector *conn;
1356         int i;
1357
1358         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1359                 struct intel_encoder *encoder =
1360                         to_intel_encoder(conn_state->best_encoder);
1361
1362                 if (conn_state->crtc != &crtc->base)
1363                         continue;
1364
1365                 if (encoder->update_pipe)
1366                         encoder->update_pipe(state, encoder,
1367                                              crtc_state, conn_state);
1368         }
1369 }
1370
1371 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1372 {
1373         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1374         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1375
1376         plane->disable_arm(plane, crtc_state);
1377 }
1378
1379 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1380 {
1381         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1382         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1383
1384         if (crtc_state->has_pch_encoder) {
1385                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1386                                                &crtc_state->fdi_m_n);
1387         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1388                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1389                                                &crtc_state->dp_m_n);
1390                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1391                                                &crtc_state->dp_m2_n2);
1392         }
1393
1394         intel_set_transcoder_timings(crtc_state);
1395
1396         ilk_set_pipeconf(crtc_state);
1397 }
1398
1399 static void ilk_crtc_enable(struct intel_atomic_state *state,
1400                             struct intel_crtc *crtc)
1401 {
1402         const struct intel_crtc_state *new_crtc_state =
1403                 intel_atomic_get_new_crtc_state(state, crtc);
1404         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1405         enum pipe pipe = crtc->pipe;
1406
1407         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1408                 return;
1409
1410         /*
1411          * Sometimes spurious CPU pipe underruns happen during FDI
1412          * training, at least with VGA+HDMI cloning. Suppress them.
1413          *
1414          * On ILK we get an occasional spurious CPU pipe underruns
1415          * between eDP port A enable and vdd enable. Also PCH port
1416          * enable seems to result in the occasional CPU pipe underrun.
1417          *
1418          * Spurious PCH underruns also occur during PCH enabling.
1419          */
1420         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1421         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1422
1423         ilk_configure_cpu_transcoder(new_crtc_state);
1424
1425         intel_set_pipe_src_size(new_crtc_state);
1426
1427         crtc->active = true;
1428
1429         intel_encoders_pre_enable(state, crtc);
1430
1431         if (new_crtc_state->has_pch_encoder) {
1432                 ilk_pch_pre_enable(state, crtc);
1433         } else {
1434                 assert_fdi_tx_disabled(dev_priv, pipe);
1435                 assert_fdi_rx_disabled(dev_priv, pipe);
1436         }
1437
1438         ilk_pfit_enable(new_crtc_state);
1439
1440         /*
1441          * On ILK+ LUT must be loaded before the pipe is running but with
1442          * clocks enabled
1443          */
1444         intel_color_load_luts(new_crtc_state);
1445         intel_color_commit_noarm(new_crtc_state);
1446         intel_color_commit_arm(new_crtc_state);
1447         /* update DSPCNTR to configure gamma for pipe bottom color */
1448         intel_disable_primary_plane(new_crtc_state);
1449
1450         intel_initial_watermarks(state, crtc);
1451         intel_enable_transcoder(new_crtc_state);
1452
1453         if (new_crtc_state->has_pch_encoder)
1454                 ilk_pch_enable(state, crtc);
1455
1456         intel_crtc_vblank_on(new_crtc_state);
1457
1458         intel_encoders_enable(state, crtc);
1459
1460         if (HAS_PCH_CPT(dev_priv))
1461                 intel_wait_for_pipe_scanline_moving(crtc);
1462
1463         /*
1464          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1465          * And a second vblank wait is needed at least on ILK with
1466          * some interlaced HDMI modes. Let's do the double wait always
1467          * in case there are more corner cases we don't know about.
1468          */
1469         if (new_crtc_state->has_pch_encoder) {
1470                 intel_crtc_wait_for_next_vblank(crtc);
1471                 intel_crtc_wait_for_next_vblank(crtc);
1472         }
1473         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1474         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1475 }
1476
1477 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1478                                             enum pipe pipe, bool apply)
1479 {
1480         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1481         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1482
1483         if (apply)
1484                 val |= mask;
1485         else
1486                 val &= ~mask;
1487
1488         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1489 }
1490
1491 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1492 {
1493         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1494         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1495
1496         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1497                        HSW_LINETIME(crtc_state->linetime) |
1498                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1499 }
1500
1501 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1502 {
1503         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1504         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1505         enum transcoder transcoder = crtc_state->cpu_transcoder;
1506         i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
1507                          CHICKEN_TRANS(transcoder);
1508
1509         intel_de_rmw(dev_priv, reg,
1510                      HSW_FRAME_START_DELAY_MASK,
1511                      HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1512 }
1513
1514 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1515                                          const struct intel_crtc_state *crtc_state)
1516 {
1517         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1518
1519         /*
1520          * Enable sequence steps 1-7 on bigjoiner master
1521          */
1522         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1523                 intel_encoders_pre_pll_enable(state, master_crtc);
1524
1525         if (crtc_state->shared_dpll)
1526                 intel_enable_shared_dpll(crtc_state);
1527
1528         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1529                 intel_encoders_pre_enable(state, master_crtc);
1530 }
1531
1532 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1533 {
1534         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1535         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1537
1538         if (crtc_state->has_pch_encoder) {
1539                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1540                                                &crtc_state->fdi_m_n);
1541         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1542                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1543                                                &crtc_state->dp_m_n);
1544                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1545                                                &crtc_state->dp_m2_n2);
1546         }
1547
1548         intel_set_transcoder_timings(crtc_state);
1549         if (HAS_VRR(dev_priv))
1550                 intel_vrr_set_transcoder_timings(crtc_state);
1551
1552         if (cpu_transcoder != TRANSCODER_EDP)
1553                 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1554                                crtc_state->pixel_multiplier - 1);
1555
1556         hsw_set_frame_start_delay(crtc_state);
1557
1558         hsw_set_transconf(crtc_state);
1559 }
1560
1561 static void hsw_crtc_enable(struct intel_atomic_state *state,
1562                             struct intel_crtc *crtc)
1563 {
1564         const struct intel_crtc_state *new_crtc_state =
1565                 intel_atomic_get_new_crtc_state(state, crtc);
1566         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1567         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1568         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1569         bool psl_clkgate_wa;
1570
1571         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1572                 return;
1573
1574         intel_dmc_enable_pipe(dev_priv, crtc->pipe);
1575
1576         if (!new_crtc_state->bigjoiner_pipes) {
1577                 intel_encoders_pre_pll_enable(state, crtc);
1578
1579                 if (new_crtc_state->shared_dpll)
1580                         intel_enable_shared_dpll(new_crtc_state);
1581
1582                 intel_encoders_pre_enable(state, crtc);
1583         } else {
1584                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1585         }
1586
1587         intel_dsc_enable(new_crtc_state);
1588
1589         if (DISPLAY_VER(dev_priv) >= 13)
1590                 intel_uncompressed_joiner_enable(new_crtc_state);
1591
1592         intel_set_pipe_src_size(new_crtc_state);
1593         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1594                 bdw_set_pipe_misc(new_crtc_state);
1595
1596         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1597             !transcoder_is_dsi(cpu_transcoder))
1598                 hsw_configure_cpu_transcoder(new_crtc_state);
1599
1600         crtc->active = true;
1601
1602         /* Display WA #1180: WaDisableScalarClockGating: glk */
1603         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1604                 new_crtc_state->pch_pfit.enabled;
1605         if (psl_clkgate_wa)
1606                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1607
1608         if (DISPLAY_VER(dev_priv) >= 9)
1609                 skl_pfit_enable(new_crtc_state);
1610         else
1611                 ilk_pfit_enable(new_crtc_state);
1612
1613         /*
1614          * On ILK+ LUT must be loaded before the pipe is running but with
1615          * clocks enabled
1616          */
1617         intel_color_load_luts(new_crtc_state);
1618         intel_color_commit_noarm(new_crtc_state);
1619         intel_color_commit_arm(new_crtc_state);
1620         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1621         if (DISPLAY_VER(dev_priv) < 9)
1622                 intel_disable_primary_plane(new_crtc_state);
1623
1624         hsw_set_linetime_wm(new_crtc_state);
1625
1626         if (DISPLAY_VER(dev_priv) >= 11)
1627                 icl_set_pipe_chicken(new_crtc_state);
1628
1629         intel_initial_watermarks(state, crtc);
1630
1631         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1632                 intel_crtc_vblank_on(new_crtc_state);
1633
1634         intel_encoders_enable(state, crtc);
1635
1636         if (psl_clkgate_wa) {
1637                 intel_crtc_wait_for_next_vblank(crtc);
1638                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1639         }
1640
1641         /* If we change the relative order between pipe/planes enabling, we need
1642          * to change the workaround. */
1643         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1644         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1645                 struct intel_crtc *wa_crtc;
1646
1647                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1648
1649                 intel_crtc_wait_for_next_vblank(wa_crtc);
1650                 intel_crtc_wait_for_next_vblank(wa_crtc);
1651         }
1652 }
1653
1654 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1655 {
1656         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1657         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1658         enum pipe pipe = crtc->pipe;
1659
1660         /* To avoid upsetting the power well on haswell only disable the pfit if
1661          * it's in use. The hw state code will make sure we get this right. */
1662         if (!old_crtc_state->pch_pfit.enabled)
1663                 return;
1664
1665         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1666         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1667         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1668 }
1669
1670 static void ilk_crtc_disable(struct intel_atomic_state *state,
1671                              struct intel_crtc *crtc)
1672 {
1673         const struct intel_crtc_state *old_crtc_state =
1674                 intel_atomic_get_old_crtc_state(state, crtc);
1675         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1676         enum pipe pipe = crtc->pipe;
1677
1678         /*
1679          * Sometimes spurious CPU pipe underruns happen when the
1680          * pipe is already disabled, but FDI RX/TX is still enabled.
1681          * Happens at least with VGA+HDMI cloning. Suppress them.
1682          */
1683         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1684         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1685
1686         intel_encoders_disable(state, crtc);
1687
1688         intel_crtc_vblank_off(old_crtc_state);
1689
1690         intel_disable_transcoder(old_crtc_state);
1691
1692         ilk_pfit_disable(old_crtc_state);
1693
1694         if (old_crtc_state->has_pch_encoder)
1695                 ilk_pch_disable(state, crtc);
1696
1697         intel_encoders_post_disable(state, crtc);
1698
1699         if (old_crtc_state->has_pch_encoder)
1700                 ilk_pch_post_disable(state, crtc);
1701
1702         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1703         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1704
1705         intel_disable_shared_dpll(old_crtc_state);
1706 }
1707
1708 static void hsw_crtc_disable(struct intel_atomic_state *state,
1709                              struct intel_crtc *crtc)
1710 {
1711         const struct intel_crtc_state *old_crtc_state =
1712                 intel_atomic_get_old_crtc_state(state, crtc);
1713         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1714
1715         /*
1716          * FIXME collapse everything to one hook.
1717          * Need care with mst->ddi interactions.
1718          */
1719         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1720                 intel_encoders_disable(state, crtc);
1721                 intel_encoders_post_disable(state, crtc);
1722         }
1723
1724         intel_disable_shared_dpll(old_crtc_state);
1725
1726         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1727                 struct intel_crtc *slave_crtc;
1728
1729                 intel_encoders_post_pll_disable(state, crtc);
1730
1731                 intel_dmc_disable_pipe(i915, crtc->pipe);
1732
1733                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
1734                                                  intel_crtc_bigjoiner_slave_pipes(old_crtc_state))
1735                         intel_dmc_disable_pipe(i915, slave_crtc->pipe);
1736         }
1737 }
1738
1739 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1740 {
1741         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1742         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1743
1744         if (!crtc_state->gmch_pfit.control)
1745                 return;
1746
1747         /*
1748          * The panel fitter should only be adjusted whilst the pipe is disabled,
1749          * according to register description and PRM.
1750          */
1751         drm_WARN_ON(&dev_priv->drm,
1752                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1753         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1754
1755         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1756                        crtc_state->gmch_pfit.pgm_ratios);
1757         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1758
1759         /* Border color in case we don't scale up to the full screen. Black by
1760          * default, change to something else for debugging. */
1761         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1762 }
1763
1764 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1765 {
1766         if (phy == PHY_NONE)
1767                 return false;
1768         else if (IS_ALDERLAKE_S(dev_priv))
1769                 return phy <= PHY_E;
1770         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1771                 return phy <= PHY_D;
1772         else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
1773                 return phy <= PHY_C;
1774         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1775                 return phy <= PHY_B;
1776         else
1777                 /*
1778                  * DG2 outputs labelled as "combo PHY" in the bspec use
1779                  * SNPS PHYs with completely different programming,
1780                  * hence we always return false here.
1781                  */
1782                 return false;
1783 }
1784
1785 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1786 {
1787         if (IS_DG2(dev_priv))
1788                 /* DG2's "TC1" output uses a SNPS PHY */
1789                 return false;
1790         else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))
1791                 return phy >= PHY_F && phy <= PHY_I;
1792         else if (IS_TIGERLAKE(dev_priv))
1793                 return phy >= PHY_D && phy <= PHY_I;
1794         else if (IS_ICELAKE(dev_priv))
1795                 return phy >= PHY_C && phy <= PHY_F;
1796         else
1797                 return false;
1798 }
1799
1800 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1801 {
1802         if (phy == PHY_NONE)
1803                 return false;
1804         else if (IS_DG2(dev_priv))
1805                 /*
1806                  * All four "combo" ports and the TC1 port (PHY E) use
1807                  * Synopsis PHYs.
1808                  */
1809                 return phy <= PHY_E;
1810
1811         return false;
1812 }
1813
1814 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
1815 {
1816         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
1817                 return PHY_D + port - PORT_D_XELPD;
1818         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
1819                 return PHY_F + port - PORT_TC1;
1820         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1821                 return PHY_B + port - PORT_TC1;
1822         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1823                 return PHY_C + port - PORT_TC1;
1824         else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
1825                  port == PORT_D)
1826                 return PHY_A;
1827
1828         return PHY_A + port - PORT_A;
1829 }
1830
1831 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1832 {
1833         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1834                 return TC_PORT_NONE;
1835
1836         if (DISPLAY_VER(dev_priv) >= 12)
1837                 return TC_PORT_1 + port - PORT_TC1;
1838         else
1839                 return TC_PORT_1 + port - PORT_C;
1840 }
1841
1842 enum intel_display_power_domain
1843 intel_aux_power_domain(struct intel_digital_port *dig_port)
1844 {
1845         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1846
1847         if (intel_tc_port_in_tbt_alt_mode(dig_port))
1848                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
1849
1850         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
1851 }
1852
1853 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1854                                    struct intel_power_domain_mask *mask)
1855 {
1856         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1857         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1858         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1859         struct drm_encoder *encoder;
1860         enum pipe pipe = crtc->pipe;
1861
1862         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1863
1864         if (!crtc_state->hw.active)
1865                 return;
1866
1867         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1868         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1869         if (crtc_state->pch_pfit.enabled ||
1870             crtc_state->pch_pfit.force_thru)
1871                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1872
1873         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
1874                                   crtc_state->uapi.encoder_mask) {
1875                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1876
1877                 set_bit(intel_encoder->power_domain, mask->bits);
1878         }
1879
1880         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
1881                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
1882
1883         if (crtc_state->shared_dpll)
1884                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
1885
1886         if (crtc_state->dsc.compression_enable)
1887                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
1888 }
1889
1890 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1891                                           struct intel_power_domain_mask *old_domains)
1892 {
1893         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1894         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1895         enum intel_display_power_domain domain;
1896         struct intel_power_domain_mask domains, new_domains;
1897
1898         get_crtc_power_domains(crtc_state, &domains);
1899
1900         bitmap_andnot(new_domains.bits,
1901                       domains.bits,
1902                       crtc->enabled_power_domains.mask.bits,
1903                       POWER_DOMAIN_NUM);
1904         bitmap_andnot(old_domains->bits,
1905                       crtc->enabled_power_domains.mask.bits,
1906                       domains.bits,
1907                       POWER_DOMAIN_NUM);
1908
1909         for_each_power_domain(domain, &new_domains)
1910                 intel_display_power_get_in_set(dev_priv,
1911                                                &crtc->enabled_power_domains,
1912                                                domain);
1913 }
1914
1915 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
1916                                           struct intel_power_domain_mask *domains)
1917 {
1918         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
1919                                             &crtc->enabled_power_domains,
1920                                             domains);
1921 }
1922
1923 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1924 {
1925         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1926         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1927
1928         if (intel_crtc_has_dp_encoder(crtc_state)) {
1929                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1930                                                &crtc_state->dp_m_n);
1931                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1932                                                &crtc_state->dp_m2_n2);
1933         }
1934
1935         intel_set_transcoder_timings(crtc_state);
1936
1937         i9xx_set_pipeconf(crtc_state);
1938 }
1939
1940 static void valleyview_crtc_enable(struct intel_atomic_state *state,
1941                                    struct intel_crtc *crtc)
1942 {
1943         const struct intel_crtc_state *new_crtc_state =
1944                 intel_atomic_get_new_crtc_state(state, crtc);
1945         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1946         enum pipe pipe = crtc->pipe;
1947
1948         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1949                 return;
1950
1951         i9xx_configure_cpu_transcoder(new_crtc_state);
1952
1953         intel_set_pipe_src_size(new_crtc_state);
1954
1955         intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
1956
1957         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1958                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
1959                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
1960         }
1961
1962         crtc->active = true;
1963
1964         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1965
1966         intel_encoders_pre_pll_enable(state, crtc);
1967
1968         if (IS_CHERRYVIEW(dev_priv))
1969                 chv_enable_pll(new_crtc_state);
1970         else
1971                 vlv_enable_pll(new_crtc_state);
1972
1973         intel_encoders_pre_enable(state, crtc);
1974
1975         i9xx_pfit_enable(new_crtc_state);
1976
1977         intel_color_load_luts(new_crtc_state);
1978         intel_color_commit_noarm(new_crtc_state);
1979         intel_color_commit_arm(new_crtc_state);
1980         /* update DSPCNTR to configure gamma for pipe bottom color */
1981         intel_disable_primary_plane(new_crtc_state);
1982
1983         intel_initial_watermarks(state, crtc);
1984         intel_enable_transcoder(new_crtc_state);
1985
1986         intel_crtc_vblank_on(new_crtc_state);
1987
1988         intel_encoders_enable(state, crtc);
1989 }
1990
1991 static void i9xx_crtc_enable(struct intel_atomic_state *state,
1992                              struct intel_crtc *crtc)
1993 {
1994         const struct intel_crtc_state *new_crtc_state =
1995                 intel_atomic_get_new_crtc_state(state, crtc);
1996         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1997         enum pipe pipe = crtc->pipe;
1998
1999         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
2000                 return;
2001
2002         i9xx_configure_cpu_transcoder(new_crtc_state);
2003
2004         intel_set_pipe_src_size(new_crtc_state);
2005
2006         crtc->active = true;
2007
2008         if (DISPLAY_VER(dev_priv) != 2)
2009                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2010
2011         intel_encoders_pre_enable(state, crtc);
2012
2013         i9xx_enable_pll(new_crtc_state);
2014
2015         i9xx_pfit_enable(new_crtc_state);
2016
2017         intel_color_load_luts(new_crtc_state);
2018         intel_color_commit_noarm(new_crtc_state);
2019         intel_color_commit_arm(new_crtc_state);
2020         /* update DSPCNTR to configure gamma for pipe bottom color */
2021         intel_disable_primary_plane(new_crtc_state);
2022
2023         if (!intel_initial_watermarks(state, crtc))
2024                 intel_update_watermarks(dev_priv);
2025         intel_enable_transcoder(new_crtc_state);
2026
2027         intel_crtc_vblank_on(new_crtc_state);
2028
2029         intel_encoders_enable(state, crtc);
2030
2031         /* prevents spurious underruns */
2032         if (DISPLAY_VER(dev_priv) == 2)
2033                 intel_crtc_wait_for_next_vblank(crtc);
2034 }
2035
2036 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2037 {
2038         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2039         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2040
2041         if (!old_crtc_state->gmch_pfit.control)
2042                 return;
2043
2044         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2045
2046         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2047                     intel_de_read(dev_priv, PFIT_CONTROL));
2048         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2049 }
2050
2051 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2052                               struct intel_crtc *crtc)
2053 {
2054         struct intel_crtc_state *old_crtc_state =
2055                 intel_atomic_get_old_crtc_state(state, crtc);
2056         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2057         enum pipe pipe = crtc->pipe;
2058
2059         /*
2060          * On gen2 planes are double buffered but the pipe isn't, so we must
2061          * wait for planes to fully turn off before disabling the pipe.
2062          */
2063         if (DISPLAY_VER(dev_priv) == 2)
2064                 intel_crtc_wait_for_next_vblank(crtc);
2065
2066         intel_encoders_disable(state, crtc);
2067
2068         intel_crtc_vblank_off(old_crtc_state);
2069
2070         intel_disable_transcoder(old_crtc_state);
2071
2072         i9xx_pfit_disable(old_crtc_state);
2073
2074         intel_encoders_post_disable(state, crtc);
2075
2076         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2077                 if (IS_CHERRYVIEW(dev_priv))
2078                         chv_disable_pll(dev_priv, pipe);
2079                 else if (IS_VALLEYVIEW(dev_priv))
2080                         vlv_disable_pll(dev_priv, pipe);
2081                 else
2082                         i9xx_disable_pll(old_crtc_state);
2083         }
2084
2085         intel_encoders_post_pll_disable(state, crtc);
2086
2087         if (DISPLAY_VER(dev_priv) != 2)
2088                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2089
2090         if (!dev_priv->display.funcs.wm->initial_watermarks)
2091                 intel_update_watermarks(dev_priv);
2092
2093         /* clock the pipe down to 640x480@60 to potentially save power */
2094         if (IS_I830(dev_priv))
2095                 i830_enable_pipe(dev_priv, pipe);
2096 }
2097
2098 void intel_encoder_destroy(struct drm_encoder *encoder)
2099 {
2100         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2101
2102         drm_encoder_cleanup(encoder);
2103         kfree(intel_encoder);
2104 }
2105
2106 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2107 {
2108         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2109
2110         /* GDG double wide on either pipe, otherwise pipe A only */
2111         return DISPLAY_VER(dev_priv) < 4 &&
2112                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2113 }
2114
2115 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2116 {
2117         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2118         struct drm_rect src;
2119
2120         /*
2121          * We only use IF-ID interlacing. If we ever use
2122          * PF-ID we'll need to adjust the pixel_rate here.
2123          */
2124
2125         if (!crtc_state->pch_pfit.enabled)
2126                 return pixel_rate;
2127
2128         drm_rect_init(&src, 0, 0,
2129                       drm_rect_width(&crtc_state->pipe_src) << 16,
2130                       drm_rect_height(&crtc_state->pipe_src) << 16);
2131
2132         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2133                                    pixel_rate);
2134 }
2135
2136 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2137                                          const struct drm_display_mode *timings)
2138 {
2139         mode->hdisplay = timings->crtc_hdisplay;
2140         mode->htotal = timings->crtc_htotal;
2141         mode->hsync_start = timings->crtc_hsync_start;
2142         mode->hsync_end = timings->crtc_hsync_end;
2143
2144         mode->vdisplay = timings->crtc_vdisplay;
2145         mode->vtotal = timings->crtc_vtotal;
2146         mode->vsync_start = timings->crtc_vsync_start;
2147         mode->vsync_end = timings->crtc_vsync_end;
2148
2149         mode->flags = timings->flags;
2150         mode->type = DRM_MODE_TYPE_DRIVER;
2151
2152         mode->clock = timings->crtc_clock;
2153
2154         drm_mode_set_name(mode);
2155 }
2156
2157 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2158 {
2159         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2160
2161         if (HAS_GMCH(dev_priv))
2162                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2163                 crtc_state->pixel_rate =
2164                         crtc_state->hw.pipe_mode.crtc_clock;
2165         else
2166                 crtc_state->pixel_rate =
2167                         ilk_pipe_pixel_rate(crtc_state);
2168 }
2169
2170 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2171                                            struct drm_display_mode *mode)
2172 {
2173         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2174
2175         if (num_pipes < 2)
2176                 return;
2177
2178         mode->crtc_clock /= num_pipes;
2179         mode->crtc_hdisplay /= num_pipes;
2180         mode->crtc_hblank_start /= num_pipes;
2181         mode->crtc_hblank_end /= num_pipes;
2182         mode->crtc_hsync_start /= num_pipes;
2183         mode->crtc_hsync_end /= num_pipes;
2184         mode->crtc_htotal /= num_pipes;
2185 }
2186
2187 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2188                                           struct drm_display_mode *mode)
2189 {
2190         int overlap = crtc_state->splitter.pixel_overlap;
2191         int n = crtc_state->splitter.link_count;
2192
2193         if (!crtc_state->splitter.enable)
2194                 return;
2195
2196         /*
2197          * eDP MSO uses segment timings from EDID for transcoder
2198          * timings, but full mode for everything else.
2199          *
2200          * h_full = (h_segment - pixel_overlap) * link_count
2201          */
2202         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2203         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2204         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2205         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2206         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2207         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2208         mode->crtc_clock *= n;
2209 }
2210
2211 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2212 {
2213         struct drm_display_mode *mode = &crtc_state->hw.mode;
2214         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2215         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2216
2217         /*
2218          * Start with the adjusted_mode crtc timings, which
2219          * have been filled with the transcoder timings.
2220          */
2221         drm_mode_copy(pipe_mode, adjusted_mode);
2222
2223         /* Expand MSO per-segment transcoder timings to full */
2224         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2225
2226         /*
2227          * We want the full numbers in adjusted_mode normal timings,
2228          * adjusted_mode crtc timings are left with the raw transcoder
2229          * timings.
2230          */
2231         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2232
2233         /* Populate the "user" mode with full numbers */
2234         drm_mode_copy(mode, pipe_mode);
2235         intel_mode_from_crtc_timings(mode, mode);
2236         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2237                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2238         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2239
2240         /* Derive per-pipe timings in case bigjoiner is used */
2241         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2242         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2243
2244         intel_crtc_compute_pixel_rate(crtc_state);
2245 }
2246
2247 void intel_encoder_get_config(struct intel_encoder *encoder,
2248                               struct intel_crtc_state *crtc_state)
2249 {
2250         encoder->get_config(encoder, crtc_state);
2251
2252         intel_crtc_readout_derived_state(crtc_state);
2253 }
2254
2255 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2256 {
2257         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2258         int width, height;
2259
2260         if (num_pipes < 2)
2261                 return;
2262
2263         width = drm_rect_width(&crtc_state->pipe_src);
2264         height = drm_rect_height(&crtc_state->pipe_src);
2265
2266         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2267                       width / num_pipes, height);
2268 }
2269
2270 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2271 {
2272         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2273         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2274
2275         intel_bigjoiner_compute_pipe_src(crtc_state);
2276
2277         /*
2278          * Pipe horizontal size must be even in:
2279          * - DVO ganged mode
2280          * - LVDS dual channel mode
2281          * - Double wide pipe
2282          */
2283         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2284                 if (crtc_state->double_wide) {
2285                         drm_dbg_kms(&i915->drm,
2286                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2287                                     crtc->base.base.id, crtc->base.name);
2288                         return -EINVAL;
2289                 }
2290
2291                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2292                     intel_is_dual_link_lvds(i915)) {
2293                         drm_dbg_kms(&i915->drm,
2294                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2295                                     crtc->base.base.id, crtc->base.name);
2296                         return -EINVAL;
2297                 }
2298         }
2299
2300         return 0;
2301 }
2302
2303 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2304 {
2305         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2306         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2307         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2308         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2309         int clock_limit = i915->max_dotclk_freq;
2310
2311         /*
2312          * Start with the adjusted_mode crtc timings, which
2313          * have been filled with the transcoder timings.
2314          */
2315         drm_mode_copy(pipe_mode, adjusted_mode);
2316
2317         /* Expand MSO per-segment transcoder timings to full */
2318         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2319
2320         /* Derive per-pipe timings in case bigjoiner is used */
2321         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2322         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2323
2324         if (DISPLAY_VER(i915) < 4) {
2325                 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2326
2327                 /*
2328                  * Enable double wide mode when the dot clock
2329                  * is > 90% of the (display) core speed.
2330                  */
2331                 if (intel_crtc_supports_double_wide(crtc) &&
2332                     pipe_mode->crtc_clock > clock_limit) {
2333                         clock_limit = i915->max_dotclk_freq;
2334                         crtc_state->double_wide = true;
2335                 }
2336         }
2337
2338         if (pipe_mode->crtc_clock > clock_limit) {
2339                 drm_dbg_kms(&i915->drm,
2340                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2341                             crtc->base.base.id, crtc->base.name,
2342                             pipe_mode->crtc_clock, clock_limit,
2343                             str_yes_no(crtc_state->double_wide));
2344                 return -EINVAL;
2345         }
2346
2347         return 0;
2348 }
2349
2350 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2351                                      struct intel_crtc *crtc)
2352 {
2353         struct intel_crtc_state *crtc_state =
2354                 intel_atomic_get_new_crtc_state(state, crtc);
2355         int ret;
2356
2357         ret = intel_dpll_crtc_compute_clock(state, crtc);
2358         if (ret)
2359                 return ret;
2360
2361         ret = intel_crtc_compute_pipe_src(crtc_state);
2362         if (ret)
2363                 return ret;
2364
2365         ret = intel_crtc_compute_pipe_mode(crtc_state);
2366         if (ret)
2367                 return ret;
2368
2369         intel_crtc_compute_pixel_rate(crtc_state);
2370
2371         if (crtc_state->has_pch_encoder)
2372                 return ilk_fdi_compute_config(crtc, crtc_state);
2373
2374         return 0;
2375 }
2376
2377 static void
2378 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2379 {
2380         while (*num > DATA_LINK_M_N_MASK ||
2381                *den > DATA_LINK_M_N_MASK) {
2382                 *num >>= 1;
2383                 *den >>= 1;
2384         }
2385 }
2386
2387 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2388                         u32 m, u32 n, u32 constant_n)
2389 {
2390         if (constant_n)
2391                 *ret_n = constant_n;
2392         else
2393                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2394
2395         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2396         intel_reduce_m_n_ratio(ret_m, ret_n);
2397 }
2398
2399 void
2400 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2401                        int pixel_clock, int link_clock,
2402                        struct intel_link_m_n *m_n,
2403                        bool fec_enable)
2404 {
2405         u32 data_clock = bits_per_pixel * pixel_clock;
2406
2407         if (fec_enable)
2408                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2409
2410         /*
2411          * Windows/BIOS uses fixed M/N values always. Follow suit.
2412          *
2413          * Also several DP dongles in particular seem to be fussy
2414          * about too large link M/N values. Presumably the 20bit
2415          * value used by Windows/BIOS is acceptable to everyone.
2416          */
2417         m_n->tu = 64;
2418         compute_m_n(&m_n->data_m, &m_n->data_n,
2419                     data_clock, link_clock * nlanes * 8,
2420                     0x8000000);
2421
2422         compute_m_n(&m_n->link_m, &m_n->link_n,
2423                     pixel_clock, link_clock,
2424                     0x80000);
2425 }
2426
2427 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2428 {
2429         /*
2430          * There may be no VBT; and if the BIOS enabled SSC we can
2431          * just keep using it to avoid unnecessary flicker.  Whereas if the
2432          * BIOS isn't using it, don't assume it will work even if the VBT
2433          * indicates as much.
2434          */
2435         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2436                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2437                                                        PCH_DREF_CONTROL) &
2438                         DREF_SSC1_ENABLE;
2439
2440                 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2441                         drm_dbg_kms(&dev_priv->drm,
2442                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2443                                     str_enabled_disabled(bios_lvds_use_ssc),
2444                                     str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2445                         dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2446                 }
2447         }
2448 }
2449
2450 void intel_zero_m_n(struct intel_link_m_n *m_n)
2451 {
2452         /* corresponds to 0 register value */
2453         memset(m_n, 0, sizeof(*m_n));
2454         m_n->tu = 1;
2455 }
2456
2457 void intel_set_m_n(struct drm_i915_private *i915,
2458                    const struct intel_link_m_n *m_n,
2459                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2460                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2461 {
2462         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2463         intel_de_write(i915, data_n_reg, m_n->data_n);
2464         intel_de_write(i915, link_m_reg, m_n->link_m);
2465         /*
2466          * On BDW+ writing LINK_N arms the double buffered update
2467          * of all the M/N registers, so it must be written last.
2468          */
2469         intel_de_write(i915, link_n_reg, m_n->link_n);
2470 }
2471
2472 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2473                                     enum transcoder transcoder)
2474 {
2475         if (IS_HASWELL(dev_priv))
2476                 return transcoder == TRANSCODER_EDP;
2477
2478         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2479 }
2480
2481 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2482                                     enum transcoder transcoder,
2483                                     const struct intel_link_m_n *m_n)
2484 {
2485         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2486         enum pipe pipe = crtc->pipe;
2487
2488         if (DISPLAY_VER(dev_priv) >= 5)
2489                 intel_set_m_n(dev_priv, m_n,
2490                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2491                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2492         else
2493                 intel_set_m_n(dev_priv, m_n,
2494                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2495                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2496 }
2497
2498 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2499                                     enum transcoder transcoder,
2500                                     const struct intel_link_m_n *m_n)
2501 {
2502         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2503
2504         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2505                 return;
2506
2507         intel_set_m_n(dev_priv, m_n,
2508                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2509                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2510 }
2511
2512 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2513 {
2514         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2515         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2516         enum pipe pipe = crtc->pipe;
2517         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2518         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2519         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2520         int vsyncshift = 0;
2521
2522         /* We need to be careful not to changed the adjusted mode, for otherwise
2523          * the hw state checker will get angry at the mismatch. */
2524         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2525         crtc_vtotal = adjusted_mode->crtc_vtotal;
2526         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2527         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2528
2529         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2530                 /* the chip adds 2 halflines automatically */
2531                 crtc_vtotal -= 1;
2532                 crtc_vblank_end -= 1;
2533
2534                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2535                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2536                 else
2537                         vsyncshift = adjusted_mode->crtc_hsync_start -
2538                                 adjusted_mode->crtc_htotal / 2;
2539                 if (vsyncshift < 0)
2540                         vsyncshift += adjusted_mode->crtc_htotal;
2541         }
2542
2543         /*
2544          * VBLANK_START no longer works on ADL+, instead we must use
2545          * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2546          */
2547         if (DISPLAY_VER(dev_priv) >= 13) {
2548                 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2549                                crtc_vblank_start - crtc_vdisplay);
2550
2551                 /*
2552                  * VBLANK_START not used by hw, just clear it
2553                  * to make it stand out in register dumps.
2554                  */
2555                 crtc_vblank_start = 1;
2556         }
2557
2558         if (DISPLAY_VER(dev_priv) > 3)
2559                 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2560                                vsyncshift);
2561
2562         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2563                        HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2564                        HTOTAL(adjusted_mode->crtc_htotal - 1));
2565         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2566                        HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2567                        HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2568         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2569                        HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2570                        HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2571
2572         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2573                        VACTIVE(crtc_vdisplay - 1) |
2574                        VTOTAL(crtc_vtotal - 1));
2575         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2576                        VBLANK_START(crtc_vblank_start - 1) |
2577                        VBLANK_END(crtc_vblank_end - 1));
2578         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2579                        VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2580                        VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2581
2582         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2583          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2584          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2585          * bits. */
2586         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2587             (pipe == PIPE_B || pipe == PIPE_C))
2588                 intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2589                                VACTIVE(crtc_vdisplay - 1) |
2590                                VTOTAL(crtc_vtotal - 1));
2591 }
2592
2593 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2594 {
2595         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2596         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2597         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2598         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2599         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2600
2601         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2602         crtc_vtotal = adjusted_mode->crtc_vtotal;
2603         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2604         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2605
2606         drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
2607
2608         /*
2609          * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2610          * But let's write it anyway to keep the state checker happy.
2611          */
2612         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2613                        VBLANK_START(crtc_vblank_start - 1) |
2614                        VBLANK_END(crtc_vblank_end - 1));
2615         /*
2616          * The double buffer latch point for TRANS_VTOTAL
2617          * is the transcoder's undelayed vblank.
2618          */
2619         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2620                        VACTIVE(crtc_vdisplay - 1) |
2621                        VTOTAL(crtc_vtotal - 1));
2622 }
2623
2624 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2625 {
2626         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2627         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2628         int width = drm_rect_width(&crtc_state->pipe_src);
2629         int height = drm_rect_height(&crtc_state->pipe_src);
2630         enum pipe pipe = crtc->pipe;
2631
2632         /* pipesrc controls the size that is scaled from, which should
2633          * always be the user's requested size.
2634          */
2635         intel_de_write(dev_priv, PIPESRC(pipe),
2636                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2637 }
2638
2639 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2640 {
2641         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2642         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2643
2644         if (DISPLAY_VER(dev_priv) == 2)
2645                 return false;
2646
2647         if (DISPLAY_VER(dev_priv) >= 9 ||
2648             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2649                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2650         else
2651                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2652 }
2653
2654 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2655                                          struct intel_crtc_state *pipe_config)
2656 {
2657         struct drm_device *dev = crtc->base.dev;
2658         struct drm_i915_private *dev_priv = to_i915(dev);
2659         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2660         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2661         u32 tmp;
2662
2663         tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2664         adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2665         adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2666
2667         if (!transcoder_is_dsi(cpu_transcoder)) {
2668                 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2669                 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2670                 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2671         }
2672
2673         tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2674         adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2675         adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2676
2677         tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2678         adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2679         adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2680
2681         /* FIXME TGL+ DSI transcoders have this! */
2682         if (!transcoder_is_dsi(cpu_transcoder)) {
2683                 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2684                 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2685                 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2686         }
2687         tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2688         adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2689         adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2690
2691         if (intel_pipe_is_interlaced(pipe_config)) {
2692                 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2693                 adjusted_mode->crtc_vtotal += 1;
2694                 adjusted_mode->crtc_vblank_end += 1;
2695         }
2696
2697         if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2698                 adjusted_mode->crtc_vblank_start =
2699                         adjusted_mode->crtc_vdisplay +
2700                         intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2701 }
2702
2703 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2704 {
2705         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2706         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2707         enum pipe master_pipe, pipe = crtc->pipe;
2708         int width;
2709
2710         if (num_pipes < 2)
2711                 return;
2712
2713         master_pipe = bigjoiner_master_pipe(crtc_state);
2714         width = drm_rect_width(&crtc_state->pipe_src);
2715
2716         drm_rect_translate_to(&crtc_state->pipe_src,
2717                               (pipe - master_pipe) * width, 0);
2718 }
2719
2720 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2721                                     struct intel_crtc_state *pipe_config)
2722 {
2723         struct drm_device *dev = crtc->base.dev;
2724         struct drm_i915_private *dev_priv = to_i915(dev);
2725         u32 tmp;
2726
2727         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2728
2729         drm_rect_init(&pipe_config->pipe_src, 0, 0,
2730                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2731                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2732
2733         intel_bigjoiner_adjust_pipe_src(pipe_config);
2734 }
2735
2736 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2737 {
2738         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2739         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2740         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2741         u32 val = 0;
2742
2743         /*
2744          * - We keep both pipes enabled on 830
2745          * - During modeset the pipe is still disabled and must remain so
2746          * - During fastset the pipe is already enabled and must remain so
2747          */
2748         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2749                 val |= TRANSCONF_ENABLE;
2750
2751         if (crtc_state->double_wide)
2752                 val |= TRANSCONF_DOUBLE_WIDE;
2753
2754         /* only g4x and later have fancy bpc/dither controls */
2755         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2756             IS_CHERRYVIEW(dev_priv)) {
2757                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2758                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2759                         val |= TRANSCONF_DITHER_EN |
2760                                 TRANSCONF_DITHER_TYPE_SP;
2761
2762                 switch (crtc_state->pipe_bpp) {
2763                 default:
2764                         /* Case prevented by intel_choose_pipe_bpp_dither. */
2765                         MISSING_CASE(crtc_state->pipe_bpp);
2766                         fallthrough;
2767                 case 18:
2768                         val |= TRANSCONF_BPC_6;
2769                         break;
2770                 case 24:
2771                         val |= TRANSCONF_BPC_8;
2772                         break;
2773                 case 30:
2774                         val |= TRANSCONF_BPC_10;
2775                         break;
2776                 }
2777         }
2778
2779         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2780                 if (DISPLAY_VER(dev_priv) < 4 ||
2781                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2782                         val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2783                 else
2784                         val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2785         } else {
2786                 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2787         }
2788
2789         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2790              crtc_state->limited_color_range)
2791                 val |= TRANSCONF_COLOR_RANGE_SELECT;
2792
2793         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2794
2795         if (crtc_state->wgc_enable)
2796                 val |= TRANSCONF_WGC_ENABLE;
2797
2798         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2799
2800         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2801         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2802 }
2803
2804 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2805 {
2806         if (IS_I830(dev_priv))
2807                 return false;
2808
2809         return DISPLAY_VER(dev_priv) >= 4 ||
2810                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2811 }
2812
2813 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2814 {
2815         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2816         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2817         enum pipe pipe;
2818         u32 tmp;
2819
2820         if (!i9xx_has_pfit(dev_priv))
2821                 return;
2822
2823         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2824         if (!(tmp & PFIT_ENABLE))
2825                 return;
2826
2827         /* Check whether the pfit is attached to our pipe. */
2828         if (DISPLAY_VER(dev_priv) >= 4)
2829                 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
2830         else
2831                 pipe = PIPE_B;
2832
2833         if (pipe != crtc->pipe)
2834                 return;
2835
2836         crtc_state->gmch_pfit.control = tmp;
2837         crtc_state->gmch_pfit.pgm_ratios =
2838                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2839 }
2840
2841 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
2842                                struct intel_crtc_state *pipe_config)
2843 {
2844         struct drm_device *dev = crtc->base.dev;
2845         struct drm_i915_private *dev_priv = to_i915(dev);
2846         enum pipe pipe = crtc->pipe;
2847         struct dpll clock;
2848         u32 mdiv;
2849         int refclk = 100000;
2850
2851         /* In case of DSI, DPLL will not be used */
2852         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2853                 return;
2854
2855         vlv_dpio_get(dev_priv);
2856         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
2857         vlv_dpio_put(dev_priv);
2858
2859         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
2860         clock.m2 = mdiv & DPIO_M2DIV_MASK;
2861         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
2862         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
2863         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
2864
2865         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
2866 }
2867
2868 static void chv_crtc_clock_get(struct intel_crtc *crtc,
2869                                struct intel_crtc_state *pipe_config)
2870 {
2871         struct drm_device *dev = crtc->base.dev;
2872         struct drm_i915_private *dev_priv = to_i915(dev);
2873         enum pipe pipe = crtc->pipe;
2874         enum dpio_channel port = vlv_pipe_to_channel(pipe);
2875         struct dpll clock;
2876         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
2877         int refclk = 100000;
2878
2879         /* In case of DSI, DPLL will not be used */
2880         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2881                 return;
2882
2883         vlv_dpio_get(dev_priv);
2884         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
2885         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
2886         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
2887         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
2888         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
2889         vlv_dpio_put(dev_priv);
2890
2891         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
2892         clock.m2 = (pll_dw0 & 0xff) << 22;
2893         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
2894                 clock.m2 |= pll_dw2 & 0x3fffff;
2895         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
2896         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
2897         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
2898
2899         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
2900 }
2901
2902 static enum intel_output_format
2903 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2904 {
2905         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2906         u32 tmp;
2907
2908         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
2909
2910         if (tmp & PIPE_MISC_YUV420_ENABLE) {
2911                 /* We support 4:2:0 in full blend mode only */
2912                 drm_WARN_ON(&dev_priv->drm,
2913                             (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
2914
2915                 return INTEL_OUTPUT_FORMAT_YCBCR420;
2916         } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
2917                 return INTEL_OUTPUT_FORMAT_YCBCR444;
2918         } else {
2919                 return INTEL_OUTPUT_FORMAT_RGB;
2920         }
2921 }
2922
2923 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
2924                                  struct intel_crtc_state *pipe_config)
2925 {
2926         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2927         enum intel_display_power_domain power_domain;
2928         intel_wakeref_t wakeref;
2929         u32 tmp;
2930         bool ret;
2931
2932         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
2933         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
2934         if (!wakeref)
2935                 return false;
2936
2937         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2938         pipe_config->sink_format = pipe_config->output_format;
2939         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
2940         pipe_config->shared_dpll = NULL;
2941
2942         ret = false;
2943
2944         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
2945         if (!(tmp & TRANSCONF_ENABLE))
2946                 goto out;
2947
2948         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2949             IS_CHERRYVIEW(dev_priv)) {
2950                 switch (tmp & TRANSCONF_BPC_MASK) {
2951                 case TRANSCONF_BPC_6:
2952                         pipe_config->pipe_bpp = 18;
2953                         break;
2954                 case TRANSCONF_BPC_8:
2955                         pipe_config->pipe_bpp = 24;
2956                         break;
2957                 case TRANSCONF_BPC_10:
2958                         pipe_config->pipe_bpp = 30;
2959                         break;
2960                 default:
2961                         MISSING_CASE(tmp);
2962                         break;
2963                 }
2964         }
2965
2966         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2967             (tmp & TRANSCONF_COLOR_RANGE_SELECT))
2968                 pipe_config->limited_color_range = true;
2969
2970         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
2971
2972         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
2973
2974         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2975             (tmp & TRANSCONF_WGC_ENABLE))
2976                 pipe_config->wgc_enable = true;
2977
2978         intel_color_get_config(pipe_config);
2979
2980         if (DISPLAY_VER(dev_priv) < 4)
2981                 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
2982
2983         intel_get_transcoder_timings(crtc, pipe_config);
2984         intel_get_pipe_src_size(crtc, pipe_config);
2985
2986         i9xx_get_pfit_config(pipe_config);
2987
2988         if (DISPLAY_VER(dev_priv) >= 4) {
2989                 /* No way to read it out on pipes B and C */
2990                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
2991                         tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
2992                 else
2993                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
2994                 pipe_config->pixel_multiplier =
2995                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
2996                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
2997                 pipe_config->dpll_hw_state.dpll_md = tmp;
2998         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
2999                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
3000                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
3001                 pipe_config->pixel_multiplier =
3002                         ((tmp & SDVO_MULTIPLIER_MASK)
3003                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3004         } else {
3005                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
3006                  * port and will be fixed up in the encoder->get_config
3007                  * function. */
3008                 pipe_config->pixel_multiplier = 1;
3009         }
3010         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
3011                                                         DPLL(crtc->pipe));
3012         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
3013                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
3014                                                                FP0(crtc->pipe));
3015                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
3016                                                                FP1(crtc->pipe));
3017         } else {
3018                 /* Mask out read-only status bits. */
3019                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3020                                                      DPLL_PORTC_READY_MASK |
3021                                                      DPLL_PORTB_READY_MASK);
3022         }
3023
3024         if (IS_CHERRYVIEW(dev_priv))
3025                 chv_crtc_clock_get(crtc, pipe_config);
3026         else if (IS_VALLEYVIEW(dev_priv))
3027                 vlv_crtc_clock_get(crtc, pipe_config);
3028         else
3029                 i9xx_crtc_clock_get(crtc, pipe_config);
3030
3031         /*
3032          * Normally the dotclock is filled in by the encoder .get_config()
3033          * but in case the pipe is enabled w/o any ports we need a sane
3034          * default.
3035          */
3036         pipe_config->hw.adjusted_mode.crtc_clock =
3037                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3038
3039         ret = true;
3040
3041 out:
3042         intel_display_power_put(dev_priv, power_domain, wakeref);
3043
3044         return ret;
3045 }
3046
3047 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3048 {
3049         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3050         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3051         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3052         u32 val = 0;
3053
3054         /*
3055          * - During modeset the pipe is still disabled and must remain so
3056          * - During fastset the pipe is already enabled and must remain so
3057          */
3058         if (!intel_crtc_needs_modeset(crtc_state))
3059                 val |= TRANSCONF_ENABLE;
3060
3061         switch (crtc_state->pipe_bpp) {
3062         default:
3063                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3064                 MISSING_CASE(crtc_state->pipe_bpp);
3065                 fallthrough;
3066         case 18:
3067                 val |= TRANSCONF_BPC_6;
3068                 break;
3069         case 24:
3070                 val |= TRANSCONF_BPC_8;
3071                 break;
3072         case 30:
3073                 val |= TRANSCONF_BPC_10;
3074                 break;
3075         case 36:
3076                 val |= TRANSCONF_BPC_12;
3077                 break;
3078         }
3079
3080         if (crtc_state->dither)
3081                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3082
3083         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3084                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3085         else
3086                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3087
3088         /*
3089          * This would end up with an odd purple hue over
3090          * the entire display. Make sure we don't do it.
3091          */
3092         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3093                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3094
3095         if (crtc_state->limited_color_range &&
3096             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3097                 val |= TRANSCONF_COLOR_RANGE_SELECT;
3098
3099         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3100                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3101
3102         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3103
3104         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3105         val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3106
3107         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3108         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3109 }
3110
3111 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3112 {
3113         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3114         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3115         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3116         u32 val = 0;
3117
3118         /*
3119          * - During modeset the pipe is still disabled and must remain so
3120          * - During fastset the pipe is already enabled and must remain so
3121          */
3122         if (!intel_crtc_needs_modeset(crtc_state))
3123                 val |= TRANSCONF_ENABLE;
3124
3125         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3126                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3127
3128         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3129                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3130         else
3131                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3132
3133         if (IS_HASWELL(dev_priv) &&
3134             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3135                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3136
3137         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3138         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3139 }
3140
3141 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3142 {
3143         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3144         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3145         u32 val = 0;
3146
3147         switch (crtc_state->pipe_bpp) {
3148         case 18:
3149                 val |= PIPE_MISC_BPC_6;
3150                 break;
3151         case 24:
3152                 val |= PIPE_MISC_BPC_8;
3153                 break;
3154         case 30:
3155                 val |= PIPE_MISC_BPC_10;
3156                 break;
3157         case 36:
3158                 /* Port output 12BPC defined for ADLP+ */
3159                 if (DISPLAY_VER(dev_priv) > 12)
3160                         val |= PIPE_MISC_BPC_12_ADLP;
3161                 break;
3162         default:
3163                 MISSING_CASE(crtc_state->pipe_bpp);
3164                 break;
3165         }
3166
3167         if (crtc_state->dither)
3168                 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3169
3170         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3171             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3172                 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3173
3174         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3175                 val |= PIPE_MISC_YUV420_ENABLE |
3176                         PIPE_MISC_YUV420_MODE_FULL_BLEND;
3177
3178         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3179                 val |= PIPE_MISC_HDR_MODE_PRECISION;
3180
3181         if (DISPLAY_VER(dev_priv) >= 12)
3182                 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3183
3184         /* allow PSR with sprite enabled */
3185         if (IS_BROADWELL(dev_priv))
3186                 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3187
3188         intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3189 }
3190
3191 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3192 {
3193         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3194         u32 tmp;
3195
3196         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3197
3198         switch (tmp & PIPE_MISC_BPC_MASK) {
3199         case PIPE_MISC_BPC_6:
3200                 return 18;
3201         case PIPE_MISC_BPC_8:
3202                 return 24;
3203         case PIPE_MISC_BPC_10:
3204                 return 30;
3205         /*
3206          * PORT OUTPUT 12 BPC defined for ADLP+.
3207          *
3208          * TODO:
3209          * For previous platforms with DSI interface, bits 5:7
3210          * are used for storing pipe_bpp irrespective of dithering.
3211          * Since the value of 12 BPC is not defined for these bits
3212          * on older platforms, need to find a workaround for 12 BPC
3213          * MIPI DSI HW readout.
3214          */
3215         case PIPE_MISC_BPC_12_ADLP:
3216                 if (DISPLAY_VER(dev_priv) > 12)
3217                         return 36;
3218                 fallthrough;
3219         default:
3220                 MISSING_CASE(tmp);
3221                 return 0;
3222         }
3223 }
3224
3225 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3226 {
3227         /*
3228          * Account for spread spectrum to avoid
3229          * oversubscribing the link. Max center spread
3230          * is 2.5%; use 5% for safety's sake.
3231          */
3232         u32 bps = target_clock * bpp * 21 / 20;
3233         return DIV_ROUND_UP(bps, link_bw * 8);
3234 }
3235
3236 void intel_get_m_n(struct drm_i915_private *i915,
3237                    struct intel_link_m_n *m_n,
3238                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3239                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3240 {
3241         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3242         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3243         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3244         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3245         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3246 }
3247
3248 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3249                                     enum transcoder transcoder,
3250                                     struct intel_link_m_n *m_n)
3251 {
3252         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3253         enum pipe pipe = crtc->pipe;
3254
3255         if (DISPLAY_VER(dev_priv) >= 5)
3256                 intel_get_m_n(dev_priv, m_n,
3257                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3258                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3259         else
3260                 intel_get_m_n(dev_priv, m_n,
3261                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3262                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3263 }
3264
3265 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3266                                     enum transcoder transcoder,
3267                                     struct intel_link_m_n *m_n)
3268 {
3269         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3270
3271         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3272                 return;
3273
3274         intel_get_m_n(dev_priv, m_n,
3275                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3276                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3277 }
3278
3279 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3280 {
3281         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3282         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3283         u32 ctl, pos, size;
3284         enum pipe pipe;
3285
3286         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3287         if ((ctl & PF_ENABLE) == 0)
3288                 return;
3289
3290         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3291                 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
3292         else
3293                 pipe = crtc->pipe;
3294
3295         crtc_state->pch_pfit.enabled = true;
3296
3297         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3298         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3299
3300         drm_rect_init(&crtc_state->pch_pfit.dst,
3301                       REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
3302                       REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
3303                       REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
3304                       REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
3305
3306         /*
3307          * We currently do not free assignements of panel fitters on
3308          * ivb/hsw (since we don't use the higher upscaling modes which
3309          * differentiates them) so just WARN about this case for now.
3310          */
3311         drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3312 }
3313
3314 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3315                                 struct intel_crtc_state *pipe_config)
3316 {
3317         struct drm_device *dev = crtc->base.dev;
3318         struct drm_i915_private *dev_priv = to_i915(dev);
3319         enum intel_display_power_domain power_domain;
3320         intel_wakeref_t wakeref;
3321         u32 tmp;
3322         bool ret;
3323
3324         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3325         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3326         if (!wakeref)
3327                 return false;
3328
3329         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3330         pipe_config->shared_dpll = NULL;
3331
3332         ret = false;
3333         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3334         if (!(tmp & TRANSCONF_ENABLE))
3335                 goto out;
3336
3337         switch (tmp & TRANSCONF_BPC_MASK) {
3338         case TRANSCONF_BPC_6:
3339                 pipe_config->pipe_bpp = 18;
3340                 break;
3341         case TRANSCONF_BPC_8:
3342                 pipe_config->pipe_bpp = 24;
3343                 break;
3344         case TRANSCONF_BPC_10:
3345                 pipe_config->pipe_bpp = 30;
3346                 break;
3347         case TRANSCONF_BPC_12:
3348                 pipe_config->pipe_bpp = 36;
3349                 break;
3350         default:
3351                 break;
3352         }
3353
3354         if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3355                 pipe_config->limited_color_range = true;
3356
3357         switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3358         case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3359         case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3360                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3361                 break;
3362         default:
3363                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3364                 break;
3365         }
3366
3367         pipe_config->sink_format = pipe_config->output_format;
3368
3369         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3370
3371         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3372
3373         pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3374
3375         intel_color_get_config(pipe_config);
3376
3377         pipe_config->pixel_multiplier = 1;
3378
3379         ilk_pch_get_config(pipe_config);
3380
3381         intel_get_transcoder_timings(crtc, pipe_config);
3382         intel_get_pipe_src_size(crtc, pipe_config);
3383
3384         ilk_get_pfit_config(pipe_config);
3385
3386         ret = true;
3387
3388 out:
3389         intel_display_power_put(dev_priv, power_domain, wakeref);
3390
3391         return ret;
3392 }
3393
3394 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3395 {
3396         u8 pipes;
3397
3398         if (DISPLAY_VER(i915) >= 12)
3399                 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3400         else if (DISPLAY_VER(i915) >= 11)
3401                 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3402         else
3403                 pipes = 0;
3404
3405         return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3406 }
3407
3408 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3409                                            enum transcoder cpu_transcoder)
3410 {
3411         enum intel_display_power_domain power_domain;
3412         intel_wakeref_t wakeref;
3413         u32 tmp = 0;
3414
3415         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3416
3417         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3418                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3419
3420         return tmp & TRANS_DDI_FUNC_ENABLE;
3421 }
3422
3423 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3424                                     u8 *master_pipes, u8 *slave_pipes)
3425 {
3426         struct intel_crtc *crtc;
3427
3428         *master_pipes = 0;
3429         *slave_pipes = 0;
3430
3431         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3432                                          bigjoiner_pipes(dev_priv)) {
3433                 enum intel_display_power_domain power_domain;
3434                 enum pipe pipe = crtc->pipe;
3435                 intel_wakeref_t wakeref;
3436
3437                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3438                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3439                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3440
3441                         if (!(tmp & BIG_JOINER_ENABLE))
3442                                 continue;
3443
3444                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3445                                 *master_pipes |= BIT(pipe);
3446                         else
3447                                 *slave_pipes |= BIT(pipe);
3448                 }
3449
3450                 if (DISPLAY_VER(dev_priv) < 13)
3451                         continue;
3452
3453                 power_domain = POWER_DOMAIN_PIPE(pipe);
3454                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3455                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3456
3457                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3458                                 *master_pipes |= BIT(pipe);
3459                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3460                                 *slave_pipes |= BIT(pipe);
3461                 }
3462         }
3463
3464         /* Bigjoiner pipes should always be consecutive master and slave */
3465         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3466                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3467                  *master_pipes, *slave_pipes);
3468 }
3469
3470 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3471 {
3472         if ((slave_pipes & BIT(pipe)) == 0)
3473                 return pipe;
3474
3475         /* ignore everything above our pipe */
3476         master_pipes &= ~GENMASK(7, pipe);
3477
3478         /* highest remaining bit should be our master pipe */
3479         return fls(master_pipes) - 1;
3480 }
3481
3482 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3483 {
3484         enum pipe master_pipe, next_master_pipe;
3485
3486         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3487
3488         if ((master_pipes & BIT(master_pipe)) == 0)
3489                 return 0;
3490
3491         /* ignore our master pipe and everything below it */
3492         master_pipes &= ~GENMASK(master_pipe, 0);
3493         /* make sure a high bit is set for the ffs() */
3494         master_pipes |= BIT(7);
3495         /* lowest remaining bit should be the next master pipe */
3496         next_master_pipe = ffs(master_pipes) - 1;
3497
3498         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3499 }
3500
3501 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3502 {
3503         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3504
3505         if (DISPLAY_VER(i915) >= 11)
3506                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3507
3508         return panel_transcoder_mask;
3509 }
3510
3511 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3512 {
3513         struct drm_device *dev = crtc->base.dev;
3514         struct drm_i915_private *dev_priv = to_i915(dev);
3515         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3516         enum transcoder cpu_transcoder;
3517         u8 master_pipes, slave_pipes;
3518         u8 enabled_transcoders = 0;
3519
3520         /*
3521          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3522          * consistency and less surprising code; it's in always on power).
3523          */
3524         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3525                                        panel_transcoder_mask) {
3526                 enum intel_display_power_domain power_domain;
3527                 intel_wakeref_t wakeref;
3528                 enum pipe trans_pipe;
3529                 u32 tmp = 0;
3530
3531                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3532                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3533                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3534
3535                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3536                         continue;
3537
3538                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3539                 default:
3540                         drm_WARN(dev, 1,
3541                                  "unknown pipe linked to transcoder %s\n",
3542                                  transcoder_name(cpu_transcoder));
3543                         fallthrough;
3544                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3545                 case TRANS_DDI_EDP_INPUT_A_ON:
3546                         trans_pipe = PIPE_A;
3547                         break;
3548                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3549                         trans_pipe = PIPE_B;
3550                         break;
3551                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3552                         trans_pipe = PIPE_C;
3553                         break;
3554                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3555                         trans_pipe = PIPE_D;
3556                         break;
3557                 }
3558
3559                 if (trans_pipe == crtc->pipe)
3560                         enabled_transcoders |= BIT(cpu_transcoder);
3561         }
3562
3563         /* single pipe or bigjoiner master */
3564         cpu_transcoder = (enum transcoder) crtc->pipe;
3565         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3566                 enabled_transcoders |= BIT(cpu_transcoder);
3567
3568         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3569         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3570         if (slave_pipes & BIT(crtc->pipe)) {
3571                 cpu_transcoder = (enum transcoder)
3572                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3573                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3574                         enabled_transcoders |= BIT(cpu_transcoder);
3575         }
3576
3577         return enabled_transcoders;
3578 }
3579
3580 static bool has_edp_transcoders(u8 enabled_transcoders)
3581 {
3582         return enabled_transcoders & BIT(TRANSCODER_EDP);
3583 }
3584
3585 static bool has_dsi_transcoders(u8 enabled_transcoders)
3586 {
3587         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3588                                       BIT(TRANSCODER_DSI_1));
3589 }
3590
3591 static bool has_pipe_transcoders(u8 enabled_transcoders)
3592 {
3593         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3594                                        BIT(TRANSCODER_DSI_0) |
3595                                        BIT(TRANSCODER_DSI_1));
3596 }
3597
3598 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3599                                        u8 enabled_transcoders)
3600 {
3601         /* Only one type of transcoder please */
3602         drm_WARN_ON(&i915->drm,
3603                     has_edp_transcoders(enabled_transcoders) +
3604                     has_dsi_transcoders(enabled_transcoders) +
3605                     has_pipe_transcoders(enabled_transcoders) > 1);
3606
3607         /* Only DSI transcoders can be ganged */
3608         drm_WARN_ON(&i915->drm,
3609                     !has_dsi_transcoders(enabled_transcoders) &&
3610                     !is_power_of_2(enabled_transcoders));
3611 }
3612
3613 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3614                                      struct intel_crtc_state *pipe_config,
3615                                      struct intel_display_power_domain_set *power_domain_set)
3616 {
3617         struct drm_device *dev = crtc->base.dev;
3618         struct drm_i915_private *dev_priv = to_i915(dev);
3619         unsigned long enabled_transcoders;
3620         u32 tmp;
3621
3622         enabled_transcoders = hsw_enabled_transcoders(crtc);
3623         if (!enabled_transcoders)
3624                 return false;
3625
3626         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3627
3628         /*
3629          * With the exception of DSI we should only ever have
3630          * a single enabled transcoder. With DSI let's just
3631          * pick the first one.
3632          */
3633         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3634
3635         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3636                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3637                 return false;
3638
3639         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3640                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3641
3642                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3643                         pipe_config->pch_pfit.force_thru = true;
3644         }
3645
3646         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3647
3648         return tmp & TRANSCONF_ENABLE;
3649 }
3650
3651 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3652                                          struct intel_crtc_state *pipe_config,
3653                                          struct intel_display_power_domain_set *power_domain_set)
3654 {
3655         struct drm_device *dev = crtc->base.dev;
3656         struct drm_i915_private *dev_priv = to_i915(dev);
3657         enum transcoder cpu_transcoder;
3658         enum port port;
3659         u32 tmp;
3660
3661         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3662                 if (port == PORT_A)
3663                         cpu_transcoder = TRANSCODER_DSI_A;
3664                 else
3665                         cpu_transcoder = TRANSCODER_DSI_C;
3666
3667                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3668                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3669                         continue;
3670
3671                 /*
3672                  * The PLL needs to be enabled with a valid divider
3673                  * configuration, otherwise accessing DSI registers will hang
3674                  * the machine. See BSpec North Display Engine
3675                  * registers/MIPI[BXT]. We can break out here early, since we
3676                  * need the same DSI PLL to be enabled for both DSI ports.
3677                  */
3678                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3679                         break;
3680
3681                 /* XXX: this works for video mode only */
3682                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
3683                 if (!(tmp & DPI_ENABLE))
3684                         continue;
3685
3686                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
3687                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3688                         continue;
3689
3690                 pipe_config->cpu_transcoder = cpu_transcoder;
3691                 break;
3692         }
3693
3694         return transcoder_is_dsi(pipe_config->cpu_transcoder);
3695 }
3696
3697 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
3698 {
3699         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3700         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3701         u8 master_pipes, slave_pipes;
3702         enum pipe pipe = crtc->pipe;
3703
3704         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
3705
3706         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
3707                 return;
3708
3709         crtc_state->bigjoiner_pipes =
3710                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
3711                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
3712 }
3713
3714 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3715                                 struct intel_crtc_state *pipe_config)
3716 {
3717         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3718         bool active;
3719         u32 tmp;
3720
3721         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3722                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
3723                 return false;
3724
3725         pipe_config->shared_dpll = NULL;
3726
3727         active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3728
3729         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3730             bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3731                 drm_WARN_ON(&dev_priv->drm, active);
3732                 active = true;
3733         }
3734
3735         if (!active)
3736                 goto out;
3737
3738         intel_dsc_get_config(pipe_config);
3739         intel_bigjoiner_get_config(pipe_config);
3740
3741         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3742             DISPLAY_VER(dev_priv) >= 11)
3743                 intel_get_transcoder_timings(crtc, pipe_config);
3744
3745         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3746                 intel_vrr_get_config(pipe_config);
3747
3748         intel_get_pipe_src_size(crtc, pipe_config);
3749
3750         if (IS_HASWELL(dev_priv)) {
3751                 u32 tmp = intel_de_read(dev_priv,
3752                                         TRANSCONF(pipe_config->cpu_transcoder));
3753
3754                 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3755                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3756                 else
3757                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3758         } else {
3759                 pipe_config->output_format =
3760                         bdw_get_pipe_misc_output_format(crtc);
3761         }
3762
3763         pipe_config->sink_format = pipe_config->output_format;
3764
3765         intel_color_get_config(pipe_config);
3766
3767         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3768         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3769         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3770                 pipe_config->ips_linetime =
3771                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3772
3773         if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3774                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3775                 if (DISPLAY_VER(dev_priv) >= 9)
3776                         skl_scaler_get_config(pipe_config);
3777                 else
3778                         ilk_get_pfit_config(pipe_config);
3779         }
3780
3781         hsw_ips_get_config(pipe_config);
3782
3783         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3784             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3785                 pipe_config->pixel_multiplier =
3786                         intel_de_read(dev_priv,
3787                                       TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
3788         } else {
3789                 pipe_config->pixel_multiplier = 1;
3790         }
3791
3792         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3793                 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ?
3794                                     MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
3795                                     CHICKEN_TRANS(pipe_config->cpu_transcoder));
3796
3797                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3798         } else {
3799                 /* no idea if this is correct */
3800                 pipe_config->framestart_delay = 1;
3801         }
3802
3803 out:
3804         intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3805
3806         return active;
3807 }
3808
3809 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3810 {
3811         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3812         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3813
3814         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3815                 return false;
3816
3817         crtc_state->hw.active = true;
3818
3819         intel_crtc_readout_derived_state(crtc_state);
3820
3821         return true;
3822 }
3823
3824 static int i9xx_pll_refclk(struct drm_device *dev,
3825                            const struct intel_crtc_state *pipe_config)
3826 {
3827         struct drm_i915_private *dev_priv = to_i915(dev);
3828         u32 dpll = pipe_config->dpll_hw_state.dpll;
3829
3830         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
3831                 return dev_priv->display.vbt.lvds_ssc_freq;
3832         else if (HAS_PCH_SPLIT(dev_priv))
3833                 return 120000;
3834         else if (DISPLAY_VER(dev_priv) != 2)
3835                 return 96000;
3836         else
3837                 return 48000;
3838 }
3839
3840 /* Returns the clock of the currently programmed mode of the given pipe. */
3841 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
3842                          struct intel_crtc_state *pipe_config)
3843 {
3844         struct drm_device *dev = crtc->base.dev;
3845         struct drm_i915_private *dev_priv = to_i915(dev);
3846         u32 dpll = pipe_config->dpll_hw_state.dpll;
3847         u32 fp;
3848         struct dpll clock;
3849         int port_clock;
3850         int refclk = i9xx_pll_refclk(dev, pipe_config);
3851
3852         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3853                 fp = pipe_config->dpll_hw_state.fp0;
3854         else
3855                 fp = pipe_config->dpll_hw_state.fp1;
3856
3857         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3858         if (IS_PINEVIEW(dev_priv)) {
3859                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3860                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3861         } else {
3862                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3863                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3864         }
3865
3866         if (DISPLAY_VER(dev_priv) != 2) {
3867                 if (IS_PINEVIEW(dev_priv))
3868                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3869                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3870                 else
3871                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3872                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3873
3874                 switch (dpll & DPLL_MODE_MASK) {
3875                 case DPLLB_MODE_DAC_SERIAL:
3876                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3877                                 5 : 10;
3878                         break;
3879                 case DPLLB_MODE_LVDS:
3880                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3881                                 7 : 14;
3882                         break;
3883                 default:
3884                         drm_dbg_kms(&dev_priv->drm,
3885                                     "Unknown DPLL mode %08x in programmed "
3886                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
3887                         return;
3888                 }
3889
3890                 if (IS_PINEVIEW(dev_priv))
3891                         port_clock = pnv_calc_dpll_params(refclk, &clock);
3892                 else
3893                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
3894         } else {
3895                 enum pipe lvds_pipe;
3896
3897                 if (IS_I85X(dev_priv) &&
3898                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
3899                     lvds_pipe == crtc->pipe) {
3900                         u32 lvds = intel_de_read(dev_priv, LVDS);
3901
3902                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3903                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3904
3905                         if (lvds & LVDS_CLKB_POWER_UP)
3906                                 clock.p2 = 7;
3907                         else
3908                                 clock.p2 = 14;
3909                 } else {
3910                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3911                                 clock.p1 = 2;
3912                         else {
3913                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3914                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3915                         }
3916                         if (dpll & PLL_P2_DIVIDE_BY_4)
3917                                 clock.p2 = 4;
3918                         else
3919                                 clock.p2 = 2;
3920                 }
3921
3922                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
3923         }
3924
3925         /*
3926          * This value includes pixel_multiplier. We will use
3927          * port_clock to compute adjusted_mode.crtc_clock in the
3928          * encoder's get_config() function.
3929          */
3930         pipe_config->port_clock = port_clock;
3931 }
3932
3933 int intel_dotclock_calculate(int link_freq,
3934                              const struct intel_link_m_n *m_n)
3935 {
3936         /*
3937          * The calculation for the data clock is:
3938          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3939          * But we want to avoid losing precison if possible, so:
3940          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3941          *
3942          * and the link clock is simpler:
3943          * link_clock = (m * link_clock) / n
3944          */
3945
3946         if (!m_n->link_n)
3947                 return 0;
3948
3949         return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq),
3950                                 m_n->link_n);
3951 }
3952
3953 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
3954 {
3955         int dotclock;
3956
3957         if (intel_crtc_has_dp_encoder(pipe_config))
3958                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
3959                                                     &pipe_config->dp_m_n);
3960         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
3961                 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
3962                                              pipe_config->pipe_bpp);
3963         else
3964                 dotclock = pipe_config->port_clock;
3965
3966         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3967             !intel_crtc_has_dp_encoder(pipe_config))
3968                 dotclock *= 2;
3969
3970         if (pipe_config->pixel_multiplier)
3971                 dotclock /= pipe_config->pixel_multiplier;
3972
3973         return dotclock;
3974 }
3975
3976 /* Returns the currently programmed mode of the given encoder. */
3977 struct drm_display_mode *
3978 intel_encoder_current_mode(struct intel_encoder *encoder)
3979 {
3980         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3981         struct intel_crtc_state *crtc_state;
3982         struct drm_display_mode *mode;
3983         struct intel_crtc *crtc;
3984         enum pipe pipe;
3985
3986         if (!encoder->get_hw_state(encoder, &pipe))
3987                 return NULL;
3988
3989         crtc = intel_crtc_for_pipe(dev_priv, pipe);
3990
3991         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3992         if (!mode)
3993                 return NULL;
3994
3995         crtc_state = intel_crtc_state_alloc(crtc);
3996         if (!crtc_state) {
3997                 kfree(mode);
3998                 return NULL;
3999         }
4000
4001         if (!intel_crtc_get_pipe_config(crtc_state)) {
4002                 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4003                 kfree(mode);
4004                 return NULL;
4005         }
4006
4007         intel_encoder_get_config(encoder, crtc_state);
4008
4009         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
4010
4011         intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
4012
4013         return mode;
4014 }
4015
4016 static bool encoders_cloneable(const struct intel_encoder *a,
4017                                const struct intel_encoder *b)
4018 {
4019         /* masks could be asymmetric, so check both ways */
4020         return a == b || (a->cloneable & BIT(b->type) &&
4021                           b->cloneable & BIT(a->type));
4022 }
4023
4024 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4025                                          struct intel_crtc *crtc,
4026                                          struct intel_encoder *encoder)
4027 {
4028         struct intel_encoder *source_encoder;
4029         struct drm_connector *connector;
4030         struct drm_connector_state *connector_state;
4031         int i;
4032
4033         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4034                 if (connector_state->crtc != &crtc->base)
4035                         continue;
4036
4037                 source_encoder =
4038                         to_intel_encoder(connector_state->best_encoder);
4039                 if (!encoders_cloneable(encoder, source_encoder))
4040                         return false;
4041         }
4042
4043         return true;
4044 }
4045
4046 static int icl_add_linked_planes(struct intel_atomic_state *state)
4047 {
4048         struct intel_plane *plane, *linked;
4049         struct intel_plane_state *plane_state, *linked_plane_state;
4050         int i;
4051
4052         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4053                 linked = plane_state->planar_linked_plane;
4054
4055                 if (!linked)
4056                         continue;
4057
4058                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4059                 if (IS_ERR(linked_plane_state))
4060                         return PTR_ERR(linked_plane_state);
4061
4062                 drm_WARN_ON(state->base.dev,
4063                             linked_plane_state->planar_linked_plane != plane);
4064                 drm_WARN_ON(state->base.dev,
4065                             linked_plane_state->planar_slave == plane_state->planar_slave);
4066         }
4067
4068         return 0;
4069 }
4070
4071 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4072 {
4073         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4074         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4075         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4076         struct intel_plane *plane, *linked;
4077         struct intel_plane_state *plane_state;
4078         int i;
4079
4080         if (DISPLAY_VER(dev_priv) < 11)
4081                 return 0;
4082
4083         /*
4084          * Destroy all old plane links and make the slave plane invisible
4085          * in the crtc_state->active_planes mask.
4086          */
4087         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4088                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4089                         continue;
4090
4091                 plane_state->planar_linked_plane = NULL;
4092                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4093                         crtc_state->enabled_planes &= ~BIT(plane->id);
4094                         crtc_state->active_planes &= ~BIT(plane->id);
4095                         crtc_state->update_planes |= BIT(plane->id);
4096                         crtc_state->data_rate[plane->id] = 0;
4097                         crtc_state->rel_data_rate[plane->id] = 0;
4098                 }
4099
4100                 plane_state->planar_slave = false;
4101         }
4102
4103         if (!crtc_state->nv12_planes)
4104                 return 0;
4105
4106         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4107                 struct intel_plane_state *linked_state = NULL;
4108
4109                 if (plane->pipe != crtc->pipe ||
4110                     !(crtc_state->nv12_planes & BIT(plane->id)))
4111                         continue;
4112
4113                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4114                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4115                                 continue;
4116
4117                         if (crtc_state->active_planes & BIT(linked->id))
4118                                 continue;
4119
4120                         linked_state = intel_atomic_get_plane_state(state, linked);
4121                         if (IS_ERR(linked_state))
4122                                 return PTR_ERR(linked_state);
4123
4124                         break;
4125                 }
4126
4127                 if (!linked_state) {
4128                         drm_dbg_kms(&dev_priv->drm,
4129                                     "Need %d free Y planes for planar YUV\n",
4130                                     hweight8(crtc_state->nv12_planes));
4131
4132                         return -EINVAL;
4133                 }
4134
4135                 plane_state->planar_linked_plane = linked;
4136
4137                 linked_state->planar_slave = true;
4138                 linked_state->planar_linked_plane = plane;
4139                 crtc_state->enabled_planes |= BIT(linked->id);
4140                 crtc_state->active_planes |= BIT(linked->id);
4141                 crtc_state->update_planes |= BIT(linked->id);
4142                 crtc_state->data_rate[linked->id] =
4143                         crtc_state->data_rate_y[plane->id];
4144                 crtc_state->rel_data_rate[linked->id] =
4145                         crtc_state->rel_data_rate_y[plane->id];
4146                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4147                             linked->base.name, plane->base.name);
4148
4149                 /* Copy parameters to slave plane */
4150                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4151                 linked_state->color_ctl = plane_state->color_ctl;
4152                 linked_state->view = plane_state->view;
4153                 linked_state->decrypt = plane_state->decrypt;
4154
4155                 intel_plane_copy_hw_state(linked_state, plane_state);
4156                 linked_state->uapi.src = plane_state->uapi.src;
4157                 linked_state->uapi.dst = plane_state->uapi.dst;
4158
4159                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4160                         if (linked->id == PLANE_SPRITE5)
4161                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4162                         else if (linked->id == PLANE_SPRITE4)
4163                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4164                         else if (linked->id == PLANE_SPRITE3)
4165                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4166                         else if (linked->id == PLANE_SPRITE2)
4167                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4168                         else
4169                                 MISSING_CASE(linked->id);
4170                 }
4171         }
4172
4173         return 0;
4174 }
4175
4176 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4177 {
4178         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4179         struct intel_atomic_state *state =
4180                 to_intel_atomic_state(new_crtc_state->uapi.state);
4181         const struct intel_crtc_state *old_crtc_state =
4182                 intel_atomic_get_old_crtc_state(state, crtc);
4183
4184         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4185 }
4186
4187 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4188 {
4189         const struct drm_display_mode *pipe_mode =
4190                 &crtc_state->hw.pipe_mode;
4191         int linetime_wm;
4192
4193         if (!crtc_state->hw.enable)
4194                 return 0;
4195
4196         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4197                                         pipe_mode->crtc_clock);
4198
4199         return min(linetime_wm, 0x1ff);
4200 }
4201
4202 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4203                                const struct intel_cdclk_state *cdclk_state)
4204 {
4205         const struct drm_display_mode *pipe_mode =
4206                 &crtc_state->hw.pipe_mode;
4207         int linetime_wm;
4208
4209         if (!crtc_state->hw.enable)
4210                 return 0;
4211
4212         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4213                                         cdclk_state->logical.cdclk);
4214
4215         return min(linetime_wm, 0x1ff);
4216 }
4217
4218 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4219 {
4220         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4221         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4222         const struct drm_display_mode *pipe_mode =
4223                 &crtc_state->hw.pipe_mode;
4224         int linetime_wm;
4225
4226         if (!crtc_state->hw.enable)
4227                 return 0;
4228
4229         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4230                                    crtc_state->pixel_rate);
4231
4232         /* Display WA #1135: BXT:ALL GLK:ALL */
4233         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4234             skl_watermark_ipc_enabled(dev_priv))
4235                 linetime_wm /= 2;
4236
4237         return min(linetime_wm, 0x1ff);
4238 }
4239
4240 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4241                                    struct intel_crtc *crtc)
4242 {
4243         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4244         struct intel_crtc_state *crtc_state =
4245                 intel_atomic_get_new_crtc_state(state, crtc);
4246         const struct intel_cdclk_state *cdclk_state;
4247
4248         if (DISPLAY_VER(dev_priv) >= 9)
4249                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4250         else
4251                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4252
4253         if (!hsw_crtc_supports_ips(crtc))
4254                 return 0;
4255
4256         cdclk_state = intel_atomic_get_cdclk_state(state);
4257         if (IS_ERR(cdclk_state))
4258                 return PTR_ERR(cdclk_state);
4259
4260         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4261                                                        cdclk_state);
4262
4263         return 0;
4264 }
4265
4266 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4267                                    struct intel_crtc *crtc)
4268 {
4269         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4270         struct intel_crtc_state *crtc_state =
4271                 intel_atomic_get_new_crtc_state(state, crtc);
4272         int ret;
4273
4274         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4275             intel_crtc_needs_modeset(crtc_state) &&
4276             !crtc_state->hw.active)
4277                 crtc_state->update_wm_post = true;
4278
4279         if (intel_crtc_needs_modeset(crtc_state)) {
4280                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4281                 if (ret)
4282                         return ret;
4283         }
4284
4285         /*
4286          * May need to update pipe gamma enable bits
4287          * when C8 planes are getting enabled/disabled.
4288          */
4289         if (c8_planes_changed(crtc_state))
4290                 crtc_state->uapi.color_mgmt_changed = true;
4291
4292         if (intel_crtc_needs_color_update(crtc_state)) {
4293                 ret = intel_color_check(crtc_state);
4294                 if (ret)
4295                         return ret;
4296         }
4297
4298         ret = intel_compute_pipe_wm(state, crtc);
4299         if (ret) {
4300                 drm_dbg_kms(&dev_priv->drm,
4301                             "Target pipe watermarks are invalid\n");
4302                 return ret;
4303         }
4304
4305         /*
4306          * Calculate 'intermediate' watermarks that satisfy both the
4307          * old state and the new state.  We can program these
4308          * immediately.
4309          */
4310         ret = intel_compute_intermediate_wm(state, crtc);
4311         if (ret) {
4312                 drm_dbg_kms(&dev_priv->drm,
4313                             "No valid intermediate pipe watermarks are possible\n");
4314                 return ret;
4315         }
4316
4317         if (DISPLAY_VER(dev_priv) >= 9) {
4318                 if (intel_crtc_needs_modeset(crtc_state) ||
4319                     intel_crtc_needs_fastset(crtc_state)) {
4320                         ret = skl_update_scaler_crtc(crtc_state);
4321                         if (ret)
4322                                 return ret;
4323                 }
4324
4325                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4326                 if (ret)
4327                         return ret;
4328         }
4329
4330         if (HAS_IPS(dev_priv)) {
4331                 ret = hsw_ips_compute_config(state, crtc);
4332                 if (ret)
4333                         return ret;
4334         }
4335
4336         if (DISPLAY_VER(dev_priv) >= 9 ||
4337             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4338                 ret = hsw_compute_linetime_wm(state, crtc);
4339                 if (ret)
4340                         return ret;
4341
4342         }
4343
4344         ret = intel_psr2_sel_fetch_update(state, crtc);
4345         if (ret)
4346                 return ret;
4347
4348         return 0;
4349 }
4350
4351 static int
4352 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4353                       struct intel_crtc_state *crtc_state)
4354 {
4355         struct drm_connector *connector = conn_state->connector;
4356         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4357         const struct drm_display_info *info = &connector->display_info;
4358         int bpp;
4359
4360         switch (conn_state->max_bpc) {
4361         case 6 ... 7:
4362                 bpp = 6 * 3;
4363                 break;
4364         case 8 ... 9:
4365                 bpp = 8 * 3;
4366                 break;
4367         case 10 ... 11:
4368                 bpp = 10 * 3;
4369                 break;
4370         case 12 ... 16:
4371                 bpp = 12 * 3;
4372                 break;
4373         default:
4374                 MISSING_CASE(conn_state->max_bpc);
4375                 return -EINVAL;
4376         }
4377
4378         if (bpp < crtc_state->pipe_bpp) {
4379                 drm_dbg_kms(&i915->drm,
4380                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4381                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4382                             connector->base.id, connector->name,
4383                             bpp, 3 * info->bpc,
4384                             3 * conn_state->max_requested_bpc,
4385                             crtc_state->pipe_bpp);
4386
4387                 crtc_state->pipe_bpp = bpp;
4388         }
4389
4390         return 0;
4391 }
4392
4393 static int
4394 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4395                           struct intel_crtc *crtc)
4396 {
4397         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4398         struct intel_crtc_state *crtc_state =
4399                 intel_atomic_get_new_crtc_state(state, crtc);
4400         struct drm_connector *connector;
4401         struct drm_connector_state *connector_state;
4402         int bpp, i;
4403
4404         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4405             IS_CHERRYVIEW(dev_priv)))
4406                 bpp = 10*3;
4407         else if (DISPLAY_VER(dev_priv) >= 5)
4408                 bpp = 12*3;
4409         else
4410                 bpp = 8*3;
4411
4412         crtc_state->pipe_bpp = bpp;
4413
4414         /* Clamp display bpp to connector max bpp */
4415         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4416                 int ret;
4417
4418                 if (connector_state->crtc != &crtc->base)
4419                         continue;
4420
4421                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4422                 if (ret)
4423                         return ret;
4424         }
4425
4426         return 0;
4427 }
4428
4429 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4430 {
4431         struct drm_device *dev = state->base.dev;
4432         struct drm_connector *connector;
4433         struct drm_connector_list_iter conn_iter;
4434         unsigned int used_ports = 0;
4435         unsigned int used_mst_ports = 0;
4436         bool ret = true;
4437
4438         /*
4439          * We're going to peek into connector->state,
4440          * hence connection_mutex must be held.
4441          */
4442         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4443
4444         /*
4445          * Walk the connector list instead of the encoder
4446          * list to detect the problem on ddi platforms
4447          * where there's just one encoder per digital port.
4448          */
4449         drm_connector_list_iter_begin(dev, &conn_iter);
4450         drm_for_each_connector_iter(connector, &conn_iter) {
4451                 struct drm_connector_state *connector_state;
4452                 struct intel_encoder *encoder;
4453
4454                 connector_state =
4455                         drm_atomic_get_new_connector_state(&state->base,
4456                                                            connector);
4457                 if (!connector_state)
4458                         connector_state = connector->state;
4459
4460                 if (!connector_state->best_encoder)
4461                         continue;
4462
4463                 encoder = to_intel_encoder(connector_state->best_encoder);
4464
4465                 drm_WARN_ON(dev, !connector_state->crtc);
4466
4467                 switch (encoder->type) {
4468                 case INTEL_OUTPUT_DDI:
4469                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4470                                 break;
4471                         fallthrough;
4472                 case INTEL_OUTPUT_DP:
4473                 case INTEL_OUTPUT_HDMI:
4474                 case INTEL_OUTPUT_EDP:
4475                         /* the same port mustn't appear more than once */
4476                         if (used_ports & BIT(encoder->port))
4477                                 ret = false;
4478
4479                         used_ports |= BIT(encoder->port);
4480                         break;
4481                 case INTEL_OUTPUT_DP_MST:
4482                         used_mst_ports |=
4483                                 1 << encoder->port;
4484                         break;
4485                 default:
4486                         break;
4487                 }
4488         }
4489         drm_connector_list_iter_end(&conn_iter);
4490
4491         /* can't mix MST and SST/HDMI on the same port */
4492         if (used_ports & used_mst_ports)
4493                 return false;
4494
4495         return ret;
4496 }
4497
4498 static void
4499 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4500                                            struct intel_crtc *crtc)
4501 {
4502         struct intel_crtc_state *crtc_state =
4503                 intel_atomic_get_new_crtc_state(state, crtc);
4504
4505         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4506
4507         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4508                                   crtc_state->uapi.degamma_lut);
4509         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4510                                   crtc_state->uapi.gamma_lut);
4511         drm_property_replace_blob(&crtc_state->hw.ctm,
4512                                   crtc_state->uapi.ctm);
4513 }
4514
4515 static void
4516 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4517                                          struct intel_crtc *crtc)
4518 {
4519         struct intel_crtc_state *crtc_state =
4520                 intel_atomic_get_new_crtc_state(state, crtc);
4521
4522         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4523
4524         crtc_state->hw.enable = crtc_state->uapi.enable;
4525         crtc_state->hw.active = crtc_state->uapi.active;
4526         drm_mode_copy(&crtc_state->hw.mode,
4527                       &crtc_state->uapi.mode);
4528         drm_mode_copy(&crtc_state->hw.adjusted_mode,
4529                       &crtc_state->uapi.adjusted_mode);
4530         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4531
4532         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4533 }
4534
4535 static void
4536 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4537                                     struct intel_crtc *slave_crtc)
4538 {
4539         struct intel_crtc_state *slave_crtc_state =
4540                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4541         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4542         const struct intel_crtc_state *master_crtc_state =
4543                 intel_atomic_get_new_crtc_state(state, master_crtc);
4544
4545         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
4546                                   master_crtc_state->hw.degamma_lut);
4547         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
4548                                   master_crtc_state->hw.gamma_lut);
4549         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
4550                                   master_crtc_state->hw.ctm);
4551
4552         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
4553 }
4554
4555 static int
4556 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
4557                                   struct intel_crtc *slave_crtc)
4558 {
4559         struct intel_crtc_state *slave_crtc_state =
4560                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4561         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4562         const struct intel_crtc_state *master_crtc_state =
4563                 intel_atomic_get_new_crtc_state(state, master_crtc);
4564         struct intel_crtc_state *saved_state;
4565
4566         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4567                 slave_crtc_state->bigjoiner_pipes);
4568
4569         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4570         if (!saved_state)
4571                 return -ENOMEM;
4572
4573         /* preserve some things from the slave's original crtc state */
4574         saved_state->uapi = slave_crtc_state->uapi;
4575         saved_state->scaler_state = slave_crtc_state->scaler_state;
4576         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
4577         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
4578
4579         intel_crtc_free_hw_state(slave_crtc_state);
4580         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
4581         kfree(saved_state);
4582
4583         /* Re-init hw state */
4584         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
4585         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
4586         slave_crtc_state->hw.active = master_crtc_state->hw.active;
4587         drm_mode_copy(&slave_crtc_state->hw.mode,
4588                       &master_crtc_state->hw.mode);
4589         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
4590                       &master_crtc_state->hw.pipe_mode);
4591         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
4592                       &master_crtc_state->hw.adjusted_mode);
4593         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
4594
4595         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
4596
4597         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
4598         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
4599         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
4600
4601         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4602                 slave_crtc_state->bigjoiner_pipes);
4603
4604         return 0;
4605 }
4606
4607 static int
4608 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4609                                  struct intel_crtc *crtc)
4610 {
4611         struct intel_crtc_state *crtc_state =
4612                 intel_atomic_get_new_crtc_state(state, crtc);
4613         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4614         struct intel_crtc_state *saved_state;
4615
4616         saved_state = intel_crtc_state_alloc(crtc);
4617         if (!saved_state)
4618                 return -ENOMEM;
4619
4620         /* free the old crtc_state->hw members */
4621         intel_crtc_free_hw_state(crtc_state);
4622
4623         /* FIXME: before the switch to atomic started, a new pipe_config was
4624          * kzalloc'd. Code that depends on any field being zero should be
4625          * fixed, so that the crtc_state can be safely duplicated. For now,
4626          * only fields that are know to not cause problems are preserved. */
4627
4628         saved_state->uapi = crtc_state->uapi;
4629         saved_state->inherited = crtc_state->inherited;
4630         saved_state->scaler_state = crtc_state->scaler_state;
4631         saved_state->shared_dpll = crtc_state->shared_dpll;
4632         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4633         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4634                sizeof(saved_state->icl_port_dplls));
4635         saved_state->crc_enabled = crtc_state->crc_enabled;
4636         if (IS_G4X(dev_priv) ||
4637             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4638                 saved_state->wm = crtc_state->wm;
4639
4640         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4641         kfree(saved_state);
4642
4643         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4644
4645         return 0;
4646 }
4647
4648 static int
4649 intel_modeset_pipe_config(struct intel_atomic_state *state,
4650                           struct intel_crtc *crtc,
4651                           const struct intel_link_bw_limits *limits)
4652 {
4653         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4654         struct intel_crtc_state *crtc_state =
4655                 intel_atomic_get_new_crtc_state(state, crtc);
4656         struct drm_connector *connector;
4657         struct drm_connector_state *connector_state;
4658         int pipe_src_w, pipe_src_h;
4659         int base_bpp, ret, i;
4660
4661         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4662
4663         crtc_state->framestart_delay = 1;
4664
4665         /*
4666          * Sanitize sync polarity flags based on requested ones. If neither
4667          * positive or negative polarity is requested, treat this as meaning
4668          * negative polarity.
4669          */
4670         if (!(crtc_state->hw.adjusted_mode.flags &
4671               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4672                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4673
4674         if (!(crtc_state->hw.adjusted_mode.flags &
4675               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4676                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4677
4678         ret = compute_baseline_pipe_bpp(state, crtc);
4679         if (ret)
4680                 return ret;
4681
4682         crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4683
4684         if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
4685                 drm_dbg_kms(&i915->drm,
4686                             "[CRTC:%d:%s] Link bpp limited to " BPP_X16_FMT "\n",
4687                             crtc->base.base.id, crtc->base.name,
4688                             BPP_X16_ARGS(crtc_state->max_link_bpp_x16));
4689                 crtc_state->bw_constrained = true;
4690         }
4691
4692         base_bpp = crtc_state->pipe_bpp;
4693
4694         /*
4695          * Determine the real pipe dimensions. Note that stereo modes can
4696          * increase the actual pipe size due to the frame doubling and
4697          * insertion of additional space for blanks between the frame. This
4698          * is stored in the crtc timings. We use the requested mode to do this
4699          * computation to clearly distinguish it from the adjusted mode, which
4700          * can be changed by the connectors in the below retry loop.
4701          */
4702         drm_mode_get_hv_timing(&crtc_state->hw.mode,
4703                                &pipe_src_w, &pipe_src_h);
4704         drm_rect_init(&crtc_state->pipe_src, 0, 0,
4705                       pipe_src_w, pipe_src_h);
4706
4707         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4708                 struct intel_encoder *encoder =
4709                         to_intel_encoder(connector_state->best_encoder);
4710
4711                 if (connector_state->crtc != &crtc->base)
4712                         continue;
4713
4714                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
4715                         drm_dbg_kms(&i915->drm,
4716                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4717                                     encoder->base.base.id, encoder->base.name);
4718                         return -EINVAL;
4719                 }
4720
4721                 /*
4722                  * Determine output_types before calling the .compute_config()
4723                  * hooks so that the hooks can use this information safely.
4724                  */
4725                 if (encoder->compute_output_type)
4726                         crtc_state->output_types |=
4727                                 BIT(encoder->compute_output_type(encoder, crtc_state,
4728                                                                  connector_state));
4729                 else
4730                         crtc_state->output_types |= BIT(encoder->type);
4731         }
4732
4733         /* Ensure the port clock defaults are reset when retrying. */
4734         crtc_state->port_clock = 0;
4735         crtc_state->pixel_multiplier = 1;
4736
4737         /* Fill in default crtc timings, allow encoders to overwrite them. */
4738         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4739                               CRTC_STEREO_DOUBLE);
4740
4741         /* Pass our mode to the connectors and the CRTC to give them a chance to
4742          * adjust it according to limitations or connector properties, and also
4743          * a chance to reject the mode entirely.
4744          */
4745         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4746                 struct intel_encoder *encoder =
4747                         to_intel_encoder(connector_state->best_encoder);
4748
4749                 if (connector_state->crtc != &crtc->base)
4750                         continue;
4751
4752                 ret = encoder->compute_config(encoder, crtc_state,
4753                                               connector_state);
4754                 if (ret == -EDEADLK)
4755                         return ret;
4756                 if (ret < 0) {
4757                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
4758                                     encoder->base.base.id, encoder->base.name, ret);
4759                         return ret;
4760                 }
4761         }
4762
4763         /* Set default port clock if not overwritten by the encoder. Needs to be
4764          * done afterwards in case the encoder adjusts the mode. */
4765         if (!crtc_state->port_clock)
4766                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4767                         * crtc_state->pixel_multiplier;
4768
4769         ret = intel_crtc_compute_config(state, crtc);
4770         if (ret == -EDEADLK)
4771                 return ret;
4772         if (ret < 0) {
4773                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
4774                             crtc->base.base.id, crtc->base.name, ret);
4775                 return ret;
4776         }
4777
4778         /* Dithering seems to not pass-through bits correctly when it should, so
4779          * only enable it on 6bpc panels and when its not a compliance
4780          * test requesting 6bpc video pattern.
4781          */
4782         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4783                 !crtc_state->dither_force_disable;
4784         drm_dbg_kms(&i915->drm,
4785                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4786                     crtc->base.base.id, crtc->base.name,
4787                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4788
4789         return 0;
4790 }
4791
4792 static int
4793 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4794                                struct intel_crtc *crtc)
4795 {
4796         struct intel_crtc_state *crtc_state =
4797                 intel_atomic_get_new_crtc_state(state, crtc);
4798         struct drm_connector_state *conn_state;
4799         struct drm_connector *connector;
4800         int i;
4801
4802         intel_bigjoiner_adjust_pipe_src(crtc_state);
4803
4804         for_each_new_connector_in_state(&state->base, connector,
4805                                         conn_state, i) {
4806                 struct intel_encoder *encoder =
4807                         to_intel_encoder(conn_state->best_encoder);
4808                 int ret;
4809
4810                 if (conn_state->crtc != &crtc->base ||
4811                     !encoder->compute_config_late)
4812                         continue;
4813
4814                 ret = encoder->compute_config_late(encoder, crtc_state,
4815                                                    conn_state);
4816                 if (ret)
4817                         return ret;
4818         }
4819
4820         return 0;
4821 }
4822
4823 bool intel_fuzzy_clock_check(int clock1, int clock2)
4824 {
4825         int diff;
4826
4827         if (clock1 == clock2)
4828                 return true;
4829
4830         if (!clock1 || !clock2)
4831                 return false;
4832
4833         diff = abs(clock1 - clock2);
4834
4835         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4836                 return true;
4837
4838         return false;
4839 }
4840
4841 static bool
4842 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4843                        const struct intel_link_m_n *m2_n2)
4844 {
4845         return m_n->tu == m2_n2->tu &&
4846                 m_n->data_m == m2_n2->data_m &&
4847                 m_n->data_n == m2_n2->data_n &&
4848                 m_n->link_m == m2_n2->link_m &&
4849                 m_n->link_n == m2_n2->link_n;
4850 }
4851
4852 static bool
4853 intel_compare_infoframe(const union hdmi_infoframe *a,
4854                         const union hdmi_infoframe *b)
4855 {
4856         return memcmp(a, b, sizeof(*a)) == 0;
4857 }
4858
4859 static bool
4860 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4861                          const struct drm_dp_vsc_sdp *b)
4862 {
4863         return memcmp(a, b, sizeof(*a)) == 0;
4864 }
4865
4866 static bool
4867 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4868 {
4869         return memcmp(a, b, len) == 0;
4870 }
4871
4872 static void
4873 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
4874                                bool fastset, const char *name,
4875                                const union hdmi_infoframe *a,
4876                                const union hdmi_infoframe *b)
4877 {
4878         if (fastset) {
4879                 if (!drm_debug_enabled(DRM_UT_KMS))
4880                         return;
4881
4882                 drm_dbg_kms(&dev_priv->drm,
4883                             "fastset requirement not met in %s infoframe\n", name);
4884                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4885                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
4886                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4887                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
4888         } else {
4889                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
4890                 drm_err(&dev_priv->drm, "expected:\n");
4891                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
4892                 drm_err(&dev_priv->drm, "found:\n");
4893                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
4894         }
4895 }
4896
4897 static void
4898 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
4899                                 bool fastset, const char *name,
4900                                 const struct drm_dp_vsc_sdp *a,
4901                                 const struct drm_dp_vsc_sdp *b)
4902 {
4903         if (fastset) {
4904                 if (!drm_debug_enabled(DRM_UT_KMS))
4905                         return;
4906
4907                 drm_dbg_kms(&dev_priv->drm,
4908                             "fastset requirement not met in %s dp sdp\n", name);
4909                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4910                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
4911                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4912                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
4913         } else {
4914                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
4915                 drm_err(&dev_priv->drm, "expected:\n");
4916                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
4917                 drm_err(&dev_priv->drm, "found:\n");
4918                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
4919         }
4920 }
4921
4922 /* Returns the length up to and including the last differing byte */
4923 static size_t
4924 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4925 {
4926         int i;
4927
4928         for (i = len - 1; i >= 0; i--) {
4929                 if (a[i] != b[i])
4930                         return i + 1;
4931         }
4932
4933         return 0;
4934 }
4935
4936 static void
4937 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv,
4938                             bool fastset, const char *name,
4939                             const u8 *a, const u8 *b, size_t len)
4940 {
4941         if (fastset) {
4942                 if (!drm_debug_enabled(DRM_UT_KMS))
4943                         return;
4944
4945                 /* only dump up to the last difference */
4946                 len = memcmp_diff_len(a, b, len);
4947
4948                 drm_dbg_kms(&dev_priv->drm,
4949                             "fastset requirement not met in %s buffer\n", name);
4950                 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
4951                                16, 0, a, len, false);
4952                 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
4953                                16, 0, b, len, false);
4954         } else {
4955                 /* only dump up to the last difference */
4956                 len = memcmp_diff_len(a, b, len);
4957
4958                 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);
4959                 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE,
4960                                16, 0, a, len, false);
4961                 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE,
4962                                16, 0, b, len, false);
4963         }
4964 }
4965
4966 static void __printf(4, 5)
4967 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
4968                      const char *name, const char *format, ...)
4969 {
4970         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4971         struct va_format vaf;
4972         va_list args;
4973
4974         va_start(args, format);
4975         vaf.fmt = format;
4976         vaf.va = &args;
4977
4978         if (fastset)
4979                 drm_dbg_kms(&i915->drm,
4980                             "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4981                             crtc->base.base.id, crtc->base.name, name, &vaf);
4982         else
4983                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
4984                         crtc->base.base.id, crtc->base.name, name, &vaf);
4985
4986         va_end(args);
4987 }
4988
4989 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
4990 {
4991         /* Enable fastboot by default on Skylake and newer */
4992         if (DISPLAY_VER(dev_priv) >= 9)
4993                 return true;
4994
4995         /* Enable fastboot by default on VLV and CHV */
4996         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4997                 return true;
4998
4999         /* Disabled by default on all others */
5000         return false;
5001 }
5002
5003 bool
5004 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5005                           const struct intel_crtc_state *pipe_config,
5006                           bool fastset)
5007 {
5008         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5009         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5010         bool ret = true;
5011         bool fixup_inherited = fastset &&
5012                 current_config->inherited && !pipe_config->inherited;
5013
5014         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5015                 drm_dbg_kms(&dev_priv->drm,
5016                             "initial modeset and fastboot not set\n");
5017                 ret = false;
5018         }
5019
5020 #define PIPE_CONF_CHECK_X(name) do { \
5021         if (current_config->name != pipe_config->name) { \
5022                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5023                                      "(expected 0x%08x, found 0x%08x)", \
5024                                      current_config->name, \
5025                                      pipe_config->name); \
5026                 ret = false; \
5027         } \
5028 } while (0)
5029
5030 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5031         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5032                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5033                                      "(expected 0x%08x, found 0x%08x)", \
5034                                      current_config->name & (mask), \
5035                                      pipe_config->name & (mask)); \
5036                 ret = false; \
5037         } \
5038 } while (0)
5039
5040 #define PIPE_CONF_CHECK_I(name) do { \
5041         if (current_config->name != pipe_config->name) { \
5042                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5043                                      "(expected %i, found %i)", \
5044                                      current_config->name, \
5045                                      pipe_config->name); \
5046                 ret = false; \
5047         } \
5048 } while (0)
5049
5050 #define PIPE_CONF_CHECK_BOOL(name) do { \
5051         if (current_config->name != pipe_config->name) { \
5052                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5053                                      "(expected %s, found %s)", \
5054                                      str_yes_no(current_config->name), \
5055                                      str_yes_no(pipe_config->name)); \
5056                 ret = false; \
5057         } \
5058 } while (0)
5059
5060 /*
5061  * Checks state where we only read out the enabling, but not the entire
5062  * state itself (like full infoframes or ELD for audio). These states
5063  * require a full modeset on bootup to fix up.
5064  */
5065 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5066         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5067                 PIPE_CONF_CHECK_BOOL(name); \
5068         } else { \
5069                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5070                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5071                                      str_yes_no(current_config->name), \
5072                                      str_yes_no(pipe_config->name)); \
5073                 ret = false; \
5074         } \
5075 } while (0)
5076
5077 #define PIPE_CONF_CHECK_P(name) do { \
5078         if (current_config->name != pipe_config->name) { \
5079                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5080                                      "(expected %p, found %p)", \
5081                                      current_config->name, \
5082                                      pipe_config->name); \
5083                 ret = false; \
5084         } \
5085 } while (0)
5086
5087 #define PIPE_CONF_CHECK_M_N(name) do { \
5088         if (!intel_compare_link_m_n(&current_config->name, \
5089                                     &pipe_config->name)) { \
5090                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5091                                      "(expected tu %i data %i/%i link %i/%i, " \
5092                                      "found tu %i, data %i/%i link %i/%i)", \
5093                                      current_config->name.tu, \
5094                                      current_config->name.data_m, \
5095                                      current_config->name.data_n, \
5096                                      current_config->name.link_m, \
5097                                      current_config->name.link_n, \
5098                                      pipe_config->name.tu, \
5099                                      pipe_config->name.data_m, \
5100                                      pipe_config->name.data_n, \
5101                                      pipe_config->name.link_m, \
5102                                      pipe_config->name.link_n); \
5103                 ret = false; \
5104         } \
5105 } while (0)
5106
5107 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5108         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5109         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5110         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5111         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5112         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5113         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5114         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5115         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5116         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5117         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5118         if (!fastset || !pipe_config->update_lrr) { \
5119                 PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5120                 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5121         } \
5122 } while (0)
5123
5124 #define PIPE_CONF_CHECK_RECT(name) do { \
5125         PIPE_CONF_CHECK_I(name.x1); \
5126         PIPE_CONF_CHECK_I(name.x2); \
5127         PIPE_CONF_CHECK_I(name.y1); \
5128         PIPE_CONF_CHECK_I(name.y2); \
5129 } while (0)
5130
5131 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5132         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5133                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5134                                      "(%x) (expected %i, found %i)", \
5135                                      (mask), \
5136                                      current_config->name & (mask), \
5137                                      pipe_config->name & (mask)); \
5138                 ret = false; \
5139         } \
5140 } while (0)
5141
5142 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5143         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5144                                      &pipe_config->infoframes.name)) { \
5145                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5146                                                &current_config->infoframes.name, \
5147                                                &pipe_config->infoframes.name); \
5148                 ret = false; \
5149         } \
5150 } while (0)
5151
5152 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5153         if (!current_config->has_psr && !pipe_config->has_psr && \
5154             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5155                                       &pipe_config->infoframes.name)) { \
5156                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5157                                                 &current_config->infoframes.name, \
5158                                                 &pipe_config->infoframes.name); \
5159                 ret = false; \
5160         } \
5161 } while (0)
5162
5163 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5164         BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5165         BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5166         if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5167                 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \
5168                                             current_config->name, \
5169                                             pipe_config->name, \
5170                                             (len)); \
5171                 ret = false; \
5172         } \
5173 } while (0)
5174
5175 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5176         if (current_config->gamma_mode == pipe_config->gamma_mode && \
5177             !intel_color_lut_equal(current_config, \
5178                                    current_config->lut, pipe_config->lut, \
5179                                    is_pre_csc_lut)) {   \
5180                 pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5181                                      "hw_state doesn't match sw_state"); \
5182                 ret = false; \
5183         } \
5184 } while (0)
5185
5186 #define PIPE_CONF_CHECK_CSC(name) do { \
5187         PIPE_CONF_CHECK_X(name.preoff[0]); \
5188         PIPE_CONF_CHECK_X(name.preoff[1]); \
5189         PIPE_CONF_CHECK_X(name.preoff[2]); \
5190         PIPE_CONF_CHECK_X(name.coeff[0]); \
5191         PIPE_CONF_CHECK_X(name.coeff[1]); \
5192         PIPE_CONF_CHECK_X(name.coeff[2]); \
5193         PIPE_CONF_CHECK_X(name.coeff[3]); \
5194         PIPE_CONF_CHECK_X(name.coeff[4]); \
5195         PIPE_CONF_CHECK_X(name.coeff[5]); \
5196         PIPE_CONF_CHECK_X(name.coeff[6]); \
5197         PIPE_CONF_CHECK_X(name.coeff[7]); \
5198         PIPE_CONF_CHECK_X(name.coeff[8]); \
5199         PIPE_CONF_CHECK_X(name.postoff[0]); \
5200         PIPE_CONF_CHECK_X(name.postoff[1]); \
5201         PIPE_CONF_CHECK_X(name.postoff[2]); \
5202 } while (0)
5203
5204 #define PIPE_CONF_QUIRK(quirk) \
5205         ((current_config->quirks | pipe_config->quirks) & (quirk))
5206
5207         PIPE_CONF_CHECK_I(hw.enable);
5208         PIPE_CONF_CHECK_I(hw.active);
5209
5210         PIPE_CONF_CHECK_I(cpu_transcoder);
5211         PIPE_CONF_CHECK_I(mst_master_transcoder);
5212
5213         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5214         PIPE_CONF_CHECK_I(fdi_lanes);
5215         PIPE_CONF_CHECK_M_N(fdi_m_n);
5216
5217         PIPE_CONF_CHECK_I(lane_count);
5218         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5219
5220         if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5221                 if (!fastset || !pipe_config->update_m_n)
5222                         PIPE_CONF_CHECK_M_N(dp_m_n);
5223         } else {
5224                 PIPE_CONF_CHECK_M_N(dp_m_n);
5225                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5226         }
5227
5228         PIPE_CONF_CHECK_X(output_types);
5229
5230         PIPE_CONF_CHECK_I(framestart_delay);
5231         PIPE_CONF_CHECK_I(msa_timing_delay);
5232
5233         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5234         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5235
5236         PIPE_CONF_CHECK_I(pixel_multiplier);
5237
5238         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5239                               DRM_MODE_FLAG_INTERLACE);
5240
5241         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5242                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5243                                       DRM_MODE_FLAG_PHSYNC);
5244                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5245                                       DRM_MODE_FLAG_NHSYNC);
5246                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5247                                       DRM_MODE_FLAG_PVSYNC);
5248                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5249                                       DRM_MODE_FLAG_NVSYNC);
5250         }
5251
5252         PIPE_CONF_CHECK_I(output_format);
5253         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5254         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5255             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5256                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5257
5258         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5259         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5260         PIPE_CONF_CHECK_BOOL(has_infoframe);
5261         PIPE_CONF_CHECK_BOOL(enhanced_framing);
5262         PIPE_CONF_CHECK_BOOL(fec_enable);
5263
5264         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5265         PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5266
5267         PIPE_CONF_CHECK_X(gmch_pfit.control);
5268         /* pfit ratios are autocomputed by the hw on gen4+ */
5269         if (DISPLAY_VER(dev_priv) < 4)
5270                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5271         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5272
5273         /*
5274          * Changing the EDP transcoder input mux
5275          * (A_ONOFF vs. A_ON) requires a full modeset.
5276          */
5277         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5278
5279         if (!fastset) {
5280                 PIPE_CONF_CHECK_RECT(pipe_src);
5281
5282                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5283                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5284
5285                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5286                 PIPE_CONF_CHECK_I(pixel_rate);
5287
5288                 PIPE_CONF_CHECK_X(gamma_mode);
5289                 if (IS_CHERRYVIEW(dev_priv))
5290                         PIPE_CONF_CHECK_X(cgm_mode);
5291                 else
5292                         PIPE_CONF_CHECK_X(csc_mode);
5293                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5294                 PIPE_CONF_CHECK_BOOL(csc_enable);
5295                 PIPE_CONF_CHECK_BOOL(wgc_enable);
5296
5297                 PIPE_CONF_CHECK_I(linetime);
5298                 PIPE_CONF_CHECK_I(ips_linetime);
5299
5300                 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5301                 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5302
5303                 PIPE_CONF_CHECK_CSC(csc);
5304                 PIPE_CONF_CHECK_CSC(output_csc);
5305
5306                 if (current_config->active_planes) {
5307                         PIPE_CONF_CHECK_BOOL(has_psr);
5308                         PIPE_CONF_CHECK_BOOL(has_psr2);
5309                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5310                         PIPE_CONF_CHECK_I(dc3co_exitline);
5311                 }
5312         }
5313
5314         PIPE_CONF_CHECK_BOOL(double_wide);
5315
5316         if (dev_priv->display.dpll.mgr) {
5317                 PIPE_CONF_CHECK_P(shared_dpll);
5318
5319                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5320                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5321                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5322                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5323                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5324                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5325                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5326                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5327                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5328                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5329                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5330                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5331                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5332                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5333                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5334                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5335                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5336                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5337                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5338                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5339                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5340                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5341                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5342                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5343                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5344                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5345                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5346                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5347                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5348                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5349                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5350                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5351         }
5352
5353         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5354         PIPE_CONF_CHECK_X(dsi_pll.div);
5355
5356         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5357                 PIPE_CONF_CHECK_I(pipe_bpp);
5358
5359         if (!fastset || !pipe_config->update_m_n) {
5360                 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5361                 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5362         }
5363         PIPE_CONF_CHECK_I(port_clock);
5364
5365         PIPE_CONF_CHECK_I(min_voltage_level);
5366
5367         if (current_config->has_psr || pipe_config->has_psr)
5368                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5369                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5370         else
5371                 PIPE_CONF_CHECK_X(infoframes.enable);
5372
5373         PIPE_CONF_CHECK_X(infoframes.gcp);
5374         PIPE_CONF_CHECK_INFOFRAME(avi);
5375         PIPE_CONF_CHECK_INFOFRAME(spd);
5376         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5377         PIPE_CONF_CHECK_INFOFRAME(drm);
5378         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5379
5380         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5381         PIPE_CONF_CHECK_I(master_transcoder);
5382         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5383
5384         PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5385         PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5386         PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5387         PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5388         PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5389         PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5390         PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5391         PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5392         PIPE_CONF_CHECK_I(dsc.config.pic_width);
5393         PIPE_CONF_CHECK_I(dsc.config.pic_height);
5394         PIPE_CONF_CHECK_I(dsc.config.slice_width);
5395         PIPE_CONF_CHECK_I(dsc.config.slice_height);
5396         PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5397         PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5398         PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5399         PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5400         PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5401         PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5402         PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5403         PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5404         PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5405         PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5406         PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5407         PIPE_CONF_CHECK_I(dsc.config.final_offset);
5408         PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5409         PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5410         PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5411         PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5412         PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5413         PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5414
5415         PIPE_CONF_CHECK_I(dsc.compression_enable);
5416         PIPE_CONF_CHECK_I(dsc.dsc_split);
5417         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5418
5419         PIPE_CONF_CHECK_BOOL(splitter.enable);
5420         PIPE_CONF_CHECK_I(splitter.link_count);
5421         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5422
5423         if (!fastset) {
5424                 PIPE_CONF_CHECK_BOOL(vrr.enable);
5425                 PIPE_CONF_CHECK_I(vrr.vmin);
5426                 PIPE_CONF_CHECK_I(vrr.vmax);
5427                 PIPE_CONF_CHECK_I(vrr.flipline);
5428                 PIPE_CONF_CHECK_I(vrr.pipeline_full);
5429                 PIPE_CONF_CHECK_I(vrr.guardband);
5430         }
5431
5432 #undef PIPE_CONF_CHECK_X
5433 #undef PIPE_CONF_CHECK_I
5434 #undef PIPE_CONF_CHECK_BOOL
5435 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5436 #undef PIPE_CONF_CHECK_P
5437 #undef PIPE_CONF_CHECK_FLAGS
5438 #undef PIPE_CONF_CHECK_COLOR_LUT
5439 #undef PIPE_CONF_CHECK_TIMINGS
5440 #undef PIPE_CONF_CHECK_RECT
5441 #undef PIPE_CONF_QUIRK
5442
5443         return ret;
5444 }
5445
5446 static void
5447 intel_verify_planes(struct intel_atomic_state *state)
5448 {
5449         struct intel_plane *plane;
5450         const struct intel_plane_state *plane_state;
5451         int i;
5452
5453         for_each_new_intel_plane_in_state(state, plane,
5454                                           plane_state, i)
5455                 assert_plane(plane, plane_state->planar_slave ||
5456                              plane_state->uapi.visible);
5457 }
5458
5459 static int intel_modeset_pipe(struct intel_atomic_state *state,
5460                               struct intel_crtc_state *crtc_state,
5461                               const char *reason)
5462 {
5463         struct drm_i915_private *i915 = to_i915(state->base.dev);
5464         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5465         int ret;
5466
5467         drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5468                     crtc->base.base.id, crtc->base.name, reason);
5469
5470         ret = drm_atomic_add_affected_connectors(&state->base,
5471                                                  &crtc->base);
5472         if (ret)
5473                 return ret;
5474
5475         ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5476         if (ret)
5477                 return ret;
5478
5479         ret = intel_atomic_add_affected_planes(state, crtc);
5480         if (ret)
5481                 return ret;
5482
5483         crtc_state->uapi.mode_changed = true;
5484
5485         return 0;
5486 }
5487
5488 /**
5489  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5490  * @state: intel atomic state
5491  * @reason: the reason for the full modeset
5492  * @mask: mask of pipes to modeset
5493  *
5494  * Add pipes in @mask to @state and force a full modeset on the enabled ones
5495  * due to the description in @reason.
5496  * This function can be called only before new plane states are computed.
5497  *
5498  * Returns 0 in case of success, negative error code otherwise.
5499  */
5500 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5501                                       const char *reason, u8 mask)
5502 {
5503         struct drm_i915_private *i915 = to_i915(state->base.dev);
5504         struct intel_crtc *crtc;
5505
5506         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {
5507                 struct intel_crtc_state *crtc_state;
5508                 int ret;
5509
5510                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5511                 if (IS_ERR(crtc_state))
5512                         return PTR_ERR(crtc_state);
5513
5514                 if (!crtc_state->hw.enable ||
5515                     intel_crtc_needs_modeset(crtc_state))
5516                         continue;
5517
5518                 ret = intel_modeset_pipe(state, crtc_state, reason);
5519                 if (ret)
5520                         return ret;
5521         }
5522
5523         return 0;
5524 }
5525
5526 /**
5527  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5528  * @state: intel atomic state
5529  * @reason: the reason for the full modeset
5530  *
5531  * Add all pipes to @state and force a full modeset on the active ones due to
5532  * the description in @reason.
5533  * This function can be called only after new plane states are computed already.
5534  *
5535  * Returns 0 in case of success, negative error code otherwise.
5536  */
5537 int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5538                                  const char *reason)
5539 {
5540         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5541         struct intel_crtc *crtc;
5542
5543         for_each_intel_crtc(&dev_priv->drm, crtc) {
5544                 struct intel_crtc_state *crtc_state;
5545                 int ret;
5546
5547                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5548                 if (IS_ERR(crtc_state))
5549                         return PTR_ERR(crtc_state);
5550
5551                 if (!crtc_state->hw.active ||
5552                     intel_crtc_needs_modeset(crtc_state))
5553                         continue;
5554
5555                 ret = intel_modeset_pipe(state, crtc_state, reason);
5556                 if (ret)
5557                         return ret;
5558
5559                 crtc_state->update_pipe = false;
5560                 crtc_state->update_m_n = false;
5561                 crtc_state->update_lrr = false;
5562                 crtc_state->update_planes |= crtc_state->active_planes;
5563                 crtc_state->async_flip_planes = 0;
5564                 crtc_state->do_async_flip = false;
5565         }
5566
5567         return 0;
5568 }
5569
5570 /*
5571  * This implements the workaround described in the "notes" section of the mode
5572  * set sequence documentation. When going from no pipes or single pipe to
5573  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5574  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5575  */
5576 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5577 {
5578         struct intel_crtc_state *crtc_state;
5579         struct intel_crtc *crtc;
5580         struct intel_crtc_state *first_crtc_state = NULL;
5581         struct intel_crtc_state *other_crtc_state = NULL;
5582         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5583         int i;
5584
5585         /* look at all crtc's that are going to be enabled in during modeset */
5586         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5587                 if (!crtc_state->hw.active ||
5588                     !intel_crtc_needs_modeset(crtc_state))
5589                         continue;
5590
5591                 if (first_crtc_state) {
5592                         other_crtc_state = crtc_state;
5593                         break;
5594                 } else {
5595                         first_crtc_state = crtc_state;
5596                         first_pipe = crtc->pipe;
5597                 }
5598         }
5599
5600         /* No workaround needed? */
5601         if (!first_crtc_state)
5602                 return 0;
5603
5604         /* w/a possibly needed, check how many crtc's are already enabled. */
5605         for_each_intel_crtc(state->base.dev, crtc) {
5606                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5607                 if (IS_ERR(crtc_state))
5608                         return PTR_ERR(crtc_state);
5609
5610                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5611
5612                 if (!crtc_state->hw.active ||
5613                     intel_crtc_needs_modeset(crtc_state))
5614                         continue;
5615
5616                 /* 2 or more enabled crtcs means no need for w/a */
5617                 if (enabled_pipe != INVALID_PIPE)
5618                         return 0;
5619
5620                 enabled_pipe = crtc->pipe;
5621         }
5622
5623         if (enabled_pipe != INVALID_PIPE)
5624                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5625         else if (other_crtc_state)
5626                 other_crtc_state->hsw_workaround_pipe = first_pipe;
5627
5628         return 0;
5629 }
5630
5631 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5632                            u8 active_pipes)
5633 {
5634         const struct intel_crtc_state *crtc_state;
5635         struct intel_crtc *crtc;
5636         int i;
5637
5638         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5639                 if (crtc_state->hw.active)
5640                         active_pipes |= BIT(crtc->pipe);
5641                 else
5642                         active_pipes &= ~BIT(crtc->pipe);
5643         }
5644
5645         return active_pipes;
5646 }
5647
5648 static int intel_modeset_checks(struct intel_atomic_state *state)
5649 {
5650         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5651
5652         state->modeset = true;
5653
5654         if (IS_HASWELL(dev_priv))
5655                 return hsw_mode_set_planes_workaround(state);
5656
5657         return 0;
5658 }
5659
5660 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5661                                      struct intel_crtc_state *new_crtc_state)
5662 {
5663         struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
5664
5665         /* only allow LRR when the timings stay within the VRR range */
5666         if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5667                 new_crtc_state->update_lrr = false;
5668
5669         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
5670                 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
5671         else
5672                 new_crtc_state->uapi.mode_changed = false;
5673
5674         if (intel_crtc_needs_modeset(new_crtc_state) ||
5675             intel_compare_link_m_n(&old_crtc_state->dp_m_n,
5676                                    &new_crtc_state->dp_m_n))
5677                 new_crtc_state->update_m_n = false;
5678
5679         if (intel_crtc_needs_modeset(new_crtc_state) ||
5680             (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal &&
5681              old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end))
5682                 new_crtc_state->update_lrr = false;
5683
5684         if (!intel_crtc_needs_modeset(new_crtc_state))
5685                 new_crtc_state->update_pipe = true;
5686 }
5687
5688 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
5689                                           struct intel_crtc *crtc,
5690                                           u8 plane_ids_mask)
5691 {
5692         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5693         struct intel_plane *plane;
5694
5695         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5696                 struct intel_plane_state *plane_state;
5697
5698                 if ((plane_ids_mask & BIT(plane->id)) == 0)
5699                         continue;
5700
5701                 plane_state = intel_atomic_get_plane_state(state, plane);
5702                 if (IS_ERR(plane_state))
5703                         return PTR_ERR(plane_state);
5704         }
5705
5706         return 0;
5707 }
5708
5709 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
5710                                      struct intel_crtc *crtc)
5711 {
5712         const struct intel_crtc_state *old_crtc_state =
5713                 intel_atomic_get_old_crtc_state(state, crtc);
5714         const struct intel_crtc_state *new_crtc_state =
5715                 intel_atomic_get_new_crtc_state(state, crtc);
5716
5717         return intel_crtc_add_planes_to_state(state, crtc,
5718                                               old_crtc_state->enabled_planes |
5719                                               new_crtc_state->enabled_planes);
5720 }
5721
5722 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5723 {
5724         /* See {hsw,vlv,ivb}_plane_ratio() */
5725         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5726                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5727                 IS_IVYBRIDGE(dev_priv);
5728 }
5729
5730 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
5731                                            struct intel_crtc *crtc,
5732                                            struct intel_crtc *other)
5733 {
5734         const struct intel_plane_state __maybe_unused *plane_state;
5735         struct intel_plane *plane;
5736         u8 plane_ids = 0;
5737         int i;
5738
5739         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5740                 if (plane->pipe == crtc->pipe)
5741                         plane_ids |= BIT(plane->id);
5742         }
5743
5744         return intel_crtc_add_planes_to_state(state, other, plane_ids);
5745 }
5746
5747 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
5748 {
5749         struct drm_i915_private *i915 = to_i915(state->base.dev);
5750         const struct intel_crtc_state *crtc_state;
5751         struct intel_crtc *crtc;
5752         int i;
5753
5754         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5755                 struct intel_crtc *other;
5756
5757                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
5758                                                  crtc_state->bigjoiner_pipes) {
5759                         int ret;
5760
5761                         if (crtc == other)
5762                                 continue;
5763
5764                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
5765                         if (ret)
5766                                 return ret;
5767                 }
5768         }
5769
5770         return 0;
5771 }
5772
5773 static int intel_atomic_check_planes(struct intel_atomic_state *state)
5774 {
5775         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5776         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5777         struct intel_plane_state __maybe_unused *plane_state;
5778         struct intel_plane *plane;
5779         struct intel_crtc *crtc;
5780         int i, ret;
5781
5782         ret = icl_add_linked_planes(state);
5783         if (ret)
5784                 return ret;
5785
5786         ret = intel_bigjoiner_add_affected_planes(state);
5787         if (ret)
5788                 return ret;
5789
5790         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5791                 ret = intel_plane_atomic_check(state, plane);
5792                 if (ret) {
5793                         drm_dbg_atomic(&dev_priv->drm,
5794                                        "[PLANE:%d:%s] atomic driver check failed\n",
5795                                        plane->base.base.id, plane->base.name);
5796                         return ret;
5797                 }
5798         }
5799
5800         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5801                                             new_crtc_state, i) {
5802                 u8 old_active_planes, new_active_planes;
5803
5804                 ret = icl_check_nv12_planes(new_crtc_state);
5805                 if (ret)
5806                         return ret;
5807
5808                 /*
5809                  * On some platforms the number of active planes affects
5810                  * the planes' minimum cdclk calculation. Add such planes
5811                  * to the state before we compute the minimum cdclk.
5812                  */
5813                 if (!active_planes_affects_min_cdclk(dev_priv))
5814                         continue;
5815
5816                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5817                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5818
5819                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
5820                         continue;
5821
5822                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
5823                 if (ret)
5824                         return ret;
5825         }
5826
5827         return 0;
5828 }
5829
5830 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5831 {
5832         struct intel_crtc_state __maybe_unused *crtc_state;
5833         struct intel_crtc *crtc;
5834         int i;
5835
5836         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5837                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5838                 int ret;
5839
5840                 ret = intel_crtc_atomic_check(state, crtc);
5841                 if (ret) {
5842                         drm_dbg_atomic(&i915->drm,
5843                                        "[CRTC:%d:%s] atomic driver check failed\n",
5844                                        crtc->base.base.id, crtc->base.name);
5845                         return ret;
5846                 }
5847         }
5848
5849         return 0;
5850 }
5851
5852 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5853                                                u8 transcoders)
5854 {
5855         const struct intel_crtc_state *new_crtc_state;
5856         struct intel_crtc *crtc;
5857         int i;
5858
5859         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5860                 if (new_crtc_state->hw.enable &&
5861                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5862                     intel_crtc_needs_modeset(new_crtc_state))
5863                         return true;
5864         }
5865
5866         return false;
5867 }
5868
5869 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5870                                      u8 pipes)
5871 {
5872         const struct intel_crtc_state *new_crtc_state;
5873         struct intel_crtc *crtc;
5874         int i;
5875
5876         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5877                 if (new_crtc_state->hw.enable &&
5878                     pipes & BIT(crtc->pipe) &&
5879                     intel_crtc_needs_modeset(new_crtc_state))
5880                         return true;
5881         }
5882
5883         return false;
5884 }
5885
5886 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
5887                                         struct intel_crtc *master_crtc)
5888 {
5889         struct drm_i915_private *i915 = to_i915(state->base.dev);
5890         struct intel_crtc_state *master_crtc_state =
5891                 intel_atomic_get_new_crtc_state(state, master_crtc);
5892         struct intel_crtc *slave_crtc;
5893
5894         if (!master_crtc_state->bigjoiner_pipes)
5895                 return 0;
5896
5897         /* sanity check */
5898         if (drm_WARN_ON(&i915->drm,
5899                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
5900                 return -EINVAL;
5901
5902         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
5903                 drm_dbg_kms(&i915->drm,
5904                             "[CRTC:%d:%s] Cannot act as big joiner master "
5905                             "(need 0x%x as pipes, only 0x%x possible)\n",
5906                             master_crtc->base.base.id, master_crtc->base.name,
5907                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
5908                 return -EINVAL;
5909         }
5910
5911         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5912                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5913                 struct intel_crtc_state *slave_crtc_state;
5914                 int ret;
5915
5916                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
5917                 if (IS_ERR(slave_crtc_state))
5918                         return PTR_ERR(slave_crtc_state);
5919
5920                 /* master being enabled, slave was already configured? */
5921                 if (slave_crtc_state->uapi.enable) {
5922                         drm_dbg_kms(&i915->drm,
5923                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
5924                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
5925                                     slave_crtc->base.base.id, slave_crtc->base.name,
5926                                     master_crtc->base.base.id, master_crtc->base.name);
5927                         return -EINVAL;
5928                 }
5929
5930                 /*
5931                  * The state copy logic assumes the master crtc gets processed
5932                  * before the slave crtc during the main compute_config loop.
5933                  * This works because the crtcs are created in pipe order,
5934                  * and the hardware requires master pipe < slave pipe as well.
5935                  * Should that change we need to rethink the logic.
5936                  */
5937                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
5938                             drm_crtc_index(&slave_crtc->base)))
5939                         return -EINVAL;
5940
5941                 drm_dbg_kms(&i915->drm,
5942                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
5943                             slave_crtc->base.base.id, slave_crtc->base.name,
5944                             master_crtc->base.base.id, master_crtc->base.name);
5945
5946                 slave_crtc_state->bigjoiner_pipes =
5947                         master_crtc_state->bigjoiner_pipes;
5948
5949                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
5950                 if (ret)
5951                         return ret;
5952         }
5953
5954         return 0;
5955 }
5956
5957 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
5958                                  struct intel_crtc *master_crtc)
5959 {
5960         struct drm_i915_private *i915 = to_i915(state->base.dev);
5961         struct intel_crtc_state *master_crtc_state =
5962                 intel_atomic_get_new_crtc_state(state, master_crtc);
5963         struct intel_crtc *slave_crtc;
5964
5965         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5966                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5967                 struct intel_crtc_state *slave_crtc_state =
5968                         intel_atomic_get_new_crtc_state(state, slave_crtc);
5969
5970                 slave_crtc_state->bigjoiner_pipes = 0;
5971
5972                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
5973         }
5974
5975         master_crtc_state->bigjoiner_pipes = 0;
5976 }
5977
5978 /**
5979  * DOC: asynchronous flip implementation
5980  *
5981  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5982  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5983  * Correspondingly, support is currently added for primary plane only.
5984  *
5985  * Async flip can only change the plane surface address, so anything else
5986  * changing is rejected from the intel_async_flip_check_hw() function.
5987  * Once this check is cleared, flip done interrupt is enabled using
5988  * the intel_crtc_enable_flip_done() function.
5989  *
5990  * As soon as the surface address register is written, flip done interrupt is
5991  * generated and the requested events are sent to the usersapce in the interrupt
5992  * handler itself. The timestamp and sequence sent during the flip done event
5993  * correspond to the last vblank and have no relation to the actual time when
5994  * the flip done event was sent.
5995  */
5996 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
5997                                        struct intel_crtc *crtc)
5998 {
5999         struct drm_i915_private *i915 = to_i915(state->base.dev);
6000         const struct intel_crtc_state *new_crtc_state =
6001                 intel_atomic_get_new_crtc_state(state, crtc);
6002         const struct intel_plane_state *old_plane_state;
6003         struct intel_plane_state *new_plane_state;
6004         struct intel_plane *plane;
6005         int i;
6006
6007         if (!new_crtc_state->uapi.async_flip)
6008                 return 0;
6009
6010         if (!new_crtc_state->uapi.active) {
6011                 drm_dbg_kms(&i915->drm,
6012                             "[CRTC:%d:%s] not active\n",
6013                             crtc->base.base.id, crtc->base.name);
6014                 return -EINVAL;
6015         }
6016
6017         if (intel_crtc_needs_modeset(new_crtc_state)) {
6018                 drm_dbg_kms(&i915->drm,
6019                             "[CRTC:%d:%s] modeset required\n",
6020                             crtc->base.base.id, crtc->base.name);
6021                 return -EINVAL;
6022         }
6023
6024         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6025                                              new_plane_state, i) {
6026                 if (plane->pipe != crtc->pipe)
6027                         continue;
6028
6029                 /*
6030                  * TODO: Async flip is only supported through the page flip IOCTL
6031                  * as of now. So support currently added for primary plane only.
6032                  * Support for other planes on platforms on which supports
6033                  * this(vlv/chv and icl+) should be added when async flip is
6034                  * enabled in the atomic IOCTL path.
6035                  */
6036                 if (!plane->async_flip) {
6037                         drm_dbg_kms(&i915->drm,
6038                                     "[PLANE:%d:%s] async flip not supported\n",
6039                                     plane->base.base.id, plane->base.name);
6040                         return -EINVAL;
6041                 }
6042
6043                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6044                         drm_dbg_kms(&i915->drm,
6045                                     "[PLANE:%d:%s] no old or new framebuffer\n",
6046                                     plane->base.base.id, plane->base.name);
6047                         return -EINVAL;
6048                 }
6049         }
6050
6051         return 0;
6052 }
6053
6054 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6055 {
6056         struct drm_i915_private *i915 = to_i915(state->base.dev);
6057         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6058         const struct intel_plane_state *new_plane_state, *old_plane_state;
6059         struct intel_plane *plane;
6060         int i;
6061
6062         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6063         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6064
6065         if (!new_crtc_state->uapi.async_flip)
6066                 return 0;
6067
6068         if (!new_crtc_state->hw.active) {
6069                 drm_dbg_kms(&i915->drm,
6070                             "[CRTC:%d:%s] not active\n",
6071                             crtc->base.base.id, crtc->base.name);
6072                 return -EINVAL;
6073         }
6074
6075         if (intel_crtc_needs_modeset(new_crtc_state)) {
6076                 drm_dbg_kms(&i915->drm,
6077                             "[CRTC:%d:%s] modeset required\n",
6078                             crtc->base.base.id, crtc->base.name);
6079                 return -EINVAL;
6080         }
6081
6082         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6083                 drm_dbg_kms(&i915->drm,
6084                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
6085                             crtc->base.base.id, crtc->base.name);
6086                 return -EINVAL;
6087         }
6088
6089         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6090                                              new_plane_state, i) {
6091                 if (plane->pipe != crtc->pipe)
6092                         continue;
6093
6094                 /*
6095                  * Only async flip capable planes should be in the state
6096                  * if we're really about to ask the hardware to perform
6097                  * an async flip. We should never get this far otherwise.
6098                  */
6099                 if (drm_WARN_ON(&i915->drm,
6100                                 new_crtc_state->do_async_flip && !plane->async_flip))
6101                         return -EINVAL;
6102
6103                 /*
6104                  * Only check async flip capable planes other planes
6105                  * may be involved in the initial commit due to
6106                  * the wm0/ddb optimization.
6107                  *
6108                  * TODO maybe should track which planes actually
6109                  * were requested to do the async flip...
6110                  */
6111                 if (!plane->async_flip)
6112                         continue;
6113
6114                 /*
6115                  * FIXME: This check is kept generic for all platforms.
6116                  * Need to verify this for all gen9 platforms to enable
6117                  * this selectively if required.
6118                  */
6119                 switch (new_plane_state->hw.fb->modifier) {
6120                 case DRM_FORMAT_MOD_LINEAR:
6121                         /*
6122                          * FIXME: Async on Linear buffer is supported on ICL as
6123                          * but with additional alignment and fbc restrictions
6124                          * need to be taken care of. These aren't applicable for
6125                          * gen12+.
6126                          */
6127                         if (DISPLAY_VER(i915) < 12) {
6128                                 drm_dbg_kms(&i915->drm,
6129                                             "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
6130                                             plane->base.base.id, plane->base.name,
6131                                             new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
6132                                 return -EINVAL;
6133                         }
6134                         break;
6135
6136                 case I915_FORMAT_MOD_X_TILED:
6137                 case I915_FORMAT_MOD_Y_TILED:
6138                 case I915_FORMAT_MOD_Yf_TILED:
6139                 case I915_FORMAT_MOD_4_TILED:
6140                         break;
6141                 default:
6142                         drm_dbg_kms(&i915->drm,
6143                                     "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n",
6144                                     plane->base.base.id, plane->base.name,
6145                                     new_plane_state->hw.fb->modifier);
6146                         return -EINVAL;
6147                 }
6148
6149                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6150                         drm_dbg_kms(&i915->drm,
6151                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6152                                     plane->base.base.id, plane->base.name);
6153                         return -EINVAL;
6154                 }
6155
6156                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6157                     new_plane_state->view.color_plane[0].mapping_stride) {
6158                         drm_dbg_kms(&i915->drm,
6159                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6160                                     plane->base.base.id, plane->base.name);
6161                         return -EINVAL;
6162                 }
6163
6164                 if (old_plane_state->hw.fb->modifier !=
6165                     new_plane_state->hw.fb->modifier) {
6166                         drm_dbg_kms(&i915->drm,
6167                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6168                                     plane->base.base.id, plane->base.name);
6169                         return -EINVAL;
6170                 }
6171
6172                 if (old_plane_state->hw.fb->format !=
6173                     new_plane_state->hw.fb->format) {
6174                         drm_dbg_kms(&i915->drm,
6175                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6176                                     plane->base.base.id, plane->base.name);
6177                         return -EINVAL;
6178                 }
6179
6180                 if (old_plane_state->hw.rotation !=
6181                     new_plane_state->hw.rotation) {
6182                         drm_dbg_kms(&i915->drm,
6183                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6184                                     plane->base.base.id, plane->base.name);
6185                         return -EINVAL;
6186                 }
6187
6188                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6189                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6190                         drm_dbg_kms(&i915->drm,
6191                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6192                                     plane->base.base.id, plane->base.name);
6193                         return -EINVAL;
6194                 }
6195
6196                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6197                         drm_dbg_kms(&i915->drm,
6198                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6199                                     plane->base.base.id, plane->base.name);
6200                         return -EINVAL;
6201                 }
6202
6203                 if (old_plane_state->hw.pixel_blend_mode !=
6204                     new_plane_state->hw.pixel_blend_mode) {
6205                         drm_dbg_kms(&i915->drm,
6206                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6207                                     plane->base.base.id, plane->base.name);
6208                         return -EINVAL;
6209                 }
6210
6211                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6212                         drm_dbg_kms(&i915->drm,
6213                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6214                                     plane->base.base.id, plane->base.name);
6215                         return -EINVAL;
6216                 }
6217
6218                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6219                         drm_dbg_kms(&i915->drm,
6220                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6221                                     plane->base.base.id, plane->base.name);
6222                         return -EINVAL;
6223                 }
6224
6225                 /* plane decryption is allow to change only in synchronous flips */
6226                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6227                         drm_dbg_kms(&i915->drm,
6228                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6229                                     plane->base.base.id, plane->base.name);
6230                         return -EINVAL;
6231                 }
6232         }
6233
6234         return 0;
6235 }
6236
6237 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6238 {
6239         struct drm_i915_private *i915 = to_i915(state->base.dev);
6240         struct intel_crtc_state *crtc_state;
6241         struct intel_crtc *crtc;
6242         u8 affected_pipes = 0;
6243         u8 modeset_pipes = 0;
6244         int i;
6245
6246         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6247                 affected_pipes |= crtc_state->bigjoiner_pipes;
6248                 if (intel_crtc_needs_modeset(crtc_state))
6249                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6250         }
6251
6252         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6253                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6254                 if (IS_ERR(crtc_state))
6255                         return PTR_ERR(crtc_state);
6256         }
6257
6258         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6259                 int ret;
6260
6261                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6262
6263                 crtc_state->uapi.mode_changed = true;
6264
6265                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6266                 if (ret)
6267                         return ret;
6268
6269                 ret = intel_atomic_add_affected_planes(state, crtc);
6270                 if (ret)
6271                         return ret;
6272         }
6273
6274         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6275                 /* Kill old bigjoiner link, we may re-establish afterwards */
6276                 if (intel_crtc_needs_modeset(crtc_state) &&
6277                     intel_crtc_is_bigjoiner_master(crtc_state))
6278                         kill_bigjoiner_slave(state, crtc);
6279         }
6280
6281         return 0;
6282 }
6283
6284 static int intel_atomic_check_config(struct intel_atomic_state *state,
6285                                      struct intel_link_bw_limits *limits,
6286                                      enum pipe *failed_pipe)
6287 {
6288         struct drm_i915_private *i915 = to_i915(state->base.dev);
6289         struct intel_crtc_state *new_crtc_state;
6290         struct intel_crtc *crtc;
6291         int ret;
6292         int i;
6293
6294         *failed_pipe = INVALID_PIPE;
6295
6296         ret = intel_bigjoiner_add_affected_crtcs(state);
6297         if (ret)
6298                 return ret;
6299
6300         ret = intel_fdi_add_affected_crtcs(state);
6301         if (ret)
6302                 return ret;
6303
6304         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6305                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6306                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6307                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6308                         else
6309                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6310                         continue;
6311                 }
6312
6313                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6314                         drm_WARN_ON(&i915->drm, new_crtc_state->uapi.enable);
6315                         continue;
6316                 }
6317
6318                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6319                 if (ret)
6320                         break;
6321
6322                 if (!new_crtc_state->hw.enable)
6323                         continue;
6324
6325                 ret = intel_modeset_pipe_config(state, crtc, limits);
6326                 if (ret)
6327                         break;
6328
6329                 ret = intel_atomic_check_bigjoiner(state, crtc);
6330                 if (ret)
6331                         break;
6332         }
6333
6334         if (ret)
6335                 *failed_pipe = crtc->pipe;
6336
6337         return ret;
6338 }
6339
6340 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6341 {
6342         struct drm_i915_private *i915 = to_i915(state->base.dev);
6343         struct intel_link_bw_limits new_limits;
6344         struct intel_link_bw_limits old_limits;
6345         int ret;
6346
6347         intel_link_bw_init_limits(i915, &new_limits);
6348         old_limits = new_limits;
6349
6350         while (true) {
6351                 enum pipe failed_pipe;
6352
6353                 ret = intel_atomic_check_config(state, &new_limits,
6354                                                 &failed_pipe);
6355                 if (ret) {
6356                         /*
6357                          * The bpp limit for a pipe is below the minimum it supports, set the
6358                          * limit to the minimum and recalculate the config.
6359                          */
6360                         if (ret == -EINVAL &&
6361                             intel_link_bw_set_bpp_limit_for_pipe(state,
6362                                                                  &old_limits,
6363                                                                  &new_limits,
6364                                                                  failed_pipe))
6365                                 continue;
6366
6367                         break;
6368                 }
6369
6370                 old_limits = new_limits;
6371
6372                 ret = intel_link_bw_atomic_check(state, &new_limits);
6373                 if (ret != -EAGAIN)
6374                         break;
6375         }
6376
6377         return ret;
6378 }
6379 /**
6380  * intel_atomic_check - validate state object
6381  * @dev: drm device
6382  * @_state: state to validate
6383  */
6384 int intel_atomic_check(struct drm_device *dev,
6385                        struct drm_atomic_state *_state)
6386 {
6387         struct drm_i915_private *dev_priv = to_i915(dev);
6388         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6389         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6390         struct intel_crtc *crtc;
6391         int ret, i;
6392         bool any_ms = false;
6393
6394         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6395                                             new_crtc_state, i) {
6396                 /*
6397                  * crtc's state no longer considered to be inherited
6398                  * after the first userspace/client initiated commit.
6399                  */
6400                 if (!state->internal)
6401                         new_crtc_state->inherited = false;
6402
6403                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6404                         new_crtc_state->uapi.mode_changed = true;
6405
6406                 if (new_crtc_state->uapi.scaling_filter !=
6407                     old_crtc_state->uapi.scaling_filter)
6408                         new_crtc_state->uapi.mode_changed = true;
6409         }
6410
6411         intel_vrr_check_modeset(state);
6412
6413         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6414         if (ret)
6415                 goto fail;
6416
6417         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6418                 ret = intel_async_flip_check_uapi(state, crtc);
6419                 if (ret)
6420                         return ret;
6421         }
6422
6423         ret = intel_atomic_check_config_and_link(state);
6424         if (ret)
6425                 goto fail;
6426
6427         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6428                                             new_crtc_state, i) {
6429                 if (!intel_crtc_needs_modeset(new_crtc_state))
6430                         continue;
6431
6432                 if (new_crtc_state->hw.enable) {
6433                         ret = intel_modeset_pipe_config_late(state, crtc);
6434                         if (ret)
6435                                 goto fail;
6436                 }
6437
6438                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6439         }
6440
6441         /**
6442          * Check if fastset is allowed by external dependencies like other
6443          * pipes and transcoders.
6444          *
6445          * Right now it only forces a fullmodeset when the MST master
6446          * transcoder did not changed but the pipe of the master transcoder
6447          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6448          * in case of port synced crtcs, if one of the synced crtcs
6449          * needs a full modeset, all other synced crtcs should be
6450          * forced a full modeset.
6451          */
6452         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6453                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6454                         continue;
6455
6456                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6457                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6458
6459                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6460                                 new_crtc_state->uapi.mode_changed = true;
6461                                 new_crtc_state->update_pipe = false;
6462                                 new_crtc_state->update_m_n = false;
6463                                 new_crtc_state->update_lrr = false;
6464                         }
6465                 }
6466
6467                 if (is_trans_port_sync_mode(new_crtc_state)) {
6468                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6469
6470                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6471                                 trans |= BIT(new_crtc_state->master_transcoder);
6472
6473                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
6474                                 new_crtc_state->uapi.mode_changed = true;
6475                                 new_crtc_state->update_pipe = false;
6476                                 new_crtc_state->update_m_n = false;
6477                                 new_crtc_state->update_lrr = false;
6478                         }
6479                 }
6480
6481                 if (new_crtc_state->bigjoiner_pipes) {
6482                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6483                                 new_crtc_state->uapi.mode_changed = true;
6484                                 new_crtc_state->update_pipe = false;
6485                                 new_crtc_state->update_m_n = false;
6486                                 new_crtc_state->update_lrr = false;
6487                         }
6488                 }
6489         }
6490
6491         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6492                                             new_crtc_state, i) {
6493                 if (!intel_crtc_needs_modeset(new_crtc_state))
6494                         continue;
6495
6496                 any_ms = true;
6497
6498                 intel_release_shared_dplls(state, crtc);
6499         }
6500
6501         if (any_ms && !check_digital_port_conflicts(state)) {
6502                 drm_dbg_kms(&dev_priv->drm,
6503                             "rejecting conflicting digital port configuration\n");
6504                 ret = -EINVAL;
6505                 goto fail;
6506         }
6507
6508         ret = drm_dp_mst_atomic_check(&state->base);
6509         if (ret)
6510                 goto fail;
6511
6512         ret = intel_atomic_check_planes(state);
6513         if (ret)
6514                 goto fail;
6515
6516         ret = intel_compute_global_watermarks(state);
6517         if (ret)
6518                 goto fail;
6519
6520         ret = intel_bw_atomic_check(state);
6521         if (ret)
6522                 goto fail;
6523
6524         ret = intel_cdclk_atomic_check(state, &any_ms);
6525         if (ret)
6526                 goto fail;
6527
6528         if (intel_any_crtc_needs_modeset(state))
6529                 any_ms = true;
6530
6531         if (any_ms) {
6532                 ret = intel_modeset_checks(state);
6533                 if (ret)
6534                         goto fail;
6535
6536                 ret = intel_modeset_calc_cdclk(state);
6537                 if (ret)
6538                         return ret;
6539         }
6540
6541         ret = intel_pmdemand_atomic_check(state);
6542         if (ret)
6543                 goto fail;
6544
6545         ret = intel_atomic_check_crtcs(state);
6546         if (ret)
6547                 goto fail;
6548
6549         ret = intel_fbc_atomic_check(state);
6550         if (ret)
6551                 goto fail;
6552
6553         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6554                                             new_crtc_state, i) {
6555                 intel_color_assert_luts(new_crtc_state);
6556
6557                 ret = intel_async_flip_check_hw(state, crtc);
6558                 if (ret)
6559                         goto fail;
6560
6561                 /* Either full modeset or fastset (or neither), never both */
6562                 drm_WARN_ON(&dev_priv->drm,
6563                             intel_crtc_needs_modeset(new_crtc_state) &&
6564                             intel_crtc_needs_fastset(new_crtc_state));
6565
6566                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6567                     !intel_crtc_needs_fastset(new_crtc_state))
6568                         continue;
6569
6570                 intel_crtc_state_dump(new_crtc_state, state,
6571                                       intel_crtc_needs_modeset(new_crtc_state) ?
6572                                       "modeset" : "fastset");
6573         }
6574
6575         return 0;
6576
6577  fail:
6578         if (ret == -EDEADLK)
6579                 return ret;
6580
6581         /*
6582          * FIXME would probably be nice to know which crtc specifically
6583          * caused the failure, in cases where we can pinpoint it.
6584          */
6585         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6586                                             new_crtc_state, i)
6587                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6588
6589         return ret;
6590 }
6591
6592 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6593 {
6594         struct intel_crtc_state *crtc_state;
6595         struct intel_crtc *crtc;
6596         int i, ret;
6597
6598         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6599         if (ret < 0)
6600                 return ret;
6601
6602         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6603                 if (intel_crtc_needs_color_update(crtc_state))
6604                         intel_color_prepare_commit(crtc_state);
6605         }
6606
6607         return 0;
6608 }
6609
6610 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6611                                   struct intel_crtc_state *crtc_state)
6612 {
6613         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6614
6615         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6616                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6617
6618         if (crtc_state->has_pch_encoder) {
6619                 enum pipe pch_transcoder =
6620                         intel_crtc_pch_transcoder(crtc);
6621
6622                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6623         }
6624 }
6625
6626 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6627                                const struct intel_crtc_state *new_crtc_state)
6628 {
6629         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6630         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6631
6632         /*
6633          * Update pipe size and adjust fitter if needed: the reason for this is
6634          * that in compute_mode_changes we check the native mode (not the pfit
6635          * mode) to see if we can flip rather than do a full mode set. In the
6636          * fastboot case, we'll flip, but if we don't update the pipesrc and
6637          * pfit state, we'll end up with a big fb scanned out into the wrong
6638          * sized surface.
6639          */
6640         intel_set_pipe_src_size(new_crtc_state);
6641
6642         /* on skylake this is done by detaching scalers */
6643         if (DISPLAY_VER(dev_priv) >= 9) {
6644                 if (new_crtc_state->pch_pfit.enabled)
6645                         skl_pfit_enable(new_crtc_state);
6646         } else if (HAS_PCH_SPLIT(dev_priv)) {
6647                 if (new_crtc_state->pch_pfit.enabled)
6648                         ilk_pfit_enable(new_crtc_state);
6649                 else if (old_crtc_state->pch_pfit.enabled)
6650                         ilk_pfit_disable(old_crtc_state);
6651         }
6652
6653         /*
6654          * The register is supposedly single buffered so perhaps
6655          * not 100% correct to do this here. But SKL+ calculate
6656          * this based on the adjust pixel rate so pfit changes do
6657          * affect it and so it must be updated for fastsets.
6658          * HSW/BDW only really need this here for fastboot, after
6659          * that the value should not change without a full modeset.
6660          */
6661         if (DISPLAY_VER(dev_priv) >= 9 ||
6662             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6663                 hsw_set_linetime_wm(new_crtc_state);
6664
6665         if (new_crtc_state->update_m_n)
6666                 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6667                                                &new_crtc_state->dp_m_n);
6668
6669         if (new_crtc_state->update_lrr)
6670                 intel_set_transcoder_timings_lrr(new_crtc_state);
6671 }
6672
6673 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6674                                    struct intel_crtc *crtc)
6675 {
6676         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6677         const struct intel_crtc_state *old_crtc_state =
6678                 intel_atomic_get_old_crtc_state(state, crtc);
6679         const struct intel_crtc_state *new_crtc_state =
6680                 intel_atomic_get_new_crtc_state(state, crtc);
6681         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6682
6683         /*
6684          * During modesets pipe configuration was programmed as the
6685          * CRTC was enabled.
6686          */
6687         if (!modeset) {
6688                 if (intel_crtc_needs_color_update(new_crtc_state))
6689                         intel_color_commit_arm(new_crtc_state);
6690
6691                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6692                         bdw_set_pipe_misc(new_crtc_state);
6693
6694                 if (intel_crtc_needs_fastset(new_crtc_state))
6695                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
6696         }
6697
6698         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
6699
6700         intel_atomic_update_watermarks(state, crtc);
6701 }
6702
6703 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6704                                     struct intel_crtc *crtc)
6705 {
6706         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6707         const struct intel_crtc_state *old_crtc_state =
6708                 intel_atomic_get_old_crtc_state(state, crtc);
6709         const struct intel_crtc_state *new_crtc_state =
6710                 intel_atomic_get_new_crtc_state(state, crtc);
6711
6712         /*
6713          * Disable the scaler(s) after the plane(s) so that we don't
6714          * get a catastrophic underrun even if the two operations
6715          * end up happening in two different frames.
6716          */
6717         if (DISPLAY_VER(dev_priv) >= 9 &&
6718             !intel_crtc_needs_modeset(new_crtc_state))
6719                 skl_detach_scalers(new_crtc_state);
6720
6721         if (vrr_enabling(old_crtc_state, new_crtc_state))
6722                 intel_vrr_enable(new_crtc_state);
6723 }
6724
6725 static void intel_enable_crtc(struct intel_atomic_state *state,
6726                               struct intel_crtc *crtc)
6727 {
6728         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6729         const struct intel_crtc_state *new_crtc_state =
6730                 intel_atomic_get_new_crtc_state(state, crtc);
6731
6732         if (!intel_crtc_needs_modeset(new_crtc_state))
6733                 return;
6734
6735         /* VRR will be enable later, if required */
6736         intel_crtc_update_active_timings(new_crtc_state, false);
6737
6738         dev_priv->display.funcs.display->crtc_enable(state, crtc);
6739
6740         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6741                 return;
6742
6743         /* vblanks work again, re-enable pipe CRC. */
6744         intel_crtc_enable_pipe_crc(crtc);
6745 }
6746
6747 static void intel_update_crtc(struct intel_atomic_state *state,
6748                               struct intel_crtc *crtc)
6749 {
6750         struct drm_i915_private *i915 = to_i915(state->base.dev);
6751         const struct intel_crtc_state *old_crtc_state =
6752                 intel_atomic_get_old_crtc_state(state, crtc);
6753         struct intel_crtc_state *new_crtc_state =
6754                 intel_atomic_get_new_crtc_state(state, crtc);
6755         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6756
6757         if (old_crtc_state->inherited ||
6758             intel_crtc_needs_modeset(new_crtc_state)) {
6759                 if (HAS_DPT(i915))
6760                         intel_dpt_configure(crtc);
6761         }
6762
6763         if (!modeset) {
6764                 if (new_crtc_state->preload_luts &&
6765                     intel_crtc_needs_color_update(new_crtc_state))
6766                         intel_color_load_luts(new_crtc_state);
6767
6768                 intel_pre_plane_update(state, crtc);
6769
6770                 if (intel_crtc_needs_fastset(new_crtc_state))
6771                         intel_encoders_update_pipe(state, crtc);
6772
6773                 if (DISPLAY_VER(i915) >= 11 &&
6774                     intel_crtc_needs_fastset(new_crtc_state))
6775                         icl_set_pipe_chicken(new_crtc_state);
6776
6777                 if (vrr_params_changed(old_crtc_state, new_crtc_state))
6778                         intel_vrr_set_transcoder_timings(new_crtc_state);
6779         }
6780
6781         intel_fbc_update(state, crtc);
6782
6783         drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
6784
6785         if (!modeset &&
6786             intel_crtc_needs_color_update(new_crtc_state))
6787                 intel_color_commit_noarm(new_crtc_state);
6788
6789         intel_crtc_planes_update_noarm(state, crtc);
6790
6791         /* Perform vblank evasion around commit operation */
6792         intel_pipe_update_start(state, crtc);
6793
6794         commit_pipe_pre_planes(state, crtc);
6795
6796         intel_crtc_planes_update_arm(state, crtc);
6797
6798         commit_pipe_post_planes(state, crtc);
6799
6800         intel_pipe_update_end(state, crtc);
6801
6802         /*
6803          * VRR/Seamless M/N update may need to update frame timings.
6804          *
6805          * FIXME Should be synchronized with the start of vblank somehow...
6806          */
6807         if (vrr_enabling(old_crtc_state, new_crtc_state) ||
6808             new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6809                 intel_crtc_update_active_timings(new_crtc_state,
6810                                                  new_crtc_state->vrr.enable);
6811
6812         /*
6813          * We usually enable FIFO underrun interrupts as part of the
6814          * CRTC enable sequence during modesets.  But when we inherit a
6815          * valid pipe configuration from the BIOS we need to take care
6816          * of enabling them on the CRTC's first fastset.
6817          */
6818         if (intel_crtc_needs_fastset(new_crtc_state) && !modeset &&
6819             old_crtc_state->inherited)
6820                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6821 }
6822
6823 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6824                                           struct intel_crtc_state *old_crtc_state,
6825                                           struct intel_crtc_state *new_crtc_state,
6826                                           struct intel_crtc *crtc)
6827 {
6828         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6829
6830         /*
6831          * We need to disable pipe CRC before disabling the pipe,
6832          * or we race against vblank off.
6833          */
6834         intel_crtc_disable_pipe_crc(crtc);
6835
6836         dev_priv->display.funcs.display->crtc_disable(state, crtc);
6837         crtc->active = false;
6838         intel_fbc_disable(crtc);
6839
6840         if (!new_crtc_state->hw.active)
6841                 intel_initial_watermarks(state, crtc);
6842 }
6843
6844 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6845 {
6846         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6847         struct intel_crtc *crtc;
6848         u32 handled = 0;
6849         int i;
6850
6851         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6852                                             new_crtc_state, i) {
6853                 if (!intel_crtc_needs_modeset(new_crtc_state))
6854                         continue;
6855
6856                 if (!old_crtc_state->hw.active)
6857                         continue;
6858
6859                 intel_pre_plane_update(state, crtc);
6860                 intel_crtc_disable_planes(state, crtc);
6861         }
6862
6863         /* Only disable port sync and MST slaves */
6864         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6865                                             new_crtc_state, i) {
6866                 if (!intel_crtc_needs_modeset(new_crtc_state))
6867                         continue;
6868
6869                 if (!old_crtc_state->hw.active)
6870                         continue;
6871
6872                 /* In case of Transcoder port Sync master slave CRTCs can be
6873                  * assigned in any order and we need to make sure that
6874                  * slave CRTCs are disabled first and then master CRTC since
6875                  * Slave vblanks are masked till Master Vblanks.
6876                  */
6877                 if (!is_trans_port_sync_slave(old_crtc_state) &&
6878                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
6879                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
6880                         continue;
6881
6882                 intel_old_crtc_state_disables(state, old_crtc_state,
6883                                               new_crtc_state, crtc);
6884                 handled |= BIT(crtc->pipe);
6885         }
6886
6887         /* Disable everything else left on */
6888         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6889                                             new_crtc_state, i) {
6890                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
6891                     (handled & BIT(crtc->pipe)))
6892                         continue;
6893
6894                 if (!old_crtc_state->hw.active)
6895                         continue;
6896
6897                 intel_old_crtc_state_disables(state, old_crtc_state,
6898                                               new_crtc_state, crtc);
6899         }
6900 }
6901
6902 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6903 {
6904         struct intel_crtc_state *new_crtc_state;
6905         struct intel_crtc *crtc;
6906         int i;
6907
6908         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6909                 if (!new_crtc_state->hw.active)
6910                         continue;
6911
6912                 intel_enable_crtc(state, crtc);
6913                 intel_update_crtc(state, crtc);
6914         }
6915 }
6916
6917 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
6918 {
6919         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6920         struct intel_crtc *crtc;
6921         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6922         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6923         u8 update_pipes = 0, modeset_pipes = 0;
6924         int i;
6925
6926         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6927                 enum pipe pipe = crtc->pipe;
6928
6929                 if (!new_crtc_state->hw.active)
6930                         continue;
6931
6932                 /* ignore allocations for crtc's that have been turned off. */
6933                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6934                         entries[pipe] = old_crtc_state->wm.skl.ddb;
6935                         update_pipes |= BIT(pipe);
6936                 } else {
6937                         modeset_pipes |= BIT(pipe);
6938                 }
6939         }
6940
6941         /*
6942          * Whenever the number of active pipes changes, we need to make sure we
6943          * update the pipes in the right order so that their ddb allocations
6944          * never overlap with each other between CRTC updates. Otherwise we'll
6945          * cause pipe underruns and other bad stuff.
6946          *
6947          * So first lets enable all pipes that do not need a fullmodeset as
6948          * those don't have any external dependency.
6949          */
6950         while (update_pipes) {
6951                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6952                                                     new_crtc_state, i) {
6953                         enum pipe pipe = crtc->pipe;
6954
6955                         if ((update_pipes & BIT(pipe)) == 0)
6956                                 continue;
6957
6958                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6959                                                         entries, I915_MAX_PIPES, pipe))
6960                                 continue;
6961
6962                         entries[pipe] = new_crtc_state->wm.skl.ddb;
6963                         update_pipes &= ~BIT(pipe);
6964
6965                         intel_update_crtc(state, crtc);
6966
6967                         /*
6968                          * If this is an already active pipe, it's DDB changed,
6969                          * and this isn't the last pipe that needs updating
6970                          * then we need to wait for a vblank to pass for the
6971                          * new ddb allocation to take effect.
6972                          */
6973                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
6974                                                  &old_crtc_state->wm.skl.ddb) &&
6975                             (update_pipes | modeset_pipes))
6976                                 intel_crtc_wait_for_next_vblank(crtc);
6977                 }
6978         }
6979
6980         update_pipes = modeset_pipes;
6981
6982         /*
6983          * Enable all pipes that needs a modeset and do not depends on other
6984          * pipes
6985          */
6986         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6987                 enum pipe pipe = crtc->pipe;
6988
6989                 if ((modeset_pipes & BIT(pipe)) == 0)
6990                         continue;
6991
6992                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
6993                     is_trans_port_sync_master(new_crtc_state) ||
6994                     intel_crtc_is_bigjoiner_master(new_crtc_state))
6995                         continue;
6996
6997                 modeset_pipes &= ~BIT(pipe);
6998
6999                 intel_enable_crtc(state, crtc);
7000         }
7001
7002         /*
7003          * Then we enable all remaining pipes that depend on other
7004          * pipes: MST slaves and port sync masters, big joiner master
7005          */
7006         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7007                 enum pipe pipe = crtc->pipe;
7008
7009                 if ((modeset_pipes & BIT(pipe)) == 0)
7010                         continue;
7011
7012                 modeset_pipes &= ~BIT(pipe);
7013
7014                 intel_enable_crtc(state, crtc);
7015         }
7016
7017         /*
7018          * Finally we do the plane updates/etc. for all pipes that got enabled.
7019          */
7020         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7021                 enum pipe pipe = crtc->pipe;
7022
7023                 if ((update_pipes & BIT(pipe)) == 0)
7024                         continue;
7025
7026                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7027                                                                         entries, I915_MAX_PIPES, pipe));
7028
7029                 entries[pipe] = new_crtc_state->wm.skl.ddb;
7030                 update_pipes &= ~BIT(pipe);
7031
7032                 intel_update_crtc(state, crtc);
7033         }
7034
7035         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
7036         drm_WARN_ON(&dev_priv->drm, update_pipes);
7037 }
7038
7039 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
7040 {
7041         struct intel_atomic_state *state, *next;
7042         struct llist_node *freed;
7043
7044         freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
7045         llist_for_each_entry_safe(state, next, freed, freed)
7046                 drm_atomic_state_put(&state->base);
7047 }
7048
7049 void intel_atomic_helper_free_state_worker(struct work_struct *work)
7050 {
7051         struct drm_i915_private *dev_priv =
7052                 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
7053
7054         intel_atomic_helper_free_state(dev_priv);
7055 }
7056
7057 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7058 {
7059         struct wait_queue_entry wait_fence, wait_reset;
7060         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
7061
7062         init_wait_entry(&wait_fence, 0);
7063         init_wait_entry(&wait_reset, 0);
7064         for (;;) {
7065                 prepare_to_wait(&intel_state->commit_ready.wait,
7066                                 &wait_fence, TASK_UNINTERRUPTIBLE);
7067                 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7068                                               I915_RESET_MODESET),
7069                                 &wait_reset, TASK_UNINTERRUPTIBLE);
7070
7071
7072                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
7073                     test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
7074                         break;
7075
7076                 schedule();
7077         }
7078         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
7079         finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
7080                                   I915_RESET_MODESET),
7081                     &wait_reset);
7082 }
7083
7084 static void intel_atomic_cleanup_work(struct work_struct *work)
7085 {
7086         struct intel_atomic_state *state =
7087                 container_of(work, struct intel_atomic_state, base.commit_work);
7088         struct drm_i915_private *i915 = to_i915(state->base.dev);
7089         struct intel_crtc_state *old_crtc_state;
7090         struct intel_crtc *crtc;
7091         int i;
7092
7093         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7094                 intel_color_cleanup_commit(old_crtc_state);
7095
7096         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
7097         drm_atomic_helper_commit_cleanup_done(&state->base);
7098         drm_atomic_state_put(&state->base);
7099
7100         intel_atomic_helper_free_state(i915);
7101 }
7102
7103 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7104 {
7105         struct drm_i915_private *i915 = to_i915(state->base.dev);
7106         struct intel_plane *plane;
7107         struct intel_plane_state *plane_state;
7108         int i;
7109
7110         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7111                 struct drm_framebuffer *fb = plane_state->hw.fb;
7112                 int cc_plane;
7113                 int ret;
7114
7115                 if (!fb)
7116                         continue;
7117
7118                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7119                 if (cc_plane < 0)
7120                         continue;
7121
7122                 /*
7123                  * The layout of the fast clear color value expected by HW
7124                  * (the DRM ABI requiring this value to be located in fb at
7125                  * offset 0 of cc plane, plane #2 previous generations or
7126                  * plane #1 for flat ccs):
7127                  * - 4 x 4 bytes per-channel value
7128                  *   (in surface type specific float/int format provided by the fb user)
7129                  * - 8 bytes native color value used by the display
7130                  *   (converted/written by GPU during a fast clear operation using the
7131                  *    above per-channel values)
7132                  *
7133                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
7134                  * caller made sure that the object is synced wrt. the related color clear value
7135                  * GPU write on it.
7136                  */
7137                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
7138                                                      fb->offsets[cc_plane] + 16,
7139                                                      &plane_state->ccval,
7140                                                      sizeof(plane_state->ccval));
7141                 /* The above could only fail if the FB obj has an unexpected backing store type. */
7142                 drm_WARN_ON(&i915->drm, ret);
7143         }
7144 }
7145
7146 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7147 {
7148         struct drm_device *dev = state->base.dev;
7149         struct drm_i915_private *dev_priv = to_i915(dev);
7150         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7151         struct intel_crtc *crtc;
7152         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7153         intel_wakeref_t wakeref = 0;
7154         int i;
7155
7156         intel_atomic_commit_fence_wait(state);
7157
7158         drm_atomic_helper_wait_for_dependencies(&state->base);
7159         drm_dp_mst_atomic_wait_for_dependencies(&state->base);
7160
7161         /*
7162          * During full modesets we write a lot of registers, wait
7163          * for PLLs, etc. Doing that while DC states are enabled
7164          * is not a good idea.
7165          *
7166          * During fastsets and other updates we also need to
7167          * disable DC states due to the following scenario:
7168          * 1. DC5 exit and PSR exit happen
7169          * 2. Some or all _noarm() registers are written
7170          * 3. Due to some long delay PSR is re-entered
7171          * 4. DC5 entry -> DMC saves the already written new
7172          *    _noarm() registers and the old not yet written
7173          *    _arm() registers
7174          * 5. DC5 exit -> DMC restores a mixture of old and
7175          *    new register values and arms the update
7176          * 6. PSR exit -> hardware latches a mixture of old and
7177          *    new register values -> corrupted frame, or worse
7178          * 7. New _arm() registers are finally written
7179          * 8. Hardware finally latches a complete set of new
7180          *    register values, and subsequent frames will be OK again
7181          *
7182          * Also note that due to the pipe CSC hardware issues on
7183          * SKL/GLK DC states must remain off until the pipe CSC
7184          * state readout has happened. Otherwise we risk corrupting
7185          * the CSC latched register values with the readout (see
7186          * skl_read_csc() and skl_color_commit_noarm()).
7187          */
7188         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
7189
7190         intel_atomic_prepare_plane_clear_colors(state);
7191
7192         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7193                                             new_crtc_state, i) {
7194                 if (intel_crtc_needs_modeset(new_crtc_state) ||
7195                     intel_crtc_needs_fastset(new_crtc_state))
7196                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
7197         }
7198
7199         intel_commit_modeset_disables(state);
7200
7201         /* FIXME: Eventually get rid of our crtc->config pointer */
7202         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7203                 crtc->config = new_crtc_state;
7204
7205         /*
7206          * In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7207          * plls, cdclk frequency, QGV point selection parameter etc. Voltage
7208          * index, cdclk/ddiclk frequencies are supposed to be configured before
7209          * the cdclk config is set.
7210          */
7211         intel_pmdemand_pre_plane_update(state);
7212
7213         if (state->modeset) {
7214                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7215
7216                 intel_set_cdclk_pre_plane_update(state);
7217
7218                 intel_modeset_verify_disabled(state);
7219         }
7220
7221         intel_sagv_pre_plane_update(state);
7222
7223         /* Complete the events for pipes that have now been disabled */
7224         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7225                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7226
7227                 /* Complete events for now disable pipes here. */
7228                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7229                         spin_lock_irq(&dev->event_lock);
7230                         drm_crtc_send_vblank_event(&crtc->base,
7231                                                    new_crtc_state->uapi.event);
7232                         spin_unlock_irq(&dev->event_lock);
7233
7234                         new_crtc_state->uapi.event = NULL;
7235                 }
7236         }
7237
7238         intel_encoders_update_prepare(state);
7239
7240         intel_dbuf_pre_plane_update(state);
7241         intel_mbus_dbox_update(state);
7242
7243         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7244                 if (new_crtc_state->do_async_flip)
7245                         intel_crtc_enable_flip_done(state, crtc);
7246         }
7247
7248         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7249         dev_priv->display.funcs.display->commit_modeset_enables(state);
7250
7251         if (state->modeset)
7252                 intel_set_cdclk_post_plane_update(state);
7253
7254         intel_wait_for_vblank_workers(state);
7255
7256         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7257          * already, but still need the state for the delayed optimization. To
7258          * fix this:
7259          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7260          * - schedule that vblank worker _before_ calling hw_done
7261          * - at the start of commit_tail, cancel it _synchrously
7262          * - switch over to the vblank wait helper in the core after that since
7263          *   we don't need out special handling any more.
7264          */
7265         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7266
7267         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7268                 if (new_crtc_state->do_async_flip)
7269                         intel_crtc_disable_flip_done(state, crtc);
7270
7271                 intel_color_wait_commit(new_crtc_state);
7272         }
7273
7274         /*
7275          * Now that the vblank has passed, we can go ahead and program the
7276          * optimal watermarks on platforms that need two-step watermark
7277          * programming.
7278          *
7279          * TODO: Move this (and other cleanup) to an async worker eventually.
7280          */
7281         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7282                                             new_crtc_state, i) {
7283                 /*
7284                  * Gen2 reports pipe underruns whenever all planes are disabled.
7285                  * So re-enable underrun reporting after some planes get enabled.
7286                  *
7287                  * We do this before .optimize_watermarks() so that we have a
7288                  * chance of catching underruns with the intermediate watermarks
7289                  * vs. the new plane configuration.
7290                  */
7291                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7292                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7293
7294                 intel_optimize_watermarks(state, crtc);
7295         }
7296
7297         intel_dbuf_post_plane_update(state);
7298
7299         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7300                 intel_post_plane_update(state, crtc);
7301
7302                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7303
7304                 intel_modeset_verify_crtc(state, crtc);
7305
7306                 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7307                 hsw_ips_post_update(state, crtc);
7308
7309                 /*
7310                  * Activate DRRS after state readout to avoid
7311                  * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7312                  */
7313                 intel_drrs_activate(new_crtc_state);
7314
7315                 /*
7316                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7317                  * cleanup. So copy and reset the dsb structure to sync with
7318                  * commit_done and later do dsb cleanup in cleanup_work.
7319                  *
7320                  * FIXME get rid of this funny new->old swapping
7321                  */
7322                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7323         }
7324
7325         /* Underruns don't always raise interrupts, so check manually */
7326         intel_check_cpu_fifo_underruns(dev_priv);
7327         intel_check_pch_fifo_underruns(dev_priv);
7328
7329         if (state->modeset)
7330                 intel_verify_planes(state);
7331
7332         intel_sagv_post_plane_update(state);
7333         intel_pmdemand_post_plane_update(state);
7334
7335         drm_atomic_helper_commit_hw_done(&state->base);
7336
7337         if (state->modeset) {
7338                 /* As one of the primary mmio accessors, KMS has a high
7339                  * likelihood of triggering bugs in unclaimed access. After we
7340                  * finish modesetting, see if an error has been flagged, and if
7341                  * so enable debugging for the next modeset - and hope we catch
7342                  * the culprit.
7343                  */
7344                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7345         }
7346         /*
7347          * Delay re-enabling DC states by 17 ms to avoid the off->on->off
7348          * toggling overhead at and above 60 FPS.
7349          */
7350         intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17);
7351         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7352
7353         /*
7354          * Defer the cleanup of the old state to a separate worker to not
7355          * impede the current task (userspace for blocking modesets) that
7356          * are executed inline. For out-of-line asynchronous modesets/flips,
7357          * deferring to a new worker seems overkill, but we would place a
7358          * schedule point (cond_resched()) here anyway to keep latencies
7359          * down.
7360          */
7361         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7362         queue_work(system_highpri_wq, &state->base.commit_work);
7363 }
7364
7365 static void intel_atomic_commit_work(struct work_struct *work)
7366 {
7367         struct intel_atomic_state *state =
7368                 container_of(work, struct intel_atomic_state, base.commit_work);
7369
7370         intel_atomic_commit_tail(state);
7371 }
7372
7373 static int
7374 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7375                           enum i915_sw_fence_notify notify)
7376 {
7377         struct intel_atomic_state *state =
7378                 container_of(fence, struct intel_atomic_state, commit_ready);
7379
7380         switch (notify) {
7381         case FENCE_COMPLETE:
7382                 /* we do blocking waits in the worker, nothing to do here */
7383                 break;
7384         case FENCE_FREE:
7385                 {
7386                         struct drm_i915_private *i915 = to_i915(state->base.dev);
7387                         struct intel_atomic_helper *helper =
7388                                 &i915->display.atomic_helper;
7389
7390                         if (llist_add(&state->freed, &helper->free_list))
7391                                 queue_work(i915->unordered_wq, &helper->free_work);
7392                         break;
7393                 }
7394         }
7395
7396         return NOTIFY_DONE;
7397 }
7398
7399 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7400 {
7401         struct intel_plane_state *old_plane_state, *new_plane_state;
7402         struct intel_plane *plane;
7403         int i;
7404
7405         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7406                                              new_plane_state, i)
7407                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7408                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7409                                         plane->frontbuffer_bit);
7410 }
7411
7412 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7413                         bool nonblock)
7414 {
7415         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7416         struct drm_i915_private *dev_priv = to_i915(dev);
7417         int ret = 0;
7418
7419         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7420
7421         drm_atomic_state_get(&state->base);
7422         i915_sw_fence_init(&state->commit_ready,
7423                            intel_atomic_commit_ready);
7424
7425         /*
7426          * The intel_legacy_cursor_update() fast path takes care
7427          * of avoiding the vblank waits for simple cursor
7428          * movement and flips. For cursor on/off and size changes,
7429          * we want to perform the vblank waits so that watermark
7430          * updates happen during the correct frames. Gen9+ have
7431          * double buffered watermarks and so shouldn't need this.
7432          *
7433          * Unset state->legacy_cursor_update before the call to
7434          * drm_atomic_helper_setup_commit() because otherwise
7435          * drm_atomic_helper_wait_for_flip_done() is a noop and
7436          * we get FIFO underruns because we didn't wait
7437          * for vblank.
7438          *
7439          * FIXME doing watermarks and fb cleanup from a vblank worker
7440          * (assuming we had any) would solve these problems.
7441          */
7442         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7443                 struct intel_crtc_state *new_crtc_state;
7444                 struct intel_crtc *crtc;
7445                 int i;
7446
7447                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7448                         if (new_crtc_state->wm.need_postvbl_update ||
7449                             new_crtc_state->update_wm_post)
7450                                 state->base.legacy_cursor_update = false;
7451         }
7452
7453         ret = intel_atomic_prepare_commit(state);
7454         if (ret) {
7455                 drm_dbg_atomic(&dev_priv->drm,
7456                                "Preparing state failed with %i\n", ret);
7457                 i915_sw_fence_commit(&state->commit_ready);
7458                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7459                 return ret;
7460         }
7461
7462         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7463         if (!ret)
7464                 ret = drm_atomic_helper_swap_state(&state->base, true);
7465         if (!ret)
7466                 intel_atomic_swap_global_state(state);
7467
7468         if (ret) {
7469                 struct intel_crtc_state *new_crtc_state;
7470                 struct intel_crtc *crtc;
7471                 int i;
7472
7473                 i915_sw_fence_commit(&state->commit_ready);
7474
7475                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7476                         intel_color_cleanup_commit(new_crtc_state);
7477
7478                 drm_atomic_helper_cleanup_planes(dev, &state->base);
7479                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7480                 return ret;
7481         }
7482         intel_shared_dpll_swap_state(state);
7483         intel_atomic_track_fbs(state);
7484
7485         drm_atomic_state_get(&state->base);
7486         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7487
7488         i915_sw_fence_commit(&state->commit_ready);
7489         if (nonblock && state->modeset) {
7490                 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7491         } else if (nonblock) {
7492                 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7493         } else {
7494                 if (state->modeset)
7495                         flush_workqueue(dev_priv->display.wq.modeset);
7496                 intel_atomic_commit_tail(state);
7497         }
7498
7499         return 0;
7500 }
7501
7502 /**
7503  * intel_plane_destroy - destroy a plane
7504  * @plane: plane to destroy
7505  *
7506  * Common destruction function for all types of planes (primary, cursor,
7507  * sprite).
7508  */
7509 void intel_plane_destroy(struct drm_plane *plane)
7510 {
7511         drm_plane_cleanup(plane);
7512         kfree(to_intel_plane(plane));
7513 }
7514
7515 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7516                                       struct drm_file *file)
7517 {
7518         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7519         struct drm_crtc *drmmode_crtc;
7520         struct intel_crtc *crtc;
7521
7522         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7523         if (!drmmode_crtc)
7524                 return -ENOENT;
7525
7526         crtc = to_intel_crtc(drmmode_crtc);
7527         pipe_from_crtc_id->pipe = crtc->pipe;
7528
7529         return 0;
7530 }
7531
7532 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7533 {
7534         struct drm_device *dev = encoder->base.dev;
7535         struct intel_encoder *source_encoder;
7536         u32 possible_clones = 0;
7537
7538         for_each_intel_encoder(dev, source_encoder) {
7539                 if (encoders_cloneable(encoder, source_encoder))
7540                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7541         }
7542
7543         return possible_clones;
7544 }
7545
7546 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7547 {
7548         struct drm_device *dev = encoder->base.dev;
7549         struct intel_crtc *crtc;
7550         u32 possible_crtcs = 0;
7551
7552         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7553                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7554
7555         return possible_crtcs;
7556 }
7557
7558 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7559 {
7560         if (!IS_MOBILE(dev_priv))
7561                 return false;
7562
7563         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7564                 return false;
7565
7566         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7567                 return false;
7568
7569         return true;
7570 }
7571
7572 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7573 {
7574         if (DISPLAY_VER(dev_priv) >= 9)
7575                 return false;
7576
7577         if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
7578                 return false;
7579
7580         if (HAS_PCH_LPT_H(dev_priv) &&
7581             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7582                 return false;
7583
7584         /* DDI E can't be used if DDI A requires 4 lanes */
7585         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7586                 return false;
7587
7588         if (!dev_priv->display.vbt.int_crt_support)
7589                 return false;
7590
7591         return true;
7592 }
7593
7594 bool assert_port_valid(struct drm_i915_private *i915, enum port port)
7595 {
7596         return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),
7597                          "Platform does not support port %c\n", port_name(port));
7598 }
7599
7600 void intel_setup_outputs(struct drm_i915_private *dev_priv)
7601 {
7602         struct intel_encoder *encoder;
7603         bool dpd_is_edp = false;
7604
7605         intel_pps_unlock_regs_wa(dev_priv);
7606
7607         if (!HAS_DISPLAY(dev_priv))
7608                 return;
7609
7610         if (HAS_DDI(dev_priv)) {
7611                 if (intel_ddi_crt_present(dev_priv))
7612                         intel_crt_init(dev_priv);
7613
7614                 intel_bios_for_each_encoder(dev_priv, intel_ddi_init);
7615
7616                 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
7617                         vlv_dsi_init(dev_priv);
7618         } else if (HAS_PCH_SPLIT(dev_priv)) {
7619                 int found;
7620
7621                 /*
7622                  * intel_edp_init_connector() depends on this completing first,
7623                  * to prevent the registration of both eDP and LVDS and the
7624                  * incorrect sharing of the PPS.
7625                  */
7626                 intel_lvds_init(dev_priv);
7627                 intel_crt_init(dev_priv);
7628
7629                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7630
7631                 if (ilk_has_edp_a(dev_priv))
7632                         g4x_dp_init(dev_priv, DP_A, PORT_A);
7633
7634                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7635                         /* PCH SDVOB multiplex with HDMIB */
7636                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7637                         if (!found)
7638                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7639                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7640                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7641                 }
7642
7643                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7644                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7645
7646                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7647                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7648
7649                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7650                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7651
7652                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7653                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7654         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7655                 bool has_edp, has_port;
7656
7657                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7658                         intel_crt_init(dev_priv);
7659
7660                 /*
7661                  * The DP_DETECTED bit is the latched state of the DDC
7662                  * SDA pin at boot. However since eDP doesn't require DDC
7663                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
7664                  * eDP ports may have been muxed to an alternate function.
7665                  * Thus we can't rely on the DP_DETECTED bit alone to detect
7666                  * eDP ports. Consult the VBT as well as DP_DETECTED to
7667                  * detect eDP ports.
7668                  *
7669                  * Sadly the straps seem to be missing sometimes even for HDMI
7670                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7671                  * and VBT for the presence of the port. Additionally we can't
7672                  * trust the port type the VBT declares as we've seen at least
7673                  * HDMI ports that the VBT claim are DP or eDP.
7674                  */
7675                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7676                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7677                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7678                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7679                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7680                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7681
7682                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7683                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7684                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7685                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7686                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7687                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7688
7689                 if (IS_CHERRYVIEW(dev_priv)) {
7690                         /*
7691                          * eDP not supported on port D,
7692                          * so no need to worry about it
7693                          */
7694                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7695                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7696                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7697                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7698                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7699                 }
7700
7701                 vlv_dsi_init(dev_priv);
7702         } else if (IS_PINEVIEW(dev_priv)) {
7703                 intel_lvds_init(dev_priv);
7704                 intel_crt_init(dev_priv);
7705         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7706                 bool found = false;
7707
7708                 if (IS_MOBILE(dev_priv))
7709                         intel_lvds_init(dev_priv);
7710
7711                 intel_crt_init(dev_priv);
7712
7713                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7714                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7715                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7716                         if (!found && IS_G4X(dev_priv)) {
7717                                 drm_dbg_kms(&dev_priv->drm,
7718                                             "probing HDMI on SDVOB\n");
7719                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7720                         }
7721
7722                         if (!found && IS_G4X(dev_priv))
7723                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
7724                 }
7725
7726                 /* Before G4X SDVOC doesn't have its own detect register */
7727
7728                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7729                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7730                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7731                 }
7732
7733                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7734
7735                         if (IS_G4X(dev_priv)) {
7736                                 drm_dbg_kms(&dev_priv->drm,
7737                                             "probing HDMI on SDVOC\n");
7738                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7739                         }
7740                         if (IS_G4X(dev_priv))
7741                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
7742                 }
7743
7744                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7745                         g4x_dp_init(dev_priv, DP_D, PORT_D);
7746
7747                 if (SUPPORTS_TV(dev_priv))
7748                         intel_tv_init(dev_priv);
7749         } else if (DISPLAY_VER(dev_priv) == 2) {
7750                 if (IS_I85X(dev_priv))
7751                         intel_lvds_init(dev_priv);
7752
7753                 intel_crt_init(dev_priv);
7754                 intel_dvo_init(dev_priv);
7755         }
7756
7757         for_each_intel_encoder(&dev_priv->drm, encoder) {
7758                 encoder->base.possible_crtcs =
7759                         intel_encoder_possible_crtcs(encoder);
7760                 encoder->base.possible_clones =
7761                         intel_encoder_possible_clones(encoder);
7762         }
7763
7764         intel_init_pch_refclk(dev_priv);
7765
7766         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7767 }
7768
7769 static int max_dotclock(struct drm_i915_private *i915)
7770 {
7771         int max_dotclock = i915->max_dotclk_freq;
7772
7773         /* icl+ might use bigjoiner */
7774         if (DISPLAY_VER(i915) >= 11)
7775                 max_dotclock *= 2;
7776
7777         return max_dotclock;
7778 }
7779
7780 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
7781                                       const struct drm_display_mode *mode)
7782 {
7783         struct drm_i915_private *dev_priv = to_i915(dev);
7784         int hdisplay_max, htotal_max;
7785         int vdisplay_max, vtotal_max;
7786
7787         /*
7788          * Can't reject DBLSCAN here because Xorg ddxen can add piles
7789          * of DBLSCAN modes to the output's mode list when they detect
7790          * the scaling mode property on the connector. And they don't
7791          * ask the kernel to validate those modes in any way until
7792          * modeset time at which point the client gets a protocol error.
7793          * So in order to not upset those clients we silently ignore the
7794          * DBLSCAN flag on such connectors. For other connectors we will
7795          * reject modes with the DBLSCAN flag in encoder->compute_config().
7796          * And we always reject DBLSCAN modes in connector->mode_valid()
7797          * as we never want such modes on the connector's mode list.
7798          */
7799
7800         if (mode->vscan > 1)
7801                 return MODE_NO_VSCAN;
7802
7803         if (mode->flags & DRM_MODE_FLAG_HSKEW)
7804                 return MODE_H_ILLEGAL;
7805
7806         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7807                            DRM_MODE_FLAG_NCSYNC |
7808                            DRM_MODE_FLAG_PCSYNC))
7809                 return MODE_HSYNC;
7810
7811         if (mode->flags & (DRM_MODE_FLAG_BCAST |
7812                            DRM_MODE_FLAG_PIXMUX |
7813                            DRM_MODE_FLAG_CLKDIV2))
7814                 return MODE_BAD;
7815
7816         /*
7817          * Reject clearly excessive dotclocks early to
7818          * avoid having to worry about huge integers later.
7819          */
7820         if (mode->clock > max_dotclock(dev_priv))
7821                 return MODE_CLOCK_HIGH;
7822
7823         /* Transcoder timing limits */
7824         if (DISPLAY_VER(dev_priv) >= 11) {
7825                 hdisplay_max = 16384;
7826                 vdisplay_max = 8192;
7827                 htotal_max = 16384;
7828                 vtotal_max = 8192;
7829         } else if (DISPLAY_VER(dev_priv) >= 9 ||
7830                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7831                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
7832                 vdisplay_max = 4096;
7833                 htotal_max = 8192;
7834                 vtotal_max = 8192;
7835         } else if (DISPLAY_VER(dev_priv) >= 3) {
7836                 hdisplay_max = 4096;
7837                 vdisplay_max = 4096;
7838                 htotal_max = 8192;
7839                 vtotal_max = 8192;
7840         } else {
7841                 hdisplay_max = 2048;
7842                 vdisplay_max = 2048;
7843                 htotal_max = 4096;
7844                 vtotal_max = 4096;
7845         }
7846
7847         if (mode->hdisplay > hdisplay_max ||
7848             mode->hsync_start > htotal_max ||
7849             mode->hsync_end > htotal_max ||
7850             mode->htotal > htotal_max)
7851                 return MODE_H_ILLEGAL;
7852
7853         if (mode->vdisplay > vdisplay_max ||
7854             mode->vsync_start > vtotal_max ||
7855             mode->vsync_end > vtotal_max ||
7856             mode->vtotal > vtotal_max)
7857                 return MODE_V_ILLEGAL;
7858
7859         if (DISPLAY_VER(dev_priv) >= 5) {
7860                 if (mode->hdisplay < 64 ||
7861                     mode->htotal - mode->hdisplay < 32)
7862                         return MODE_H_ILLEGAL;
7863
7864                 if (mode->vtotal - mode->vdisplay < 5)
7865                         return MODE_V_ILLEGAL;
7866         } else {
7867                 if (mode->htotal - mode->hdisplay < 32)
7868                         return MODE_H_ILLEGAL;
7869
7870                 if (mode->vtotal - mode->vdisplay < 3)
7871                         return MODE_V_ILLEGAL;
7872         }
7873
7874         /*
7875          * Cantiga+ cannot handle modes with a hsync front porch of 0.
7876          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7877          */
7878         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7879             mode->hsync_start == mode->hdisplay)
7880                 return MODE_H_ILLEGAL;
7881
7882         return MODE_OK;
7883 }
7884
7885 enum drm_mode_status
7886 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
7887                                 const struct drm_display_mode *mode,
7888                                 bool bigjoiner)
7889 {
7890         int plane_width_max, plane_height_max;
7891
7892         /*
7893          * intel_mode_valid() should be
7894          * sufficient on older platforms.
7895          */
7896         if (DISPLAY_VER(dev_priv) < 9)
7897                 return MODE_OK;
7898
7899         /*
7900          * Most people will probably want a fullscreen
7901          * plane so let's not advertize modes that are
7902          * too big for that.
7903          */
7904         if (DISPLAY_VER(dev_priv) >= 11) {
7905                 plane_width_max = 5120 << bigjoiner;
7906                 plane_height_max = 4320;
7907         } else {
7908                 plane_width_max = 5120;
7909                 plane_height_max = 4096;
7910         }
7911
7912         if (mode->hdisplay > plane_width_max)
7913                 return MODE_H_ILLEGAL;
7914
7915         if (mode->vdisplay > plane_height_max)
7916                 return MODE_V_ILLEGAL;
7917
7918         return MODE_OK;
7919 }
7920
7921 static const struct intel_display_funcs skl_display_funcs = {
7922         .get_pipe_config = hsw_get_pipe_config,
7923         .crtc_enable = hsw_crtc_enable,
7924         .crtc_disable = hsw_crtc_disable,
7925         .commit_modeset_enables = skl_commit_modeset_enables,
7926         .get_initial_plane_config = skl_get_initial_plane_config,
7927 };
7928
7929 static const struct intel_display_funcs ddi_display_funcs = {
7930         .get_pipe_config = hsw_get_pipe_config,
7931         .crtc_enable = hsw_crtc_enable,
7932         .crtc_disable = hsw_crtc_disable,
7933         .commit_modeset_enables = intel_commit_modeset_enables,
7934         .get_initial_plane_config = i9xx_get_initial_plane_config,
7935 };
7936
7937 static const struct intel_display_funcs pch_split_display_funcs = {
7938         .get_pipe_config = ilk_get_pipe_config,
7939         .crtc_enable = ilk_crtc_enable,
7940         .crtc_disable = ilk_crtc_disable,
7941         .commit_modeset_enables = intel_commit_modeset_enables,
7942         .get_initial_plane_config = i9xx_get_initial_plane_config,
7943 };
7944
7945 static const struct intel_display_funcs vlv_display_funcs = {
7946         .get_pipe_config = i9xx_get_pipe_config,
7947         .crtc_enable = valleyview_crtc_enable,
7948         .crtc_disable = i9xx_crtc_disable,
7949         .commit_modeset_enables = intel_commit_modeset_enables,
7950         .get_initial_plane_config = i9xx_get_initial_plane_config,
7951 };
7952
7953 static const struct intel_display_funcs i9xx_display_funcs = {
7954         .get_pipe_config = i9xx_get_pipe_config,
7955         .crtc_enable = i9xx_crtc_enable,
7956         .crtc_disable = i9xx_crtc_disable,
7957         .commit_modeset_enables = intel_commit_modeset_enables,
7958         .get_initial_plane_config = i9xx_get_initial_plane_config,
7959 };
7960
7961 /**
7962  * intel_init_display_hooks - initialize the display modesetting hooks
7963  * @dev_priv: device private
7964  */
7965 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
7966 {
7967         if (DISPLAY_VER(dev_priv) >= 9) {
7968                 dev_priv->display.funcs.display = &skl_display_funcs;
7969         } else if (HAS_DDI(dev_priv)) {
7970                 dev_priv->display.funcs.display = &ddi_display_funcs;
7971         } else if (HAS_PCH_SPLIT(dev_priv)) {
7972                 dev_priv->display.funcs.display = &pch_split_display_funcs;
7973         } else if (IS_CHERRYVIEW(dev_priv) ||
7974                    IS_VALLEYVIEW(dev_priv)) {
7975                 dev_priv->display.funcs.display = &vlv_display_funcs;
7976         } else {
7977                 dev_priv->display.funcs.display = &i9xx_display_funcs;
7978         }
7979 }
7980
7981 int intel_initial_commit(struct drm_device *dev)
7982 {
7983         struct drm_atomic_state *state = NULL;
7984         struct drm_modeset_acquire_ctx ctx;
7985         struct intel_crtc *crtc;
7986         int ret = 0;
7987
7988         state = drm_atomic_state_alloc(dev);
7989         if (!state)
7990                 return -ENOMEM;
7991
7992         drm_modeset_acquire_init(&ctx, 0);
7993
7994         state->acquire_ctx = &ctx;
7995         to_intel_atomic_state(state)->internal = true;
7996
7997 retry:
7998         for_each_intel_crtc(dev, crtc) {
7999                 struct intel_crtc_state *crtc_state =
8000                         intel_atomic_get_crtc_state(state, crtc);
8001
8002                 if (IS_ERR(crtc_state)) {
8003                         ret = PTR_ERR(crtc_state);
8004                         goto out;
8005                 }
8006
8007                 if (crtc_state->hw.active) {
8008                         struct intel_encoder *encoder;
8009
8010                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
8011                         if (ret)
8012                                 goto out;
8013
8014                         /*
8015                          * FIXME hack to force a LUT update to avoid the
8016                          * plane update forcing the pipe gamma on without
8017                          * having a proper LUT loaded. Remove once we
8018                          * have readout for pipe gamma enable.
8019                          */
8020                         crtc_state->uapi.color_mgmt_changed = true;
8021
8022                         for_each_intel_encoder_mask(dev, encoder,
8023                                                     crtc_state->uapi.encoder_mask) {
8024                                 if (encoder->initial_fastset_check &&
8025                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
8026                                         ret = drm_atomic_add_affected_connectors(state,
8027                                                                                  &crtc->base);
8028                                         if (ret)
8029                                                 goto out;
8030                                 }
8031                         }
8032                 }
8033         }
8034
8035         ret = drm_atomic_commit(state);
8036
8037 out:
8038         if (ret == -EDEADLK) {
8039                 drm_atomic_state_clear(state);
8040                 drm_modeset_backoff(&ctx);
8041                 goto retry;
8042         }
8043
8044         drm_atomic_state_put(state);
8045
8046         drm_modeset_drop_locks(&ctx);
8047         drm_modeset_acquire_fini(&ctx);
8048
8049         return ret;
8050 }
8051
8052 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8053 {
8054         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8055         enum transcoder cpu_transcoder = (enum transcoder)pipe;
8056         /* 640x480@60Hz, ~25175 kHz */
8057         struct dpll clock = {
8058                 .m1 = 18,
8059                 .m2 = 7,
8060                 .p1 = 13,
8061                 .p2 = 4,
8062                 .n = 2,
8063         };
8064         u32 dpll, fp;
8065         int i;
8066
8067         drm_WARN_ON(&dev_priv->drm,
8068                     i9xx_calc_dpll_params(48000, &clock) != 25154);
8069
8070         drm_dbg_kms(&dev_priv->drm,
8071                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8072                     pipe_name(pipe), clock.vco, clock.dot);
8073
8074         fp = i9xx_dpll_compute_fp(&clock);
8075         dpll = DPLL_DVO_2X_MODE |
8076                 DPLL_VGA_MODE_DIS |
8077                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8078                 PLL_P2_DIVIDE_BY_4 |
8079                 PLL_REF_INPUT_DREFCLK |
8080                 DPLL_VCO_ENABLE;
8081
8082         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
8083                        HACTIVE(640 - 1) | HTOTAL(800 - 1));
8084         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
8085                        HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8086         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
8087                        HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8088         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
8089                        VACTIVE(480 - 1) | VTOTAL(525 - 1));
8090         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
8091                        VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8092         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
8093                        VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8094         intel_de_write(dev_priv, PIPESRC(pipe),
8095                        PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8096
8097         intel_de_write(dev_priv, FP0(pipe), fp);
8098         intel_de_write(dev_priv, FP1(pipe), fp);
8099
8100         /*
8101          * Apparently we need to have VGA mode enabled prior to changing
8102          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
8103          * dividers, even though the register value does change.
8104          */
8105         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
8106         intel_de_write(dev_priv, DPLL(pipe), dpll);
8107
8108         /* Wait for the clocks to stabilize. */
8109         intel_de_posting_read(dev_priv, DPLL(pipe));
8110         udelay(150);
8111
8112         /* The pixel multiplier can only be updated once the
8113          * DPLL is enabled and the clocks are stable.
8114          *
8115          * So write it again.
8116          */
8117         intel_de_write(dev_priv, DPLL(pipe), dpll);
8118
8119         /* We do this three times for luck */
8120         for (i = 0; i < 3 ; i++) {
8121                 intel_de_write(dev_priv, DPLL(pipe), dpll);
8122                 intel_de_posting_read(dev_priv, DPLL(pipe));
8123                 udelay(150); /* wait for warmup */
8124         }
8125
8126         intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
8127         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8128
8129         intel_wait_for_pipe_scanline_moving(crtc);
8130 }
8131
8132 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
8133 {
8134         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
8135
8136         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
8137                     pipe_name(pipe));
8138
8139         drm_WARN_ON(&dev_priv->drm,
8140                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
8141         drm_WARN_ON(&dev_priv->drm,
8142                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
8143         drm_WARN_ON(&dev_priv->drm,
8144                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
8145         drm_WARN_ON(&dev_priv->drm,
8146                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8147         drm_WARN_ON(&dev_priv->drm,
8148                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8149
8150         intel_de_write(dev_priv, TRANSCONF(pipe), 0);
8151         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8152
8153         intel_wait_for_pipe_scanline_stopped(crtc);
8154
8155         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8156         intel_de_posting_read(dev_priv, DPLL(pipe));
8157 }
8158
8159 void intel_hpd_poll_fini(struct drm_i915_private *i915)
8160 {
8161         struct intel_connector *connector;
8162         struct drm_connector_list_iter conn_iter;
8163
8164         /* Kill all the work that may have been queued by hpd. */
8165         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8166         for_each_intel_connector_iter(connector, &conn_iter) {
8167                 if (connector->modeset_retry_work.func)
8168                         cancel_work_sync(&connector->modeset_retry_work);
8169                 if (connector->hdcp.shim) {
8170                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8171                         cancel_work_sync(&connector->hdcp.prop_work);
8172                 }
8173         }
8174         drm_connector_list_iter_end(&conn_iter);
8175 }
8176
8177 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8178 {
8179         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8180 }