drivers/gpu/drm/i915/display/intel_atomic_plane.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic plane helpers
  26  *
  27  * The functions here are used by the atomic plane helper functions to
  28  * implement legacy plane updates (i.e., drm_plane->update_plane() and
  29  * drm_plane->disable_plane()).  This allows plane updates to use the
  30  * atomic state infrastructure and perform plane updates as separate
  31  * prepare/check/commit/cleanup steps.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_blend.h>
  36 #include <drm/drm_fourcc.h>
  37
  38 #include "i915_config.h"
  39 #include "i915_reg.h"
  40 #include "intel_atomic_plane.h"
  41 #include "intel_cdclk.h"
  42 #include "intel_display_rps.h"
  43 #include "intel_display_trace.h"
  44 #include "intel_display_types.h"
  45 #include "intel_fb.h"
  46 #include "intel_fb_pin.h"
  47 #include "skl_scaler.h"
  48 #include "skl_watermark.h"
  49
  50 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
  51                                     struct intel_plane *plane)
  52 {
  53         memset(plane_state, 0, sizeof(*plane_state));
  54
  55         __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
  56
  57         plane_state->scaler_id = -1;
  58 }
  59
  60 struct intel_plane *intel_plane_alloc(void)
  61 {
  62         struct intel_plane_state *plane_state;
  63         struct intel_plane *plane;
  64
  65         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
  66         if (!plane)
  67                 return ERR_PTR(-ENOMEM);
  68
  69         plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
  70         if (!plane_state) {
  71                 kfree(plane);
  72                 return ERR_PTR(-ENOMEM);
  73         }
  74
  75         intel_plane_state_reset(plane_state, plane);
  76
  77         plane->base.state = &plane_state->uapi;
  78
  79         return plane;
  80 }
  81
  82 void intel_plane_free(struct intel_plane *plane)
  83 {
  84         intel_plane_destroy_state(&plane->base, plane->base.state);
  85         kfree(plane);
  86 }
  87
  88 /**
  89  * intel_plane_duplicate_state - duplicate plane state
  90  * @plane: drm plane
  91  *
  92  * Allocates and returns a copy of the plane state (both common and
  93  * Intel-specific) for the specified plane.
  94  *
  95  * Returns: The newly allocated plane state, or NULL on failure.
  96  */
  97 struct drm_plane_state *
  98 intel_plane_duplicate_state(struct drm_plane *plane)
  99 {
 100         struct intel_plane_state *intel_state;
 101
 102         intel_state = to_intel_plane_state(plane->state);
 103         intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
 104
 105         if (!intel_state)
 106                 return NULL;
 107
 108         __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
 109
 110         intel_state->ggtt_vma = NULL;
 111         intel_state->dpt_vma = NULL;
 112         intel_state->flags = 0;
 113
 114         /* add reference to fb */
 115         if (intel_state->hw.fb)
 116                 drm_framebuffer_get(intel_state->hw.fb);
 117
 118         return &intel_state->uapi;
 119 }
 120
 121 /**
 122  * intel_plane_destroy_state - destroy plane state
 123  * @plane: drm plane
 124  * @state: state object to destroy
 125  *
 126  * Destroys the plane state (both common and Intel-specific) for the
 127  * specified plane.
 128  */
 129 void
 130 intel_plane_destroy_state(struct drm_plane *plane,
 131                           struct drm_plane_state *state)
 132 {
 133         struct intel_plane_state *plane_state = to_intel_plane_state(state);
 134
 135         drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
 136         drm_WARN_ON(plane->dev, plane_state->dpt_vma);
 137
 138         __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
 139         if (plane_state->hw.fb)
 140                 drm_framebuffer_put(plane_state->hw.fb);
 141         kfree(plane_state);
 142 }
 143
 144 unsigned int intel_adjusted_rate(const struct drm_rect *src,
 145                                  const struct drm_rect *dst,
 146                                  unsigned int rate)
 147 {
 148         unsigned int src_w, src_h, dst_w, dst_h;
 149
 150         src_w = drm_rect_width(src) >> 16;
 151         src_h = drm_rect_height(src) >> 16;
 152         dst_w = drm_rect_width(dst);
 153         dst_h = drm_rect_height(dst);
 154
 155         /* Downscaling limits the maximum pixel rate */
 156         dst_w = min(src_w, dst_w);
 157         dst_h = min(src_h, dst_h);
 158
 159         return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
 160                                 dst_w * dst_h);
 161 }
 162
 163 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
 164                                     const struct intel_plane_state *plane_state)
 165 {
 166         /*
 167          * Note we don't check for plane visibility here as
 168          * we want to use this when calculating the cursor
 169          * watermarks even if the cursor is fully offscreen.
 170          * That depends on the src/dst rectangles being
 171          * correctly populated whenever the watermark code
 172          * considers the cursor to be visible, whether or not
 173          * it is actually visible.
 174          *
 175          * See: intel_wm_plane_visible() and intel_check_cursor()
 176          */
 177
 178         return intel_adjusted_rate(&plane_state->uapi.src,
 179                                    &plane_state->uapi.dst,
 180                                    crtc_state->pixel_rate);
 181 }
 182
 183 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 184                                    const struct intel_plane_state *plane_state,
 185                                    int color_plane)
 186 {
 187         const struct drm_framebuffer *fb = plane_state->hw.fb;
 188
 189         if (!plane_state->uapi.visible)
 190                 return 0;
 191
 192         return intel_plane_pixel_rate(crtc_state, plane_state) *
 193                 fb->format->cpp[color_plane];
 194 }
 195
 196 static bool
 197 use_min_ddb(const struct intel_crtc_state *crtc_state,
 198             struct intel_plane *plane)
 199 {
 200         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 201
 202         return DISPLAY_VER(i915) >= 13 &&
 203                crtc_state->uapi.async_flip &&
 204                plane->async_flip;
 205 }
 206
 207 static unsigned int
 208 intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 209                                const struct intel_plane_state *plane_state,
 210                                int color_plane)
 211 {
 212         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 213         const struct drm_framebuffer *fb = plane_state->hw.fb;
 214         int width, height;
 215         unsigned int rel_data_rate;
 216
 217         if (!plane_state->uapi.visible)
 218                 return 0;
 219
 220         /*
 221          * We calculate extra ddb based on ratio plane rate/total data rate
 222          * in case, in some cases we should not allocate extra ddb for the plane,
 223          * so do not count its data rate, if this is the case.
 224          */
 225         if (use_min_ddb(crtc_state, plane))
 226                 return 0;
 227
 228         /*
 229          * Src coordinates are already rotated by 270 degrees for
 230          * the 90/270 degree plane rotation cases (to match the
 231          * GTT mapping), hence no need to account for rotation here.
 232          */
 233         width = drm_rect_width(&plane_state->uapi.src) >> 16;
 234         height = drm_rect_height(&plane_state->uapi.src) >> 16;
 235
 236         /* UV plane does 1/2 pixel sub-sampling */
 237         if (color_plane == 1) {
 238                 width /= 2;
 239                 height /= 2;
 240         }
 241
 242         rel_data_rate = width * height * fb->format->cpp[color_plane];
 243
 244         if (plane->id == PLANE_CURSOR)
 245                 return rel_data_rate;
 246
 247         return intel_adjusted_rate(&plane_state->uapi.src,
 248                                    &plane_state->uapi.dst,
 249                                    rel_data_rate);
 250 }
 251
 252 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 253                                struct intel_plane *plane,
 254                                bool *need_cdclk_calc)
 255 {
 256         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 257         const struct intel_plane_state *plane_state =
 258                 intel_atomic_get_new_plane_state(state, plane);
 259         struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
 260         const struct intel_cdclk_state *cdclk_state;
 261         const struct intel_crtc_state *old_crtc_state;
 262         struct intel_crtc_state *new_crtc_state;
 263
 264         if (!plane_state->uapi.visible || !plane->min_cdclk)
 265                 return 0;
 266
 267         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
 268         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 269
 270         new_crtc_state->min_cdclk[plane->id] =
 271                 plane->min_cdclk(new_crtc_state, plane_state);
 272
 273         /*
 274          * No need to check against the cdclk state if
 275          * the min cdclk for the plane doesn't increase.
 276          *
 277          * Ie. we only ever increase the cdclk due to plane
 278          * requirements. This can reduce back and forth
 279          * display blinking due to constant cdclk changes.
 280          */
 281         if (new_crtc_state->min_cdclk[plane->id] <=
 282             old_crtc_state->min_cdclk[plane->id])
 283                 return 0;
 284
 285         cdclk_state = intel_atomic_get_cdclk_state(state);
 286         if (IS_ERR(cdclk_state))
 287                 return PTR_ERR(cdclk_state);
 288
 289         /*
 290          * No need to recalculate the cdclk state if
 291          * the min cdclk for the pipe doesn't increase.
 292          *
 293          * Ie. we only ever increase the cdclk due to plane
 294          * requirements. This can reduce back and forth
 295          * display blinking due to constant cdclk changes.
 296          */
 297         if (new_crtc_state->min_cdclk[plane->id] <=
 298             cdclk_state->min_cdclk[crtc->pipe])
 299                 return 0;
 300
 301         drm_dbg_kms(&dev_priv->drm,
 302                     "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
 303                     plane->base.base.id, plane->base.name,
 304                     new_crtc_state->min_cdclk[plane->id],
 305                     crtc->base.base.id, crtc->base.name,
 306                     cdclk_state->min_cdclk[crtc->pipe]);
 307         *need_cdclk_calc = true;
 308
 309         return 0;
 310 }
 311
 312 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
 313 {
 314         if (plane_state->hw.fb)
 315                 drm_framebuffer_put(plane_state->hw.fb);
 316
 317         memset(&plane_state->hw, 0, sizeof(plane_state->hw));
 318 }
 319
 320 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 321                                        const struct intel_plane_state *from_plane_state,
 322                                        struct intel_crtc *crtc)
 323 {
 324         intel_plane_clear_hw_state(plane_state);
 325
 326         /*
 327          * For the bigjoiner slave uapi.crtc will point at
 328          * the master crtc. So we explicitly assign the right
 329          * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
 330          * the plane is logically enabled on the uapi level.
 331          */
 332         plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
 333
 334         plane_state->hw.fb = from_plane_state->uapi.fb;
 335         if (plane_state->hw.fb)
 336                 drm_framebuffer_get(plane_state->hw.fb);
 337
 338         plane_state->hw.alpha = from_plane_state->uapi.alpha;
 339         plane_state->hw.pixel_blend_mode =
 340                 from_plane_state->uapi.pixel_blend_mode;
 341         plane_state->hw.rotation = from_plane_state->uapi.rotation;
 342         plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
 343         plane_state->hw.color_range = from_plane_state->uapi.color_range;
 344         plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
 345
 346         plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
 347         plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
 348 }
 349
 350 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
 351                                const struct intel_plane_state *from_plane_state)
 352 {
 353         intel_plane_clear_hw_state(plane_state);
 354
 355         memcpy(&plane_state->hw, &from_plane_state->hw,
 356                sizeof(plane_state->hw));
 357
 358         if (plane_state->hw.fb)
 359                 drm_framebuffer_get(plane_state->hw.fb);
 360 }
 361
 362 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 363                                struct intel_plane_state *plane_state)
 364 {
 365         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 366
 367         crtc_state->active_planes &= ~BIT(plane->id);
 368         crtc_state->scaled_planes &= ~BIT(plane->id);
 369         crtc_state->nv12_planes &= ~BIT(plane->id);
 370         crtc_state->c8_planes &= ~BIT(plane->id);
 371         crtc_state->async_flip_planes &= ~BIT(plane->id);
 372         crtc_state->data_rate[plane->id] = 0;
 373         crtc_state->data_rate_y[plane->id] = 0;
 374         crtc_state->rel_data_rate[plane->id] = 0;
 375         crtc_state->rel_data_rate_y[plane->id] = 0;
 376         crtc_state->min_cdclk[plane->id] = 0;
 377
 378         plane_state->uapi.visible = false;
 379 }
 380
 381 /* FIXME nuke when all wm code is atomic */
 382 static bool intel_wm_need_update(const struct intel_plane_state *cur,
 383                                  struct intel_plane_state *new)
 384 {
 385         /* Update watermarks on tiling or size changes. */
 386         if (new->uapi.visible != cur->uapi.visible)
 387                 return true;
 388
 389         if (!cur->hw.fb || !new->hw.fb)
 390                 return false;
 391
 392         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
 393             cur->hw.rotation != new->hw.rotation ||
 394             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
 395             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
 396             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
 397             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
 398                 return true;
 399
 400         return false;
 401 }
 402
 403 static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
 404 {
 405         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 406         int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 407         int dst_w = drm_rect_width(&plane_state->uapi.dst);
 408         int dst_h = drm_rect_height(&plane_state->uapi.dst);
 409
 410         return src_w != dst_w || src_h != dst_h;
 411 }
 412
 413 static bool intel_plane_do_async_flip(struct intel_plane *plane,
 414                                       const struct intel_crtc_state *old_crtc_state,
 415                                       const struct intel_crtc_state *new_crtc_state)
 416 {
 417         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 418
 419         if (!plane->async_flip)
 420                 return false;
 421
 422         if (!new_crtc_state->uapi.async_flip)
 423                 return false;
 424
 425         /*
 426          * In platforms after DISPLAY13, we might need to override
 427          * first async flip in order to change watermark levels
 428          * as part of optimization.
 429          * So for those, we are checking if this is a first async flip.
 430          * For platforms earlier than DISPLAY13 we always do async flip.
 431          */
 432         return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
 433 }
 434
 435 static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
 436                                    const struct intel_plane_state *old_plane_state,
 437                                    const struct intel_plane_state *new_plane_state)
 438 {
 439         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 440         bool old_visible = old_plane_state->uapi.visible;
 441         bool new_visible = new_plane_state->uapi.visible;
 442         u32 old_ctl = old_plane_state->ctl;
 443         u32 new_ctl = new_plane_state->ctl;
 444         bool modeset, turn_on, turn_off;
 445
 446         if (plane->id == PLANE_CURSOR)
 447                 return false;
 448
 449         modeset = intel_crtc_needs_modeset(new_crtc_state);
 450         turn_off = old_visible && (!new_visible || modeset);
 451         turn_on = new_visible && (!old_visible || modeset);
 452
 453         /* Must disable CxSR around plane enable/disable */
 454         if (turn_on || turn_off)
 455                 return true;
 456
 457         if (!old_visible || !new_visible)
 458                 return false;
 459
 460         /*
 461          * Most plane control register updates are blocked while in CxSR.
 462          *
 463          * Tiling mode is one exception where the primary plane can
 464          * apparently handle it, whereas the sprites can not (the
 465          * sprite issue being only relevant on VLV/CHV where CxSR
 466          * is actually possible with a sprite enabled).
 467          */
 468         if (plane->id == PLANE_PRIMARY) {
 469                 old_ctl &= ~DISP_TILED;
 470                 new_ctl &= ~DISP_TILED;
 471         }
 472
 473         return old_ctl != new_ctl;
 474 }
 475
 476 static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
 477                                            struct intel_crtc_state *new_crtc_state,
 478                                            const struct intel_plane_state *old_plane_state,
 479                                            struct intel_plane_state *new_plane_state)
 480 {
 481         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 482         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 483         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 484         bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
 485         bool was_crtc_enabled = old_crtc_state->hw.active;
 486         bool is_crtc_enabled = new_crtc_state->hw.active;
 487         bool turn_off, turn_on, visible, was_visible;
 488         int ret;
 489
 490         if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
 491                 ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
 492                 if (ret)
 493                         return ret;
 494         }
 495
 496         was_visible = old_plane_state->uapi.visible;
 497         visible = new_plane_state->uapi.visible;
 498
 499         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
 500                 was_visible = false;
 501
 502         /*
 503          * Visibility is calculated as if the crtc was on, but
 504          * after scaler setup everything depends on it being off
 505          * when the crtc isn't active.
 506          *
 507          * FIXME this is wrong for watermarks. Watermarks should also
 508          * be computed as if the pipe would be active. Perhaps move
 509          * per-plane wm computation to the .check_plane() hook, and
 510          * only combine the results from all planes in the current place?
 511          */
 512         if (!is_crtc_enabled) {
 513                 intel_plane_set_invisible(new_crtc_state, new_plane_state);
 514                 visible = false;
 515         }
 516
 517         if (!was_visible && !visible)
 518                 return 0;
 519
 520         turn_off = was_visible && (!visible || mode_changed);
 521         turn_on = visible && (!was_visible || mode_changed);
 522
 523         drm_dbg_atomic(&dev_priv->drm,
 524                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
 525                        crtc->base.base.id, crtc->base.name,
 526                        plane->base.base.id, plane->base.name,
 527                        was_visible, visible,
 528                        turn_off, turn_on, mode_changed);
 529
 530         if (turn_on) {
 531                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 532                         new_crtc_state->update_wm_pre = true;
 533         } else if (turn_off) {
 534                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 535                         new_crtc_state->update_wm_post = true;
 536         } else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
 537                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
 538                         /* FIXME bollocks */
 539                         new_crtc_state->update_wm_pre = true;
 540                         new_crtc_state->update_wm_post = true;
 541                 }
 542         }
 543
 544         if (visible || was_visible)
 545                 new_crtc_state->fb_bits |= plane->frontbuffer_bit;
 546
 547         if (HAS_GMCH(dev_priv) &&
 548             i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
 549                 new_crtc_state->disable_cxsr = true;
 550
 551         /*
 552          * ILK/SNB DVSACNTR/Sprite Enable
 553          * IVB SPR_CTL/Sprite Enable
 554          * "When in Self Refresh Big FIFO mode, a write to enable the
 555          *  plane will be internally buffered and delayed while Big FIFO
 556          *  mode is exiting."
 557          *
 558          * Which means that enabling the sprite can take an extra frame
 559          * when we start in big FIFO mode (LP1+). Thus we need to drop
 560          * down to LP0 and wait for vblank in order to make sure the
 561          * sprite gets enabled on the next vblank after the register write.
 562          * Doing otherwise would risk enabling the sprite one frame after
 563          * we've already signalled flip completion. We can resume LP1+
 564          * once the sprite has been enabled.
 565          *
 566          *
 567          * WaCxSRDisabledForSpriteScaling:ivb
 568          * IVB SPR_SCALE/Scaling Enable
 569          * "Low Power watermarks must be disabled for at least one
 570          *  frame before enabling sprite scaling, and kept disabled
 571          *  until sprite scaling is disabled."
 572          *
 573          * ILK/SNB DVSASCALE/Scaling Enable
 574          * "When in Self Refresh Big FIFO mode, scaling enable will be
 575          *  masked off while Big FIFO mode is exiting."
 576          *
 577          * Despite the w/a only being listed for IVB we assume that
 578          * the ILK/SNB note has similar ramifications, hence we apply
 579          * the w/a on all three platforms.
 580          *
 581          * With experimental results seems this is needed also for primary
 582          * plane, not only sprite plane.
 583          */
 584         if (plane->id != PLANE_CURSOR &&
 585             (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
 586              IS_IVYBRIDGE(dev_priv)) &&
 587             (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
 588                          intel_plane_is_scaled(new_plane_state))))
 589                 new_crtc_state->disable_lp_wm = true;
 590
 591         if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
 592                 new_crtc_state->do_async_flip = true;
 593                 new_crtc_state->async_flip_planes |= BIT(plane->id);
 594         }
 595
 596         return 0;
 597 }
 598
 599 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 600                                         struct intel_crtc_state *new_crtc_state,
 601                                         const struct intel_plane_state *old_plane_state,
 602                                         struct intel_plane_state *new_plane_state)
 603 {
 604         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 605         const struct drm_framebuffer *fb = new_plane_state->hw.fb;
 606         int ret;
 607
 608         intel_plane_set_invisible(new_crtc_state, new_plane_state);
 609         new_crtc_state->enabled_planes &= ~BIT(plane->id);
 610
 611         if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
 612                 return 0;
 613
 614         ret = plane->check_plane(new_crtc_state, new_plane_state);
 615         if (ret)
 616                 return ret;
 617
 618         if (fb)
 619                 new_crtc_state->enabled_planes |= BIT(plane->id);
 620
 621         /* FIXME pre-g4x don't work like this */
 622         if (new_plane_state->uapi.visible)
 623                 new_crtc_state->active_planes |= BIT(plane->id);
 624
 625         if (new_plane_state->uapi.visible &&
 626             intel_plane_is_scaled(new_plane_state))
 627                 new_crtc_state->scaled_planes |= BIT(plane->id);
 628
 629         if (new_plane_state->uapi.visible &&
 630             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 631                 new_crtc_state->nv12_planes |= BIT(plane->id);
 632
 633         if (new_plane_state->uapi.visible &&
 634             fb->format->format == DRM_FORMAT_C8)
 635                 new_crtc_state->c8_planes |= BIT(plane->id);
 636
 637         if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
 638                 new_crtc_state->update_planes |= BIT(plane->id);
 639
 640         if (new_plane_state->uapi.visible &&
 641             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 642                 new_crtc_state->data_rate_y[plane->id] =
 643                         intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 644                 new_crtc_state->data_rate[plane->id] =
 645                         intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
 646
 647                 new_crtc_state->rel_data_rate_y[plane->id] =
 648                         intel_plane_relative_data_rate(new_crtc_state,
 649                                                        new_plane_state, 0);
 650                 new_crtc_state->rel_data_rate[plane->id] =
 651                         intel_plane_relative_data_rate(new_crtc_state,
 652                                                        new_plane_state, 1);
 653         } else if (new_plane_state->uapi.visible) {
 654                 new_crtc_state->data_rate[plane->id] =
 655                         intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 656
 657                 new_crtc_state->rel_data_rate[plane->id] =
 658                         intel_plane_relative_data_rate(new_crtc_state,
 659                                                        new_plane_state, 0);
 660         }
 661
 662         return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
 663                                                old_plane_state, new_plane_state);
 664 }
 665
 666 static struct intel_plane *
 667 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
 668 {
 669         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 670         struct intel_plane *plane;
 671
 672         for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 673                 if (plane->id == plane_id)
 674                         return plane;
 675         }
 676
 677         return NULL;
 678 }
 679
 680 int intel_plane_atomic_check(struct intel_atomic_state *state,
 681                              struct intel_plane *plane)
 682 {
 683         struct drm_i915_private *i915 = to_i915(state->base.dev);
 684         struct intel_plane_state *new_plane_state =
 685                 intel_atomic_get_new_plane_state(state, plane);
 686         const struct intel_plane_state *old_plane_state =
 687                 intel_atomic_get_old_plane_state(state, plane);
 688         const struct intel_plane_state *new_master_plane_state;
 689         struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
 690         const struct intel_crtc_state *old_crtc_state =
 691                 intel_atomic_get_old_crtc_state(state, crtc);
 692         struct intel_crtc_state *new_crtc_state =
 693                 intel_atomic_get_new_crtc_state(state, crtc);
 694
 695         if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
 696                 struct intel_crtc *master_crtc =
 697                         intel_master_crtc(new_crtc_state);
 698                 struct intel_plane *master_plane =
 699                         intel_crtc_get_plane(master_crtc, plane->id);
 700
 701                 new_master_plane_state =
 702                         intel_atomic_get_new_plane_state(state, master_plane);
 703         } else {
 704                 new_master_plane_state = new_plane_state;
 705         }
 706
 707         intel_plane_copy_uapi_to_hw_state(new_plane_state,
 708                                           new_master_plane_state,
 709                                           crtc);
 710
 711         new_plane_state->uapi.visible = false;
 712         if (!new_crtc_state)
 713                 return 0;
 714
 715         return intel_plane_atomic_check_with_state(old_crtc_state,
 716                                                    new_crtc_state,
 717                                                    old_plane_state,
 718                                                    new_plane_state);
 719 }
 720
 721 static struct intel_plane *
 722 skl_next_plane_to_commit(struct intel_atomic_state *state,
 723                          struct intel_crtc *crtc,
 724                          struct skl_ddb_entry ddb[I915_MAX_PLANES],
 725                          struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
 726                          unsigned int *update_mask)
 727 {
 728         struct intel_crtc_state *crtc_state =
 729                 intel_atomic_get_new_crtc_state(state, crtc);
 730         struct intel_plane_state __maybe_unused *plane_state;
 731         struct intel_plane *plane;
 732         int i;
 733
 734         if (*update_mask == 0)
 735                 return NULL;
 736
 737         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 738                 enum plane_id plane_id = plane->id;
 739
 740                 if (crtc->pipe != plane->pipe ||
 741                     !(*update_mask & BIT(plane_id)))
 742                         continue;
 743
 744                 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
 745                                                 ddb, I915_MAX_PLANES, plane_id) ||
 746                     skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
 747                                                 ddb_y, I915_MAX_PLANES, plane_id))
 748                         continue;
 749
 750                 *update_mask &= ~BIT(plane_id);
 751                 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
 752                 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
 753
 754                 return plane;
 755         }
 756
 757         /* should never happen */
 758         drm_WARN_ON(state->base.dev, 1);
 759
 760         return NULL;
 761 }
 762
 763 void intel_plane_update_noarm(struct intel_plane *plane,
 764                               const struct intel_crtc_state *crtc_state,
 765                               const struct intel_plane_state *plane_state)
 766 {
 767         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 768
 769         trace_intel_plane_update_noarm(plane, crtc);
 770
 771         if (plane->update_noarm)
 772                 plane->update_noarm(plane, crtc_state, plane_state);
 773 }
 774
 775 void intel_plane_update_arm(struct intel_plane *plane,
 776                             const struct intel_crtc_state *crtc_state,
 777                             const struct intel_plane_state *plane_state)
 778 {
 779         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 780
 781         trace_intel_plane_update_arm(plane, crtc);
 782
 783         if (crtc_state->do_async_flip && plane->async_flip)
 784                 plane->async_flip(plane, crtc_state, plane_state, true);
 785         else
 786                 plane->update_arm(plane, crtc_state, plane_state);
 787 }
 788
 789 void intel_plane_disable_arm(struct intel_plane *plane,
 790                              const struct intel_crtc_state *crtc_state)
 791 {
 792         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 793
 794         trace_intel_plane_disable_arm(plane, crtc);
 795         plane->disable_arm(plane, crtc_state);
 796 }
 797
 798 void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
 799                                     struct intel_crtc *crtc)
 800 {
 801         struct intel_crtc_state *new_crtc_state =
 802                 intel_atomic_get_new_crtc_state(state, crtc);
 803         u32 update_mask = new_crtc_state->update_planes;
 804         struct intel_plane_state *new_plane_state;
 805         struct intel_plane *plane;
 806         int i;
 807
 808         if (new_crtc_state->do_async_flip)
 809                 return;
 810
 811         /*
 812          * Since we only write non-arming registers here,
 813          * the order does not matter even for skl+.
 814          */
 815         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 816                 if (crtc->pipe != plane->pipe ||
 817                     !(update_mask & BIT(plane->id)))
 818                         continue;
 819
 820                 /* TODO: for mailbox updates this should be skipped */
 821                 if (new_plane_state->uapi.visible ||
 822                     new_plane_state->planar_slave)
 823                         intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
 824         }
 825 }
 826
 827 static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
 828                                        struct intel_crtc *crtc)
 829 {
 830         struct intel_crtc_state *old_crtc_state =
 831                 intel_atomic_get_old_crtc_state(state, crtc);
 832         struct intel_crtc_state *new_crtc_state =
 833                 intel_atomic_get_new_crtc_state(state, crtc);
 834         struct skl_ddb_entry ddb[I915_MAX_PLANES];
 835         struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
 836         u32 update_mask = new_crtc_state->update_planes;
 837         struct intel_plane *plane;
 838
 839         memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
 840                sizeof(old_crtc_state->wm.skl.plane_ddb));
 841         memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
 842                sizeof(old_crtc_state->wm.skl.plane_ddb_y));
 843
 844         while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
 845                 struct intel_plane_state *new_plane_state =
 846                         intel_atomic_get_new_plane_state(state, plane);
 847
 848                 /*
 849                  * TODO: for mailbox updates intel_plane_update_noarm()
 850                  * would have to be called here as well.
 851                  */
 852                 if (new_plane_state->uapi.visible ||
 853                     new_plane_state->planar_slave)
 854                         intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
 855                 else
 856                         intel_plane_disable_arm(plane, new_crtc_state);
 857         }
 858 }
 859
 860 static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
 861                                         struct intel_crtc *crtc)
 862 {
 863         struct intel_crtc_state *new_crtc_state =
 864                 intel_atomic_get_new_crtc_state(state, crtc);
 865         u32 update_mask = new_crtc_state->update_planes;
 866         struct intel_plane_state *new_plane_state;
 867         struct intel_plane *plane;
 868         int i;
 869
 870         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 871                 if (crtc->pipe != plane->pipe ||
 872                     !(update_mask & BIT(plane->id)))
 873                         continue;
 874
 875                 /*
 876                  * TODO: for mailbox updates intel_plane_update_noarm()
 877                  * would have to be called here as well.
 878                  */
 879                 if (new_plane_state->uapi.visible)
 880                         intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
 881                 else
 882                         intel_plane_disable_arm(plane, new_crtc_state);
 883         }
 884 }
 885
 886 void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
 887                                   struct intel_crtc *crtc)
 888 {
 889         struct drm_i915_private *i915 = to_i915(state->base.dev);
 890
 891         if (DISPLAY_VER(i915) >= 9)
 892                 skl_crtc_planes_update_arm(state, crtc);
 893         else
 894                 i9xx_crtc_planes_update_arm(state, crtc);
 895 }
 896
 897 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
 898                                       struct intel_crtc_state *crtc_state,
 899                                       int min_scale, int max_scale,
 900                                       bool can_position)
 901 {
 902         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 903         struct drm_framebuffer *fb = plane_state->hw.fb;
 904         struct drm_rect *src = &plane_state->uapi.src;
 905         struct drm_rect *dst = &plane_state->uapi.dst;
 906         const struct drm_rect *clip = &crtc_state->pipe_src;
 907         unsigned int rotation = plane_state->hw.rotation;
 908         int hscale, vscale;
 909
 910         if (!fb) {
 911                 plane_state->uapi.visible = false;
 912                 return 0;
 913         }
 914
 915         drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
 916
 917         /* Check scaling */
 918         hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 919         vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 920         if (hscale < 0 || vscale < 0) {
 921                 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
 922                 drm_rect_debug_print("src: ", src, true);
 923                 drm_rect_debug_print("dst: ", dst, false);
 924                 return -ERANGE;
 925         }
 926
 927         /*
 928          * FIXME: This might need further adjustment for seamless scaling
 929          * with phase information, for the 2p2 and 2p1 scenarios.
 930          */
 931         plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
 932
 933         drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
 934
 935         if (!can_position && plane_state->uapi.visible &&
 936             !drm_rect_equals(dst, clip)) {
 937                 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
 938                 drm_rect_debug_print("dst: ", dst, false);
 939                 drm_rect_debug_print("clip: ", clip, false);
 940                 return -EINVAL;
 941         }
 942
 943         /* final plane coordinates will be relative to the plane's pipe */
 944         drm_rect_translate(dst, -clip->x1, -clip->y1);
 945
 946         return 0;
 947 }
 948
 949 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 950 {
 951         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 952         const struct drm_framebuffer *fb = plane_state->hw.fb;
 953         struct drm_rect *src = &plane_state->uapi.src;
 954         u32 src_x, src_y, src_w, src_h, hsub, vsub;
 955         bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
 956
 957         /*
 958          * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
 959          * abuses hsub/vsub so we can't use them here. But as they
 960          * are limited to 32bpp RGB formats we don't actually need
 961          * to check anything.
 962          */
 963         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 964             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
 965                 return 0;
 966
 967         /*
 968          * Hardware doesn't handle subpixel coordinates.
 969          * Adjust to (macro)pixel boundary, but be careful not to
 970          * increase the source viewport size, because that could
 971          * push the downscaling factor out of bounds.
 972          */
 973         src_x = src->x1 >> 16;
 974         src_w = drm_rect_width(src) >> 16;
 975         src_y = src->y1 >> 16;
 976         src_h = drm_rect_height(src) >> 16;
 977
 978         drm_rect_init(src, src_x << 16, src_y << 16,
 979                       src_w << 16, src_h << 16);
 980
 981         if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
 982                 hsub = 2;
 983                 vsub = 2;
 984         } else if (DISPLAY_VER(i915) >= 20 &&
 985                    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 986                 /*
 987                  * This allows NV12 and P0xx formats to have odd size and/or odd
 988                  * source coordinates on DISPLAY_VER(i915) >= 20
 989                  */
 990                 hsub = 1;
 991                 vsub = 1;
 992         } else {
 993                 hsub = fb->format->hsub;
 994                 vsub = fb->format->vsub;
 995         }
 996
 997         if (rotated)
 998                 hsub = vsub = max(hsub, vsub);
 999
1000         if (src_x % hsub || src_w % hsub) {
1001                 drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
1002                             src_x, src_w, hsub, str_yes_no(rotated));
1003                 return -EINVAL;
1004         }
1005
1006         if (src_y % vsub || src_h % vsub) {
1007                 drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
1008                             src_y, src_h, vsub, str_yes_no(rotated));
1009                 return -EINVAL;
1010         }
1011
1012         return 0;
1013 }
1014
1015 /**
1016  * intel_prepare_plane_fb - Prepare fb for usage on plane
1017  * @_plane: drm plane to prepare for
1018  * @_new_plane_state: the plane state being prepared
1019  *
1020  * Prepares a framebuffer for usage on a display plane.  Generally this
1021  * involves pinning the underlying object and updating the frontbuffer tracking
1022  * bits.  Some older platforms need special physical address handling for
1023  * cursor planes.
1024  *
1025  * Returns 0 on success, negative error code on failure.
1026  */
1027 static int
1028 intel_prepare_plane_fb(struct drm_plane *_plane,
1029                        struct drm_plane_state *_new_plane_state)
1030 {
1031         struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
1032         struct intel_plane *plane = to_intel_plane(_plane);
1033         struct intel_plane_state *new_plane_state =
1034                 to_intel_plane_state(_new_plane_state);
1035         struct intel_atomic_state *state =
1036                 to_intel_atomic_state(new_plane_state->uapi.state);
1037         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1038         const struct intel_plane_state *old_plane_state =
1039                 intel_atomic_get_old_plane_state(state, plane);
1040         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
1041         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
1042         int ret;
1043
1044         if (old_obj) {
1045                 const struct intel_crtc_state *new_crtc_state =
1046                         intel_atomic_get_new_crtc_state(state,
1047                                                         to_intel_crtc(old_plane_state->hw.crtc));
1048
1049                 /* Big Hammer, we also need to ensure that any pending
1050                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1051                  * current scanout is retired before unpinning the old
1052                  * framebuffer. Note that we rely on userspace rendering
1053                  * into the buffer attached to the pipe they are waiting
1054                  * on. If not, userspace generates a GPU hang with IPEHR
1055                  * point to the MI_WAIT_FOR_EVENT.
1056                  *
1057                  * This should only fail upon a hung GPU, in which case we
1058                  * can safely continue.
1059                  */
1060                 if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state)) {
1061                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
1062                                                               old_obj->base.resv,
1063                                                               false, 0,
1064                                                               GFP_KERNEL);
1065                         if (ret < 0)
1066                                 return ret;
1067                 }
1068         }
1069
1070         if (new_plane_state->uapi.fence) { /* explicit fencing */
1071                 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
1072                                              &attr);
1073                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
1074                                                     new_plane_state->uapi.fence,
1075                                                     i915_fence_timeout(dev_priv),
1076                                                     GFP_KERNEL);
1077                 if (ret < 0)
1078                         return ret;
1079         }
1080
1081         if (!obj)
1082                 return 0;
1083
1084
1085         ret = intel_plane_pin_fb(new_plane_state);
1086         if (ret)
1087                 return ret;
1088
1089         i915_gem_object_wait_priority(obj, 0, &attr);
1090
1091         if (!new_plane_state->uapi.fence) { /* implicit fencing */
1092                 struct dma_resv_iter cursor;
1093                 struct dma_fence *fence;
1094
1095                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
1096                                                       obj->base.resv, false,
1097                                                       i915_fence_timeout(dev_priv),
1098                                                       GFP_KERNEL);
1099                 if (ret < 0)
1100                         goto unpin_fb;
1101
1102                 dma_resv_iter_begin(&cursor, obj->base.resv,
1103                                     DMA_RESV_USAGE_WRITE);
1104                 dma_resv_for_each_fence_unlocked(&cursor, fence) {
1105                         intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
1106                                                              fence);
1107                 }
1108                 dma_resv_iter_end(&cursor);
1109         } else {
1110                 intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
1111                                                      new_plane_state->uapi.fence);
1112         }
1113
1114         /*
1115          * We declare pageflips to be interactive and so merit a small bias
1116          * towards upclocking to deliver the frame on time. By only changing
1117          * the RPS thresholds to sample more regularly and aim for higher
1118          * clocks we can hopefully deliver low power workloads (like kodi)
1119          * that are not quite steady state without resorting to forcing
1120          * maximum clocks following a vblank miss (see do_rps_boost()).
1121          */
1122         intel_display_rps_mark_interactive(dev_priv, state, true);
1123
1124         return 0;
1125
1126 unpin_fb:
1127         intel_plane_unpin_fb(new_plane_state);
1128
1129         return ret;
1130 }
1131
1132 /**
1133  * intel_cleanup_plane_fb - Cleans up an fb after plane use
1134  * @plane: drm plane to clean up for
1135  * @_old_plane_state: the state from the previous modeset
1136  *
1137  * Cleans up a framebuffer that has just been removed from a plane.
1138  */
1139 static void
1140 intel_cleanup_plane_fb(struct drm_plane *plane,
1141                        struct drm_plane_state *_old_plane_state)
1142 {
1143         struct intel_plane_state *old_plane_state =
1144                 to_intel_plane_state(_old_plane_state);
1145         struct intel_atomic_state *state =
1146                 to_intel_atomic_state(old_plane_state->uapi.state);
1147         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1148         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
1149
1150         if (!obj)
1151                 return;
1152
1153         intel_display_rps_mark_interactive(dev_priv, state, false);
1154
1155         /* Should only be called after a successful intel_prepare_plane_fb()! */
1156         intel_plane_unpin_fb(old_plane_state);
1157 }
1158
1159 static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1160         .prepare_fb = intel_prepare_plane_fb,
1161         .cleanup_fb = intel_cleanup_plane_fb,
1162 };
1163
1164 void intel_plane_helper_add(struct intel_plane *plane)
1165 {
1166         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1167 }