drivers/gpu/drm/arm/hdlcd_drv.c

   1 /*
   2  * Copyright (C) 2013-2015 ARM Limited
   3  * Author: Liviu Dudau <[email protected]>
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive
   7  * for more details.
   8  *
   9  *  ARM HDLCD Driver
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/list.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/of_reserved_mem.h>
  19 #include <linux/pm_runtime.h>
  20
  21 #include <drm/drmP.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_crtc.h>
  24 #include <drm/drm_crtc_helper.h>
  25 #include <drm/drm_fb_helper.h>
  26 #include <drm/drm_fb_cma_helper.h>
  27 #include <drm/drm_gem_cma_helper.h>
  28 #include <drm/drm_of.h>
  29
  30 #include "hdlcd_drv.h"
  31 #include "hdlcd_regs.h"
  32
  33 static int hdlcd_load(struct drm_device *drm, unsigned long flags)
  34 {
  35         struct hdlcd_drm_private *hdlcd = drm->dev_private;
  36         struct platform_device *pdev = to_platform_device(drm->dev);
  37         struct resource *res;
  38         u32 version;
  39         int ret;
  40
  41         hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
  42         if (IS_ERR(hdlcd->clk))
  43                 return PTR_ERR(hdlcd->clk);
  44
  45 #ifdef CONFIG_DEBUG_FS
  46         atomic_set(&hdlcd->buffer_underrun_count, 0);
  47         atomic_set(&hdlcd->bus_error_count, 0);
  48         atomic_set(&hdlcd->vsync_count, 0);
  49         atomic_set(&hdlcd->dma_end_count, 0);
  50 #endif
  51
  52         INIT_LIST_HEAD(&hdlcd->event_list);
  53
  54         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  55         hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
  56         if (IS_ERR(hdlcd->mmio)) {
  57                 DRM_ERROR("failed to map control registers area\n");
  58                 ret = PTR_ERR(hdlcd->mmio);
  59                 hdlcd->mmio = NULL;
  60                 goto fail;
  61         }
  62
  63         version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
  64         if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
  65                 DRM_ERROR("unknown product id: 0x%x\n", version);
  66                 ret = -EINVAL;
  67                 goto fail;
  68         }
  69         DRM_INFO("found ARM HDLCD version r%dp%d\n",
  70                 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
  71                 version & HDLCD_VERSION_MINOR_MASK);
  72
  73         /* Get the optional framebuffer memory resource */
  74         ret = of_reserved_mem_device_init(drm->dev);
  75         if (ret && ret != -ENODEV)
  76                 goto fail;
  77
  78         ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
  79         if (ret)
  80                 goto setup_fail;
  81
  82         ret = hdlcd_setup_crtc(drm);
  83         if (ret < 0) {
  84                 DRM_ERROR("failed to create crtc\n");
  85                 goto setup_fail;
  86         }
  87
  88         pm_runtime_enable(drm->dev);
  89
  90         pm_runtime_get_sync(drm->dev);
  91         ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
  92         pm_runtime_put_sync(drm->dev);
  93         if (ret < 0) {
  94                 DRM_ERROR("failed to install IRQ handler\n");
  95                 goto irq_fail;
  96         }
  97
  98         return 0;
  99
 100 irq_fail:
 101         drm_crtc_cleanup(&hdlcd->crtc);
 102 setup_fail:
 103         of_reserved_mem_device_release(drm->dev);
 104 fail:
 105         devm_clk_put(drm->dev, hdlcd->clk);
 106
 107         return ret;
 108 }
 109
 110 static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
 111 {
 112         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 113
 114         if (hdlcd->fbdev)
 115                 drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
 116 }
 117
 118 static int hdlcd_atomic_commit(struct drm_device *dev,
 119                                struct drm_atomic_state *state, bool async)
 120 {
 121         return drm_atomic_helper_commit(dev, state, false);
 122 }
 123
 124 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
 125         .fb_create = drm_fb_cma_create,
 126         .output_poll_changed = hdlcd_fb_output_poll_changed,
 127         .atomic_check = drm_atomic_helper_check,
 128         .atomic_commit = hdlcd_atomic_commit,
 129 };
 130
 131 static void hdlcd_setup_mode_config(struct drm_device *drm)
 132 {
 133         drm_mode_config_init(drm);
 134         drm->mode_config.min_width = 0;
 135         drm->mode_config.min_height = 0;
 136         drm->mode_config.max_width = HDLCD_MAX_XRES;
 137         drm->mode_config.max_height = HDLCD_MAX_YRES;
 138         drm->mode_config.funcs = &hdlcd_mode_config_funcs;
 139 }
 140
 141 static void hdlcd_lastclose(struct drm_device *drm)
 142 {
 143         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 144
 145         drm_fbdev_cma_restore_mode(hdlcd->fbdev);
 146 }
 147
 148 static irqreturn_t hdlcd_irq(int irq, void *arg)
 149 {
 150         struct drm_device *drm = arg;
 151         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 152         unsigned long irq_status;
 153
 154         irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
 155
 156 #ifdef CONFIG_DEBUG_FS
 157         if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
 158                 atomic_inc(&hdlcd->buffer_underrun_count);
 159
 160         if (irq_status & HDLCD_INTERRUPT_DMA_END)
 161                 atomic_inc(&hdlcd->dma_end_count);
 162
 163         if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
 164                 atomic_inc(&hdlcd->bus_error_count);
 165
 166         if (irq_status & HDLCD_INTERRUPT_VSYNC)
 167                 atomic_inc(&hdlcd->vsync_count);
 168
 169 #endif
 170         if (irq_status & HDLCD_INTERRUPT_VSYNC) {
 171                 bool events_sent = false;
 172                 unsigned long flags;
 173                 struct drm_pending_vblank_event *e, *t;
 174
 175                 drm_crtc_handle_vblank(&hdlcd->crtc);
 176
 177                 spin_lock_irqsave(&drm->event_lock, flags);
 178                 list_for_each_entry_safe(e, t, &hdlcd->event_list, base.link) {
 179                         list_del(&e->base.link);
 180                         drm_crtc_send_vblank_event(&hdlcd->crtc, e);
 181                         events_sent = true;
 182                 }
 183                 if (events_sent)
 184                         drm_crtc_vblank_put(&hdlcd->crtc);
 185                 spin_unlock_irqrestore(&drm->event_lock, flags);
 186         }
 187
 188         /* acknowledge interrupt(s) */
 189         hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
 190
 191         return IRQ_HANDLED;
 192 }
 193
 194 static void hdlcd_irq_preinstall(struct drm_device *drm)
 195 {
 196         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 197         /* Ensure interrupts are disabled */
 198         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
 199         hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
 200 }
 201
 202 static int hdlcd_irq_postinstall(struct drm_device *drm)
 203 {
 204 #ifdef CONFIG_DEBUG_FS
 205         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 206         unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
 207
 208         /* enable debug interrupts */
 209         irq_mask |= HDLCD_DEBUG_INT_MASK;
 210
 211         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
 212 #endif
 213         return 0;
 214 }
 215
 216 static void hdlcd_irq_uninstall(struct drm_device *drm)
 217 {
 218         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 219         /* disable all the interrupts that we might have enabled */
 220         unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
 221
 222 #ifdef CONFIG_DEBUG_FS
 223         /* disable debug interrupts */
 224         irq_mask &= ~HDLCD_DEBUG_INT_MASK;
 225 #endif
 226
 227         /* disable vsync interrupts */
 228         irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
 229
 230         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
 231 }
 232
 233 static int hdlcd_enable_vblank(struct drm_device *drm, unsigned int crtc)
 234 {
 235         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 236         unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
 237
 238         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
 239
 240         return 0;
 241 }
 242
 243 static void hdlcd_disable_vblank(struct drm_device *drm, unsigned int crtc)
 244 {
 245         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 246         unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
 247
 248         hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
 249 }
 250
 251 #ifdef CONFIG_DEBUG_FS
 252 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
 253 {
 254         struct drm_info_node *node = (struct drm_info_node *)m->private;
 255         struct drm_device *drm = node->minor->dev;
 256         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 257
 258         seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
 259         seq_printf(m, "dma_end  : %d\n", atomic_read(&hdlcd->dma_end_count));
 260         seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
 261         seq_printf(m, "vsync    : %d\n", atomic_read(&hdlcd->vsync_count));
 262         return 0;
 263 }
 264
 265 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
 266 {
 267         struct drm_info_node *node = (struct drm_info_node *)m->private;
 268         struct drm_device *drm = node->minor->dev;
 269         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 270         unsigned long clkrate = clk_get_rate(hdlcd->clk);
 271         unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
 272
 273         seq_printf(m, "hw  : %lu\n", clkrate);
 274         seq_printf(m, "mode: %lu\n", mode_clock);
 275         return 0;
 276 }
 277
 278 static struct drm_info_list hdlcd_debugfs_list[] = {
 279         { "interrupt_count", hdlcd_show_underrun_count, 0 },
 280         { "clocks", hdlcd_show_pxlclock, 0 },
 281 };
 282
 283 static int hdlcd_debugfs_init(struct drm_minor *minor)
 284 {
 285         return drm_debugfs_create_files(hdlcd_debugfs_list,
 286                 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
 287 }
 288
 289 static void hdlcd_debugfs_cleanup(struct drm_minor *minor)
 290 {
 291         drm_debugfs_remove_files(hdlcd_debugfs_list,
 292                 ARRAY_SIZE(hdlcd_debugfs_list), minor);
 293 }
 294 #endif
 295
 296 static const struct file_operations fops = {
 297         .owner          = THIS_MODULE,
 298         .open           = drm_open,
 299         .release        = drm_release,
 300         .unlocked_ioctl = drm_ioctl,
 301 #ifdef CONFIG_COMPAT
 302         .compat_ioctl   = drm_compat_ioctl,
 303 #endif
 304         .poll           = drm_poll,
 305         .read           = drm_read,
 306         .llseek         = noop_llseek,
 307         .mmap           = drm_gem_cma_mmap,
 308 };
 309
 310 static struct drm_driver hdlcd_driver = {
 311         .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
 312                            DRIVER_MODESET | DRIVER_PRIME |
 313                            DRIVER_ATOMIC,
 314         .lastclose = hdlcd_lastclose,
 315         .irq_handler = hdlcd_irq,
 316         .irq_preinstall = hdlcd_irq_preinstall,
 317         .irq_postinstall = hdlcd_irq_postinstall,
 318         .irq_uninstall = hdlcd_irq_uninstall,
 319         .get_vblank_counter = drm_vblank_no_hw_counter,
 320         .enable_vblank = hdlcd_enable_vblank,
 321         .disable_vblank = hdlcd_disable_vblank,
 322         .gem_free_object = drm_gem_cma_free_object,
 323         .gem_vm_ops = &drm_gem_cma_vm_ops,
 324         .dumb_create = drm_gem_cma_dumb_create,
 325         .dumb_map_offset = drm_gem_cma_dumb_map_offset,
 326         .dumb_destroy = drm_gem_dumb_destroy,
 327         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 328         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 329         .gem_prime_export = drm_gem_prime_export,
 330         .gem_prime_import = drm_gem_prime_import,
 331         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 332         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 333         .gem_prime_vmap = drm_gem_cma_prime_vmap,
 334         .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
 335         .gem_prime_mmap = drm_gem_cma_prime_mmap,
 336 #ifdef CONFIG_DEBUG_FS
 337         .debugfs_init = hdlcd_debugfs_init,
 338         .debugfs_cleanup = hdlcd_debugfs_cleanup,
 339 #endif
 340         .fops = &fops,
 341         .name = "hdlcd",
 342         .desc = "ARM HDLCD Controller DRM",
 343         .date = "20151021",
 344         .major = 1,
 345         .minor = 0,
 346 };
 347
 348 static int hdlcd_drm_bind(struct device *dev)
 349 {
 350         struct drm_device *drm;
 351         struct hdlcd_drm_private *hdlcd;
 352         int ret;
 353
 354         hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
 355         if (!hdlcd)
 356                 return -ENOMEM;
 357
 358         drm = drm_dev_alloc(&hdlcd_driver, dev);
 359         if (!drm)
 360                 return -ENOMEM;
 361
 362         drm->dev_private = hdlcd;
 363         hdlcd_setup_mode_config(drm);
 364         ret = hdlcd_load(drm, 0);
 365         if (ret)
 366                 goto err_free;
 367
 368         ret = drm_dev_register(drm, 0);
 369         if (ret)
 370                 goto err_unload;
 371
 372         dev_set_drvdata(dev, drm);
 373
 374         ret = component_bind_all(dev, drm);
 375         if (ret) {
 376                 DRM_ERROR("Failed to bind all components\n");
 377                 goto err_unregister;
 378         }
 379
 380         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
 381         if (ret < 0) {
 382                 DRM_ERROR("failed to initialise vblank\n");
 383                 goto err_vblank;
 384         }
 385         drm->vblank_disable_allowed = true;
 386
 387         drm_mode_config_reset(drm);
 388         drm_kms_helper_poll_init(drm);
 389
 390         hdlcd->fbdev = drm_fbdev_cma_init(drm, 32, drm->mode_config.num_crtc,
 391                                           drm->mode_config.num_connector);
 392
 393         if (IS_ERR(hdlcd->fbdev)) {
 394                 ret = PTR_ERR(hdlcd->fbdev);
 395                 hdlcd->fbdev = NULL;
 396                 goto err_fbdev;
 397         }
 398
 399         return 0;
 400
 401 err_fbdev:
 402         drm_kms_helper_poll_fini(drm);
 403         drm_mode_config_cleanup(drm);
 404         drm_vblank_cleanup(drm);
 405 err_vblank:
 406         component_unbind_all(dev, drm);
 407 err_unregister:
 408         drm_dev_unregister(drm);
 409 err_unload:
 410         pm_runtime_get_sync(drm->dev);
 411         drm_irq_uninstall(drm);
 412         pm_runtime_put_sync(drm->dev);
 413         pm_runtime_disable(drm->dev);
 414         of_reserved_mem_device_release(drm->dev);
 415         devm_clk_put(dev, hdlcd->clk);
 416 err_free:
 417         drm_dev_unref(drm);
 418
 419         return ret;
 420 }
 421
 422 static void hdlcd_drm_unbind(struct device *dev)
 423 {
 424         struct drm_device *drm = dev_get_drvdata(dev);
 425         struct hdlcd_drm_private *hdlcd = drm->dev_private;
 426
 427         if (hdlcd->fbdev) {
 428                 drm_fbdev_cma_fini(hdlcd->fbdev);
 429                 hdlcd->fbdev = NULL;
 430         }
 431         drm_kms_helper_poll_fini(drm);
 432         component_unbind_all(dev, drm);
 433         drm_vblank_cleanup(drm);
 434         pm_runtime_get_sync(drm->dev);
 435         drm_irq_uninstall(drm);
 436         pm_runtime_put_sync(drm->dev);
 437         pm_runtime_disable(drm->dev);
 438         of_reserved_mem_device_release(drm->dev);
 439         if (!IS_ERR(hdlcd->clk)) {
 440                 devm_clk_put(drm->dev, hdlcd->clk);
 441                 hdlcd->clk = NULL;
 442         }
 443         drm_mode_config_cleanup(drm);
 444         drm_dev_unregister(drm);
 445         drm_dev_unref(drm);
 446         drm->dev_private = NULL;
 447         dev_set_drvdata(dev, NULL);
 448 }
 449
 450 static const struct component_master_ops hdlcd_master_ops = {
 451         .bind           = hdlcd_drm_bind,
 452         .unbind         = hdlcd_drm_unbind,
 453 };
 454
 455 static int compare_dev(struct device *dev, void *data)
 456 {
 457         return dev->of_node == data;
 458 }
 459
 460 static int hdlcd_probe(struct platform_device *pdev)
 461 {
 462         struct device_node *port, *ep;
 463         struct component_match *match = NULL;
 464
 465         if (!pdev->dev.of_node)
 466                 return -ENODEV;
 467
 468         /* there is only one output port inside each device, find it */
 469         ep = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);
 470         if (!ep)
 471                 return -ENODEV;
 472
 473         if (!of_device_is_available(ep)) {
 474                 of_node_put(ep);
 475                 return -ENODEV;
 476         }
 477
 478         /* add the remote encoder port as component */
 479         port = of_graph_get_remote_port_parent(ep);
 480         of_node_put(ep);
 481         if (!port || !of_device_is_available(port)) {
 482                 of_node_put(port);
 483                 return -EAGAIN;
 484         }
 485
 486         component_match_add(&pdev->dev, &match, compare_dev, port);
 487
 488         return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
 489                                                match);
 490 }
 491
 492 static int hdlcd_remove(struct platform_device *pdev)
 493 {
 494         component_master_del(&pdev->dev, &hdlcd_master_ops);
 495         return 0;
 496 }
 497
 498 static const struct of_device_id  hdlcd_of_match[] = {
 499         { .compatible   = "arm,hdlcd" },
 500         {},
 501 };
 502 MODULE_DEVICE_TABLE(of, hdlcd_of_match);
 503
 504 static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
 505 {
 506         struct drm_device *drm = dev_get_drvdata(dev);
 507         struct drm_crtc *crtc;
 508
 509         if (pm_runtime_suspended(dev))
 510                 return 0;
 511
 512         drm_modeset_lock_all(drm);
 513         list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
 514                 hdlcd_crtc_suspend(crtc);
 515         drm_modeset_unlock_all(drm);
 516         return 0;
 517 }
 518
 519 static int __maybe_unused hdlcd_pm_resume(struct device *dev)
 520 {
 521         struct drm_device *drm = dev_get_drvdata(dev);
 522         struct drm_crtc *crtc;
 523
 524         if (!pm_runtime_suspended(dev))
 525                 return 0;
 526
 527         drm_modeset_lock_all(drm);
 528         list_for_each_entry(crtc, &drm->mode_config.crtc_list, head)
 529                 hdlcd_crtc_resume(crtc);
 530         drm_modeset_unlock_all(drm);
 531         return 0;
 532 }
 533
 534 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
 535
 536 static struct platform_driver hdlcd_platform_driver = {
 537         .probe          = hdlcd_probe,
 538         .remove         = hdlcd_remove,
 539         .driver = {
 540                 .name = "hdlcd",
 541                 .pm = &hdlcd_pm_ops,
 542                 .of_match_table = hdlcd_of_match,
 543         },
 544 };
 545
 546 module_platform_driver(hdlcd_platform_driver);
 547
 548 MODULE_AUTHOR("Liviu Dudau");
 549 MODULE_DESCRIPTION("ARM HDLCD DRM driver");
 550 MODULE_LICENSE("GPL v2");