drivers/iommu/mtk_iommu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015-2016 MediaTek Inc.
   4  * Author: Yong Wu <[email protected]>
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/bug.h>
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-direct.h>
  12 #include <linux/err.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/iommu.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/io-pgtable.h>
  18 #include <linux/list.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/pci.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regmap.h>
  28 #include <linux/slab.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/soc/mediatek/infracfg.h>
  31 #include <asm/barrier.h>
  32 #include <soc/mediatek/smi.h>
  33
  34 #include <dt-bindings/memory/mtk-memory-port.h>
  35
  36 #define REG_MMU_PT_BASE_ADDR                    0x000
  37
  38 #define REG_MMU_INVALIDATE                      0x020
  39 #define F_ALL_INVLD                             0x2
  40 #define F_MMU_INV_RANGE                         0x1
  41
  42 #define REG_MMU_INVLD_START_A                   0x024
  43 #define REG_MMU_INVLD_END_A                     0x028
  44
  45 #define REG_MMU_INV_SEL_GEN2                    0x02c
  46 #define REG_MMU_INV_SEL_GEN1                    0x038
  47 #define F_INVLD_EN0                             BIT(0)
  48 #define F_INVLD_EN1                             BIT(1)
  49
  50 #define REG_MMU_MISC_CTRL                       0x048
  51 #define F_MMU_IN_ORDER_WR_EN_MASK               (BIT(1) | BIT(17))
  52 #define F_MMU_STANDARD_AXI_MODE_MASK            (BIT(3) | BIT(19))
  53
  54 #define REG_MMU_DCM_DIS                         0x050
  55 #define F_MMU_DCM                               BIT(8)
  56
  57 #define REG_MMU_WR_LEN_CTRL                     0x054
  58 #define F_MMU_WR_THROT_DIS_MASK                 (BIT(5) | BIT(21))
  59
  60 #define REG_MMU_CTRL_REG                        0x110
  61 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR           (2 << 4)
  62 #define F_MMU_PREFETCH_RT_REPLACE_MOD           BIT(4)
  63 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173    (2 << 5)
  64
  65 #define REG_MMU_IVRP_PADDR                      0x114
  66
  67 #define REG_MMU_VLD_PA_RNG                      0x118
  68 #define F_MMU_VLD_PA_RNG(EA, SA)                (((EA) << 8) | (SA))
  69
  70 #define REG_MMU_INT_CONTROL0                    0x120
  71 #define F_L2_MULIT_HIT_EN                       BIT(0)
  72 #define F_TABLE_WALK_FAULT_INT_EN               BIT(1)
  73 #define F_PREETCH_FIFO_OVERFLOW_INT_EN          BIT(2)
  74 #define F_MISS_FIFO_OVERFLOW_INT_EN             BIT(3)
  75 #define F_PREFETCH_FIFO_ERR_INT_EN              BIT(5)
  76 #define F_MISS_FIFO_ERR_INT_EN                  BIT(6)
  77 #define F_INT_CLR_BIT                           BIT(12)
  78
  79 #define REG_MMU_INT_MAIN_CONTROL                0x124
  80                                                 /* mmu0 | mmu1 */
  81 #define F_INT_TRANSLATION_FAULT                 (BIT(0) | BIT(7))
  82 #define F_INT_MAIN_MULTI_HIT_FAULT              (BIT(1) | BIT(8))
  83 #define F_INT_INVALID_PA_FAULT                  (BIT(2) | BIT(9))
  84 #define F_INT_ENTRY_REPLACEMENT_FAULT           (BIT(3) | BIT(10))
  85 #define F_INT_TLB_MISS_FAULT                    (BIT(4) | BIT(11))
  86 #define F_INT_MISS_TRANSACTION_FIFO_FAULT       (BIT(5) | BIT(12))
  87 #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT    (BIT(6) | BIT(13))
  88
  89 #define REG_MMU_CPE_DONE                        0x12C
  90
  91 #define REG_MMU_FAULT_ST1                       0x134
  92 #define F_REG_MMU0_FAULT_MASK                   GENMASK(6, 0)
  93 #define F_REG_MMU1_FAULT_MASK                   GENMASK(13, 7)
  94
  95 #define REG_MMU0_FAULT_VA                       0x13c
  96 #define F_MMU_INVAL_VA_31_12_MASK               GENMASK(31, 12)
  97 #define F_MMU_INVAL_VA_34_32_MASK               GENMASK(11, 9)
  98 #define F_MMU_INVAL_PA_34_32_MASK               GENMASK(8, 6)
  99 #define F_MMU_FAULT_VA_WRITE_BIT                BIT(1)
 100 #define F_MMU_FAULT_VA_LAYER_BIT                BIT(0)
 101
 102 #define REG_MMU0_INVLD_PA                       0x140
 103 #define REG_MMU1_FAULT_VA                       0x144
 104 #define REG_MMU1_INVLD_PA                       0x148
 105 #define REG_MMU0_INT_ID                         0x150
 106 #define REG_MMU1_INT_ID                         0x154
 107 #define F_MMU_INT_ID_COMM_ID(a)                 (((a) >> 9) & 0x7)
 108 #define F_MMU_INT_ID_SUB_COMM_ID(a)             (((a) >> 7) & 0x3)
 109 #define F_MMU_INT_ID_COMM_ID_EXT(a)             (((a) >> 10) & 0x7)
 110 #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a)         (((a) >> 7) & 0x7)
 111 #define F_MMU_INT_ID_LARB_ID(a)                 (((a) >> 7) & 0x7)
 112 #define F_MMU_INT_ID_PORT_ID(a)                 (((a) >> 2) & 0x1f)
 113
 114 #define MTK_PROTECT_PA_ALIGN                    256
 115 #define MTK_IOMMU_BANK_SZ                       0x1000
 116
 117 #define PERICFG_IOMMU_1                         0x714
 118
 119 #define HAS_4GB_MODE                    BIT(0)
 120 /* HW will use the EMI clock if there isn't the "bclk". */
 121 #define HAS_BCLK                        BIT(1)
 122 #define HAS_VLD_PA_RNG                  BIT(2)
 123 #define RESET_AXI                       BIT(3)
 124 #define OUT_ORDER_WR_EN                 BIT(4)
 125 #define HAS_SUB_COMM_2BITS              BIT(5)
 126 #define HAS_SUB_COMM_3BITS              BIT(6)
 127 #define WR_THROT_EN                     BIT(7)
 128 #define HAS_LEGACY_IVRP_PADDR           BIT(8)
 129 #define IOVA_34_EN                      BIT(9)
 130 #define SHARE_PGTABLE                   BIT(10) /* 2 HW share pgtable */
 131 #define DCM_DISABLE                     BIT(11)
 132 #define STD_AXI_MODE                    BIT(12) /* For non MM iommu */
 133 /* 2 bits: iommu type */
 134 #define MTK_IOMMU_TYPE_MM               (0x0 << 13)
 135 #define MTK_IOMMU_TYPE_INFRA            (0x1 << 13)
 136 #define MTK_IOMMU_TYPE_MASK             (0x3 << 13)
 137 /* PM and clock always on. e.g. infra iommu */
 138 #define PM_CLK_AO                       BIT(15)
 139 #define IFA_IOMMU_PCIE_SUPPORT          BIT(16)
 140 #define PGTABLE_PA_35_EN                BIT(17)
 141
 142 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)        \
 143                                 ((((pdata)->flags) & (mask)) == (_x))
 144
 145 #define MTK_IOMMU_HAS_FLAG(pdata, _x)   MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, _x)
 146 #define MTK_IOMMU_IS_TYPE(pdata, _x)    MTK_IOMMU_HAS_FLAG_MASK(pdata, _x,\
 147                                                         MTK_IOMMU_TYPE_MASK)
 148
 149 #define MTK_INVALID_LARBID              MTK_LARB_NR_MAX
 150
 151 #define MTK_LARB_COM_MAX        8
 152 #define MTK_LARB_SUBCOM_MAX     8
 153
 154 #define MTK_IOMMU_GROUP_MAX     8
 155 #define MTK_IOMMU_BANK_MAX      5
 156
 157 enum mtk_iommu_plat {
 158         M4U_MT2712,
 159         M4U_MT6779,
 160         M4U_MT8167,
 161         M4U_MT8173,
 162         M4U_MT8183,
 163         M4U_MT8186,
 164         M4U_MT8192,
 165         M4U_MT8195,
 166 };
 167
 168 struct mtk_iommu_iova_region {
 169         dma_addr_t              iova_base;
 170         unsigned long long      size;
 171 };
 172
 173 struct mtk_iommu_suspend_reg {
 174         u32                     misc_ctrl;
 175         u32                     dcm_dis;
 176         u32                     ctrl_reg;
 177         u32                     vld_pa_rng;
 178         u32                     wr_len_ctrl;
 179
 180         u32                     int_control[MTK_IOMMU_BANK_MAX];
 181         u32                     int_main_control[MTK_IOMMU_BANK_MAX];
 182         u32                     ivrp_paddr[MTK_IOMMU_BANK_MAX];
 183 };
 184
 185 struct mtk_iommu_plat_data {
 186         enum mtk_iommu_plat     m4u_plat;
 187         u32                     flags;
 188         u32                     inv_sel_reg;
 189
 190         char                    *pericfg_comp_str;
 191         struct list_head        *hw_list;
 192         unsigned int            iova_region_nr;
 193         const struct mtk_iommu_iova_region      *iova_region;
 194
 195         u8                  banks_num;
 196         bool                banks_enable[MTK_IOMMU_BANK_MAX];
 197         unsigned int        banks_portmsk[MTK_IOMMU_BANK_MAX];
 198         unsigned char       larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
 199 };
 200
 201 struct mtk_iommu_bank_data {
 202         void __iomem                    *base;
 203         int                             irq;
 204         u8                              id;
 205         struct device                   *parent_dev;
 206         struct mtk_iommu_data           *parent_data;
 207         spinlock_t                      tlb_lock; /* lock for tlb range flush */
 208         struct mtk_iommu_domain         *m4u_dom; /* Each bank has a domain */
 209 };
 210
 211 struct mtk_iommu_data {
 212         struct device                   *dev;
 213         struct clk                      *bclk;
 214         phys_addr_t                     protect_base; /* protect memory base */
 215         struct mtk_iommu_suspend_reg    reg;
 216         struct iommu_group              *m4u_group[MTK_IOMMU_GROUP_MAX];
 217         bool                            enable_4GB;
 218
 219         struct iommu_device             iommu;
 220         const struct mtk_iommu_plat_data *plat_data;
 221         struct device                   *smicomm_dev;
 222
 223         struct mtk_iommu_bank_data      *bank;
 224
 225         struct dma_iommu_mapping        *mapping; /* For mtk_iommu_v1.c */
 226         struct regmap                   *pericfg;
 227
 228         struct mutex                    mutex; /* Protect m4u_group/m4u_dom above */
 229
 230         /*
 231          * In the sharing pgtable case, list data->list to the global list like m4ulist.
 232          * In the non-sharing pgtable case, list data->list to the itself hw_list_head.
 233          */
 234         struct list_head                *hw_list;
 235         struct list_head                hw_list_head;
 236         struct list_head                list;
 237         struct mtk_smi_larb_iommu       larb_imu[MTK_LARB_NR_MAX];
 238 };
 239
 240 struct mtk_iommu_domain {
 241         struct io_pgtable_cfg           cfg;
 242         struct io_pgtable_ops           *iop;
 243
 244         struct mtk_iommu_bank_data      *bank;
 245         struct iommu_domain             domain;
 246
 247         struct mutex                    mutex; /* Protect "data" in this structure */
 248 };
 249
 250 static int mtk_iommu_bind(struct device *dev)
 251 {
 252         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 253
 254         return component_bind_all(dev, &data->larb_imu);
 255 }
 256
 257 static void mtk_iommu_unbind(struct device *dev)
 258 {
 259         struct mtk_iommu_data *data = dev_get_drvdata(dev);
 260
 261         component_unbind_all(dev, &data->larb_imu);
 262 }
 263
 264 static const struct iommu_ops mtk_iommu_ops;
 265
 266 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid);
 267
 268 #define MTK_IOMMU_TLB_ADDR(iova) ({                                     \
 269         dma_addr_t _addr = iova;                                        \
 270         ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
 271 })
 272
 273 /*
 274  * In M4U 4GB mode, the physical address is remapped as below:
 275  *
 276  * CPU Physical address:
 277  * ====================
 278  *
 279  * 0      1G       2G     3G       4G     5G
 280  * |---A---|---B---|---C---|---D---|---E---|
 281  * +--I/O--+------------Memory-------------+
 282  *
 283  * IOMMU output physical address:
 284  *  =============================
 285  *
 286  *                                 4G      5G     6G      7G      8G
 287  *                                 |---E---|---B---|---C---|---D---|
 288  *                                 +------------Memory-------------+
 289  *
 290  * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
 291  * bit32 of the CPU physical address always is needed to set, and for Region
 292  * 'E', the CPU physical address keep as is.
 293  * Additionally, The iommu consumers always use the CPU phyiscal address.
 294  */
 295 #define MTK_IOMMU_4GB_MODE_REMAP_BASE    0x140000000UL
 296
 297 static LIST_HEAD(m4ulist);      /* List all the M4U HWs */
 298
 299 #define for_each_m4u(data, head)  list_for_each_entry(data, head, list)
 300
 301 static const struct mtk_iommu_iova_region single_domain[] = {
 302         {.iova_base = 0,                .size = SZ_4G},
 303 };
 304
 305 static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
 306         { .iova_base = 0x0,             .size = SZ_4G},         /* 0 ~ 4G */
 307         #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
 308         { .iova_base = SZ_4G,           .size = SZ_4G},         /* 4G ~ 8G */
 309         { .iova_base = SZ_4G * 2,       .size = SZ_4G},         /* 8G ~ 12G */
 310         { .iova_base = SZ_4G * 3,       .size = SZ_4G},         /* 12G ~ 16G */
 311
 312         { .iova_base = 0x240000000ULL,  .size = 0x4000000},     /* CCU0 */
 313         { .iova_base = 0x244000000ULL,  .size = 0x4000000},     /* CCU1 */
 314         #endif
 315 };
 316
 317 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
 318 static struct mtk_iommu_data *mtk_iommu_get_frst_data(struct list_head *hwlist)
 319 {
 320         return list_first_entry(hwlist, struct mtk_iommu_data, list);
 321 }
 322
 323 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
 324 {
 325         return container_of(dom, struct mtk_iommu_domain, domain);
 326 }
 327
 328 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
 329 {
 330         /* Tlb flush all always is in bank0. */
 331         struct mtk_iommu_bank_data *bank = &data->bank[0];
 332         void __iomem *base = bank->base;
 333         unsigned long flags;
 334
 335         spin_lock_irqsave(&bank->tlb_lock, flags);
 336         writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
 337         writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
 338         wmb(); /* Make sure the tlb flush all done */
 339         spin_unlock_irqrestore(&bank->tlb_lock, flags);
 340 }
 341
 342 static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
 343                                            struct mtk_iommu_bank_data *bank)
 344 {
 345         struct list_head *head = bank->parent_data->hw_list;
 346         struct mtk_iommu_bank_data *curbank;
 347         struct mtk_iommu_data *data;
 348         bool check_pm_status;
 349         unsigned long flags;
 350         void __iomem *base;
 351         int ret;
 352         u32 tmp;
 353
 354         for_each_m4u(data, head) {
 355                 /*
 356                  * To avoid resume the iommu device frequently when the iommu device
 357                  * is not active, it doesn't always call pm_runtime_get here, then tlb
 358                  * flush depends on the tlb flush all in the runtime resume.
 359                  *
 360                  * There are 2 special cases:
 361                  *
 362                  * Case1: The iommu dev doesn't have power domain but has bclk. This case
 363                  * should also avoid the tlb flush while the dev is not active to mute
 364                  * the tlb timeout log. like mt8173.
 365                  *
 366                  * Case2: The power/clock of infra iommu is always on, and it doesn't
 367                  * have the device link with the master devices. This case should avoid
 368                  * the PM status check.
 369                  */
 370                 check_pm_status = !MTK_IOMMU_HAS_FLAG(data->plat_data, PM_CLK_AO);
 371
 372                 if (check_pm_status) {
 373                         if (pm_runtime_get_if_in_use(data->dev) <= 0)
 374                                 continue;
 375                 }
 376
 377                 curbank = &data->bank[bank->id];
 378                 base = curbank->base;
 379
 380                 spin_lock_irqsave(&curbank->tlb_lock, flags);
 381                 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
 382                                base + data->plat_data->inv_sel_reg);
 383
 384                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
 385                 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
 386                                base + REG_MMU_INVLD_END_A);
 387                 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
 388
 389                 /* tlb sync */
 390                 ret = readl_poll_timeout_atomic(base + REG_MMU_CPE_DONE,
 391                                                 tmp, tmp != 0, 10, 1000);
 392
 393                 /* Clear the CPE status */
 394                 writel_relaxed(0, base + REG_MMU_CPE_DONE);
 395                 spin_unlock_irqrestore(&curbank->tlb_lock, flags);
 396
 397                 if (ret) {
 398                         dev_warn(data->dev,
 399                                  "Partial TLB flush timed out, falling back to full flush\n");
 400                         mtk_iommu_tlb_flush_all(data);
 401                 }
 402
 403                 if (check_pm_status)
 404                         pm_runtime_put(data->dev);
 405         }
 406 }
 407
 408 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
 409 {
 410         struct mtk_iommu_bank_data *bank = dev_id;
 411         struct mtk_iommu_data *data = bank->parent_data;
 412         struct mtk_iommu_domain *dom = bank->m4u_dom;
 413         unsigned int fault_larb = MTK_INVALID_LARBID, fault_port = 0, sub_comm = 0;
 414         u32 int_state, regval, va34_32, pa34_32;
 415         const struct mtk_iommu_plat_data *plat_data = data->plat_data;
 416         void __iomem *base = bank->base;
 417         u64 fault_iova, fault_pa;
 418         bool layer, write;
 419
 420         /* Read error info from registers */
 421         int_state = readl_relaxed(base + REG_MMU_FAULT_ST1);
 422         if (int_state & F_REG_MMU0_FAULT_MASK) {
 423                 regval = readl_relaxed(base + REG_MMU0_INT_ID);
 424                 fault_iova = readl_relaxed(base + REG_MMU0_FAULT_VA);
 425                 fault_pa = readl_relaxed(base + REG_MMU0_INVLD_PA);
 426         } else {
 427                 regval = readl_relaxed(base + REG_MMU1_INT_ID);
 428                 fault_iova = readl_relaxed(base + REG_MMU1_FAULT_VA);
 429                 fault_pa = readl_relaxed(base + REG_MMU1_INVLD_PA);
 430         }
 431         layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
 432         write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
 433         if (MTK_IOMMU_HAS_FLAG(plat_data, IOVA_34_EN)) {
 434                 va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
 435                 fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
 436                 fault_iova |= (u64)va34_32 << 32;
 437         }
 438         pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
 439         fault_pa |= (u64)pa34_32 << 32;
 440
 441         if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
 442                 fault_port = F_MMU_INT_ID_PORT_ID(regval);
 443                 if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
 444                         fault_larb = F_MMU_INT_ID_COMM_ID(regval);
 445                         sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
 446                 } else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
 447                         fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
 448                         sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
 449                 } else {
 450                         fault_larb = F_MMU_INT_ID_LARB_ID(regval);
 451                 }
 452                 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
 453         }
 454
 455         if (report_iommu_fault(&dom->domain, bank->parent_dev, fault_iova,
 456                                write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
 457                 dev_err_ratelimited(
 458                         bank->parent_dev,
 459                         "fault type=0x%x iova=0x%llx pa=0x%llx master=0x%x(larb=%d port=%d) layer=%d %s\n",
 460                         int_state, fault_iova, fault_pa, regval, fault_larb, fault_port,
 461                         layer, write ? "write" : "read");
 462         }
 463
 464         /* Interrupt clear */
 465         regval = readl_relaxed(base + REG_MMU_INT_CONTROL0);
 466         regval |= F_INT_CLR_BIT;
 467         writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
 468
 469         mtk_iommu_tlb_flush_all(data);
 470
 471         return IRQ_HANDLED;
 472 }
 473
 474 static unsigned int mtk_iommu_get_bank_id(struct device *dev,
 475                                           const struct mtk_iommu_plat_data *plat_data)
 476 {
 477         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 478         unsigned int i, portmsk = 0, bankid = 0;
 479
 480         if (plat_data->banks_num == 1)
 481                 return bankid;
 482
 483         for (i = 0; i < fwspec->num_ids; i++)
 484                 portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i]));
 485
 486         for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) {
 487                 if (!plat_data->banks_enable[i])
 488                         continue;
 489
 490                 if (portmsk & plat_data->banks_portmsk[i]) {
 491                         bankid = i;
 492                         break;
 493                 }
 494         }
 495         return bankid; /* default is 0 */
 496 }
 497
 498 static int mtk_iommu_get_iova_region_id(struct device *dev,
 499                                         const struct mtk_iommu_plat_data *plat_data)
 500 {
 501         const struct mtk_iommu_iova_region *rgn = plat_data->iova_region;
 502         const struct bus_dma_region *dma_rgn = dev->dma_range_map;
 503         int i, candidate = -1;
 504         dma_addr_t dma_end;
 505
 506         if (!dma_rgn || plat_data->iova_region_nr == 1)
 507                 return 0;
 508
 509         dma_end = dma_rgn->dma_start + dma_rgn->size - 1;
 510         for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) {
 511                 /* Best fit. */
 512                 if (dma_rgn->dma_start == rgn->iova_base &&
 513                     dma_end == rgn->iova_base + rgn->size - 1)
 514                         return i;
 515                 /* ok if it is inside this region. */
 516                 if (dma_rgn->dma_start >= rgn->iova_base &&
 517                     dma_end < rgn->iova_base + rgn->size)
 518                         candidate = i;
 519         }
 520
 521         if (candidate >= 0)
 522                 return candidate;
 523         dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n",
 524                 &dma_rgn->dma_start, dma_rgn->size);
 525         return -EINVAL;
 526 }
 527
 528 static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
 529                             bool enable, unsigned int regionid)
 530 {
 531         struct mtk_smi_larb_iommu    *larb_mmu;
 532         unsigned int                 larbid, portid;
 533         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 534         const struct mtk_iommu_iova_region *region;
 535         u32 peri_mmuen, peri_mmuen_msk;
 536         int i, ret = 0;
 537
 538         for (i = 0; i < fwspec->num_ids; ++i) {
 539                 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
 540                 portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
 541
 542                 if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
 543                         larb_mmu = &data->larb_imu[larbid];
 544
 545                         region = data->plat_data->iova_region + regionid;
 546                         larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
 547
 548                         dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n",
 549                                 enable ? "enable" : "disable", dev_name(larb_mmu->dev),
 550                                 portid, regionid, larb_mmu->bank[portid]);
 551
 552                         if (enable)
 553                                 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
 554                         else
 555                                 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
 556                 } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
 557                         peri_mmuen_msk = BIT(portid);
 558                         /* PCI dev has only one output id, enable the next writing bit for PCIe */
 559                         if (dev_is_pci(dev))
 560                                 peri_mmuen_msk |= BIT(portid + 1);
 561
 562                         peri_mmuen = enable ? peri_mmuen_msk : 0;
 563                         ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
 564                                                  peri_mmuen_msk, peri_mmuen);
 565                         if (ret)
 566                                 dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n",
 567                                         enable ? "enable" : "disable",
 568                                         dev_name(data->dev), peri_mmuen_msk, ret);
 569                 }
 570         }
 571         return ret;
 572 }
 573
 574 static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
 575                                      struct mtk_iommu_data *data,
 576                                      unsigned int region_id)
 577 {
 578         const struct mtk_iommu_iova_region *region;
 579         struct mtk_iommu_domain *m4u_dom;
 580
 581         /* Always use bank0 in sharing pgtable case */
 582         m4u_dom = data->bank[0].m4u_dom;
 583         if (m4u_dom) {
 584                 dom->iop = m4u_dom->iop;
 585                 dom->cfg = m4u_dom->cfg;
 586                 dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap;
 587                 goto update_iova_region;
 588         }
 589
 590         dom->cfg = (struct io_pgtable_cfg) {
 591                 .quirks = IO_PGTABLE_QUIRK_ARM_NS |
 592                         IO_PGTABLE_QUIRK_NO_PERMS |
 593                         IO_PGTABLE_QUIRK_ARM_MTK_EXT,
 594                 .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
 595                 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
 596                 .iommu_dev = data->dev,
 597         };
 598
 599         if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
 600                 dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
 601
 602         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
 603                 dom->cfg.oas = data->enable_4GB ? 33 : 32;
 604         else
 605                 dom->cfg.oas = 35;
 606
 607         dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
 608         if (!dom->iop) {
 609                 dev_err(data->dev, "Failed to alloc io pgtable\n");
 610                 return -EINVAL;
 611         }
 612
 613         /* Update our support page sizes bitmap */
 614         dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
 615
 616 update_iova_region:
 617         /* Update the iova region for this domain */
 618         region = data->plat_data->iova_region + region_id;
 619         dom->domain.geometry.aperture_start = region->iova_base;
 620         dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
 621         dom->domain.geometry.force_aperture = true;
 622         return 0;
 623 }
 624
 625 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
 626 {
 627         struct mtk_iommu_domain *dom;
 628
 629         if (type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_UNMANAGED)
 630                 return NULL;
 631
 632         dom = kzalloc(sizeof(*dom), GFP_KERNEL);
 633         if (!dom)
 634                 return NULL;
 635         mutex_init(&dom->mutex);
 636
 637         return &dom->domain;
 638 }
 639
 640 static void mtk_iommu_domain_free(struct iommu_domain *domain)
 641 {
 642         kfree(to_mtk_domain(domain));
 643 }
 644
 645 static int mtk_iommu_attach_device(struct iommu_domain *domain,
 646                                    struct device *dev)
 647 {
 648         struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata;
 649         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 650         struct list_head *hw_list = data->hw_list;
 651         struct device *m4udev = data->dev;
 652         struct mtk_iommu_bank_data *bank;
 653         unsigned int bankid;
 654         int ret, region_id;
 655
 656         region_id = mtk_iommu_get_iova_region_id(dev, data->plat_data);
 657         if (region_id < 0)
 658                 return region_id;
 659
 660         bankid = mtk_iommu_get_bank_id(dev, data->plat_data);
 661         mutex_lock(&dom->mutex);
 662         if (!dom->bank) {
 663                 /* Data is in the frstdata in sharing pgtable case. */
 664                 frstdata = mtk_iommu_get_frst_data(hw_list);
 665
 666                 ret = mtk_iommu_domain_finalise(dom, frstdata, region_id);
 667                 if (ret) {
 668                         mutex_unlock(&dom->mutex);
 669                         return -ENODEV;
 670                 }
 671                 dom->bank = &data->bank[bankid];
 672         }
 673         mutex_unlock(&dom->mutex);
 674
 675         mutex_lock(&data->mutex);
 676         bank = &data->bank[bankid];
 677         if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */
 678                 ret = pm_runtime_resume_and_get(m4udev);
 679                 if (ret < 0) {
 680                         dev_err(m4udev, "pm get fail(%d) in attach.\n", ret);
 681                         goto err_unlock;
 682                 }
 683
 684                 ret = mtk_iommu_hw_init(data, bankid);
 685                 if (ret) {
 686                         pm_runtime_put(m4udev);
 687                         goto err_unlock;
 688                 }
 689                 bank->m4u_dom = dom;
 690                 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
 691
 692                 pm_runtime_put(m4udev);
 693         }
 694         mutex_unlock(&data->mutex);
 695
 696         return mtk_iommu_config(data, dev, true, region_id);
 697
 698 err_unlock:
 699         mutex_unlock(&data->mutex);
 700         return ret;
 701 }
 702
 703 static void mtk_iommu_detach_device(struct iommu_domain *domain,
 704                                     struct device *dev)
 705 {
 706         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 707
 708         mtk_iommu_config(data, dev, false, 0);
 709 }
 710
 711 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
 712                          phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
 713 {
 714         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 715
 716         /* The "4GB mode" M4U physically can not use the lower remap of Dram. */
 717         if (dom->bank->parent_data->enable_4GB)
 718                 paddr |= BIT_ULL(32);
 719
 720         /* Synchronize with the tlb_lock */
 721         return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp);
 722 }
 723
 724 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
 725                               unsigned long iova, size_t size,
 726                               struct iommu_iotlb_gather *gather)
 727 {
 728         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 729
 730         iommu_iotlb_gather_add_range(gather, iova, size);
 731         return dom->iop->unmap(dom->iop, iova, size, gather);
 732 }
 733
 734 static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
 735 {
 736         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 737
 738         mtk_iommu_tlb_flush_all(dom->bank->parent_data);
 739 }
 740
 741 static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
 742                                  struct iommu_iotlb_gather *gather)
 743 {
 744         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 745         size_t length = gather->end - gather->start + 1;
 746
 747         mtk_iommu_tlb_flush_range_sync(gather->start, length, dom->bank);
 748 }
 749
 750 static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
 751                                size_t size)
 752 {
 753         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 754
 755         mtk_iommu_tlb_flush_range_sync(iova, size, dom->bank);
 756 }
 757
 758 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
 759                                           dma_addr_t iova)
 760 {
 761         struct mtk_iommu_domain *dom = to_mtk_domain(domain);
 762         phys_addr_t pa;
 763
 764         pa = dom->iop->iova_to_phys(dom->iop, iova);
 765         if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT) &&
 766             dom->bank->parent_data->enable_4GB &&
 767             pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
 768                 pa &= ~BIT_ULL(32);
 769
 770         return pa;
 771 }
 772
 773 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
 774 {
 775         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 776         struct mtk_iommu_data *data;
 777         struct device_link *link;
 778         struct device *larbdev;
 779         unsigned int larbid, larbidx, i;
 780
 781         if (!fwspec || fwspec->ops != &mtk_iommu_ops)
 782                 return ERR_PTR(-ENODEV); /* Not a iommu client device */
 783
 784         data = dev_iommu_priv_get(dev);
 785
 786         if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
 787                 return &data->iommu;
 788
 789         /*
 790          * Link the consumer device with the smi-larb device(supplier).
 791          * The device that connects with each a larb is a independent HW.
 792          * All the ports in each a device should be in the same larbs.
 793          */
 794         larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 795         if (larbid >= MTK_LARB_NR_MAX)
 796                 return ERR_PTR(-EINVAL);
 797
 798         for (i = 1; i < fwspec->num_ids; i++) {
 799                 larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]);
 800                 if (larbid != larbidx) {
 801                         dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
 802                                 larbid, larbidx);
 803                         return ERR_PTR(-EINVAL);
 804                 }
 805         }
 806         larbdev = data->larb_imu[larbid].dev;
 807         if (!larbdev)
 808                 return ERR_PTR(-EINVAL);
 809
 810         link = device_link_add(dev, larbdev,
 811                                DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
 812         if (!link)
 813                 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
 814         return &data->iommu;
 815 }
 816
 817 static void mtk_iommu_release_device(struct device *dev)
 818 {
 819         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 820         struct mtk_iommu_data *data;
 821         struct device *larbdev;
 822         unsigned int larbid;
 823
 824         data = dev_iommu_priv_get(dev);
 825         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
 826                 larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
 827                 larbdev = data->larb_imu[larbid].dev;
 828                 device_link_remove(dev, larbdev);
 829         }
 830 }
 831
 832 static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data)
 833 {
 834         unsigned int bankid;
 835
 836         /*
 837          * If the bank function is enabled, each bank is a iommu group/domain.
 838          * Otherwise, each iova region is a iommu group/domain.
 839          */
 840         bankid = mtk_iommu_get_bank_id(dev, plat_data);
 841         if (bankid)
 842                 return bankid;
 843
 844         return mtk_iommu_get_iova_region_id(dev, plat_data);
 845 }
 846
 847 static struct iommu_group *mtk_iommu_device_group(struct device *dev)
 848 {
 849         struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data;
 850         struct list_head *hw_list = c_data->hw_list;
 851         struct iommu_group *group;
 852         int groupid;
 853
 854         data = mtk_iommu_get_frst_data(hw_list);
 855         if (!data)
 856                 return ERR_PTR(-ENODEV);
 857
 858         groupid = mtk_iommu_get_group_id(dev, data->plat_data);
 859         if (groupid < 0)
 860                 return ERR_PTR(groupid);
 861
 862         mutex_lock(&data->mutex);
 863         group = data->m4u_group[groupid];
 864         if (!group) {
 865                 group = iommu_group_alloc();
 866                 if (!IS_ERR(group))
 867                         data->m4u_group[groupid] = group;
 868         } else {
 869                 iommu_group_ref_get(group);
 870         }
 871         mutex_unlock(&data->mutex);
 872         return group;
 873 }
 874
 875 static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
 876 {
 877         struct platform_device *m4updev;
 878
 879         if (args->args_count != 1) {
 880                 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
 881                         args->args_count);
 882                 return -EINVAL;
 883         }
 884
 885         if (!dev_iommu_priv_get(dev)) {
 886                 /* Get the m4u device */
 887                 m4updev = of_find_device_by_node(args->np);
 888                 if (WARN_ON(!m4updev))
 889                         return -EINVAL;
 890
 891                 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
 892         }
 893
 894         return iommu_fwspec_add_ids(dev, args->args, 1);
 895 }
 896
 897 static void mtk_iommu_get_resv_regions(struct device *dev,
 898                                        struct list_head *head)
 899 {
 900         struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
 901         unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i;
 902         const struct mtk_iommu_iova_region *resv, *curdom;
 903         struct iommu_resv_region *region;
 904         int prot = IOMMU_WRITE | IOMMU_READ;
 905
 906         if ((int)regionid < 0)
 907                 return;
 908         curdom = data->plat_data->iova_region + regionid;
 909         for (i = 0; i < data->plat_data->iova_region_nr; i++) {
 910                 resv = data->plat_data->iova_region + i;
 911
 912                 /* Only reserve when the region is inside the current domain */
 913                 if (resv->iova_base <= curdom->iova_base ||
 914                     resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
 915                         continue;
 916
 917                 region = iommu_alloc_resv_region(resv->iova_base, resv->size,
 918                                                  prot, IOMMU_RESV_RESERVED);
 919                 if (!region)
 920                         return;
 921
 922                 list_add_tail(&region->list, head);
 923         }
 924 }
 925
 926 static const struct iommu_ops mtk_iommu_ops = {
 927         .domain_alloc   = mtk_iommu_domain_alloc,
 928         .probe_device   = mtk_iommu_probe_device,
 929         .release_device = mtk_iommu_release_device,
 930         .device_group   = mtk_iommu_device_group,
 931         .of_xlate       = mtk_iommu_of_xlate,
 932         .get_resv_regions = mtk_iommu_get_resv_regions,
 933         .pgsize_bitmap  = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
 934         .owner          = THIS_MODULE,
 935         .default_domain_ops = &(const struct iommu_domain_ops) {
 936                 .attach_dev     = mtk_iommu_attach_device,
 937                 .detach_dev     = mtk_iommu_detach_device,
 938                 .map            = mtk_iommu_map,
 939                 .unmap          = mtk_iommu_unmap,
 940                 .flush_iotlb_all = mtk_iommu_flush_iotlb_all,
 941                 .iotlb_sync     = mtk_iommu_iotlb_sync,
 942                 .iotlb_sync_map = mtk_iommu_sync_map,
 943                 .iova_to_phys   = mtk_iommu_iova_to_phys,
 944                 .free           = mtk_iommu_domain_free,
 945         }
 946 };
 947
 948 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int bankid)
 949 {
 950         const struct mtk_iommu_bank_data *bankx = &data->bank[bankid];
 951         const struct mtk_iommu_bank_data *bank0 = &data->bank[0];
 952         u32 regval;
 953
 954         /*
 955          * Global control settings are in bank0. May re-init these global registers
 956          * since no sure if there is bank0 consumers.
 957          */
 958         if (data->plat_data->m4u_plat == M4U_MT8173) {
 959                 regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
 960                          F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
 961         } else {
 962                 regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);
 963                 regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
 964         }
 965         writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
 966
 967         if (data->enable_4GB &&
 968             MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
 969                 /*
 970                  * If 4GB mode is enabled, the validate PA range is from
 971                  * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
 972                  */
 973                 regval = F_MMU_VLD_PA_RNG(7, 4);
 974                 writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);
 975         }
 976         if (MTK_IOMMU_HAS_FLAG(data->plat_data, DCM_DISABLE))
 977                 writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);
 978         else
 979                 writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);
 980
 981         if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
 982                 /* write command throttling mode */
 983                 regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);
 984                 regval &= ~F_MMU_WR_THROT_DIS_MASK;
 985                 writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);
 986         }
 987
 988         if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
 989                 /* The register is called STANDARD_AXI_MODE in this case */
 990                 regval = 0;
 991         } else {
 992                 regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);
 993                 if (!MTK_IOMMU_HAS_FLAG(data->plat_data, STD_AXI_MODE))
 994                         regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
 995                 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
 996                         regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
 997         }
 998         writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);
 999
1000         /* Independent settings for each bank */
1001         regval = F_L2_MULIT_HIT_EN |
1002                 F_TABLE_WALK_FAULT_INT_EN |
1003                 F_PREETCH_FIFO_OVERFLOW_INT_EN |
1004                 F_MISS_FIFO_OVERFLOW_INT_EN |
1005                 F_PREFETCH_FIFO_ERR_INT_EN |
1006                 F_MISS_FIFO_ERR_INT_EN;
1007         writel_relaxed(regval, bankx->base + REG_MMU_INT_CONTROL0);
1008
1009         regval = F_INT_TRANSLATION_FAULT |
1010                 F_INT_MAIN_MULTI_HIT_FAULT |
1011                 F_INT_INVALID_PA_FAULT |
1012                 F_INT_ENTRY_REPLACEMENT_FAULT |
1013                 F_INT_TLB_MISS_FAULT |
1014                 F_INT_MISS_TRANSACTION_FIFO_FAULT |
1015                 F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
1016         writel_relaxed(regval, bankx->base + REG_MMU_INT_MAIN_CONTROL);
1017
1018         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
1019                 regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
1020         else
1021                 regval = lower_32_bits(data->protect_base) |
1022                          upper_32_bits(data->protect_base);
1023         writel_relaxed(regval, bankx->base + REG_MMU_IVRP_PADDR);
1024
1025         if (devm_request_irq(bankx->parent_dev, bankx->irq, mtk_iommu_isr, 0,
1026                              dev_name(bankx->parent_dev), (void *)bankx)) {
1027                 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR);
1028                 dev_err(bankx->parent_dev, "Failed @ IRQ-%d Request\n", bankx->irq);
1029                 return -ENODEV;
1030         }
1031
1032         return 0;
1033 }
1034
1035 static const struct component_master_ops mtk_iommu_com_ops = {
1036         .bind           = mtk_iommu_bind,
1037         .unbind         = mtk_iommu_unbind,
1038 };
1039
1040 static int mtk_iommu_mm_dts_parse(struct device *dev, struct component_match **match,
1041                                   struct mtk_iommu_data *data)
1042 {
1043         struct device_node *larbnode, *smicomm_node, *smi_subcomm_node;
1044         struct platform_device *plarbdev;
1045         struct device_link *link;
1046         int i, larb_nr, ret;
1047
1048         larb_nr = of_count_phandle_with_args(dev->of_node, "mediatek,larbs", NULL);
1049         if (larb_nr < 0)
1050                 return larb_nr;
1051
1052         for (i = 0; i < larb_nr; i++) {
1053                 u32 id;
1054
1055                 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
1056                 if (!larbnode)
1057                         return -EINVAL;
1058
1059                 if (!of_device_is_available(larbnode)) {
1060                         of_node_put(larbnode);
1061                         continue;
1062                 }
1063
1064                 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
1065                 if (ret)/* The id is consecutive if there is no this property */
1066                         id = i;
1067
1068                 plarbdev = of_find_device_by_node(larbnode);
1069                 if (!plarbdev) {
1070                         of_node_put(larbnode);
1071                         return -ENODEV;
1072                 }
1073                 if (!plarbdev->dev.driver) {
1074                         of_node_put(larbnode);
1075                         return -EPROBE_DEFER;
1076                 }
1077                 data->larb_imu[id].dev = &plarbdev->dev;
1078
1079                 component_match_add_release(dev, match, component_release_of,
1080                                             component_compare_of, larbnode);
1081         }
1082
1083         /* Get smi-(sub)-common dev from the last larb. */
1084         smi_subcomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
1085         if (!smi_subcomm_node)
1086                 return -EINVAL;
1087
1088         /*
1089          * It may have two level smi-common. the node is smi-sub-common if it
1090          * has a new mediatek,smi property. otherwise it is smi-commmon.
1091          */
1092         smicomm_node = of_parse_phandle(smi_subcomm_node, "mediatek,smi", 0);
1093         if (smicomm_node)
1094                 of_node_put(smi_subcomm_node);
1095         else
1096                 smicomm_node = smi_subcomm_node;
1097
1098         plarbdev = of_find_device_by_node(smicomm_node);
1099         of_node_put(smicomm_node);
1100         data->smicomm_dev = &plarbdev->dev;
1101
1102         link = device_link_add(data->smicomm_dev, dev,
1103                                DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1104         if (!link) {
1105                 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
1106                 return -EINVAL;
1107         }
1108         return 0;
1109 }
1110
1111 static int mtk_iommu_probe(struct platform_device *pdev)
1112 {
1113         struct mtk_iommu_data   *data;
1114         struct device           *dev = &pdev->dev;
1115         struct resource         *res;
1116         resource_size_t         ioaddr;
1117         struct component_match  *match = NULL;
1118         struct regmap           *infracfg;
1119         void                    *protect;
1120         int                     ret, banks_num, i = 0;
1121         u32                     val;
1122         char                    *p;
1123         struct mtk_iommu_bank_data *bank;
1124         void __iomem            *base;
1125
1126         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
1127         if (!data)
1128                 return -ENOMEM;
1129         data->dev = dev;
1130         data->plat_data = of_device_get_match_data(dev);
1131
1132         /* Protect memory. HW will access here while translation fault.*/
1133         protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
1134         if (!protect)
1135                 return -ENOMEM;
1136         data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
1137
1138         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
1139                 infracfg = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,infracfg");
1140                 if (IS_ERR(infracfg)) {
1141                         /*
1142                          * Legacy devicetrees will not specify a phandle to
1143                          * mediatek,infracfg: in that case, we use the older
1144                          * way to retrieve a syscon to infra.
1145                          *
1146                          * This is for retrocompatibility purposes only, hence
1147                          * no more compatibles shall be added to this.
1148                          */
1149                         switch (data->plat_data->m4u_plat) {
1150                         case M4U_MT2712:
1151                                 p = "mediatek,mt2712-infracfg";
1152                                 break;
1153                         case M4U_MT8173:
1154                                 p = "mediatek,mt8173-infracfg";
1155                                 break;
1156                         default:
1157                                 p = NULL;
1158                         }
1159
1160                         infracfg = syscon_regmap_lookup_by_compatible(p);
1161                         if (IS_ERR(infracfg))
1162                                 return PTR_ERR(infracfg);
1163                 }
1164
1165                 ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
1166                 if (ret)
1167                         return ret;
1168                 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
1169         }
1170
1171         banks_num = data->plat_data->banks_num;
1172         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1173         if (resource_size(res) < banks_num * MTK_IOMMU_BANK_SZ) {
1174                 dev_err(dev, "banknr %d. res %pR is not enough.\n", banks_num, res);
1175                 return -EINVAL;
1176         }
1177         base = devm_ioremap_resource(dev, res);
1178         if (IS_ERR(base))
1179                 return PTR_ERR(base);
1180         ioaddr = res->start;
1181
1182         data->bank = devm_kmalloc(dev, banks_num * sizeof(*data->bank), GFP_KERNEL);
1183         if (!data->bank)
1184                 return -ENOMEM;
1185
1186         do {
1187                 if (!data->plat_data->banks_enable[i])
1188                         continue;
1189                 bank = &data->bank[i];
1190                 bank->id = i;
1191                 bank->base = base + i * MTK_IOMMU_BANK_SZ;
1192                 bank->m4u_dom = NULL;
1193
1194                 bank->irq = platform_get_irq(pdev, i);
1195                 if (bank->irq < 0)
1196                         return bank->irq;
1197                 bank->parent_dev = dev;
1198                 bank->parent_data = data;
1199                 spin_lock_init(&bank->tlb_lock);
1200         } while (++i < banks_num);
1201
1202         if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
1203                 data->bclk = devm_clk_get(dev, "bclk");
1204                 if (IS_ERR(data->bclk))
1205                         return PTR_ERR(data->bclk);
1206         }
1207
1208         pm_runtime_enable(dev);
1209
1210         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1211                 ret = mtk_iommu_mm_dts_parse(dev, &match, data);
1212                 if (ret) {
1213                         dev_err_probe(dev, ret, "mm dts parse fail\n");
1214                         goto out_runtime_disable;
1215                 }
1216         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
1217                 p = data->plat_data->pericfg_comp_str;
1218                 data->pericfg = syscon_regmap_lookup_by_compatible(p);
1219                 if (IS_ERR(data->pericfg)) {
1220                         ret = PTR_ERR(data->pericfg);
1221                         goto out_runtime_disable;
1222                 }
1223         }
1224
1225         platform_set_drvdata(pdev, data);
1226         mutex_init(&data->mutex);
1227
1228         ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
1229                                      "mtk-iommu.%pa", &ioaddr);
1230         if (ret)
1231                 goto out_link_remove;
1232
1233         ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
1234         if (ret)
1235                 goto out_sysfs_remove;
1236
1237         if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE)) {
1238                 list_add_tail(&data->list, data->plat_data->hw_list);
1239                 data->hw_list = data->plat_data->hw_list;
1240         } else {
1241                 INIT_LIST_HEAD(&data->hw_list_head);
1242                 list_add_tail(&data->list, &data->hw_list_head);
1243                 data->hw_list = &data->hw_list_head;
1244         }
1245
1246         if (!iommu_present(&platform_bus_type)) {
1247                 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
1248                 if (ret)
1249                         goto out_list_del;
1250         }
1251
1252         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1253                 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
1254                 if (ret)
1255                         goto out_bus_set_null;
1256         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
1257                    MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) {
1258 #ifdef CONFIG_PCI
1259                 if (!iommu_present(&pci_bus_type)) {
1260                         ret = bus_set_iommu(&pci_bus_type, &mtk_iommu_ops);
1261                         if (ret) /* PCIe fail don't affect platform_bus. */
1262                                 goto out_list_del;
1263                 }
1264 #endif
1265         }
1266         return ret;
1267
1268 out_bus_set_null:
1269         bus_set_iommu(&platform_bus_type, NULL);
1270 out_list_del:
1271         list_del(&data->list);
1272         iommu_device_unregister(&data->iommu);
1273 out_sysfs_remove:
1274         iommu_device_sysfs_remove(&data->iommu);
1275 out_link_remove:
1276         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM))
1277                 device_link_remove(data->smicomm_dev, dev);
1278 out_runtime_disable:
1279         pm_runtime_disable(dev);
1280         return ret;
1281 }
1282
1283 static int mtk_iommu_remove(struct platform_device *pdev)
1284 {
1285         struct mtk_iommu_data *data = platform_get_drvdata(pdev);
1286         struct mtk_iommu_bank_data *bank;
1287         int i;
1288
1289         iommu_device_sysfs_remove(&data->iommu);
1290         iommu_device_unregister(&data->iommu);
1291
1292         list_del(&data->list);
1293
1294         if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
1295                 device_link_remove(data->smicomm_dev, &pdev->dev);
1296                 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
1297         } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
1298                    MTK_IOMMU_HAS_FLAG(data->plat_data, IFA_IOMMU_PCIE_SUPPORT)) {
1299 #ifdef CONFIG_PCI
1300                 bus_set_iommu(&pci_bus_type, NULL);
1301 #endif
1302         }
1303         pm_runtime_disable(&pdev->dev);
1304         for (i = 0; i < data->plat_data->banks_num; i++) {
1305                 bank = &data->bank[i];
1306                 if (!bank->m4u_dom)
1307                         continue;
1308                 devm_free_irq(&pdev->dev, bank->irq, bank);
1309         }
1310         return 0;
1311 }
1312
1313 static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
1314 {
1315         struct mtk_iommu_data *data = dev_get_drvdata(dev);
1316         struct mtk_iommu_suspend_reg *reg = &data->reg;
1317         void __iomem *base;
1318         int i = 0;
1319
1320         base = data->bank[i].base;
1321         reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
1322         reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
1323         reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
1324         reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
1325         reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
1326         do {
1327                 if (!data->plat_data->banks_enable[i])
1328                         continue;
1329                 base = data->bank[i].base;
1330                 reg->int_control[i] = readl_relaxed(base + REG_MMU_INT_CONTROL0);
1331                 reg->int_main_control[i] = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
1332                 reg->ivrp_paddr[i] = readl_relaxed(base + REG_MMU_IVRP_PADDR);
1333         } while (++i < data->plat_data->banks_num);
1334         clk_disable_unprepare(data->bclk);
1335         return 0;
1336 }
1337
1338 static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
1339 {
1340         struct mtk_iommu_data *data = dev_get_drvdata(dev);
1341         struct mtk_iommu_suspend_reg *reg = &data->reg;
1342         struct mtk_iommu_domain *m4u_dom;
1343         void __iomem *base;
1344         int ret, i = 0;
1345
1346         ret = clk_prepare_enable(data->bclk);
1347         if (ret) {
1348                 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
1349                 return ret;
1350         }
1351
1352         /*
1353          * Uppon first resume, only enable the clk and return, since the values of the
1354          * registers are not yet set.
1355          */
1356         if (!reg->wr_len_ctrl)
1357                 return 0;
1358
1359         base = data->bank[i].base;
1360         writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
1361         writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
1362         writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
1363         writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
1364         writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
1365         do {
1366                 m4u_dom = data->bank[i].m4u_dom;
1367                 if (!data->plat_data->banks_enable[i] || !m4u_dom)
1368                         continue;
1369                 base = data->bank[i].base;
1370                 writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
1371                 writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
1372                 writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
1373                 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
1374         } while (++i < data->plat_data->banks_num);
1375
1376         /*
1377          * Users may allocate dma buffer before they call pm_runtime_get,
1378          * in which case it will lack the necessary tlb flush.
1379          * Thus, make sure to update the tlb after each PM resume.
1380          */
1381         mtk_iommu_tlb_flush_all(data);
1382         return 0;
1383 }
1384
1385 static const struct dev_pm_ops mtk_iommu_pm_ops = {
1386         SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
1387         SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1388                                      pm_runtime_force_resume)
1389 };
1390
1391 static const struct mtk_iommu_plat_data mt2712_data = {
1392         .m4u_plat     = M4U_MT2712,
1393         .flags        = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
1394                         MTK_IOMMU_TYPE_MM,
1395         .hw_list      = &m4ulist,
1396         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1397         .iova_region  = single_domain,
1398         .banks_num    = 1,
1399         .banks_enable = {true},
1400         .iova_region_nr = ARRAY_SIZE(single_domain),
1401         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
1402 };
1403
1404 static const struct mtk_iommu_plat_data mt6779_data = {
1405         .m4u_plat      = M4U_MT6779,
1406         .flags         = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
1407                          MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
1408         .inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
1409         .banks_num    = 1,
1410         .banks_enable = {true},
1411         .iova_region   = single_domain,
1412         .iova_region_nr = ARRAY_SIZE(single_domain),
1413         .larbid_remap  = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
1414 };
1415
1416 static const struct mtk_iommu_plat_data mt8167_data = {
1417         .m4u_plat     = M4U_MT8167,
1418         .flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
1419         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1420         .banks_num    = 1,
1421         .banks_enable = {true},
1422         .iova_region  = single_domain,
1423         .iova_region_nr = ARRAY_SIZE(single_domain),
1424         .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
1425 };
1426
1427 static const struct mtk_iommu_plat_data mt8173_data = {
1428         .m4u_plat     = M4U_MT8173,
1429         .flags        = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
1430                         HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
1431         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1432         .banks_num    = 1,
1433         .banks_enable = {true},
1434         .iova_region  = single_domain,
1435         .iova_region_nr = ARRAY_SIZE(single_domain),
1436         .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
1437 };
1438
1439 static const struct mtk_iommu_plat_data mt8183_data = {
1440         .m4u_plat     = M4U_MT8183,
1441         .flags        = RESET_AXI | MTK_IOMMU_TYPE_MM,
1442         .inv_sel_reg  = REG_MMU_INV_SEL_GEN1,
1443         .banks_num    = 1,
1444         .banks_enable = {true},
1445         .iova_region  = single_domain,
1446         .iova_region_nr = ARRAY_SIZE(single_domain),
1447         .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
1448 };
1449
1450 static const struct mtk_iommu_plat_data mt8186_data_mm = {
1451         .m4u_plat       = M4U_MT8186,
1452         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1453                           WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1454         .larbid_remap   = {{0}, {1, MTK_INVALID_LARBID, 8}, {4}, {7}, {2}, {9, 11, 19, 20},
1455                            {MTK_INVALID_LARBID, 14, 16},
1456                            {MTK_INVALID_LARBID, 13, MTK_INVALID_LARBID, 17}},
1457         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1458         .banks_num      = 1,
1459         .banks_enable   = {true},
1460         .iova_region    = mt8192_multi_dom,
1461         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1462 };
1463
1464 static const struct mtk_iommu_plat_data mt8192_data = {
1465         .m4u_plat       = M4U_MT8192,
1466         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1467                           WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM,
1468         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1469         .banks_num      = 1,
1470         .banks_enable   = {true},
1471         .iova_region    = mt8192_multi_dom,
1472         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1473         .larbid_remap   = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
1474                            {0, 14, 16}, {0, 13, 18, 17}},
1475 };
1476
1477 static const struct mtk_iommu_plat_data mt8195_data_infra = {
1478         .m4u_plat         = M4U_MT8195,
1479         .flags            = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
1480                             MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT,
1481         .pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
1482         .inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
1483         .banks_num        = 5,
1484         .banks_enable     = {true, false, false, false, true},
1485         .banks_portmsk    = {[0] = GENMASK(19, 16),     /* PCIe */
1486                              [4] = GENMASK(31, 20),     /* USB */
1487                             },
1488         .iova_region      = single_domain,
1489         .iova_region_nr   = ARRAY_SIZE(single_domain),
1490 };
1491
1492 static const struct mtk_iommu_plat_data mt8195_data_vdo = {
1493         .m4u_plat       = M4U_MT8195,
1494         .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
1495                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1496         .hw_list        = &m4ulist,
1497         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1498         .banks_num      = 1,
1499         .banks_enable   = {true},
1500         .iova_region    = mt8192_multi_dom,
1501         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1502         .larbid_remap   = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
1503                            {13, 17, 15/* 17b */, 25}, {5}},
1504 };
1505
1506 static const struct mtk_iommu_plat_data mt8195_data_vpp = {
1507         .m4u_plat       = M4U_MT8195,
1508         .flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
1509                           WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
1510         .hw_list        = &m4ulist,
1511         .inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
1512         .banks_num      = 1,
1513         .banks_enable   = {true},
1514         .iova_region    = mt8192_multi_dom,
1515         .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
1516         .larbid_remap   = {{1}, {3},
1517                            {22, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 23},
1518                            {8}, {20}, {12},
1519                            /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
1520                            {14, 16, 29, 26, 30, 31, 18},
1521                            {4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
1522 };
1523
1524 static const struct of_device_id mtk_iommu_of_ids[] = {
1525         { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1526         { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1527         { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1528         { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1529         { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1530         { .compatible = "mediatek,mt8186-iommu-mm",    .data = &mt8186_data_mm}, /* mm: m4u */
1531         { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1532         { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
1533         { .compatible = "mediatek,mt8195-iommu-vdo",   .data = &mt8195_data_vdo},
1534         { .compatible = "mediatek,mt8195-iommu-vpp",   .data = &mt8195_data_vpp},
1535         {}
1536 };
1537
1538 static struct platform_driver mtk_iommu_driver = {
1539         .probe  = mtk_iommu_probe,
1540         .remove = mtk_iommu_remove,
1541         .driver = {
1542                 .name = "mtk-iommu",
1543                 .of_match_table = mtk_iommu_of_ids,
1544                 .pm = &mtk_iommu_pm_ops,
1545         }
1546 };
1547 module_platform_driver(mtk_iommu_driver);
1548
1549 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
1550 MODULE_LICENSE("GPL v2");