drivers/gpu/drm/sun4i/sun4i_frontend.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Free Electrons
   4  * Maxime Ripard <[email protected]>
   5  */
   6 #include <drm/drmP.h>
   7 #include <drm/drm_gem_cma_helper.h>
   8 #include <drm/drm_fb_cma_helper.h>
   9
  10 #include <linux/clk.h>
  11 #include <linux/component.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18
  19 #include "sun4i_drv.h"
  20 #include "sun4i_frontend.h"
  21
  22 static const u32 sun4i_frontend_vert_coef[32] = {
  23         0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
  24         0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
  25         0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
  26         0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
  27         0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
  28         0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
  29         0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
  30         0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
  31 };
  32
  33 static const u32 sun4i_frontend_horz_coef[64] = {
  34         0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
  35         0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
  36         0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09,
  37         0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f,
  38         0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12,
  39         0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18,
  40         0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e,
  41         0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23,
  42         0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29,
  43         0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e,
  44         0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33,
  45         0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37,
  46         0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b,
  47         0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e,
  48         0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40,
  49         0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42,
  50 };
  51
  52 /*
  53  * These coefficients are taken from the A33 BSP from Allwinner.
  54  *
  55  * The first three values of each row are coded as 13-bit signed fixed-point
  56  * numbers, with 10 bits for the fractional part. The fourth value is a
  57  * constant coded as a 14-bit signed fixed-point number with 4 bits for the
  58  * fractional part.
  59  *
  60  * The values in table order give the following colorspace translation:
  61  * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
  62  * R = 1.164 * Y + 1.596 * V - 222
  63  * B = 1.164 * Y + 2.018 * U + 276
  64  *
  65  * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255],
  66  * following the BT601 spec.
  67  */
  68 const u32 sunxi_bt601_yuv2rgb_coef[12] = {
  69         0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877,
  70         0x000004a7, 0x00000000, 0x00000662, 0x00003211,
  71         0x000004a7, 0x00000812, 0x00000000, 0x00002eb1,
  72 };
  73 EXPORT_SYMBOL(sunxi_bt601_yuv2rgb_coef);
  74
  75 static void sun4i_frontend_scaler_init(struct sun4i_frontend *frontend)
  76 {
  77         int i;
  78
  79         if (frontend->data->has_coef_access_ctrl)
  80                 regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
  81                                   SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL,
  82                                   SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL);
  83
  84         for (i = 0; i < 32; i++) {
  85                 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF0_REG(i),
  86                              sun4i_frontend_horz_coef[2 * i]);
  87                 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF0_REG(i),
  88                              sun4i_frontend_horz_coef[2 * i]);
  89                 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF1_REG(i),
  90                              sun4i_frontend_horz_coef[2 * i + 1]);
  91                 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF1_REG(i),
  92                              sun4i_frontend_horz_coef[2 * i + 1]);
  93                 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTCOEF_REG(i),
  94                              sun4i_frontend_vert_coef[i]);
  95                 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTCOEF_REG(i),
  96                              sun4i_frontend_vert_coef[i]);
  97         }
  98
  99         if (frontend->data->has_coef_rdy)
 100                 regmap_write_bits(frontend->regs,
 101                                   SUN4I_FRONTEND_FRM_CTRL_REG,
 102                                   SUN4I_FRONTEND_FRM_CTRL_COEF_RDY,
 103                                   SUN4I_FRONTEND_FRM_CTRL_COEF_RDY);
 104 }
 105
 106 int sun4i_frontend_init(struct sun4i_frontend *frontend)
 107 {
 108         return pm_runtime_get_sync(frontend->dev);
 109 }
 110 EXPORT_SYMBOL(sun4i_frontend_init);
 111
 112 void sun4i_frontend_exit(struct sun4i_frontend *frontend)
 113 {
 114         pm_runtime_put(frontend->dev);
 115 }
 116 EXPORT_SYMBOL(sun4i_frontend_exit);
 117
 118 static bool sun4i_frontend_format_chroma_requires_swap(uint32_t fmt)
 119 {
 120         switch (fmt) {
 121         case DRM_FORMAT_YVU411:
 122         case DRM_FORMAT_YVU420:
 123         case DRM_FORMAT_YVU422:
 124         case DRM_FORMAT_YVU444:
 125                 return true;
 126
 127         default:
 128                 return false;
 129         }
 130 }
 131
 132 static bool sun4i_frontend_format_supports_tiling(uint32_t fmt)
 133 {
 134         switch (fmt) {
 135         case DRM_FORMAT_NV12:
 136         case DRM_FORMAT_NV16:
 137         case DRM_FORMAT_NV21:
 138         case DRM_FORMAT_NV61:
 139         case DRM_FORMAT_YUV411:
 140         case DRM_FORMAT_YUV420:
 141         case DRM_FORMAT_YUV422:
 142         case DRM_FORMAT_YVU420:
 143         case DRM_FORMAT_YVU422:
 144         case DRM_FORMAT_YVU411:
 145                 return true;
 146
 147         default:
 148                 return false;
 149         }
 150 }
 151
 152 void sun4i_frontend_update_buffer(struct sun4i_frontend *frontend,
 153                                   struct drm_plane *plane)
 154 {
 155         struct drm_plane_state *state = plane->state;
 156         struct drm_framebuffer *fb = state->fb;
 157         unsigned int strides[3] = {};
 158
 159         dma_addr_t paddr;
 160         bool swap;
 161
 162         if (fb->modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) {
 163                 unsigned int width = state->src_w >> 16;
 164                 unsigned int offset;
 165
 166                 strides[0] = SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[0]);
 167
 168                 /*
 169                  * The X1 offset is the offset to the bottom-right point in the
 170                  * end tile, which is the final pixel (at offset width - 1)
 171                  * within the end tile (with a 32-byte mask).
 172                  */
 173                 offset = (width - 1) & (32 - 1);
 174
 175                 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF0_REG,
 176                              SUN4I_FRONTEND_TB_OFF_X1(offset));
 177
 178                 if (fb->format->num_planes > 1) {
 179                         strides[1] =
 180                                 SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[1]);
 181
 182                         regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF1_REG,
 183                                      SUN4I_FRONTEND_TB_OFF_X1(offset));
 184                 }
 185
 186                 if (fb->format->num_planes > 2) {
 187                         strides[2] =
 188                                 SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[2]);
 189
 190                         regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF2_REG,
 191                                      SUN4I_FRONTEND_TB_OFF_X1(offset));
 192                 }
 193         } else {
 194                 strides[0] = fb->pitches[0];
 195
 196                 if (fb->format->num_planes > 1)
 197                         strides[1] = fb->pitches[1];
 198
 199                 if (fb->format->num_planes > 2)
 200                         strides[2] = fb->pitches[2];
 201         }
 202
 203         /* Set the line width */
 204         DRM_DEBUG_DRIVER("Frontend stride: %d bytes\n", fb->pitches[0]);
 205         regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD0_REG,
 206                      strides[0]);
 207
 208         if (fb->format->num_planes > 1)
 209                 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD1_REG,
 210                              strides[1]);
 211
 212         if (fb->format->num_planes > 2)
 213                 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD2_REG,
 214                              strides[2]);
 215
 216         /* Some planar formats require chroma channel swapping by hand. */
 217         swap = sun4i_frontend_format_chroma_requires_swap(fb->format->format);
 218
 219         /* Set the physical address of the buffer in memory */
 220         paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
 221         paddr -= PHYS_OFFSET;
 222         DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &paddr);
 223         regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, paddr);
 224
 225         if (fb->format->num_planes > 1) {
 226                 paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 2 : 1);
 227                 paddr -= PHYS_OFFSET;
 228                 DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n", &paddr);
 229                 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG,
 230                              paddr);
 231         }
 232
 233         if (fb->format->num_planes > 2) {
 234                 paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 1 : 2);
 235                 paddr -= PHYS_OFFSET;
 236                 DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n", &paddr);
 237                 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG,
 238                              paddr);
 239         }
 240 }
 241 EXPORT_SYMBOL(sun4i_frontend_update_buffer);
 242
 243 static int
 244 sun4i_frontend_drm_format_to_input_fmt(const struct drm_format_info *format,
 245                                        u32 *val)
 246 {
 247         if (!format->is_yuv)
 248                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_RGB;
 249         else if (drm_format_info_is_yuv_sampling_411(format))
 250                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV411;
 251         else if (drm_format_info_is_yuv_sampling_420(format))
 252                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV420;
 253         else if (drm_format_info_is_yuv_sampling_422(format))
 254                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV422;
 255         else if (drm_format_info_is_yuv_sampling_444(format))
 256                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV444;
 257         else
 258                 return -EINVAL;
 259
 260         return 0;
 261 }
 262
 263 static int
 264 sun4i_frontend_drm_format_to_input_mode(const struct drm_format_info *format,
 265                                         uint64_t modifier, u32 *val)
 266 {
 267         bool tiled = (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED);
 268
 269         switch (format->num_planes) {
 270         case 1:
 271                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED;
 272                 return 0;
 273
 274         case 2:
 275                 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR
 276                              : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_SEMIPLANAR;
 277                 return 0;
 278
 279         case 3:
 280                 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR
 281                              : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PLANAR;
 282                 return 0;
 283
 284         default:
 285                 return -EINVAL;
 286         }
 287 }
 288
 289 static int
 290 sun4i_frontend_drm_format_to_input_sequence(const struct drm_format_info *format,
 291                                             u32 *val)
 292 {
 293         /* Planar formats have an explicit input sequence. */
 294         if (drm_format_info_is_yuv_planar(format)) {
 295                 *val = 0;
 296                 return 0;
 297         }
 298
 299         switch (format->format) {
 300         case DRM_FORMAT_BGRX8888:
 301                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_BGRX;
 302                 return 0;
 303
 304         case DRM_FORMAT_NV12:
 305                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV;
 306                 return 0;
 307
 308         case DRM_FORMAT_NV16:
 309                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV;
 310                 return 0;
 311
 312         case DRM_FORMAT_NV21:
 313                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU;
 314                 return 0;
 315
 316         case DRM_FORMAT_NV61:
 317                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU;
 318                 return 0;
 319
 320         case DRM_FORMAT_UYVY:
 321                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UYVY;
 322                 return 0;
 323
 324         case DRM_FORMAT_VYUY:
 325                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VYUY;
 326                 return 0;
 327
 328         case DRM_FORMAT_XRGB8888:
 329                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_XRGB;
 330                 return 0;
 331
 332         case DRM_FORMAT_YUYV:
 333                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YUYV;
 334                 return 0;
 335
 336         case DRM_FORMAT_YVYU:
 337                 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YVYU;
 338                 return 0;
 339
 340         default:
 341                 return -EINVAL;
 342         }
 343 }
 344
 345 static int sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt, u32 *val)
 346 {
 347         switch (fmt) {
 348         case DRM_FORMAT_BGRX8888:
 349                 *val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_BGRX8888;
 350                 return 0;
 351
 352         case DRM_FORMAT_XRGB8888:
 353                 *val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_XRGB8888;
 354                 return 0;
 355
 356         default:
 357                 return -EINVAL;
 358         }
 359 }
 360
 361 static const uint32_t sun4i_frontend_formats[] = {
 362         DRM_FORMAT_BGRX8888,
 363         DRM_FORMAT_NV12,
 364         DRM_FORMAT_NV16,
 365         DRM_FORMAT_NV21,
 366         DRM_FORMAT_NV61,
 367         DRM_FORMAT_UYVY,
 368         DRM_FORMAT_VYUY,
 369         DRM_FORMAT_XRGB8888,
 370         DRM_FORMAT_YUV411,
 371         DRM_FORMAT_YUV420,
 372         DRM_FORMAT_YUV422,
 373         DRM_FORMAT_YUV444,
 374         DRM_FORMAT_YUYV,
 375         DRM_FORMAT_YVU411,
 376         DRM_FORMAT_YVU420,
 377         DRM_FORMAT_YVU422,
 378         DRM_FORMAT_YVU444,
 379         DRM_FORMAT_YVYU,
 380 };
 381
 382 bool sun4i_frontend_format_is_supported(uint32_t fmt, uint64_t modifier)
 383 {
 384         unsigned int i;
 385
 386         if (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED)
 387                 return sun4i_frontend_format_supports_tiling(fmt);
 388         else if (modifier != DRM_FORMAT_MOD_LINEAR)
 389                 return false;
 390
 391         for (i = 0; i < ARRAY_SIZE(sun4i_frontend_formats); i++)
 392                 if (sun4i_frontend_formats[i] == fmt)
 393                         return true;
 394
 395         return false;
 396 }
 397 EXPORT_SYMBOL(sun4i_frontend_format_is_supported);
 398
 399 int sun4i_frontend_update_formats(struct sun4i_frontend *frontend,
 400                                   struct drm_plane *plane, uint32_t out_fmt)
 401 {
 402         struct drm_plane_state *state = plane->state;
 403         struct drm_framebuffer *fb = state->fb;
 404         const struct drm_format_info *format = fb->format;
 405         uint64_t modifier = fb->modifier;
 406         u32 out_fmt_val;
 407         u32 in_fmt_val, in_mod_val, in_ps_val;
 408         unsigned int i;
 409         u32 bypass;
 410         int ret;
 411
 412         ret = sun4i_frontend_drm_format_to_input_fmt(format, &in_fmt_val);
 413         if (ret) {
 414                 DRM_DEBUG_DRIVER("Invalid input format\n");
 415                 return ret;
 416         }
 417
 418         ret = sun4i_frontend_drm_format_to_input_mode(format, modifier,
 419                                                       &in_mod_val);
 420         if (ret) {
 421                 DRM_DEBUG_DRIVER("Invalid input mode\n");
 422                 return ret;
 423         }
 424
 425         ret = sun4i_frontend_drm_format_to_input_sequence(format, &in_ps_val);
 426         if (ret) {
 427                 DRM_DEBUG_DRIVER("Invalid pixel sequence\n");
 428                 return ret;
 429         }
 430
 431         ret = sun4i_frontend_drm_format_to_output_fmt(out_fmt, &out_fmt_val);
 432         if (ret) {
 433                 DRM_DEBUG_DRIVER("Invalid output format\n");
 434                 return ret;
 435         }
 436
 437         /*
 438          * I have no idea what this does exactly, but it seems to be
 439          * related to the scaler FIR filter phase parameters.
 440          */
 441         regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG,
 442                      frontend->data->ch_phase[0].horzphase);
 443         regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG,
 444                      frontend->data->ch_phase[1].horzphase);
 445         regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG,
 446                      frontend->data->ch_phase[0].vertphase[0]);
 447         regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG,
 448                      frontend->data->ch_phase[1].vertphase[0]);
 449         regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG,
 450                      frontend->data->ch_phase[0].vertphase[1]);
 451         regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG,
 452                      frontend->data->ch_phase[1].vertphase[1]);
 453
 454         /*
 455          * Checking the input format is sufficient since we currently only
 456          * support RGB output formats to the backend. If YUV output formats
 457          * ever get supported, an YUV input and output would require bypassing
 458          * the CSC engine too.
 459          */
 460         if (format->is_yuv) {
 461                 /* Setup the CSC engine for YUV to RGB conversion. */
 462                 bypass = 0;
 463
 464                 for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
 465                         regmap_write(frontend->regs,
 466                                      SUN4I_FRONTEND_CSC_COEF_REG(i),
 467                                      sunxi_bt601_yuv2rgb_coef[i]);
 468         } else {
 469                 bypass = SUN4I_FRONTEND_BYPASS_CSC_EN;
 470         }
 471
 472         regmap_update_bits(frontend->regs, SUN4I_FRONTEND_BYPASS_REG,
 473                            SUN4I_FRONTEND_BYPASS_CSC_EN, bypass);
 474
 475         regmap_write(frontend->regs, SUN4I_FRONTEND_INPUT_FMT_REG,
 476                      in_mod_val | in_fmt_val | in_ps_val);
 477
 478         /*
 479          * TODO: It look like the A31 and A80 at least will need the
 480          * bit 7 (ALPHA_EN) enabled when using a format with alpha (so
 481          * ARGB8888).
 482          */
 483         regmap_write(frontend->regs, SUN4I_FRONTEND_OUTPUT_FMT_REG,
 484                      out_fmt_val);
 485
 486         return 0;
 487 }
 488 EXPORT_SYMBOL(sun4i_frontend_update_formats);
 489
 490 void sun4i_frontend_update_coord(struct sun4i_frontend *frontend,
 491                                  struct drm_plane *plane)
 492 {
 493         struct drm_plane_state *state = plane->state;
 494         struct drm_framebuffer *fb = state->fb;
 495         uint32_t luma_width, luma_height;
 496         uint32_t chroma_width, chroma_height;
 497
 498         /* Set height and width */
 499         DRM_DEBUG_DRIVER("Frontend size W: %u H: %u\n",
 500                          state->crtc_w, state->crtc_h);
 501
 502         luma_width = state->src_w >> 16;
 503         luma_height = state->src_h >> 16;
 504
 505         chroma_width = DIV_ROUND_UP(luma_width, fb->format->hsub);
 506         chroma_height = DIV_ROUND_UP(luma_height, fb->format->vsub);
 507
 508         regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_INSIZE_REG,
 509                      SUN4I_FRONTEND_INSIZE(luma_height, luma_width));
 510         regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_INSIZE_REG,
 511                      SUN4I_FRONTEND_INSIZE(chroma_height, chroma_width));
 512
 513         regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_OUTSIZE_REG,
 514                      SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w));
 515         regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_OUTSIZE_REG,
 516                      SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w));
 517
 518         regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZFACT_REG,
 519                      (luma_width << 16) / state->crtc_w);
 520         regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZFACT_REG,
 521                      (chroma_width << 16) / state->crtc_w);
 522
 523         regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTFACT_REG,
 524                      (luma_height << 16) / state->crtc_h);
 525         regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTFACT_REG,
 526                      (chroma_height << 16) / state->crtc_h);
 527
 528         regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
 529                           SUN4I_FRONTEND_FRM_CTRL_REG_RDY,
 530                           SUN4I_FRONTEND_FRM_CTRL_REG_RDY);
 531 }
 532 EXPORT_SYMBOL(sun4i_frontend_update_coord);
 533
 534 int sun4i_frontend_enable(struct sun4i_frontend *frontend)
 535 {
 536         regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
 537                           SUN4I_FRONTEND_FRM_CTRL_FRM_START,
 538                           SUN4I_FRONTEND_FRM_CTRL_FRM_START);
 539
 540         return 0;
 541 }
 542 EXPORT_SYMBOL(sun4i_frontend_enable);
 543
 544 static struct regmap_config sun4i_frontend_regmap_config = {
 545         .reg_bits       = 32,
 546         .val_bits       = 32,
 547         .reg_stride     = 4,
 548         .max_register   = 0x0a14,
 549 };
 550
 551 static int sun4i_frontend_bind(struct device *dev, struct device *master,
 552                          void *data)
 553 {
 554         struct platform_device *pdev = to_platform_device(dev);
 555         struct sun4i_frontend *frontend;
 556         struct drm_device *drm = data;
 557         struct sun4i_drv *drv = drm->dev_private;
 558         struct resource *res;
 559         void __iomem *regs;
 560
 561         frontend = devm_kzalloc(dev, sizeof(*frontend), GFP_KERNEL);
 562         if (!frontend)
 563                 return -ENOMEM;
 564
 565         dev_set_drvdata(dev, frontend);
 566         frontend->dev = dev;
 567         frontend->node = dev->of_node;
 568
 569         frontend->data = of_device_get_match_data(dev);
 570         if (!frontend->data)
 571                 return -ENODEV;
 572
 573         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 574         regs = devm_ioremap_resource(dev, res);
 575         if (IS_ERR(regs))
 576                 return PTR_ERR(regs);
 577
 578         frontend->regs = devm_regmap_init_mmio(dev, regs,
 579                                                &sun4i_frontend_regmap_config);
 580         if (IS_ERR(frontend->regs)) {
 581                 dev_err(dev, "Couldn't create the frontend regmap\n");
 582                 return PTR_ERR(frontend->regs);
 583         }
 584
 585         frontend->reset = devm_reset_control_get(dev, NULL);
 586         if (IS_ERR(frontend->reset)) {
 587                 dev_err(dev, "Couldn't get our reset line\n");
 588                 return PTR_ERR(frontend->reset);
 589         }
 590
 591         frontend->bus_clk = devm_clk_get(dev, "ahb");
 592         if (IS_ERR(frontend->bus_clk)) {
 593                 dev_err(dev, "Couldn't get our bus clock\n");
 594                 return PTR_ERR(frontend->bus_clk);
 595         }
 596
 597         frontend->mod_clk = devm_clk_get(dev, "mod");
 598         if (IS_ERR(frontend->mod_clk)) {
 599                 dev_err(dev, "Couldn't get our mod clock\n");
 600                 return PTR_ERR(frontend->mod_clk);
 601         }
 602
 603         frontend->ram_clk = devm_clk_get(dev, "ram");
 604         if (IS_ERR(frontend->ram_clk)) {
 605                 dev_err(dev, "Couldn't get our ram clock\n");
 606                 return PTR_ERR(frontend->ram_clk);
 607         }
 608
 609         list_add_tail(&frontend->list, &drv->frontend_list);
 610         pm_runtime_enable(dev);
 611
 612         return 0;
 613 }
 614
 615 static void sun4i_frontend_unbind(struct device *dev, struct device *master,
 616                             void *data)
 617 {
 618         struct sun4i_frontend *frontend = dev_get_drvdata(dev);
 619
 620         list_del(&frontend->list);
 621         pm_runtime_force_suspend(dev);
 622 }
 623
 624 static const struct component_ops sun4i_frontend_ops = {
 625         .bind   = sun4i_frontend_bind,
 626         .unbind = sun4i_frontend_unbind,
 627 };
 628
 629 static int sun4i_frontend_probe(struct platform_device *pdev)
 630 {
 631         return component_add(&pdev->dev, &sun4i_frontend_ops);
 632 }
 633
 634 static int sun4i_frontend_remove(struct platform_device *pdev)
 635 {
 636         component_del(&pdev->dev, &sun4i_frontend_ops);
 637
 638         return 0;
 639 }
 640
 641 static int sun4i_frontend_runtime_resume(struct device *dev)
 642 {
 643         struct sun4i_frontend *frontend = dev_get_drvdata(dev);
 644         int ret;
 645
 646         clk_set_rate(frontend->mod_clk, 300000000);
 647
 648         clk_prepare_enable(frontend->bus_clk);
 649         clk_prepare_enable(frontend->mod_clk);
 650         clk_prepare_enable(frontend->ram_clk);
 651
 652         ret = reset_control_reset(frontend->reset);
 653         if (ret) {
 654                 dev_err(dev, "Couldn't reset our device\n");
 655                 return ret;
 656         }
 657
 658         regmap_update_bits(frontend->regs, SUN4I_FRONTEND_EN_REG,
 659                            SUN4I_FRONTEND_EN_EN,
 660                            SUN4I_FRONTEND_EN_EN);
 661
 662         sun4i_frontend_scaler_init(frontend);
 663
 664         return 0;
 665 }
 666
 667 static int sun4i_frontend_runtime_suspend(struct device *dev)
 668 {
 669         struct sun4i_frontend *frontend = dev_get_drvdata(dev);
 670
 671         clk_disable_unprepare(frontend->ram_clk);
 672         clk_disable_unprepare(frontend->mod_clk);
 673         clk_disable_unprepare(frontend->bus_clk);
 674
 675         reset_control_assert(frontend->reset);
 676
 677         return 0;
 678 }
 679
 680 static const struct dev_pm_ops sun4i_frontend_pm_ops = {
 681         .runtime_resume         = sun4i_frontend_runtime_resume,
 682         .runtime_suspend        = sun4i_frontend_runtime_suspend,
 683 };
 684
 685 static const struct sun4i_frontend_data sun4i_a10_frontend = {
 686         .ch_phase               = {
 687                 {
 688                         .horzphase = 0,
 689                         .vertphase = { 0, 0 },
 690                 },
 691                 {
 692                         .horzphase = 0xfc000,
 693                         .vertphase = { 0xfc000, 0xfc000 },
 694                 },
 695         },
 696         .has_coef_rdy           = true,
 697 };
 698
 699 static const struct sun4i_frontend_data sun8i_a33_frontend = {
 700         .ch_phase               = {
 701                 {
 702                         .horzphase = 0x400,
 703                         .vertphase = { 0x400, 0x400 },
 704                 },
 705                 {
 706                         .horzphase = 0x400,
 707                         .vertphase = { 0x400, 0x400 },
 708                 },
 709         },
 710         .has_coef_access_ctrl   = true,
 711 };
 712
 713 const struct of_device_id sun4i_frontend_of_table[] = {
 714         {
 715                 .compatible = "allwinner,sun4i-a10-display-frontend",
 716                 .data = &sun4i_a10_frontend
 717         },
 718         {
 719                 .compatible = "allwinner,sun7i-a20-display-frontend",
 720                 .data = &sun4i_a10_frontend
 721         },
 722         {
 723                 .compatible = "allwinner,sun8i-a23-display-frontend",
 724                 .data = &sun8i_a33_frontend
 725         },
 726         {
 727                 .compatible = "allwinner,sun8i-a33-display-frontend",
 728                 .data = &sun8i_a33_frontend
 729         },
 730         { }
 731 };
 732 EXPORT_SYMBOL(sun4i_frontend_of_table);
 733 MODULE_DEVICE_TABLE(of, sun4i_frontend_of_table);
 734
 735 static struct platform_driver sun4i_frontend_driver = {
 736         .probe          = sun4i_frontend_probe,
 737         .remove         = sun4i_frontend_remove,
 738         .driver         = {
 739                 .name           = "sun4i-frontend",
 740                 .of_match_table = sun4i_frontend_of_table,
 741                 .pm             = &sun4i_frontend_pm_ops,
 742         },
 743 };
 744 module_platform_driver(sun4i_frontend_driver);
 745
 746 MODULE_AUTHOR("Maxime Ripard <[email protected]>");
 747 MODULE_DESCRIPTION("Allwinner A10 Display Engine Frontend Driver");
 748 MODULE_LICENSE("GPL");