drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include "amdgpu.h"
  37 #include "amdgpu_trace.h"
  38
  39
  40 int amdgpu_ttm_init(struct amdgpu_device *adev);
  41 void amdgpu_ttm_fini(struct amdgpu_device *adev);
  42
  43 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
  44                                                 struct ttm_mem_reg *mem)
  45 {
  46         u64 ret = 0;
  47         if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) {
  48                 ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) >
  49                            adev->mc.visible_vram_size ?
  50                            adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
  51                            mem->size;
  52         }
  53         return ret;
  54 }
  55
  56 static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
  57                        struct ttm_mem_reg *old_mem,
  58                        struct ttm_mem_reg *new_mem)
  59 {
  60         u64 vis_size;
  61         if (!adev)
  62                 return;
  63
  64         if (new_mem) {
  65                 switch (new_mem->mem_type) {
  66                 case TTM_PL_TT:
  67                         atomic64_add(new_mem->size, &adev->gtt_usage);
  68                         break;
  69                 case TTM_PL_VRAM:
  70                         atomic64_add(new_mem->size, &adev->vram_usage);
  71                         vis_size = amdgpu_get_vis_part_size(adev, new_mem);
  72                         atomic64_add(vis_size, &adev->vram_vis_usage);
  73                         break;
  74                 }
  75         }
  76
  77         if (old_mem) {
  78                 switch (old_mem->mem_type) {
  79                 case TTM_PL_TT:
  80                         atomic64_sub(old_mem->size, &adev->gtt_usage);
  81                         break;
  82                 case TTM_PL_VRAM:
  83                         atomic64_sub(old_mem->size, &adev->vram_usage);
  84                         vis_size = amdgpu_get_vis_part_size(adev, old_mem);
  85                         atomic64_sub(vis_size, &adev->vram_vis_usage);
  86                         break;
  87                 }
  88         }
  89 }
  90
  91 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  92 {
  93         struct amdgpu_bo *bo;
  94
  95         bo = container_of(tbo, struct amdgpu_bo, tbo);
  96
  97         amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
  98
  99         mutex_lock(&bo->adev->gem.mutex);
 100         list_del_init(&bo->list);
 101         mutex_unlock(&bo->adev->gem.mutex);
 102         drm_gem_object_release(&bo->gem_base);
 103         amdgpu_bo_unref(&bo->parent);
 104         kfree(bo->metadata);
 105         kfree(bo);
 106 }
 107
 108 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 109 {
 110         if (bo->destroy == &amdgpu_ttm_bo_destroy)
 111                 return true;
 112         return false;
 113 }
 114
 115 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
 116                                       struct ttm_placement *placement,
 117                                       struct ttm_place *placements,
 118                                       u32 domain, u64 flags)
 119 {
 120         u32 c = 0, i;
 121
 122         placement->placement = placements;
 123         placement->busy_placement = placements;
 124
 125         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 126                 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
 127                         adev->mc.visible_vram_size < adev->mc.real_vram_size) {
 128                         placements[c].fpfn =
 129                                 adev->mc.visible_vram_size >> PAGE_SHIFT;
 130                         placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 131                                 TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN;
 132                 }
 133                 placements[c].fpfn = 0;
 134                 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 135                         TTM_PL_FLAG_VRAM;
 136                 if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))
 137                         placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN;
 138         }
 139
 140         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 141                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
 142                         placements[c].fpfn = 0;
 143                         placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
 144                                 TTM_PL_FLAG_UNCACHED;
 145                 } else {
 146                         placements[c].fpfn = 0;
 147                         placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
 148                 }
 149         }
 150
 151         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 152                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
 153                         placements[c].fpfn = 0;
 154                         placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM |
 155                                 TTM_PL_FLAG_UNCACHED;
 156                 } else {
 157                         placements[c].fpfn = 0;
 158                         placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
 159                 }
 160         }
 161
 162         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 163                 placements[c].fpfn = 0;
 164                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 165                         AMDGPU_PL_FLAG_GDS;
 166         }
 167         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 168                 placements[c].fpfn = 0;
 169                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 170                         AMDGPU_PL_FLAG_GWS;
 171         }
 172         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 173                 placements[c].fpfn = 0;
 174                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 175                         AMDGPU_PL_FLAG_OA;
 176         }
 177
 178         if (!c) {
 179                 placements[c].fpfn = 0;
 180                 placements[c++].flags = TTM_PL_MASK_CACHING |
 181                         TTM_PL_FLAG_SYSTEM;
 182         }
 183         placement->num_placement = c;
 184         placement->num_busy_placement = c;
 185
 186         for (i = 0; i < c; i++) {
 187                 if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 188                         (placements[i].flags & TTM_PL_FLAG_VRAM) &&
 189                         !placements[i].fpfn)
 190                         placements[i].lpfn =
 191                                 adev->mc.visible_vram_size >> PAGE_SHIFT;
 192                 else
 193                         placements[i].lpfn = 0;
 194         }
 195 }
 196
 197 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
 198 {
 199         amdgpu_ttm_placement_init(rbo->adev, &rbo->placement,
 200                                   rbo->placements, domain, rbo->flags);
 201 }
 202
 203 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
 204                                         struct ttm_placement *placement)
 205 {
 206         BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
 207
 208         memcpy(bo->placements, placement->placement,
 209                placement->num_placement * sizeof(struct ttm_place));
 210         bo->placement.num_placement = placement->num_placement;
 211         bo->placement.num_busy_placement = placement->num_busy_placement;
 212         bo->placement.placement = bo->placements;
 213         bo->placement.busy_placement = bo->placements;
 214 }
 215
 216 int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 217                                 unsigned long size, int byte_align,
 218                                 bool kernel, u32 domain, u64 flags,
 219                                 struct sg_table *sg,
 220                                 struct ttm_placement *placement,
 221                                 struct reservation_object *resv,
 222                                 struct amdgpu_bo **bo_ptr)
 223 {
 224         struct amdgpu_bo *bo;
 225         enum ttm_bo_type type;
 226         unsigned long page_align;
 227         size_t acc_size;
 228         int r;
 229
 230         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 231         size = ALIGN(size, PAGE_SIZE);
 232
 233         if (kernel) {
 234                 type = ttm_bo_type_kernel;
 235         } else if (sg) {
 236                 type = ttm_bo_type_sg;
 237         } else {
 238                 type = ttm_bo_type_device;
 239         }
 240         *bo_ptr = NULL;
 241
 242         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 243                                        sizeof(struct amdgpu_bo));
 244
 245         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 246         if (bo == NULL)
 247                 return -ENOMEM;
 248         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 249         if (unlikely(r)) {
 250                 kfree(bo);
 251                 return r;
 252         }
 253         bo->adev = adev;
 254         INIT_LIST_HEAD(&bo->list);
 255         INIT_LIST_HEAD(&bo->va);
 256         bo->initial_domain = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 257                                        AMDGPU_GEM_DOMAIN_GTT |
 258                                        AMDGPU_GEM_DOMAIN_CPU |
 259                                        AMDGPU_GEM_DOMAIN_GDS |
 260                                        AMDGPU_GEM_DOMAIN_GWS |
 261                                        AMDGPU_GEM_DOMAIN_OA);
 262
 263         bo->flags = flags;
 264         amdgpu_fill_placement_to_bo(bo, placement);
 265         /* Kernel allocation are uninterruptible */
 266         r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
 267                         &bo->placement, page_align, !kernel, NULL,
 268                         acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 269         if (unlikely(r != 0)) {
 270                 return r;
 271         }
 272         *bo_ptr = bo;
 273
 274         trace_amdgpu_bo_create(bo);
 275
 276         return 0;
 277 }
 278
 279 int amdgpu_bo_create(struct amdgpu_device *adev,
 280                      unsigned long size, int byte_align,
 281                      bool kernel, u32 domain, u64 flags,
 282                      struct sg_table *sg,
 283                      struct reservation_object *resv,
 284                      struct amdgpu_bo **bo_ptr)
 285 {
 286         struct ttm_placement placement = {0};
 287         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 288
 289         memset(&placements, 0,
 290                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 291
 292         amdgpu_ttm_placement_init(adev, &placement,
 293                                   placements, domain, flags);
 294
 295         return amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
 296                                            domain, flags, sg, &placement,
 297                                            resv, bo_ptr);
 298 }
 299
 300 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 301 {
 302         bool is_iomem;
 303         int r;
 304
 305         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 306                 return -EPERM;
 307
 308         if (bo->kptr) {
 309                 if (ptr) {
 310                         *ptr = bo->kptr;
 311                 }
 312                 return 0;
 313         }
 314         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 315         if (r) {
 316                 return r;
 317         }
 318         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 319         if (ptr) {
 320                 *ptr = bo->kptr;
 321         }
 322         return 0;
 323 }
 324
 325 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 326 {
 327         if (bo->kptr == NULL)
 328                 return;
 329         bo->kptr = NULL;
 330         ttm_bo_kunmap(&bo->kmap);
 331 }
 332
 333 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 334 {
 335         if (bo == NULL)
 336                 return NULL;
 337
 338         ttm_bo_reference(&bo->tbo);
 339         return bo;
 340 }
 341
 342 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 343 {
 344         struct ttm_buffer_object *tbo;
 345
 346         if ((*bo) == NULL)
 347                 return;
 348
 349         tbo = &((*bo)->tbo);
 350         ttm_bo_unref(&tbo);
 351         if (tbo == NULL)
 352                 *bo = NULL;
 353 }
 354
 355 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 356                              u64 min_offset, u64 max_offset,
 357                              u64 *gpu_addr)
 358 {
 359         int r, i;
 360         unsigned fpfn, lpfn;
 361
 362         if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm))
 363                 return -EPERM;
 364
 365         if (WARN_ON_ONCE(min_offset > max_offset))
 366                 return -EINVAL;
 367
 368         if (bo->pin_count) {
 369                 bo->pin_count++;
 370                 if (gpu_addr)
 371                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 372
 373                 if (max_offset != 0) {
 374                         u64 domain_start;
 375                         if (domain == AMDGPU_GEM_DOMAIN_VRAM)
 376                                 domain_start = bo->adev->mc.vram_start;
 377                         else
 378                                 domain_start = bo->adev->mc.gtt_start;
 379                         WARN_ON_ONCE(max_offset <
 380                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 381                 }
 382
 383                 return 0;
 384         }
 385         amdgpu_ttm_placement_from_domain(bo, domain);
 386         for (i = 0; i < bo->placement.num_placement; i++) {
 387                 /* force to pin into visible video ram */
 388                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 389                     !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
 390                     (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) {
 391                         if (WARN_ON_ONCE(min_offset >
 392                                          bo->adev->mc.visible_vram_size))
 393                                 return -EINVAL;
 394                         fpfn = min_offset >> PAGE_SHIFT;
 395                         lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
 396                 } else {
 397                         fpfn = min_offset >> PAGE_SHIFT;
 398                         lpfn = max_offset >> PAGE_SHIFT;
 399                 }
 400                 if (fpfn > bo->placements[i].fpfn)
 401                         bo->placements[i].fpfn = fpfn;
 402                 if (!bo->placements[i].lpfn ||
 403                     (lpfn && lpfn < bo->placements[i].lpfn))
 404                         bo->placements[i].lpfn = lpfn;
 405                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 406         }
 407
 408         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 409         if (likely(r == 0)) {
 410                 bo->pin_count = 1;
 411                 if (gpu_addr != NULL)
 412                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 413                 if (domain == AMDGPU_GEM_DOMAIN_VRAM)
 414                         bo->adev->vram_pin_size += amdgpu_bo_size(bo);
 415                 else
 416                         bo->adev->gart_pin_size += amdgpu_bo_size(bo);
 417         } else {
 418                 dev_err(bo->adev->dev, "%p pin failed\n", bo);
 419         }
 420         return r;
 421 }
 422
 423 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 424 {
 425         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 426 }
 427
 428 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 429 {
 430         int r, i;
 431
 432         if (!bo->pin_count) {
 433                 dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
 434                 return 0;
 435         }
 436         bo->pin_count--;
 437         if (bo->pin_count)
 438                 return 0;
 439         for (i = 0; i < bo->placement.num_placement; i++) {
 440                 bo->placements[i].lpfn = 0;
 441                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 442         }
 443         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 444         if (likely(r == 0)) {
 445                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 446                         bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
 447                 else
 448                         bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
 449         } else {
 450                 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
 451         }
 452         return r;
 453 }
 454
 455 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 456 {
 457         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 458         if (0 && (adev->flags & AMD_IS_APU)) {
 459                 /* Useless to evict on IGP chips */
 460                 return 0;
 461         }
 462         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 463 }
 464
 465 void amdgpu_bo_force_delete(struct amdgpu_device *adev)
 466 {
 467         struct amdgpu_bo *bo, *n;
 468
 469         if (list_empty(&adev->gem.objects)) {
 470                 return;
 471         }
 472         dev_err(adev->dev, "Userspace still has active objects !\n");
 473         list_for_each_entry_safe(bo, n, &adev->gem.objects, list) {
 474                 dev_err(adev->dev, "%p %p %lu %lu force free\n",
 475                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 476                         *((unsigned long *)&bo->gem_base.refcount));
 477                 mutex_lock(&bo->adev->gem.mutex);
 478                 list_del_init(&bo->list);
 479                 mutex_unlock(&bo->adev->gem.mutex);
 480                 /* this should unref the ttm bo */
 481                 drm_gem_object_unreference_unlocked(&bo->gem_base);
 482         }
 483 }
 484
 485 int amdgpu_bo_init(struct amdgpu_device *adev)
 486 {
 487         /* Add an MTRR for the VRAM */
 488         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 489                                               adev->mc.aper_size);
 490         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 491                 adev->mc.mc_vram_size >> 20,
 492                 (unsigned long long)adev->mc.aper_size >> 20);
 493         DRM_INFO("RAM width %dbits DDR\n",
 494                         adev->mc.vram_width);
 495         return amdgpu_ttm_init(adev);
 496 }
 497
 498 void amdgpu_bo_fini(struct amdgpu_device *adev)
 499 {
 500         amdgpu_ttm_fini(adev);
 501         arch_phys_wc_del(adev->mc.vram_mtrr);
 502 }
 503
 504 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 505                              struct vm_area_struct *vma)
 506 {
 507         return ttm_fbdev_mmap(vma, &bo->tbo);
 508 }
 509
 510 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 511 {
 512         if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 513                 return -EINVAL;
 514
 515         bo->tiling_flags = tiling_flags;
 516         return 0;
 517 }
 518
 519 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 520 {
 521         lockdep_assert_held(&bo->tbo.resv->lock.base);
 522
 523         if (tiling_flags)
 524                 *tiling_flags = bo->tiling_flags;
 525 }
 526
 527 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 528                             uint32_t metadata_size, uint64_t flags)
 529 {
 530         void *buffer;
 531
 532         if (!metadata_size) {
 533                 if (bo->metadata_size) {
 534                         kfree(bo->metadata);
 535                         bo->metadata_size = 0;
 536                 }
 537                 return 0;
 538         }
 539
 540         if (metadata == NULL)
 541                 return -EINVAL;
 542
 543         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 544         if (buffer == NULL)
 545                 return -ENOMEM;
 546
 547         kfree(bo->metadata);
 548         bo->metadata_flags = flags;
 549         bo->metadata = buffer;
 550         bo->metadata_size = metadata_size;
 551
 552         return 0;
 553 }
 554
 555 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 556                            size_t buffer_size, uint32_t *metadata_size,
 557                            uint64_t *flags)
 558 {
 559         if (!buffer && !metadata_size)
 560                 return -EINVAL;
 561
 562         if (buffer) {
 563                 if (buffer_size < bo->metadata_size)
 564                         return -EINVAL;
 565
 566                 if (bo->metadata_size)
 567                         memcpy(buffer, bo->metadata, bo->metadata_size);
 568         }
 569
 570         if (metadata_size)
 571                 *metadata_size = bo->metadata_size;
 572         if (flags)
 573                 *flags = bo->metadata_flags;
 574
 575         return 0;
 576 }
 577
 578 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 579                            struct ttm_mem_reg *new_mem)
 580 {
 581         struct amdgpu_bo *rbo;
 582
 583         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 584                 return;
 585
 586         rbo = container_of(bo, struct amdgpu_bo, tbo);
 587         amdgpu_vm_bo_invalidate(rbo->adev, rbo);
 588
 589         /* update statistics */
 590         if (!new_mem)
 591                 return;
 592
 593         /* move_notify is called before move happens */
 594         amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
 595 }
 596
 597 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 598 {
 599         struct amdgpu_device *adev;
 600         struct amdgpu_bo *abo;
 601         unsigned long offset, size, lpfn;
 602         int i, r;
 603
 604         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 605                 return 0;
 606
 607         abo = container_of(bo, struct amdgpu_bo, tbo);
 608         adev = abo->adev;
 609         if (bo->mem.mem_type != TTM_PL_VRAM)
 610                 return 0;
 611
 612         size = bo->mem.num_pages << PAGE_SHIFT;
 613         offset = bo->mem.start << PAGE_SHIFT;
 614         if ((offset + size) <= adev->mc.visible_vram_size)
 615                 return 0;
 616
 617         /* hurrah the memory is not visible ! */
 618         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
 619         lpfn =  adev->mc.visible_vram_size >> PAGE_SHIFT;
 620         for (i = 0; i < abo->placement.num_placement; i++) {
 621                 /* Force into visible VRAM */
 622                 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 623                     (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn))
 624                         abo->placements[i].lpfn = lpfn;
 625         }
 626         r = ttm_bo_validate(bo, &abo->placement, false, false);
 627         if (unlikely(r == -ENOMEM)) {
 628                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 629                 return ttm_bo_validate(bo, &abo->placement, false, false);
 630         } else if (unlikely(r != 0)) {
 631                 return r;
 632         }
 633
 634         offset = bo->mem.start << PAGE_SHIFT;
 635         /* this should never happen */
 636         if ((offset + size) > adev->mc.visible_vram_size)
 637                 return -EINVAL;
 638
 639         return 0;
 640 }
 641
 642 /**
 643  * amdgpu_bo_fence - add fence to buffer object
 644  *
 645  * @bo: buffer object in question
 646  * @fence: fence to add
 647  * @shared: true if fence should be added shared
 648  *
 649  */
 650 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
 651                      bool shared)
 652 {
 653         struct reservation_object *resv = bo->tbo.resv;
 654
 655         if (shared)
 656                 reservation_object_add_shared_fence(resv, fence);
 657         else
 658                 reservation_object_add_excl_fence(resv, fence);
 659 }