drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <[email protected]>,
   8  *          Sebastian Andrzej Siewior <[email protected]>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29 #include <linux/bitfield.h>
  30
  31 #include <linux/usb/ch9.h>
  32 #include <linux/usb/gadget.h>
  33 #include <linux/usb/of.h>
  34 #include <linux/usb/otg.h>
  35
  36 #include "core.h"
  37 #include "gadget.h"
  38 #include "io.h"
  39
  40 #include "debug.h"
  41
  42 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  43
  44 /**
  45  * dwc3_get_dr_mode - Validates and sets dr_mode
  46  * @dwc: pointer to our context structure
  47  */
  48 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  49 {
  50         enum usb_dr_mode mode;
  51         struct device *dev = dwc->dev;
  52         unsigned int hw_mode;
  53
  54         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  55                 dwc->dr_mode = USB_DR_MODE_OTG;
  56
  57         mode = dwc->dr_mode;
  58         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  59
  60         switch (hw_mode) {
  61         case DWC3_GHWPARAMS0_MODE_GADGET:
  62                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  63                         dev_err(dev,
  64                                 "Controller does not support host mode.\n");
  65                         return -EINVAL;
  66                 }
  67                 mode = USB_DR_MODE_PERIPHERAL;
  68                 break;
  69         case DWC3_GHWPARAMS0_MODE_HOST:
  70                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  71                         dev_err(dev,
  72                                 "Controller does not support device mode.\n");
  73                         return -EINVAL;
  74                 }
  75                 mode = USB_DR_MODE_HOST;
  76                 break;
  77         default:
  78                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  79                         mode = USB_DR_MODE_HOST;
  80                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  81                         mode = USB_DR_MODE_PERIPHERAL;
  82
  83                 /*
  84                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  85                  * mode. If the controller supports DRD but the dr_mode is not
  86                  * specified or set to OTG, then set the mode to peripheral.
  87                  */
  88                 if (mode == USB_DR_MODE_OTG &&
  89                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  90                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  91                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
  92                         mode = USB_DR_MODE_PERIPHERAL;
  93         }
  94
  95         if (mode != dwc->dr_mode) {
  96                 dev_warn(dev,
  97                          "Configuration mismatch. dr_mode forced to %s\n",
  98                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  99
 100                 dwc->dr_mode = mode;
 101         }
 102
 103         return 0;
 104 }
 105
 106 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 107 {
 108         u32 reg;
 109
 110         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 111         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 112         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 113         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 114
 115         dwc->current_dr_role = mode;
 116 }
 117
 118 static void __dwc3_set_mode(struct work_struct *work)
 119 {
 120         struct dwc3 *dwc = work_to_dwc(work);
 121         unsigned long flags;
 122         int ret;
 123         u32 reg;
 124
 125         mutex_lock(&dwc->mutex);
 126
 127         pm_runtime_get_sync(dwc->dev);
 128
 129         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 130                 dwc3_otg_update(dwc, 0);
 131
 132         if (!dwc->desired_dr_role)
 133                 goto out;
 134
 135         if (dwc->desired_dr_role == dwc->current_dr_role)
 136                 goto out;
 137
 138         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 139                 goto out;
 140
 141         switch (dwc->current_dr_role) {
 142         case DWC3_GCTL_PRTCAP_HOST:
 143                 dwc3_host_exit(dwc);
 144                 break;
 145         case DWC3_GCTL_PRTCAP_DEVICE:
 146                 dwc3_gadget_exit(dwc);
 147                 dwc3_event_buffers_cleanup(dwc);
 148                 break;
 149         case DWC3_GCTL_PRTCAP_OTG:
 150                 dwc3_otg_exit(dwc);
 151                 spin_lock_irqsave(&dwc->lock, flags);
 152                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 153                 spin_unlock_irqrestore(&dwc->lock, flags);
 154                 dwc3_otg_update(dwc, 1);
 155                 break;
 156         default:
 157                 break;
 158         }
 159
 160         /*
 161          * When current_dr_role is not set, there's no role switching.
 162          * Only perform GCTL.CoreSoftReset when there's DRD role switching.
 163          */
 164         if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
 165                         DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
 166                         dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
 167                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 168                 reg |= DWC3_GCTL_CORESOFTRESET;
 169                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 170
 171                 /*
 172                  * Wait for internal clocks to synchronized. DWC_usb31 and
 173                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 174                  * keep it consistent across different IPs, let's wait up to
 175                  * 100ms before clearing GCTL.CORESOFTRESET.
 176                  */
 177                 msleep(100);
 178
 179                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 180                 reg &= ~DWC3_GCTL_CORESOFTRESET;
 181                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 182         }
 183
 184         spin_lock_irqsave(&dwc->lock, flags);
 185
 186         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 187
 188         spin_unlock_irqrestore(&dwc->lock, flags);
 189
 190         switch (dwc->desired_dr_role) {
 191         case DWC3_GCTL_PRTCAP_HOST:
 192                 ret = dwc3_host_init(dwc);
 193                 if (ret) {
 194                         dev_err(dwc->dev, "failed to initialize host\n");
 195                 } else {
 196                         if (dwc->usb2_phy)
 197                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 198                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 199                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 200                         if (dwc->dis_split_quirk) {
 201                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 202                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
 203                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 204                         }
 205                 }
 206                 break;
 207         case DWC3_GCTL_PRTCAP_DEVICE:
 208                 dwc3_core_soft_reset(dwc);
 209
 210                 dwc3_event_buffers_setup(dwc);
 211
 212                 if (dwc->usb2_phy)
 213                         otg_set_vbus(dwc->usb2_phy->otg, false);
 214                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 215                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 216
 217                 ret = dwc3_gadget_init(dwc);
 218                 if (ret)
 219                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 220                 break;
 221         case DWC3_GCTL_PRTCAP_OTG:
 222                 dwc3_otg_init(dwc);
 223                 dwc3_otg_update(dwc, 0);
 224                 break;
 225         default:
 226                 break;
 227         }
 228
 229 out:
 230         pm_runtime_mark_last_busy(dwc->dev);
 231         pm_runtime_put_autosuspend(dwc->dev);
 232         mutex_unlock(&dwc->mutex);
 233 }
 234
 235 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 236 {
 237         unsigned long flags;
 238
 239         if (dwc->dr_mode != USB_DR_MODE_OTG)
 240                 return;
 241
 242         spin_lock_irqsave(&dwc->lock, flags);
 243         dwc->desired_dr_role = mode;
 244         spin_unlock_irqrestore(&dwc->lock, flags);
 245
 246         queue_work(system_freezable_wq, &dwc->drd_work);
 247 }
 248
 249 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 250 {
 251         struct dwc3             *dwc = dep->dwc;
 252         u32                     reg;
 253
 254         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 255                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 256                         DWC3_GDBGFIFOSPACE_TYPE(type));
 257
 258         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 259
 260         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 261 }
 262
 263 /**
 264  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 265  * @dwc: pointer to our context structure
 266  */
 267 int dwc3_core_soft_reset(struct dwc3 *dwc)
 268 {
 269         u32             reg;
 270         int             retries = 1000;
 271
 272         /*
 273          * We're resetting only the device side because, if we're in host mode,
 274          * XHCI driver will reset the host block. If dwc3 was configured for
 275          * host-only mode, then we can return early.
 276          */
 277         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 278                 return 0;
 279
 280         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 281         reg |= DWC3_DCTL_CSFTRST;
 282         reg &= ~DWC3_DCTL_RUN_STOP;
 283         dwc3_gadget_dctl_write_safe(dwc, reg);
 284
 285         /*
 286          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 287          * is cleared only after all the clocks are synchronized. This can
 288          * take a little more than 50ms. Set the polling rate at 20ms
 289          * for 10 times instead.
 290          */
 291         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 292                 retries = 10;
 293
 294         do {
 295                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 296                 if (!(reg & DWC3_DCTL_CSFTRST))
 297                         goto done;
 298
 299                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 300                         msleep(20);
 301                 else
 302                         udelay(1);
 303         } while (--retries);
 304
 305         dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
 306         return -ETIMEDOUT;
 307
 308 done:
 309         /*
 310          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 311          * is cleared, we must wait at least 50ms before accessing the PHY
 312          * domain (synchronization delay).
 313          */
 314         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 315                 msleep(50);
 316
 317         return 0;
 318 }
 319
 320 /*
 321  * dwc3_frame_length_adjustment - Adjusts frame length if required
 322  * @dwc3: Pointer to our controller context structure
 323  */
 324 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 325 {
 326         u32 reg;
 327         u32 dft;
 328
 329         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 330                 return;
 331
 332         if (dwc->fladj == 0)
 333                 return;
 334
 335         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 336         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 337         if (dft != dwc->fladj) {
 338                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 339                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 340                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 341         }
 342 }
 343
 344 /**
 345  * dwc3_ref_clk_period - Reference clock period configuration
 346  *              Default reference clock period depends on hardware
 347  *              configuration. For systems with reference clock that differs
 348  *              from the default, this will set clock period in DWC3_GUCTL
 349  *              register.
 350  * @dwc: Pointer to our controller context structure
 351  */
 352 static void dwc3_ref_clk_period(struct dwc3 *dwc)
 353 {
 354         unsigned long period;
 355         unsigned long fladj;
 356         unsigned long decr;
 357         unsigned long rate;
 358         u32 reg;
 359
 360         if (dwc->ref_clk) {
 361                 rate = clk_get_rate(dwc->ref_clk);
 362                 if (!rate)
 363                         return;
 364                 period = NSEC_PER_SEC / rate;
 365         } else if (dwc->ref_clk_per) {
 366                 period = dwc->ref_clk_per;
 367                 rate = NSEC_PER_SEC / period;
 368         } else {
 369                 return;
 370         }
 371
 372         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 373         reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
 374         reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
 375         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 376
 377         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 378                 return;
 379
 380         /*
 381          * The calculation below is
 382          *
 383          * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
 384          *
 385          * but rearranged for fixed-point arithmetic. The division must be
 386          * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
 387          * neither does rate * period).
 388          *
 389          * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
 390          * nanoseconds of error caused by the truncation which happened during
 391          * the division when calculating rate or period (whichever one was
 392          * derived from the other). We first calculate the relative error, then
 393          * scale it to units of 8 ppm.
 394          */
 395         fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
 396         fladj -= 125000;
 397
 398         /*
 399          * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
 400          */
 401         decr = 480000000 / rate;
 402
 403         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 404         reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
 405             &  ~DWC3_GFLADJ_240MHZDECR
 406             &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
 407         reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
 408             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
 409             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
 410
 411         if (dwc->gfladj_refclk_lpm_sel)
 412                 reg |=  DWC3_GFLADJ_REFCLK_LPM_SEL;
 413
 414         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 415 }
 416
 417 /**
 418  * dwc3_free_one_event_buffer - Frees one event buffer
 419  * @dwc: Pointer to our controller context structure
 420  * @evt: Pointer to event buffer to be freed
 421  */
 422 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 423                 struct dwc3_event_buffer *evt)
 424 {
 425         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 426 }
 427
 428 /**
 429  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 430  * @dwc: Pointer to our controller context structure
 431  * @length: size of the event buffer
 432  *
 433  * Returns a pointer to the allocated event buffer structure on success
 434  * otherwise ERR_PTR(errno).
 435  */
 436 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 437                 unsigned int length)
 438 {
 439         struct dwc3_event_buffer        *evt;
 440
 441         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 442         if (!evt)
 443                 return ERR_PTR(-ENOMEM);
 444
 445         evt->dwc        = dwc;
 446         evt->length     = length;
 447         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 448         if (!evt->cache)
 449                 return ERR_PTR(-ENOMEM);
 450
 451         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 452                         &evt->dma, GFP_KERNEL);
 453         if (!evt->buf)
 454                 return ERR_PTR(-ENOMEM);
 455
 456         return evt;
 457 }
 458
 459 /**
 460  * dwc3_free_event_buffers - frees all allocated event buffers
 461  * @dwc: Pointer to our controller context structure
 462  */
 463 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 464 {
 465         struct dwc3_event_buffer        *evt;
 466
 467         evt = dwc->ev_buf;
 468         if (evt)
 469                 dwc3_free_one_event_buffer(dwc, evt);
 470 }
 471
 472 /**
 473  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 474  * @dwc: pointer to our controller context structure
 475  * @length: size of event buffer
 476  *
 477  * Returns 0 on success otherwise negative errno. In the error case, dwc
 478  * may contain some buffers allocated but not all which were requested.
 479  */
 480 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
 481 {
 482         struct dwc3_event_buffer *evt;
 483
 484         evt = dwc3_alloc_one_event_buffer(dwc, length);
 485         if (IS_ERR(evt)) {
 486                 dev_err(dwc->dev, "can't allocate event buffer\n");
 487                 return PTR_ERR(evt);
 488         }
 489         dwc->ev_buf = evt;
 490
 491         return 0;
 492 }
 493
 494 /**
 495  * dwc3_event_buffers_setup - setup our allocated event buffers
 496  * @dwc: pointer to our controller context structure
 497  *
 498  * Returns 0 on success otherwise negative errno.
 499  */
 500 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 501 {
 502         struct dwc3_event_buffer        *evt;
 503
 504         evt = dwc->ev_buf;
 505         evt->lpos = 0;
 506         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 507                         lower_32_bits(evt->dma));
 508         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 509                         upper_32_bits(evt->dma));
 510         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 511                         DWC3_GEVNTSIZ_SIZE(evt->length));
 512         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 513
 514         return 0;
 515 }
 516
 517 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 518 {
 519         struct dwc3_event_buffer        *evt;
 520
 521         evt = dwc->ev_buf;
 522
 523         evt->lpos = 0;
 524
 525         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 526         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 527         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 528                         | DWC3_GEVNTSIZ_SIZE(0));
 529         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 530 }
 531
 532 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 533 {
 534         if (!dwc->has_hibernation)
 535                 return 0;
 536
 537         if (!dwc->nr_scratch)
 538                 return 0;
 539
 540         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 541                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 542         if (!dwc->scratchbuf)
 543                 return -ENOMEM;
 544
 545         return 0;
 546 }
 547
 548 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 549 {
 550         dma_addr_t scratch_addr;
 551         u32 param;
 552         int ret;
 553
 554         if (!dwc->has_hibernation)
 555                 return 0;
 556
 557         if (!dwc->nr_scratch)
 558                 return 0;
 559
 560          /* should never fall here */
 561         if (!WARN_ON(dwc->scratchbuf))
 562                 return 0;
 563
 564         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 565                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 566                         DMA_BIDIRECTIONAL);
 567         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 568                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 569                 ret = -EFAULT;
 570                 goto err0;
 571         }
 572
 573         dwc->scratch_addr = scratch_addr;
 574
 575         param = lower_32_bits(scratch_addr);
 576
 577         ret = dwc3_send_gadget_generic_command(dwc,
 578                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 579         if (ret < 0)
 580                 goto err1;
 581
 582         param = upper_32_bits(scratch_addr);
 583
 584         ret = dwc3_send_gadget_generic_command(dwc,
 585                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 586         if (ret < 0)
 587                 goto err1;
 588
 589         return 0;
 590
 591 err1:
 592         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 593                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 594
 595 err0:
 596         return ret;
 597 }
 598
 599 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 600 {
 601         if (!dwc->has_hibernation)
 602                 return;
 603
 604         if (!dwc->nr_scratch)
 605                 return;
 606
 607          /* should never fall here */
 608         if (!WARN_ON(dwc->scratchbuf))
 609                 return;
 610
 611         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 612                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 613         kfree(dwc->scratchbuf);
 614 }
 615
 616 static void dwc3_core_num_eps(struct dwc3 *dwc)
 617 {
 618         struct dwc3_hwparams    *parms = &dwc->hwparams;
 619
 620         dwc->num_eps = DWC3_NUM_EPS(parms);
 621 }
 622
 623 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 624 {
 625         struct dwc3_hwparams    *parms = &dwc->hwparams;
 626
 627         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 628         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 629         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 630         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 631         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 632         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 633         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 634         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 635         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 636
 637         if (DWC3_IP_IS(DWC32))
 638                 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
 639 }
 640
 641 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 642 {
 643         int intf;
 644         int ret = 0;
 645
 646         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 647
 648         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 649             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 650              dwc->hsphy_interface &&
 651              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 652                 ret = dwc3_ulpi_init(dwc);
 653
 654         return ret;
 655 }
 656
 657 /**
 658  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 659  * @dwc: Pointer to our controller context structure
 660  *
 661  * Returns 0 on success. The USB PHY interfaces are configured but not
 662  * initialized. The PHY interfaces and the PHYs get initialized together with
 663  * the core in dwc3_core_init.
 664  */
 665 static int dwc3_phy_setup(struct dwc3 *dwc)
 666 {
 667         unsigned int hw_mode;
 668         u32 reg;
 669
 670         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 671
 672         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 673
 674         /*
 675          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 676          * PHYs. Also, this bit is not supposed to be used in normal operation.
 677          */
 678         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 679
 680         /*
 681          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 682          * to '0' during coreConsultant configuration. So default value
 683          * will be '0' when the core is reset. Application needs to set it
 684          * to '1' after the core initialization is completed.
 685          */
 686         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 687                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 688
 689         /*
 690          * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
 691          * power-on reset, and it can be set after core initialization, which is
 692          * after device soft-reset during initialization.
 693          */
 694         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 695                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 696
 697         if (dwc->u2ss_inp3_quirk)
 698                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 699
 700         if (dwc->dis_rxdet_inp3_quirk)
 701                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 702
 703         if (dwc->req_p1p2p3_quirk)
 704                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 705
 706         if (dwc->del_p1p2p3_quirk)
 707                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 708
 709         if (dwc->del_phy_power_chg_quirk)
 710                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 711
 712         if (dwc->lfps_filter_quirk)
 713                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 714
 715         if (dwc->rx_detect_poll_quirk)
 716                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 717
 718         if (dwc->tx_de_emphasis_quirk)
 719                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 720
 721         if (dwc->dis_u3_susphy_quirk)
 722                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 723
 724         if (dwc->dis_del_phy_power_chg_quirk)
 725                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 726
 727         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 728
 729         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 730
 731         /* Select the HS PHY interface */
 732         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 733         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 734                 if (dwc->hsphy_interface &&
 735                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 736                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 737                         break;
 738                 } else if (dwc->hsphy_interface &&
 739                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 740                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 741                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 742                 } else {
 743                         /* Relying on default value. */
 744                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 745                                 break;
 746                 }
 747                 fallthrough;
 748         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 749         default:
 750                 break;
 751         }
 752
 753         switch (dwc->hsphy_mode) {
 754         case USBPHY_INTERFACE_MODE_UTMI:
 755                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 756                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 757                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 758                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 759                 break;
 760         case USBPHY_INTERFACE_MODE_UTMIW:
 761                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 762                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 763                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 764                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 765                 break;
 766         default:
 767                 break;
 768         }
 769
 770         /*
 771          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 772          * '0' during coreConsultant configuration. So default value will
 773          * be '0' when the core is reset. Application needs to set it to
 774          * '1' after the core initialization is completed.
 775          */
 776         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 777                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 778
 779         /*
 780          * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
 781          * power-on reset, and it can be set after core initialization, which is
 782          * after device soft-reset during initialization.
 783          */
 784         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 785                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 786
 787         if (dwc->dis_u2_susphy_quirk)
 788                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 789
 790         if (dwc->dis_enblslpm_quirk)
 791                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 792         else
 793                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 794
 795         if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
 796                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 797
 798         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 799
 800         return 0;
 801 }
 802
 803 static int dwc3_clk_enable(struct dwc3 *dwc)
 804 {
 805         int ret;
 806
 807         ret = clk_prepare_enable(dwc->bus_clk);
 808         if (ret)
 809                 return ret;
 810
 811         ret = clk_prepare_enable(dwc->ref_clk);
 812         if (ret)
 813                 goto disable_bus_clk;
 814
 815         ret = clk_prepare_enable(dwc->susp_clk);
 816         if (ret)
 817                 goto disable_ref_clk;
 818
 819         return 0;
 820
 821 disable_ref_clk:
 822         clk_disable_unprepare(dwc->ref_clk);
 823 disable_bus_clk:
 824         clk_disable_unprepare(dwc->bus_clk);
 825         return ret;
 826 }
 827
 828 static void dwc3_clk_disable(struct dwc3 *dwc)
 829 {
 830         clk_disable_unprepare(dwc->susp_clk);
 831         clk_disable_unprepare(dwc->ref_clk);
 832         clk_disable_unprepare(dwc->bus_clk);
 833 }
 834
 835 static void dwc3_core_exit(struct dwc3 *dwc)
 836 {
 837         dwc3_event_buffers_cleanup(dwc);
 838
 839         usb_phy_set_suspend(dwc->usb2_phy, 1);
 840         usb_phy_set_suspend(dwc->usb3_phy, 1);
 841         phy_power_off(dwc->usb2_generic_phy);
 842         phy_power_off(dwc->usb3_generic_phy);
 843
 844         usb_phy_shutdown(dwc->usb2_phy);
 845         usb_phy_shutdown(dwc->usb3_phy);
 846         phy_exit(dwc->usb2_generic_phy);
 847         phy_exit(dwc->usb3_generic_phy);
 848
 849         dwc3_clk_disable(dwc);
 850         reset_control_assert(dwc->reset);
 851 }
 852
 853 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 854 {
 855         u32 reg;
 856
 857         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 858         dwc->ip = DWC3_GSNPS_ID(reg);
 859
 860         /* This should read as U3 followed by revision number */
 861         if (DWC3_IP_IS(DWC3)) {
 862                 dwc->revision = reg;
 863         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 864                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 865                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 866         } else {
 867                 return false;
 868         }
 869
 870         return true;
 871 }
 872
 873 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 874 {
 875         u32 hwparams4 = dwc->hwparams.hwparams4;
 876         u32 reg;
 877
 878         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 879         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 880
 881         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 882         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 883                 /**
 884                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 885                  * issue which would cause xHCI compliance tests to fail.
 886                  *
 887                  * Because of that we cannot enable clock gating on such
 888                  * configurations.
 889                  *
 890                  * Refers to:
 891                  *
 892                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 893                  * SOF/ITP Mode Used
 894                  */
 895                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 896                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 897                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 898                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 899                 else
 900                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 901                 break;
 902         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 903                 /* enable hibernation here */
 904                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 905
 906                 /*
 907                  * REVISIT Enabling this bit so that host-mode hibernation
 908                  * will work. Device-mode hibernation is not yet implemented.
 909                  */
 910                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 911                 break;
 912         default:
 913                 /* nothing */
 914                 break;
 915         }
 916
 917         /* check if current dwc3 is on simulation board */
 918         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 919                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 920                 dwc->is_fpga = true;
 921         }
 922
 923         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 924                         "disable_scramble cannot be used on non-FPGA builds\n");
 925
 926         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 927                 reg |= DWC3_GCTL_DISSCRAMBLE;
 928         else
 929                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 930
 931         if (dwc->u2exit_lfps_quirk)
 932                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 933
 934         /*
 935          * WORKAROUND: DWC3 revisions <1.90a have a bug
 936          * where the device can fail to connect at SuperSpeed
 937          * and falls back to high-speed mode which causes
 938          * the device to enter a Connect/Disconnect loop
 939          */
 940         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
 941                 reg |= DWC3_GCTL_U2RSTECN;
 942
 943         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 944 }
 945
 946 static int dwc3_core_get_phy(struct dwc3 *dwc);
 947 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 948
 949 /* set global incr burst type configuration registers */
 950 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 951 {
 952         struct device *dev = dwc->dev;
 953         /* incrx_mode : for INCR burst type. */
 954         bool incrx_mode;
 955         /* incrx_size : for size of INCRX burst. */
 956         u32 incrx_size;
 957         u32 *vals;
 958         u32 cfg;
 959         int ntype;
 960         int ret;
 961         int i;
 962
 963         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 964
 965         /*
 966          * Handle property "snps,incr-burst-type-adjustment".
 967          * Get the number of value from this property:
 968          * result <= 0, means this property is not supported.
 969          * result = 1, means INCRx burst mode supported.
 970          * result > 1, means undefined length burst mode supported.
 971          */
 972         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 973         if (ntype <= 0)
 974                 return;
 975
 976         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 977         if (!vals)
 978                 return;
 979
 980         /* Get INCR burst type, and parse it */
 981         ret = device_property_read_u32_array(dev,
 982                         "snps,incr-burst-type-adjustment", vals, ntype);
 983         if (ret) {
 984                 kfree(vals);
 985                 dev_err(dev, "Error to get property\n");
 986                 return;
 987         }
 988
 989         incrx_size = *vals;
 990
 991         if (ntype > 1) {
 992                 /* INCRX (undefined length) burst mode */
 993                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 994                 for (i = 1; i < ntype; i++) {
 995                         if (vals[i] > incrx_size)
 996                                 incrx_size = vals[i];
 997                 }
 998         } else {
 999                 /* INCRX burst mode */
1000                 incrx_mode = INCRX_BURST_MODE;
1001         }
1002
1003         kfree(vals);
1004
1005         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1006         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1007         if (incrx_mode)
1008                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1009         switch (incrx_size) {
1010         case 256:
1011                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1012                 break;
1013         case 128:
1014                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1015                 break;
1016         case 64:
1017                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1018                 break;
1019         case 32:
1020                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1021                 break;
1022         case 16:
1023                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1024                 break;
1025         case 8:
1026                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1027                 break;
1028         case 4:
1029                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1030                 break;
1031         case 1:
1032                 break;
1033         default:
1034                 dev_err(dev, "Invalid property\n");
1035                 break;
1036         }
1037
1038         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1039 }
1040
1041 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1042 {
1043         u32 scale;
1044         u32 reg;
1045
1046         if (!dwc->susp_clk)
1047                 return;
1048
1049         /*
1050          * The power down scale field specifies how many suspend_clk
1051          * periods fit into a 16KHz clock period. When performing
1052          * the division, round up the remainder.
1053          *
1054          * The power down scale value is calculated using the fastest
1055          * frequency of the suspend_clk. If it isn't fixed (but within
1056          * the accuracy requirement), the driver may not know the max
1057          * rate of the suspend_clk, so only update the power down scale
1058          * if the default is less than the calculated value from
1059          * clk_get_rate() or if the default is questionably high
1060          * (3x or more) to be within the requirement.
1061          */
1062         scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1063         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1064         if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1065             (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1066                 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1067                 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1068                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1069         }
1070 }
1071
1072 /**
1073  * dwc3_core_init - Low-level initialization of DWC3 Core
1074  * @dwc: Pointer to our controller context structure
1075  *
1076  * Returns 0 on success otherwise negative errno.
1077  */
1078 static int dwc3_core_init(struct dwc3 *dwc)
1079 {
1080         unsigned int            hw_mode;
1081         u32                     reg;
1082         int                     ret;
1083
1084         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1085
1086         /*
1087          * Write Linux Version Code to our GUID register so it's easy to figure
1088          * out which kernel version a bug was found.
1089          */
1090         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1091
1092         ret = dwc3_phy_setup(dwc);
1093         if (ret)
1094                 goto err0;
1095
1096         if (!dwc->ulpi_ready) {
1097                 ret = dwc3_core_ulpi_init(dwc);
1098                 if (ret)
1099                         goto err0;
1100                 dwc->ulpi_ready = true;
1101         }
1102
1103         if (!dwc->phys_ready) {
1104                 ret = dwc3_core_get_phy(dwc);
1105                 if (ret)
1106                         goto err0a;
1107                 dwc->phys_ready = true;
1108         }
1109
1110         usb_phy_init(dwc->usb2_phy);
1111         usb_phy_init(dwc->usb3_phy);
1112         ret = phy_init(dwc->usb2_generic_phy);
1113         if (ret < 0)
1114                 goto err0a;
1115
1116         ret = phy_init(dwc->usb3_generic_phy);
1117         if (ret < 0) {
1118                 phy_exit(dwc->usb2_generic_phy);
1119                 goto err0a;
1120         }
1121
1122         ret = dwc3_core_soft_reset(dwc);
1123         if (ret)
1124                 goto err1;
1125
1126         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1127             !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1128                 if (!dwc->dis_u3_susphy_quirk) {
1129                         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1130                         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1131                         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1132                 }
1133
1134                 if (!dwc->dis_u2_susphy_quirk) {
1135                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1136                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1137                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1138                 }
1139         }
1140
1141         dwc3_core_setup_global_control(dwc);
1142         dwc3_core_num_eps(dwc);
1143
1144         ret = dwc3_setup_scratch_buffers(dwc);
1145         if (ret)
1146                 goto err1;
1147
1148         /* Set power down scale of suspend_clk */
1149         dwc3_set_power_down_clk_scale(dwc);
1150
1151         /* Adjust Frame Length */
1152         dwc3_frame_length_adjustment(dwc);
1153
1154         /* Adjust Reference Clock Period */
1155         dwc3_ref_clk_period(dwc);
1156
1157         dwc3_set_incr_burst_type(dwc);
1158
1159         usb_phy_set_suspend(dwc->usb2_phy, 0);
1160         usb_phy_set_suspend(dwc->usb3_phy, 0);
1161         ret = phy_power_on(dwc->usb2_generic_phy);
1162         if (ret < 0)
1163                 goto err2;
1164
1165         ret = phy_power_on(dwc->usb3_generic_phy);
1166         if (ret < 0)
1167                 goto err3;
1168
1169         ret = dwc3_event_buffers_setup(dwc);
1170         if (ret) {
1171                 dev_err(dwc->dev, "failed to setup event buffers\n");
1172                 goto err4;
1173         }
1174
1175         /*
1176          * ENDXFER polling is available on version 3.10a and later of
1177          * the DWC_usb3 controller. It is NOT available in the
1178          * DWC_usb31 controller.
1179          */
1180         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1181                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1182                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1183                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1184         }
1185
1186         /*
1187          * When configured in HOST mode, after issuing U3/L2 exit controller
1188          * fails to send proper CRC checksum in CRC5 feild. Because of this
1189          * behaviour Transaction Error is generated, resulting in reset and
1190          * re-enumeration of usb device attached. All the termsel, xcvrsel,
1191          * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1192          * will correct this problem. This option is to support certain
1193          * legacy ULPI PHYs.
1194          */
1195         if (dwc->resume_hs_terminations) {
1196                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1197                 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1198                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1199         }
1200
1201         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1202                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1203
1204                 /*
1205                  * Enable hardware control of sending remote wakeup
1206                  * in HS when the device is in the L1 state.
1207                  */
1208                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1209                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1210
1211                 /*
1212                  * Decouple USB 2.0 L1 & L2 events which will allow for
1213                  * gadget driver to only receive U3/L2 suspend & wakeup
1214                  * events and prevent the more frequent L1 LPM transitions
1215                  * from interrupting the driver.
1216                  */
1217                 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1218                         reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1219
1220                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1221                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1222
1223                 if (dwc->parkmode_disable_ss_quirk)
1224                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1225
1226                 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1227                     (dwc->maximum_speed == USB_SPEED_HIGH ||
1228                      dwc->maximum_speed == USB_SPEED_FULL))
1229                         reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1230
1231                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1232         }
1233
1234         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1235             dwc->dr_mode == USB_DR_MODE_OTG) {
1236                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1237
1238                 /*
1239                  * Enable Auto retry Feature to make the controller operating in
1240                  * Host mode on seeing transaction errors(CRC errors or internal
1241                  * overrun scenerios) on IN transfers to reply to the device
1242                  * with a non-terminating retry ACK (i.e, an ACK transcation
1243                  * packet with Retry=1 & Nump != 0)
1244                  */
1245                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1246
1247                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1248         }
1249
1250         /*
1251          * Must config both number of packets and max burst settings to enable
1252          * RX and/or TX threshold.
1253          */
1254         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1255                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1256                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1257                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1258                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1259
1260                 if (rx_thr_num && rx_maxburst) {
1261                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1262                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1263
1264                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1265                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1266
1267                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1268                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1269
1270                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1271                 }
1272
1273                 if (tx_thr_num && tx_maxburst) {
1274                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1275                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1276
1277                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1278                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1279
1280                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1281                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1282
1283                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1284                 }
1285         }
1286
1287         return 0;
1288
1289 err4:
1290         phy_power_off(dwc->usb3_generic_phy);
1291
1292 err3:
1293         phy_power_off(dwc->usb2_generic_phy);
1294
1295 err2:
1296         usb_phy_set_suspend(dwc->usb2_phy, 1);
1297         usb_phy_set_suspend(dwc->usb3_phy, 1);
1298
1299 err1:
1300         usb_phy_shutdown(dwc->usb2_phy);
1301         usb_phy_shutdown(dwc->usb3_phy);
1302         phy_exit(dwc->usb2_generic_phy);
1303         phy_exit(dwc->usb3_generic_phy);
1304
1305 err0a:
1306         dwc3_ulpi_exit(dwc);
1307
1308 err0:
1309         return ret;
1310 }
1311
1312 static int dwc3_core_get_phy(struct dwc3 *dwc)
1313 {
1314         struct device           *dev = dwc->dev;
1315         struct device_node      *node = dev->of_node;
1316         int ret;
1317
1318         if (node) {
1319                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1320                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1321         } else {
1322                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1323                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1324         }
1325
1326         if (IS_ERR(dwc->usb2_phy)) {
1327                 ret = PTR_ERR(dwc->usb2_phy);
1328                 if (ret == -ENXIO || ret == -ENODEV)
1329                         dwc->usb2_phy = NULL;
1330                 else
1331                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1332         }
1333
1334         if (IS_ERR(dwc->usb3_phy)) {
1335                 ret = PTR_ERR(dwc->usb3_phy);
1336                 if (ret == -ENXIO || ret == -ENODEV)
1337                         dwc->usb3_phy = NULL;
1338                 else
1339                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1340         }
1341
1342         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1343         if (IS_ERR(dwc->usb2_generic_phy)) {
1344                 ret = PTR_ERR(dwc->usb2_generic_phy);
1345                 if (ret == -ENOSYS || ret == -ENODEV)
1346                         dwc->usb2_generic_phy = NULL;
1347                 else
1348                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1349         }
1350
1351         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1352         if (IS_ERR(dwc->usb3_generic_phy)) {
1353                 ret = PTR_ERR(dwc->usb3_generic_phy);
1354                 if (ret == -ENOSYS || ret == -ENODEV)
1355                         dwc->usb3_generic_phy = NULL;
1356                 else
1357                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1358         }
1359
1360         return 0;
1361 }
1362
1363 static int dwc3_core_init_mode(struct dwc3 *dwc)
1364 {
1365         struct device *dev = dwc->dev;
1366         int ret;
1367
1368         switch (dwc->dr_mode) {
1369         case USB_DR_MODE_PERIPHERAL:
1370                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1371
1372                 if (dwc->usb2_phy)
1373                         otg_set_vbus(dwc->usb2_phy->otg, false);
1374                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1375                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1376
1377                 ret = dwc3_gadget_init(dwc);
1378                 if (ret)
1379                         return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1380                 break;
1381         case USB_DR_MODE_HOST:
1382                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1383
1384                 if (dwc->usb2_phy)
1385                         otg_set_vbus(dwc->usb2_phy->otg, true);
1386                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1387                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1388
1389                 ret = dwc3_host_init(dwc);
1390                 if (ret)
1391                         return dev_err_probe(dev, ret, "failed to initialize host\n");
1392                 break;
1393         case USB_DR_MODE_OTG:
1394                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1395                 ret = dwc3_drd_init(dwc);
1396                 if (ret)
1397                         return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1398                 break;
1399         default:
1400                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1401                 return -EINVAL;
1402         }
1403
1404         return 0;
1405 }
1406
1407 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1408 {
1409         switch (dwc->dr_mode) {
1410         case USB_DR_MODE_PERIPHERAL:
1411                 dwc3_gadget_exit(dwc);
1412                 break;
1413         case USB_DR_MODE_HOST:
1414                 dwc3_host_exit(dwc);
1415                 break;
1416         case USB_DR_MODE_OTG:
1417                 dwc3_drd_exit(dwc);
1418                 break;
1419         default:
1420                 /* do nothing */
1421                 break;
1422         }
1423
1424         /* de-assert DRVVBUS for HOST and OTG mode */
1425         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1426 }
1427
1428 static void dwc3_get_properties(struct dwc3 *dwc)
1429 {
1430         struct device           *dev = dwc->dev;
1431         u8                      lpm_nyet_threshold;
1432         u8                      tx_de_emphasis;
1433         u8                      hird_threshold;
1434         u8                      rx_thr_num_pkt_prd = 0;
1435         u8                      rx_max_burst_prd = 0;
1436         u8                      tx_thr_num_pkt_prd = 0;
1437         u8                      tx_max_burst_prd = 0;
1438         u8                      tx_fifo_resize_max_num;
1439         const char              *usb_psy_name;
1440         int                     ret;
1441
1442         /* default to highest possible threshold */
1443         lpm_nyet_threshold = 0xf;
1444
1445         /* default to -3.5dB de-emphasis */
1446         tx_de_emphasis = 1;
1447
1448         /*
1449          * default to assert utmi_sleep_n and use maximum allowed HIRD
1450          * threshold value of 0b1100
1451          */
1452         hird_threshold = 12;
1453
1454         /*
1455          * default to a TXFIFO size large enough to fit 6 max packets.  This
1456          * allows for systems with larger bus latencies to have some headroom
1457          * for endpoints that have a large bMaxBurst value.
1458          */
1459         tx_fifo_resize_max_num = 6;
1460
1461         dwc->maximum_speed = usb_get_maximum_speed(dev);
1462         dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1463         dwc->dr_mode = usb_get_dr_mode(dev);
1464         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1465
1466         dwc->sysdev_is_parent = device_property_read_bool(dev,
1467                                 "linux,sysdev_is_parent");
1468         if (dwc->sysdev_is_parent)
1469                 dwc->sysdev = dwc->dev->parent;
1470         else
1471                 dwc->sysdev = dwc->dev;
1472
1473         ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1474         if (ret >= 0) {
1475                 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1476                 if (!dwc->usb_psy)
1477                         dev_err(dev, "couldn't get usb power supply\n");
1478         }
1479
1480         dwc->has_lpm_erratum = device_property_read_bool(dev,
1481                                 "snps,has-lpm-erratum");
1482         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1483                                 &lpm_nyet_threshold);
1484         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1485                                 "snps,is-utmi-l1-suspend");
1486         device_property_read_u8(dev, "snps,hird-threshold",
1487                                 &hird_threshold);
1488         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1489                                 "snps,dis-start-transfer-quirk");
1490         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1491                                 "snps,usb3_lpm_capable");
1492         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1493                                 "snps,usb2-lpm-disable");
1494         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1495                                 "snps,usb2-gadget-lpm-disable");
1496         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1497                                 &rx_thr_num_pkt_prd);
1498         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1499                                 &rx_max_burst_prd);
1500         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1501                                 &tx_thr_num_pkt_prd);
1502         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1503                                 &tx_max_burst_prd);
1504         dwc->do_fifo_resize = device_property_read_bool(dev,
1505                                                         "tx-fifo-resize");
1506         if (dwc->do_fifo_resize)
1507                 device_property_read_u8(dev, "tx-fifo-max-num",
1508                                         &tx_fifo_resize_max_num);
1509
1510         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1511                                 "snps,disable_scramble_quirk");
1512         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1513                                 "snps,u2exit_lfps_quirk");
1514         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1515                                 "snps,u2ss_inp3_quirk");
1516         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1517                                 "snps,req_p1p2p3_quirk");
1518         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1519                                 "snps,del_p1p2p3_quirk");
1520         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1521                                 "snps,del_phy_power_chg_quirk");
1522         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1523                                 "snps,lfps_filter_quirk");
1524         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1525                                 "snps,rx_detect_poll_quirk");
1526         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1527                                 "snps,dis_u3_susphy_quirk");
1528         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1529                                 "snps,dis_u2_susphy_quirk");
1530         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1531                                 "snps,dis_enblslpm_quirk");
1532         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1533                                 "snps,dis-u1-entry-quirk");
1534         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1535                                 "snps,dis-u2-entry-quirk");
1536         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1537                                 "snps,dis_rxdet_inp3_quirk");
1538         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1539                                 "snps,dis-u2-freeclk-exists-quirk");
1540         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1541                                 "snps,dis-del-phy-power-chg-quirk");
1542         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1543                                 "snps,dis-tx-ipgap-linecheck-quirk");
1544         dwc->resume_hs_terminations = device_property_read_bool(dev,
1545                                 "snps,resume-hs-terminations");
1546         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1547                                 "snps,parkmode-disable-ss-quirk");
1548         dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1549                                 "snps,gfladj-refclk-lpm-sel-quirk");
1550
1551         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1552                                 "snps,tx_de_emphasis_quirk");
1553         device_property_read_u8(dev, "snps,tx_de_emphasis",
1554                                 &tx_de_emphasis);
1555         device_property_read_string(dev, "snps,hsphy_interface",
1556                                     &dwc->hsphy_interface);
1557         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1558                                  &dwc->fladj);
1559         device_property_read_u32(dev, "snps,ref-clock-period-ns",
1560                                  &dwc->ref_clk_per);
1561
1562         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1563                                 "snps,dis_metastability_quirk");
1564
1565         dwc->dis_split_quirk = device_property_read_bool(dev,
1566                                 "snps,dis-split-quirk");
1567
1568         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1569         dwc->tx_de_emphasis = tx_de_emphasis;
1570
1571         dwc->hird_threshold = hird_threshold;
1572
1573         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1574         dwc->rx_max_burst_prd = rx_max_burst_prd;
1575
1576         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1577         dwc->tx_max_burst_prd = tx_max_burst_prd;
1578
1579         dwc->imod_interval = 0;
1580
1581         dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1582 }
1583
1584 /* check whether the core supports IMOD */
1585 bool dwc3_has_imod(struct dwc3 *dwc)
1586 {
1587         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1588                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1589                 DWC3_IP_IS(DWC32);
1590 }
1591
1592 static void dwc3_check_params(struct dwc3 *dwc)
1593 {
1594         struct device *dev = dwc->dev;
1595         unsigned int hwparam_gen =
1596                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1597
1598         /* Check for proper value of imod_interval */
1599         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1600                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1601                 dwc->imod_interval = 0;
1602         }
1603
1604         /*
1605          * Workaround for STAR 9000961433 which affects only version
1606          * 3.00a of the DWC_usb3 core. This prevents the controller
1607          * interrupt from being masked while handling events. IMOD
1608          * allows us to work around this issue. Enable it for the
1609          * affected version.
1610          */
1611         if (!dwc->imod_interval &&
1612             DWC3_VER_IS(DWC3, 300A))
1613                 dwc->imod_interval = 1;
1614
1615         /* Check the maximum_speed parameter */
1616         switch (dwc->maximum_speed) {
1617         case USB_SPEED_FULL:
1618         case USB_SPEED_HIGH:
1619                 break;
1620         case USB_SPEED_SUPER:
1621                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1622                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1623                 break;
1624         case USB_SPEED_SUPER_PLUS:
1625                 if ((DWC3_IP_IS(DWC32) &&
1626                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1627                     (!DWC3_IP_IS(DWC32) &&
1628                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1629                         dev_warn(dev, "UDC doesn't support SSP\n");
1630                 break;
1631         default:
1632                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1633                         dwc->maximum_speed);
1634                 fallthrough;
1635         case USB_SPEED_UNKNOWN:
1636                 switch (hwparam_gen) {
1637                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1638                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1639                         break;
1640                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1641                         if (DWC3_IP_IS(DWC32))
1642                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1643                         else
1644                                 dwc->maximum_speed = USB_SPEED_SUPER;
1645                         break;
1646                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1647                         dwc->maximum_speed = USB_SPEED_HIGH;
1648                         break;
1649                 default:
1650                         dwc->maximum_speed = USB_SPEED_SUPER;
1651                         break;
1652                 }
1653                 break;
1654         }
1655
1656         /*
1657          * Currently the controller does not have visibility into the HW
1658          * parameter to determine the maximum number of lanes the HW supports.
1659          * If the number of lanes is not specified in the device property, then
1660          * set the default to support dual-lane for DWC_usb32 and single-lane
1661          * for DWC_usb31 for super-speed-plus.
1662          */
1663         if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1664                 switch (dwc->max_ssp_rate) {
1665                 case USB_SSP_GEN_2x1:
1666                         if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1667                                 dev_warn(dev, "UDC only supports Gen 1\n");
1668                         break;
1669                 case USB_SSP_GEN_1x2:
1670                 case USB_SSP_GEN_2x2:
1671                         if (DWC3_IP_IS(DWC31))
1672                                 dev_warn(dev, "UDC only supports single lane\n");
1673                         break;
1674                 case USB_SSP_GEN_UNKNOWN:
1675                 default:
1676                         switch (hwparam_gen) {
1677                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1678                                 if (DWC3_IP_IS(DWC32))
1679                                         dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1680                                 else
1681                                         dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1682                                 break;
1683                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1684                                 if (DWC3_IP_IS(DWC32))
1685                                         dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1686                                 break;
1687                         }
1688                         break;
1689                 }
1690         }
1691 }
1692
1693 static int dwc3_probe(struct platform_device *pdev)
1694 {
1695         struct device           *dev = &pdev->dev;
1696         struct resource         *res, dwc_res;
1697         struct dwc3             *dwc;
1698
1699         int                     ret;
1700
1701         void __iomem            *regs;
1702
1703         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1704         if (!dwc)
1705                 return -ENOMEM;
1706
1707         dwc->dev = dev;
1708
1709         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1710         if (!res) {
1711                 dev_err(dev, "missing memory resource\n");
1712                 return -ENODEV;
1713         }
1714
1715         dwc->xhci_resources[0].start = res->start;
1716         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1717                                         DWC3_XHCI_REGS_END;
1718         dwc->xhci_resources[0].flags = res->flags;
1719         dwc->xhci_resources[0].name = res->name;
1720
1721         /*
1722          * Request memory region but exclude xHCI regs,
1723          * since it will be requested by the xhci-plat driver.
1724          */
1725         dwc_res = *res;
1726         dwc_res.start += DWC3_GLOBALS_REGS_START;
1727
1728         regs = devm_ioremap_resource(dev, &dwc_res);
1729         if (IS_ERR(regs))
1730                 return PTR_ERR(regs);
1731
1732         dwc->regs       = regs;
1733         dwc->regs_size  = resource_size(&dwc_res);
1734
1735         dwc3_get_properties(dwc);
1736
1737         dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1738         if (IS_ERR(dwc->reset)) {
1739                 ret = PTR_ERR(dwc->reset);
1740                 goto put_usb_psy;
1741         }
1742
1743         if (dev->of_node) {
1744                 /*
1745                  * Clocks are optional, but new DT platforms should support all
1746                  * clocks as required by the DT-binding.
1747                  * Some devices have different clock names in legacy device trees,
1748                  * check for them to retain backwards compatibility.
1749                  */
1750                 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1751                 if (IS_ERR(dwc->bus_clk)) {
1752                         ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1753                                             "could not get bus clock\n");
1754                         goto put_usb_psy;
1755                 }
1756
1757                 if (dwc->bus_clk == NULL) {
1758                         dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1759                         if (IS_ERR(dwc->bus_clk)) {
1760                                 ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1761                                                     "could not get bus clock\n");
1762                                 goto put_usb_psy;
1763                         }
1764                 }
1765
1766                 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1767                 if (IS_ERR(dwc->ref_clk)) {
1768                         ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1769                                             "could not get ref clock\n");
1770                         goto put_usb_psy;
1771                 }
1772
1773                 if (dwc->ref_clk == NULL) {
1774                         dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1775                         if (IS_ERR(dwc->ref_clk)) {
1776                                 ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1777                                                     "could not get ref clock\n");
1778                                 goto put_usb_psy;
1779                         }
1780                 }
1781
1782                 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1783                 if (IS_ERR(dwc->susp_clk)) {
1784                         ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1785                                             "could not get suspend clock\n");
1786                         goto put_usb_psy;
1787                 }
1788
1789                 if (dwc->susp_clk == NULL) {
1790                         dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1791                         if (IS_ERR(dwc->susp_clk)) {
1792                                 ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1793                                                     "could not get suspend clock\n");
1794                                 goto put_usb_psy;
1795                         }
1796                 }
1797         }
1798
1799         ret = reset_control_deassert(dwc->reset);
1800         if (ret)
1801                 goto put_usb_psy;
1802
1803         ret = dwc3_clk_enable(dwc);
1804         if (ret)
1805                 goto assert_reset;
1806
1807         if (!dwc3_core_is_valid(dwc)) {
1808                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1809                 ret = -ENODEV;
1810                 goto disable_clks;
1811         }
1812
1813         platform_set_drvdata(pdev, dwc);
1814         dwc3_cache_hwparams(dwc);
1815
1816         if (!dwc->sysdev_is_parent &&
1817             DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1818                 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1819                 if (ret)
1820                         goto disable_clks;
1821         }
1822
1823         spin_lock_init(&dwc->lock);
1824         mutex_init(&dwc->mutex);
1825
1826         pm_runtime_set_active(dev);
1827         pm_runtime_use_autosuspend(dev);
1828         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1829         pm_runtime_enable(dev);
1830         ret = pm_runtime_get_sync(dev);
1831         if (ret < 0)
1832                 goto err1;
1833
1834         pm_runtime_forbid(dev);
1835
1836         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1837         if (ret) {
1838                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1839                 ret = -ENOMEM;
1840                 goto err2;
1841         }
1842
1843         ret = dwc3_get_dr_mode(dwc);
1844         if (ret)
1845                 goto err3;
1846
1847         ret = dwc3_alloc_scratch_buffers(dwc);
1848         if (ret)
1849                 goto err3;
1850
1851         ret = dwc3_core_init(dwc);
1852         if (ret) {
1853                 dev_err_probe(dev, ret, "failed to initialize core\n");
1854                 goto err4;
1855         }
1856
1857         dwc3_check_params(dwc);
1858         dwc3_debugfs_init(dwc);
1859
1860         ret = dwc3_core_init_mode(dwc);
1861         if (ret)
1862                 goto err5;
1863
1864         pm_runtime_put(dev);
1865
1866         return 0;
1867
1868 err5:
1869         dwc3_debugfs_exit(dwc);
1870         dwc3_event_buffers_cleanup(dwc);
1871
1872         usb_phy_set_suspend(dwc->usb2_phy, 1);
1873         usb_phy_set_suspend(dwc->usb3_phy, 1);
1874         phy_power_off(dwc->usb2_generic_phy);
1875         phy_power_off(dwc->usb3_generic_phy);
1876
1877         usb_phy_shutdown(dwc->usb2_phy);
1878         usb_phy_shutdown(dwc->usb3_phy);
1879         phy_exit(dwc->usb2_generic_phy);
1880         phy_exit(dwc->usb3_generic_phy);
1881
1882         dwc3_ulpi_exit(dwc);
1883
1884 err4:
1885         dwc3_free_scratch_buffers(dwc);
1886
1887 err3:
1888         dwc3_free_event_buffers(dwc);
1889
1890 err2:
1891         pm_runtime_allow(&pdev->dev);
1892
1893 err1:
1894         pm_runtime_put_sync(&pdev->dev);
1895         pm_runtime_disable(&pdev->dev);
1896
1897 disable_clks:
1898         dwc3_clk_disable(dwc);
1899 assert_reset:
1900         reset_control_assert(dwc->reset);
1901 put_usb_psy:
1902         if (dwc->usb_psy)
1903                 power_supply_put(dwc->usb_psy);
1904
1905         return ret;
1906 }
1907
1908 static int dwc3_remove(struct platform_device *pdev)
1909 {
1910         struct dwc3     *dwc = platform_get_drvdata(pdev);
1911
1912         pm_runtime_get_sync(&pdev->dev);
1913
1914         dwc3_core_exit_mode(dwc);
1915         dwc3_debugfs_exit(dwc);
1916
1917         dwc3_core_exit(dwc);
1918         dwc3_ulpi_exit(dwc);
1919
1920         pm_runtime_disable(&pdev->dev);
1921         pm_runtime_put_noidle(&pdev->dev);
1922         pm_runtime_set_suspended(&pdev->dev);
1923
1924         dwc3_free_event_buffers(dwc);
1925         dwc3_free_scratch_buffers(dwc);
1926
1927         if (dwc->usb_psy)
1928                 power_supply_put(dwc->usb_psy);
1929
1930         return 0;
1931 }
1932
1933 #ifdef CONFIG_PM
1934 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1935 {
1936         int ret;
1937
1938         ret = reset_control_deassert(dwc->reset);
1939         if (ret)
1940                 return ret;
1941
1942         ret = dwc3_clk_enable(dwc);
1943         if (ret)
1944                 goto assert_reset;
1945
1946         ret = dwc3_core_init(dwc);
1947         if (ret)
1948                 goto disable_clks;
1949
1950         return 0;
1951
1952 disable_clks:
1953         dwc3_clk_disable(dwc);
1954 assert_reset:
1955         reset_control_assert(dwc->reset);
1956
1957         return ret;
1958 }
1959
1960 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1961 {
1962         unsigned long   flags;
1963         u32 reg;
1964
1965         switch (dwc->current_dr_role) {
1966         case DWC3_GCTL_PRTCAP_DEVICE:
1967                 if (pm_runtime_suspended(dwc->dev))
1968                         break;
1969                 dwc3_gadget_suspend(dwc);
1970                 synchronize_irq(dwc->irq_gadget);
1971                 dwc3_core_exit(dwc);
1972                 break;
1973         case DWC3_GCTL_PRTCAP_HOST:
1974                 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
1975                         dwc3_core_exit(dwc);
1976                         break;
1977                 }
1978
1979                 /* Let controller to suspend HSPHY before PHY driver suspends */
1980                 if (dwc->dis_u2_susphy_quirk ||
1981                     dwc->dis_enblslpm_quirk) {
1982                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1983                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1984                                 DWC3_GUSB2PHYCFG_SUSPHY;
1985                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1986
1987                         /* Give some time for USB2 PHY to suspend */
1988                         usleep_range(5000, 6000);
1989                 }
1990
1991                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1992                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1993                 break;
1994         case DWC3_GCTL_PRTCAP_OTG:
1995                 /* do nothing during runtime_suspend */
1996                 if (PMSG_IS_AUTO(msg))
1997                         break;
1998
1999                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2000                         spin_lock_irqsave(&dwc->lock, flags);
2001                         dwc3_gadget_suspend(dwc);
2002                         spin_unlock_irqrestore(&dwc->lock, flags);
2003                         synchronize_irq(dwc->irq_gadget);
2004                 }
2005
2006                 dwc3_otg_exit(dwc);
2007                 dwc3_core_exit(dwc);
2008                 break;
2009         default:
2010                 /* do nothing */
2011                 break;
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2018 {
2019         unsigned long   flags;
2020         int             ret;
2021         u32             reg;
2022
2023         switch (dwc->current_dr_role) {
2024         case DWC3_GCTL_PRTCAP_DEVICE:
2025                 ret = dwc3_core_init_for_resume(dwc);
2026                 if (ret)
2027                         return ret;
2028
2029                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2030                 dwc3_gadget_resume(dwc);
2031                 break;
2032         case DWC3_GCTL_PRTCAP_HOST:
2033                 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2034                         ret = dwc3_core_init_for_resume(dwc);
2035                         if (ret)
2036                                 return ret;
2037                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2038                         break;
2039                 }
2040                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2041                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2042                 if (dwc->dis_u2_susphy_quirk)
2043                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2044
2045                 if (dwc->dis_enblslpm_quirk)
2046                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2047
2048                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2049
2050                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2051                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2052                 break;
2053         case DWC3_GCTL_PRTCAP_OTG:
2054                 /* nothing to do on runtime_resume */
2055                 if (PMSG_IS_AUTO(msg))
2056                         break;
2057
2058                 ret = dwc3_core_init_for_resume(dwc);
2059                 if (ret)
2060                         return ret;
2061
2062                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2063
2064                 dwc3_otg_init(dwc);
2065                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2066                         dwc3_otg_host_init(dwc);
2067                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2068                         spin_lock_irqsave(&dwc->lock, flags);
2069                         dwc3_gadget_resume(dwc);
2070                         spin_unlock_irqrestore(&dwc->lock, flags);
2071                 }
2072
2073                 break;
2074         default:
2075                 /* do nothing */
2076                 break;
2077         }
2078
2079         return 0;
2080 }
2081
2082 static int dwc3_runtime_checks(struct dwc3 *dwc)
2083 {
2084         switch (dwc->current_dr_role) {
2085         case DWC3_GCTL_PRTCAP_DEVICE:
2086                 if (dwc->connected)
2087                         return -EBUSY;
2088                 break;
2089         case DWC3_GCTL_PRTCAP_HOST:
2090         default:
2091                 /* do nothing */
2092                 break;
2093         }
2094
2095         return 0;
2096 }
2097
2098 static int dwc3_runtime_suspend(struct device *dev)
2099 {
2100         struct dwc3     *dwc = dev_get_drvdata(dev);
2101         int             ret;
2102
2103         if (dwc3_runtime_checks(dwc))
2104                 return -EBUSY;
2105
2106         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2107         if (ret)
2108                 return ret;
2109
2110         return 0;
2111 }
2112
2113 static int dwc3_runtime_resume(struct device *dev)
2114 {
2115         struct dwc3     *dwc = dev_get_drvdata(dev);
2116         int             ret;
2117
2118         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2119         if (ret)
2120                 return ret;
2121
2122         switch (dwc->current_dr_role) {
2123         case DWC3_GCTL_PRTCAP_DEVICE:
2124                 dwc3_gadget_process_pending_events(dwc);
2125                 break;
2126         case DWC3_GCTL_PRTCAP_HOST:
2127         default:
2128                 /* do nothing */
2129                 break;
2130         }
2131
2132         pm_runtime_mark_last_busy(dev);
2133
2134         return 0;
2135 }
2136
2137 static int dwc3_runtime_idle(struct device *dev)
2138 {
2139         struct dwc3     *dwc = dev_get_drvdata(dev);
2140
2141         switch (dwc->current_dr_role) {
2142         case DWC3_GCTL_PRTCAP_DEVICE:
2143                 if (dwc3_runtime_checks(dwc))
2144                         return -EBUSY;
2145                 break;
2146         case DWC3_GCTL_PRTCAP_HOST:
2147         default:
2148                 /* do nothing */
2149                 break;
2150         }
2151
2152         pm_runtime_mark_last_busy(dev);
2153         pm_runtime_autosuspend(dev);
2154
2155         return 0;
2156 }
2157 #endif /* CONFIG_PM */
2158
2159 #ifdef CONFIG_PM_SLEEP
2160 static int dwc3_suspend(struct device *dev)
2161 {
2162         struct dwc3     *dwc = dev_get_drvdata(dev);
2163         int             ret;
2164
2165         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2166         if (ret)
2167                 return ret;
2168
2169         pinctrl_pm_select_sleep_state(dev);
2170
2171         return 0;
2172 }
2173
2174 static int dwc3_resume(struct device *dev)
2175 {
2176         struct dwc3     *dwc = dev_get_drvdata(dev);
2177         int             ret;
2178
2179         pinctrl_pm_select_default_state(dev);
2180
2181         ret = dwc3_resume_common(dwc, PMSG_RESUME);
2182         if (ret)
2183                 return ret;
2184
2185         pm_runtime_disable(dev);
2186         pm_runtime_set_active(dev);
2187         pm_runtime_enable(dev);
2188
2189         return 0;
2190 }
2191
2192 static void dwc3_complete(struct device *dev)
2193 {
2194         struct dwc3     *dwc = dev_get_drvdata(dev);
2195         u32             reg;
2196
2197         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2198                         dwc->dis_split_quirk) {
2199                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2200                 reg |= DWC3_GUCTL3_SPLITDISABLE;
2201                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2202         }
2203 }
2204 #else
2205 #define dwc3_complete NULL
2206 #endif /* CONFIG_PM_SLEEP */
2207
2208 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2209         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2210         .complete = dwc3_complete,
2211         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2212                         dwc3_runtime_idle)
2213 };
2214
2215 #ifdef CONFIG_OF
2216 static const struct of_device_id of_dwc3_match[] = {
2217         {
2218                 .compatible = "snps,dwc3"
2219         },
2220         {
2221                 .compatible = "synopsys,dwc3"
2222         },
2223         { },
2224 };
2225 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2226 #endif
2227
2228 #ifdef CONFIG_ACPI
2229
2230 #define ACPI_ID_INTEL_BSW       "808622B7"
2231
2232 static const struct acpi_device_id dwc3_acpi_match[] = {
2233         { ACPI_ID_INTEL_BSW, 0 },
2234         { },
2235 };
2236 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2237 #endif
2238
2239 static struct platform_driver dwc3_driver = {
2240         .probe          = dwc3_probe,
2241         .remove         = dwc3_remove,
2242         .driver         = {
2243                 .name   = "dwc3",
2244                 .of_match_table = of_match_ptr(of_dwc3_match),
2245                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2246                 .pm     = &dwc3_dev_pm_ops,
2247         },
2248 };
2249
2250 module_platform_driver(dwc3_driver);
2251
2252 MODULE_ALIAS("platform:dwc3");
2253 MODULE_AUTHOR("Felipe Balbi <[email protected]>");
2254 MODULE_LICENSE("GPL v2");
2255 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");