drivers/soundwire/qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/completion.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/io.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/of.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/reset.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/slimbus.h>
  20 #include <linux/soundwire/sdw.h>
  21 #include <linux/soundwire/sdw_registers.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/soc.h>
  24 #include "bus.h"
  25
  26 #define SWRM_COMP_SW_RESET                                      0x008
  27 #define SWRM_COMP_STATUS                                        0x014
  28 #define SWRM_FRM_GEN_ENABLED                                    BIT(0)
  29 #define SWRM_COMP_HW_VERSION                                    0x00
  30 #define SWRM_COMP_CFG_ADDR                                      0x04
  31 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK                    BIT(1)
  32 #define SWRM_COMP_CFG_ENABLE_MSK                                BIT(0)
  33 #define SWRM_COMP_PARAMS                                        0x100
  34 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH                          GENMASK(14, 10)
  35 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH                          GENMASK(19, 15)
  36 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK                        GENMASK(4, 0)
  37 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK                         GENMASK(9, 5)
  38 #define SWRM_COMP_MASTER_ID                                     0x104
  39 #define SWRM_INTERRUPT_STATUS                                   0x200
  40 #define SWRM_INTERRUPT_STATUS_RMSK                              GENMASK(16, 0)
  41 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ                    BIT(0)
  42 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED                BIT(1)
  43 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS          BIT(2)
  44 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET                  BIT(3)
  45 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW                  BIT(4)
  46 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW                 BIT(5)
  47 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW              BIT(6)
  48 #define SWRM_INTERRUPT_STATUS_CMD_ERROR                         BIT(7)
  49 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION               BIT(8)
  50 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH         BIT(9)
  51 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED           BIT(10)
  52 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
  53 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
  54 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
  55 #define SWRM_INTERRUPT_MAX                                      17
  56 #define SWRM_INTERRUPT_MASK_ADDR                                0x204
  57 #define SWRM_INTERRUPT_CLEAR                                    0x208
  58 #define SWRM_INTERRUPT_CPU_EN                                   0x210
  59 #define SWRM_CMD_FIFO_WR_CMD                                    0x300
  60 #define SWRM_CMD_FIFO_RD_CMD                                    0x304
  61 #define SWRM_CMD_FIFO_CMD                                       0x308
  62 #define SWRM_CMD_FIFO_FLUSH                                     0x1
  63 #define SWRM_CMD_FIFO_STATUS                                    0x30C
  64 #define SWRM_RD_CMD_FIFO_CNT_MASK                               GENMASK(20, 16)
  65 #define SWRM_WR_CMD_FIFO_CNT_MASK                               GENMASK(12, 8)
  66 #define SWRM_CMD_FIFO_CFG_ADDR                                  0x314
  67 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE                        BIT(31)
  68 #define SWRM_RD_WR_CMD_RETRIES                                  0x7
  69 #define SWRM_CMD_FIFO_RD_FIFO_ADDR                              0x318
  70 #define SWRM_RD_FIFO_CMD_ID_MASK                                GENMASK(11, 8)
  71 #define SWRM_ENUMERATOR_CFG_ADDR                                0x500
  72 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)               (0x530 + 0x8 * (m))
  73 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)               (0x534 + 0x8 * (m))
  74 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)                (0x101C + 0x40 * (m))
  75 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK                  GENMASK(2, 0)
  76 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK                  GENMASK(7, 3)
  77 #define SWRM_MCP_BUS_CTRL                                       0x1044
  78 #define SWRM_MCP_BUS_CLK_START                                  BIT(1)
  79 #define SWRM_MCP_CFG_ADDR                                       0x1048
  80 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK               GENMASK(21, 17)
  81 #define SWRM_DEF_CMD_NO_PINGS                                   0x1f
  82 #define SWRM_MCP_STATUS                                         0x104C
  83 #define SWRM_MCP_STATUS_BANK_NUM_MASK                           BIT(0)
  84 #define SWRM_MCP_SLV_STATUS                                     0x1090
  85 #define SWRM_MCP_SLV_STATUS_MASK                                GENMASK(1, 0)
  86 #define SWRM_MCP_SLV_STATUS_SZ                                  2
  87 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
  88 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
  89 #define SWRM_DP_BLOCK_CTRL_1(n)         (0x112C + 0x100 * (n - 1))
  90 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
  91 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
  92 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
  93 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
  94 #define SWR_MSTR_MAX_REG_ADDR           (0x1740)
  95
  96 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT                          0x18
  97 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT                          0x10
  98 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT                          0x08
  99 #define SWRM_AHB_BRIDGE_WR_DATA_0                               0xc85
 100 #define SWRM_AHB_BRIDGE_WR_ADDR_0                               0xc89
 101 #define SWRM_AHB_BRIDGE_RD_ADDR_0                               0xc8d
 102 #define SWRM_AHB_BRIDGE_RD_DATA_0                               0xc91
 103
 104 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
 105                         ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
 106
 107 #define SWRM_SPECIAL_CMD_ID     0xF
 108 #define MAX_FREQ_NUM            1
 109 #define TIMEOUT_MS              100
 110 #define QCOM_SWRM_MAX_RD_LEN    0x1
 111 #define QCOM_SDW_MAX_PORTS      14
 112 #define DEFAULT_CLK_FREQ        9600000
 113 #define SWRM_MAX_DAIS           0xF
 114 #define SWR_INVALID_PARAM 0xFF
 115 #define SWR_HSTOP_MAX_VAL 0xF
 116 #define SWR_HSTART_MIN_VAL 0x0
 117 #define SWR_BROADCAST_CMD_ID    0x0F
 118 #define SWR_MAX_CMD_ID  14
 119 #define MAX_FIFO_RD_RETRY 3
 120 #define SWR_OVERFLOW_RETRY_COUNT 30
 121 #define SWRM_LINK_STATUS_RETRY_CNT 100
 122
 123 enum {
 124         MASTER_ID_WSA = 1,
 125         MASTER_ID_RX,
 126         MASTER_ID_TX
 127 };
 128
 129 struct qcom_swrm_port_config {
 130         u8 si;
 131         u8 off1;
 132         u8 off2;
 133         u8 bp_mode;
 134         u8 hstart;
 135         u8 hstop;
 136         u8 word_length;
 137         u8 blk_group_count;
 138         u8 lane_control;
 139 };
 140
 141 struct qcom_swrm_ctrl {
 142         struct sdw_bus bus;
 143         struct device *dev;
 144         struct regmap *regmap;
 145         void __iomem *mmio;
 146         struct reset_control *audio_cgcr;
 147 #ifdef CONFIG_DEBUG_FS
 148         struct dentry *debugfs;
 149 #endif
 150         struct completion broadcast;
 151         struct completion enumeration;
 152         struct work_struct slave_work;
 153         /* Port alloc/free lock */
 154         struct mutex port_lock;
 155         struct clk *hclk;
 156         u8 wr_cmd_id;
 157         u8 rd_cmd_id;
 158         int irq;
 159         unsigned int version;
 160         int wake_irq;
 161         int num_din_ports;
 162         int num_dout_ports;
 163         int cols_index;
 164         int rows_index;
 165         unsigned long dout_port_mask;
 166         unsigned long din_port_mask;
 167         u32 intr_mask;
 168         u8 rcmd_id;
 169         u8 wcmd_id;
 170         struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
 171         struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
 172         enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
 173         int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
 174         int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
 175         u32 slave_status;
 176         u32 wr_fifo_depth;
 177         u32 rd_fifo_depth;
 178         bool clock_stop_not_supported;
 179 };
 180
 181 struct qcom_swrm_data {
 182         u32 default_cols;
 183         u32 default_rows;
 184         bool sw_clk_gate_required;
 185 };
 186
 187 static const struct qcom_swrm_data swrm_v1_3_data = {
 188         .default_rows = 48,
 189         .default_cols = 16,
 190 };
 191
 192 static const struct qcom_swrm_data swrm_v1_5_data = {
 193         .default_rows = 50,
 194         .default_cols = 16,
 195 };
 196
 197 static const struct qcom_swrm_data swrm_v1_6_data = {
 198         .default_rows = 50,
 199         .default_cols = 16,
 200         .sw_clk_gate_required = true,
 201 };
 202
 203 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
 204
 205 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 206                                   u32 *val)
 207 {
 208         struct regmap *wcd_regmap = ctrl->regmap;
 209         int ret;
 210
 211         /* pg register + offset */
 212         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
 213                           (u8 *)&reg, 4);
 214         if (ret < 0)
 215                 return SDW_CMD_FAIL;
 216
 217         ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
 218                                val, 4);
 219         if (ret < 0)
 220                 return SDW_CMD_FAIL;
 221
 222         return SDW_CMD_OK;
 223 }
 224
 225 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
 226                                    int reg, int val)
 227 {
 228         struct regmap *wcd_regmap = ctrl->regmap;
 229         int ret;
 230         /* pg register + offset */
 231         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
 232                           (u8 *)&val, 4);
 233         if (ret)
 234                 return SDW_CMD_FAIL;
 235
 236         /* write address register */
 237         ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
 238                           (u8 *)&reg, 4);
 239         if (ret)
 240                 return SDW_CMD_FAIL;
 241
 242         return SDW_CMD_OK;
 243 }
 244
 245 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
 246                                   u32 *val)
 247 {
 248         *val = readl(ctrl->mmio + reg);
 249         return SDW_CMD_OK;
 250 }
 251
 252 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
 253                                    int val)
 254 {
 255         writel(val, ctrl->mmio + reg);
 256         return SDW_CMD_OK;
 257 }
 258
 259 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
 260                                    u8 dev_addr, u16 reg_addr)
 261 {
 262         u32 val;
 263         u8 id = *cmd_id;
 264
 265         if (id != SWR_BROADCAST_CMD_ID) {
 266                 if (id < SWR_MAX_CMD_ID)
 267                         id += 1;
 268                 else
 269                         id = 0;
 270                 *cmd_id = id;
 271         }
 272         val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
 273
 274         return val;
 275 }
 276
 277 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
 278 {
 279         u32 fifo_outstanding_data, value;
 280         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 281
 282         do {
 283                 /* Check for fifo underflow during read */
 284                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 285                 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
 286
 287                 /* Check if read data is available in read fifo */
 288                 if (fifo_outstanding_data > 0)
 289                         return 0;
 290
 291                 usleep_range(500, 510);
 292         } while (fifo_retry_count--);
 293
 294         if (fifo_outstanding_data == 0) {
 295                 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
 296                 return -EIO;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
 303 {
 304         u32 fifo_outstanding_cmds, value;
 305         int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
 306
 307         do {
 308                 /* Check for fifo overflow during write */
 309                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 310                 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
 311
 312                 /* Check for space in write fifo before writing */
 313                 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
 314                         return 0;
 315
 316                 usleep_range(500, 510);
 317         } while (fifo_retry_count--);
 318
 319         if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
 320                 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
 321                 return -EIO;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
 328                                      u8 dev_addr, u16 reg_addr)
 329 {
 330
 331         u32 val;
 332         int ret = 0;
 333         u8 cmd_id = 0x0;
 334
 335         if (dev_addr == SDW_BROADCAST_DEV_NUM) {
 336                 cmd_id = SWR_BROADCAST_CMD_ID;
 337                 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
 338                                               dev_addr, reg_addr);
 339         } else {
 340                 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
 341                                               dev_addr, reg_addr);
 342         }
 343
 344         if (swrm_wait_for_wr_fifo_avail(swrm))
 345                 return SDW_CMD_FAIL_OTHER;
 346
 347         /* Its assumed that write is okay as we do not get any status back */
 348         swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
 349
 350         /* version 1.3 or less */
 351         if (swrm->version <= 0x01030000)
 352                 usleep_range(150, 155);
 353
 354         if (cmd_id == SWR_BROADCAST_CMD_ID) {
 355                 /*
 356                  * sleep for 10ms for MSM soundwire variant to allow broadcast
 357                  * command to complete.
 358                  */
 359                 ret = wait_for_completion_timeout(&swrm->broadcast,
 360                                                   msecs_to_jiffies(TIMEOUT_MS));
 361                 if (!ret)
 362                         ret = SDW_CMD_IGNORED;
 363                 else
 364                         ret = SDW_CMD_OK;
 365
 366         } else {
 367                 ret = SDW_CMD_OK;
 368         }
 369         return ret;
 370 }
 371
 372 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
 373                                      u8 dev_addr, u16 reg_addr,
 374                                      u32 len, u8 *rval)
 375 {
 376         u32 cmd_data, cmd_id, val, retry_attempt = 0;
 377
 378         val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
 379
 380         /* wait for FIFO RD to complete to avoid overflow */
 381         usleep_range(100, 105);
 382         swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 383         /* wait for FIFO RD CMD complete to avoid overflow */
 384         usleep_range(250, 255);
 385
 386         if (swrm_wait_for_rd_fifo_avail(swrm))
 387                 return SDW_CMD_FAIL_OTHER;
 388
 389         do {
 390                 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
 391                 rval[0] = cmd_data & 0xFF;
 392                 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
 393
 394                 if (cmd_id != swrm->rcmd_id) {
 395                         if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
 396                                 /* wait 500 us before retry on fifo read failure */
 397                                 usleep_range(500, 505);
 398                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
 399                                                 SWRM_CMD_FIFO_FLUSH);
 400                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
 401                         }
 402                         retry_attempt++;
 403                 } else {
 404                         return SDW_CMD_OK;
 405                 }
 406
 407         } while (retry_attempt < MAX_FIFO_RD_RETRY);
 408
 409         dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
 410                 dev_num: 0x%x, cmd_data: 0x%x\n",
 411                 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
 412
 413         return SDW_CMD_IGNORED;
 414 }
 415
 416 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
 417 {
 418         u32 val, status;
 419         int dev_num;
 420
 421         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 422
 423         for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
 424                 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
 425
 426                 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
 427                         ctrl->status[dev_num] = status;
 428                         return dev_num;
 429                 }
 430         }
 431
 432         return -EINVAL;
 433 }
 434
 435 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
 436 {
 437         u32 val;
 438         int i;
 439
 440         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
 441         ctrl->slave_status = val;
 442
 443         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 444                 u32 s;
 445
 446                 s = (val >> (i * 2));
 447                 s &= SWRM_MCP_SLV_STATUS_MASK;
 448                 ctrl->status[i] = s;
 449         }
 450 }
 451
 452 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
 453                                         struct sdw_slave *slave, int devnum)
 454 {
 455         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 456         u32 status;
 457
 458         ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
 459         status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
 460         status &= SWRM_MCP_SLV_STATUS_MASK;
 461
 462         if (status == SDW_SLAVE_ATTACHED) {
 463                 if (slave)
 464                         slave->dev_num = devnum;
 465                 mutex_lock(&bus->bus_lock);
 466                 set_bit(devnum, bus->assigned);
 467                 mutex_unlock(&bus->bus_lock);
 468         }
 469 }
 470
 471 static int qcom_swrm_enumerate(struct sdw_bus *bus)
 472 {
 473         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 474         struct sdw_slave *slave, *_s;
 475         struct sdw_slave_id id;
 476         u32 val1, val2;
 477         bool found;
 478         u64 addr;
 479         int i;
 480         char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
 481
 482         for (i = 1; i <= SDW_MAX_DEVICES; i++) {
 483                 /* do not continue if the status is Not Present  */
 484                 if (!ctrl->status[i])
 485                         continue;
 486
 487                 /*SCP_Devid5 - Devid 4*/
 488                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
 489
 490                 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
 491                 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
 492
 493                 if (!val1 && !val2)
 494                         break;
 495
 496                 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
 497                         ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
 498                         ((u64)buf1[0] << 40);
 499
 500                 sdw_extract_slave_id(bus, addr, &id);
 501                 found = false;
 502                 /* Now compare with entries */
 503                 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
 504                         if (sdw_compare_devid(slave, id) == 0) {
 505                                 qcom_swrm_set_slave_dev_num(bus, slave, i);
 506                                 found = true;
 507                                 break;
 508                         }
 509                 }
 510
 511                 if (!found) {
 512                         qcom_swrm_set_slave_dev_num(bus, NULL, i);
 513                         sdw_slave_add(bus, &id, NULL);
 514                 }
 515         }
 516
 517         complete(&ctrl->enumeration);
 518         return 0;
 519 }
 520
 521 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
 522 {
 523         struct qcom_swrm_ctrl *swrm = dev_id;
 524         int ret;
 525
 526         ret = pm_runtime_resume_and_get(swrm->dev);
 527         if (ret < 0 && ret != -EACCES) {
 528                 dev_err_ratelimited(swrm->dev,
 529                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
 530                                     __func__, ret);
 531                 return ret;
 532         }
 533
 534         if (swrm->wake_irq > 0) {
 535                 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))
 536                         disable_irq_nosync(swrm->wake_irq);
 537         }
 538
 539         pm_runtime_mark_last_busy(swrm->dev);
 540         pm_runtime_put_autosuspend(swrm->dev);
 541
 542         return IRQ_HANDLED;
 543 }
 544
 545 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
 546 {
 547         struct qcom_swrm_ctrl *swrm = dev_id;
 548         u32 value, intr_sts, intr_sts_masked, slave_status;
 549         u32 i;
 550         int devnum;
 551         int ret = IRQ_HANDLED;
 552         clk_prepare_enable(swrm->hclk);
 553
 554         swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 555         intr_sts_masked = intr_sts & swrm->intr_mask;
 556
 557         do {
 558                 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
 559                         value = intr_sts_masked & BIT(i);
 560                         if (!value)
 561                                 continue;
 562
 563                         switch (value) {
 564                         case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
 565                                 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
 566                                 if (devnum < 0) {
 567                                         dev_err_ratelimited(swrm->dev,
 568                                             "no slave alert found.spurious interrupt\n");
 569                                 } else {
 570                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 571                                 }
 572
 573                                 break;
 574                         case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
 575                         case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
 576                                 dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n");
 577                                 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
 578                                 if (swrm->slave_status == slave_status) {
 579                                         dev_dbg(swrm->dev, "Slave status not changed %x\n",
 580                                                 slave_status);
 581                                 } else {
 582                                         qcom_swrm_get_device_status(swrm);
 583                                         qcom_swrm_enumerate(&swrm->bus);
 584                                         sdw_handle_slave_status(&swrm->bus, swrm->status);
 585                                 }
 586                                 break;
 587                         case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
 588                                 dev_err_ratelimited(swrm->dev,
 589                                                 "%s: SWR bus clsh detected\n",
 590                                                 __func__);
 591                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
 592                                 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 593                                 break;
 594                         case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
 595                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 596                                 dev_err_ratelimited(swrm->dev,
 597                                         "%s: SWR read FIFO overflow fifo status 0x%x\n",
 598                                         __func__, value);
 599                                 break;
 600                         case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
 601                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 602                                 dev_err_ratelimited(swrm->dev,
 603                                         "%s: SWR read FIFO underflow fifo status 0x%x\n",
 604                                         __func__, value);
 605                                 break;
 606                         case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
 607                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 608                                 dev_err(swrm->dev,
 609                                         "%s: SWR write FIFO overflow fifo status %x\n",
 610                                         __func__, value);
 611                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 612                                 break;
 613                         case SWRM_INTERRUPT_STATUS_CMD_ERROR:
 614                                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
 615                                 dev_err_ratelimited(swrm->dev,
 616                                         "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
 617                                         __func__, value);
 618                                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
 619                                 break;
 620                         case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
 621                                 dev_err_ratelimited(swrm->dev,
 622                                                 "%s: SWR Port collision detected\n",
 623                                                 __func__);
 624                                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
 625                                 swrm->reg_write(swrm,
 626                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 627                                 break;
 628                         case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
 629                                 dev_err_ratelimited(swrm->dev,
 630                                         "%s: SWR read enable valid mismatch\n",
 631                                         __func__);
 632                                 swrm->intr_mask &=
 633                                         ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
 634                                 swrm->reg_write(swrm,
 635                                         SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
 636                                 break;
 637                         case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
 638                                 complete(&swrm->broadcast);
 639                                 break;
 640                         case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
 641                                 break;
 642                         case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
 643                                 break;
 644                         case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
 645                                 break;
 646                         default:
 647                                 dev_err_ratelimited(swrm->dev,
 648                                                 "%s: SWR unknown interrupt value: %d\n",
 649                                                 __func__, value);
 650                                 ret = IRQ_NONE;
 651                                 break;
 652                         }
 653                 }
 654                 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
 655                 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
 656                 intr_sts_masked = intr_sts & swrm->intr_mask;
 657         } while (intr_sts_masked);
 658
 659         clk_disable_unprepare(swrm->hclk);
 660         return ret;
 661 }
 662
 663 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 664 {
 665         u32 val;
 666
 667         /* Clear Rows and Cols */
 668         val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
 669         val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
 670
 671         reset_control_reset(ctrl->audio_cgcr);
 672
 673         ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
 674
 675         /* Enable Auto enumeration */
 676         ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
 677
 678         ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
 679         /* Mask soundwire interrupts */
 680         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
 681                         SWRM_INTERRUPT_STATUS_RMSK);
 682
 683         /* Configure No pings */
 684         ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
 685         u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 686         ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 687
 688         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 689         /* Configure number of retries of a read/write cmd */
 690         if (ctrl->version > 0x01050001) {
 691                 /* Only for versions >= 1.5.1 */
 692                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 693                                 SWRM_RD_WR_CMD_RETRIES |
 694                                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
 695         } else {
 696                 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
 697                                 SWRM_RD_WR_CMD_RETRIES);
 698         }
 699
 700         /* Set IRQ to PULSE */
 701         ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
 702                         SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
 703                         SWRM_COMP_CFG_ENABLE_MSK);
 704
 705         /* enable CPU IRQs */
 706         if (ctrl->mmio) {
 707                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
 708                                 SWRM_INTERRUPT_STATUS_RMSK);
 709         }
 710         ctrl->slave_status = 0;
 711         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
 712         ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
 713         ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
 714
 715         return 0;
 716 }
 717
 718 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
 719                                                     struct sdw_msg *msg)
 720 {
 721         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 722         int ret, i, len;
 723
 724         if (msg->flags == SDW_MSG_FLAG_READ) {
 725                 for (i = 0; i < msg->len;) {
 726                         if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
 727                                 len = msg->len - i;
 728                         else
 729                                 len = QCOM_SWRM_MAX_RD_LEN;
 730
 731                         ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
 732                                                         msg->addr + i, len,
 733                                                        &msg->buf[i]);
 734                         if (ret)
 735                                 return ret;
 736
 737                         i = i + len;
 738                 }
 739         } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
 740                 for (i = 0; i < msg->len; i++) {
 741                         ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
 742                                                         msg->dev_num,
 743                                                        msg->addr + i);
 744                         if (ret)
 745                                 return SDW_CMD_IGNORED;
 746                 }
 747         }
 748
 749         return SDW_CMD_OK;
 750 }
 751
 752 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
 753 {
 754         u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
 755         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 756         u32 val;
 757
 758         ctrl->reg_read(ctrl, reg, &val);
 759
 760         u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
 761         u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
 762
 763         return ctrl->reg_write(ctrl, reg, val);
 764 }
 765
 766 static int qcom_swrm_port_params(struct sdw_bus *bus,
 767                                  struct sdw_port_params *p_params,
 768                                  unsigned int bank)
 769 {
 770         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 771
 772         return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
 773                                p_params->bps - 1);
 774
 775 }
 776
 777 static int qcom_swrm_transport_params(struct sdw_bus *bus,
 778                                       struct sdw_transport_params *params,
 779                                       enum sdw_reg_bank bank)
 780 {
 781         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 782         struct qcom_swrm_port_config *pcfg;
 783         u32 value;
 784         int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
 785         int ret;
 786
 787         pcfg = &ctrl->pconfig[params->port_num];
 788
 789         value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
 790         value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
 791         value |= pcfg->si;
 792
 793         ret = ctrl->reg_write(ctrl, reg, value);
 794         if (ret)
 795                 goto err;
 796
 797         if (pcfg->lane_control != SWR_INVALID_PARAM) {
 798                 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
 799                 value = pcfg->lane_control;
 800                 ret = ctrl->reg_write(ctrl, reg, value);
 801                 if (ret)
 802                         goto err;
 803         }
 804
 805         if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
 806                 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
 807                 value = pcfg->blk_group_count;
 808                 ret = ctrl->reg_write(ctrl, reg, value);
 809                 if (ret)
 810                         goto err;
 811         }
 812
 813         if (pcfg->hstart != SWR_INVALID_PARAM
 814                         && pcfg->hstop != SWR_INVALID_PARAM) {
 815                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 816                 value = (pcfg->hstop << 4) | pcfg->hstart;
 817                 ret = ctrl->reg_write(ctrl, reg, value);
 818         } else {
 819                 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
 820                 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
 821                 ret = ctrl->reg_write(ctrl, reg, value);
 822         }
 823
 824         if (ret)
 825                 goto err;
 826
 827         if (pcfg->bp_mode != SWR_INVALID_PARAM) {
 828                 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
 829                 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
 830         }
 831
 832 err:
 833         return ret;
 834 }
 835
 836 static int qcom_swrm_port_enable(struct sdw_bus *bus,
 837                                  struct sdw_enable_ch *enable_ch,
 838                                  unsigned int bank)
 839 {
 840         u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
 841         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 842         u32 val;
 843
 844         ctrl->reg_read(ctrl, reg, &val);
 845
 846         if (enable_ch->enable)
 847                 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 848         else
 849                 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
 850
 851         return ctrl->reg_write(ctrl, reg, val);
 852 }
 853
 854 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
 855         .dpn_set_port_params = qcom_swrm_port_params,
 856         .dpn_set_port_transport_params = qcom_swrm_transport_params,
 857         .dpn_port_enable_ch = qcom_swrm_port_enable,
 858 };
 859
 860 static const struct sdw_master_ops qcom_swrm_ops = {
 861         .xfer_msg = qcom_swrm_xfer_msg,
 862         .pre_bank_switch = qcom_swrm_pre_bank_switch,
 863 };
 864
 865 static int qcom_swrm_compute_params(struct sdw_bus *bus)
 866 {
 867         struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
 868         struct sdw_master_runtime *m_rt;
 869         struct sdw_slave_runtime *s_rt;
 870         struct sdw_port_runtime *p_rt;
 871         struct qcom_swrm_port_config *pcfg;
 872         struct sdw_slave *slave;
 873         unsigned int m_port;
 874         int i = 1;
 875
 876         list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
 877                 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
 878                         pcfg = &ctrl->pconfig[p_rt->num];
 879                         p_rt->transport_params.port_num = p_rt->num;
 880                         if (pcfg->word_length != SWR_INVALID_PARAM) {
 881                                 sdw_fill_port_params(&p_rt->port_params,
 882                                              p_rt->num,  pcfg->word_length + 1,
 883                                              SDW_PORT_FLOW_MODE_ISOCH,
 884                                              SDW_PORT_DATA_MODE_NORMAL);
 885                         }
 886
 887                 }
 888
 889                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 890                         slave = s_rt->slave;
 891                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 892                                 m_port = slave->m_port_map[p_rt->num];
 893                                 /* port config starts at offset 0 so -1 from actual port number */
 894                                 if (m_port)
 895                                         pcfg = &ctrl->pconfig[m_port];
 896                                 else
 897                                         pcfg = &ctrl->pconfig[i];
 898                                 p_rt->transport_params.port_num = p_rt->num;
 899                                 p_rt->transport_params.sample_interval =
 900                                         pcfg->si + 1;
 901                                 p_rt->transport_params.offset1 = pcfg->off1;
 902                                 p_rt->transport_params.offset2 = pcfg->off2;
 903                                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
 904                                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
 905
 906                                 p_rt->transport_params.hstart = pcfg->hstart;
 907                                 p_rt->transport_params.hstop = pcfg->hstop;
 908                                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
 909                                 if (pcfg->word_length != SWR_INVALID_PARAM) {
 910                                         sdw_fill_port_params(&p_rt->port_params,
 911                                                      p_rt->num,
 912                                                      pcfg->word_length + 1,
 913                                                      SDW_PORT_FLOW_MODE_ISOCH,
 914                                                      SDW_PORT_DATA_MODE_NORMAL);
 915                                 }
 916                                 i++;
 917                         }
 918                 }
 919         }
 920
 921         return 0;
 922 }
 923
 924 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
 925         DEFAULT_CLK_FREQ,
 926 };
 927
 928 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
 929                                         struct sdw_stream_runtime *stream)
 930 {
 931         struct sdw_master_runtime *m_rt;
 932         struct sdw_port_runtime *p_rt;
 933         unsigned long *port_mask;
 934
 935         mutex_lock(&ctrl->port_lock);
 936
 937         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 938                 if (m_rt->direction == SDW_DATA_DIR_RX)
 939                         port_mask = &ctrl->dout_port_mask;
 940                 else
 941                         port_mask = &ctrl->din_port_mask;
 942
 943                 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
 944                         clear_bit(p_rt->num, port_mask);
 945         }
 946
 947         mutex_unlock(&ctrl->port_lock);
 948 }
 949
 950 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
 951                                         struct sdw_stream_runtime *stream,
 952                                        struct snd_pcm_hw_params *params,
 953                                        int direction)
 954 {
 955         struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
 956         struct sdw_stream_config sconfig;
 957         struct sdw_master_runtime *m_rt;
 958         struct sdw_slave_runtime *s_rt;
 959         struct sdw_port_runtime *p_rt;
 960         struct sdw_slave *slave;
 961         unsigned long *port_mask;
 962         int i, maxport, pn, nports = 0, ret = 0;
 963         unsigned int m_port;
 964
 965         mutex_lock(&ctrl->port_lock);
 966         list_for_each_entry(m_rt, &stream->master_list, stream_node) {
 967                 if (m_rt->direction == SDW_DATA_DIR_RX) {
 968                         maxport = ctrl->num_dout_ports;
 969                         port_mask = &ctrl->dout_port_mask;
 970                 } else {
 971                         maxport = ctrl->num_din_ports;
 972                         port_mask = &ctrl->din_port_mask;
 973                 }
 974
 975                 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
 976                         slave = s_rt->slave;
 977                         list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
 978                                 m_port = slave->m_port_map[p_rt->num];
 979                                 /* Port numbers start from 1 - 14*/
 980                                 if (m_port)
 981                                         pn = m_port;
 982                                 else
 983                                         pn = find_first_zero_bit(port_mask, maxport);
 984
 985                                 if (pn > maxport) {
 986                                         dev_err(ctrl->dev, "All ports busy\n");
 987                                         ret = -EBUSY;
 988                                         goto err;
 989                                 }
 990                                 set_bit(pn, port_mask);
 991                                 pconfig[nports].num = pn;
 992                                 pconfig[nports].ch_mask = p_rt->ch_mask;
 993                                 nports++;
 994                         }
 995                 }
 996         }
 997
 998         if (direction == SNDRV_PCM_STREAM_CAPTURE)
 999                 sconfig.direction = SDW_DATA_DIR_TX;
1000         else
1001                 sconfig.direction = SDW_DATA_DIR_RX;
1002
1003         /* hw parameters wil be ignored as we only support PDM */
1004         sconfig.ch_count = 1;
1005         sconfig.frame_rate = params_rate(params);
1006         sconfig.type = stream->type;
1007         sconfig.bps = 1;
1008         sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1009                               nports, stream);
1010 err:
1011         if (ret) {
1012                 for (i = 0; i < nports; i++)
1013                         clear_bit(pconfig[i].num, port_mask);
1014         }
1015
1016         mutex_unlock(&ctrl->port_lock);
1017
1018         return ret;
1019 }
1020
1021 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1022                                struct snd_pcm_hw_params *params,
1023                               struct snd_soc_dai *dai)
1024 {
1025         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1026         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1027         int ret;
1028
1029         ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1030                                            substream->stream);
1031         if (ret)
1032                 qcom_swrm_stream_free_ports(ctrl, sruntime);
1033
1034         return ret;
1035 }
1036
1037 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1038                              struct snd_soc_dai *dai)
1039 {
1040         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1041         struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1042
1043         qcom_swrm_stream_free_ports(ctrl, sruntime);
1044         sdw_stream_remove_master(&ctrl->bus, sruntime);
1045
1046         return 0;
1047 }
1048
1049 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1050                                     void *stream, int direction)
1051 {
1052         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1053
1054         ctrl->sruntime[dai->id] = stream;
1055
1056         return 0;
1057 }
1058
1059 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1060 {
1061         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1062
1063         return ctrl->sruntime[dai->id];
1064 }
1065
1066 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1067                              struct snd_soc_dai *dai)
1068 {
1069         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1070         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1071         struct sdw_stream_runtime *sruntime;
1072         struct snd_soc_dai *codec_dai;
1073         int ret, i;
1074
1075         ret = pm_runtime_resume_and_get(ctrl->dev);
1076         if (ret < 0 && ret != -EACCES) {
1077                 dev_err_ratelimited(ctrl->dev,
1078                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1079                                     __func__, ret);
1080                 return ret;
1081         }
1082
1083         sruntime = sdw_alloc_stream(dai->name);
1084         if (!sruntime)
1085                 return -ENOMEM;
1086
1087         ctrl->sruntime[dai->id] = sruntime;
1088
1089         for_each_rtd_codec_dais(rtd, i, codec_dai) {
1090                 ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1091                                              substream->stream);
1092                 if (ret < 0 && ret != -ENOTSUPP) {
1093                         dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1094                                 codec_dai->name);
1095                         sdw_release_stream(sruntime);
1096                         return ret;
1097                 }
1098         }
1099
1100         return 0;
1101 }
1102
1103 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1104                                struct snd_soc_dai *dai)
1105 {
1106         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1107
1108         sdw_release_stream(ctrl->sruntime[dai->id]);
1109         ctrl->sruntime[dai->id] = NULL;
1110         pm_runtime_mark_last_busy(ctrl->dev);
1111         pm_runtime_put_autosuspend(ctrl->dev);
1112
1113 }
1114
1115 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1116         .hw_params = qcom_swrm_hw_params,
1117         .hw_free = qcom_swrm_hw_free,
1118         .startup = qcom_swrm_startup,
1119         .shutdown = qcom_swrm_shutdown,
1120         .set_stream = qcom_swrm_set_sdw_stream,
1121         .get_stream = qcom_swrm_get_sdw_stream,
1122 };
1123
1124 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1125         .name = "soundwire",
1126 };
1127
1128 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1129 {
1130         int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1131         struct snd_soc_dai_driver *dais;
1132         struct snd_soc_pcm_stream *stream;
1133         struct device *dev = ctrl->dev;
1134         int i;
1135
1136         /* PDM dais are only tested for now */
1137         dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1138         if (!dais)
1139                 return -ENOMEM;
1140
1141         for (i = 0; i < num_dais; i++) {
1142                 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1143                 if (!dais[i].name)
1144                         return -ENOMEM;
1145
1146                 if (i < ctrl->num_dout_ports)
1147                         stream = &dais[i].playback;
1148                 else
1149                         stream = &dais[i].capture;
1150
1151                 stream->channels_min = 1;
1152                 stream->channels_max = 1;
1153                 stream->rates = SNDRV_PCM_RATE_48000;
1154                 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1155
1156                 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1157                 dais[i].id = i;
1158         }
1159
1160         return devm_snd_soc_register_component(ctrl->dev,
1161                                                 &qcom_swrm_dai_component,
1162                                                 dais, num_dais);
1163 }
1164
1165 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1166 {
1167         struct device_node *np = ctrl->dev->of_node;
1168         u8 off1[QCOM_SDW_MAX_PORTS];
1169         u8 off2[QCOM_SDW_MAX_PORTS];
1170         u8 si[QCOM_SDW_MAX_PORTS];
1171         u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1172         u8 hstart[QCOM_SDW_MAX_PORTS];
1173         u8 hstop[QCOM_SDW_MAX_PORTS];
1174         u8 word_length[QCOM_SDW_MAX_PORTS];
1175         u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1176         u8 lane_control[QCOM_SDW_MAX_PORTS];
1177         int i, ret, nports, val;
1178
1179         ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1180
1181         ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1182         ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1183
1184         ret = of_property_read_u32(np, "qcom,din-ports", &val);
1185         if (ret)
1186                 return ret;
1187
1188         if (val > ctrl->num_din_ports)
1189                 return -EINVAL;
1190
1191         ctrl->num_din_ports = val;
1192
1193         ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1194         if (ret)
1195                 return ret;
1196
1197         if (val > ctrl->num_dout_ports)
1198                 return -EINVAL;
1199
1200         ctrl->num_dout_ports = val;
1201
1202         nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1203         /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1204         set_bit(0, &ctrl->dout_port_mask);
1205         set_bit(0, &ctrl->din_port_mask);
1206
1207         ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1208                                         off1, nports);
1209         if (ret)
1210                 return ret;
1211
1212         ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1213                                         off2, nports);
1214         if (ret)
1215                 return ret;
1216
1217         ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1218                                         si, nports);
1219         if (ret)
1220                 return ret;
1221
1222         ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1223                                         bp_mode, nports);
1224         if (ret) {
1225                 if (ctrl->version <= 0x01030000)
1226                         memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1227                 else
1228                         return ret;
1229         }
1230
1231         memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1232         of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1233
1234         memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1235         of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1236
1237         memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1238         of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1239
1240         memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1241         of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1242
1243         memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1244         of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1245
1246         for (i = 0; i < nports; i++) {
1247                 /* Valid port number range is from 1-14 */
1248                 ctrl->pconfig[i + 1].si = si[i];
1249                 ctrl->pconfig[i + 1].off1 = off1[i];
1250                 ctrl->pconfig[i + 1].off2 = off2[i];
1251                 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1252                 ctrl->pconfig[i + 1].hstart = hstart[i];
1253                 ctrl->pconfig[i + 1].hstop = hstop[i];
1254                 ctrl->pconfig[i + 1].word_length = word_length[i];
1255                 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1256                 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1257         }
1258
1259         return 0;
1260 }
1261
1262 #ifdef CONFIG_DEBUG_FS
1263 static int swrm_reg_show(struct seq_file *s_file, void *data)
1264 {
1265         struct qcom_swrm_ctrl *swrm = s_file->private;
1266         int reg, reg_val, ret;
1267
1268         ret = pm_runtime_resume_and_get(swrm->dev);
1269         if (ret < 0 && ret != -EACCES) {
1270                 dev_err_ratelimited(swrm->dev,
1271                                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1272                                     __func__, ret);
1273                 return ret;
1274         }
1275
1276         for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1277                 swrm->reg_read(swrm, reg, &reg_val);
1278                 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1279         }
1280         pm_runtime_mark_last_busy(swrm->dev);
1281         pm_runtime_put_autosuspend(swrm->dev);
1282
1283
1284         return 0;
1285 }
1286 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1287 #endif
1288
1289 static int qcom_swrm_probe(struct platform_device *pdev)
1290 {
1291         struct device *dev = &pdev->dev;
1292         struct sdw_master_prop *prop;
1293         struct sdw_bus_params *params;
1294         struct qcom_swrm_ctrl *ctrl;
1295         const struct qcom_swrm_data *data;
1296         int ret;
1297         u32 val;
1298
1299         ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1300         if (!ctrl)
1301                 return -ENOMEM;
1302
1303         data = of_device_get_match_data(dev);
1304         ctrl->rows_index = sdw_find_row_index(data->default_rows);
1305         ctrl->cols_index = sdw_find_col_index(data->default_cols);
1306 #if IS_REACHABLE(CONFIG_SLIMBUS)
1307         if (dev->parent->bus == &slimbus_bus) {
1308 #else
1309         if (false) {
1310 #endif
1311                 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1312                 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1313                 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1314                 if (!ctrl->regmap)
1315                         return -EINVAL;
1316         } else {
1317                 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1318                 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1319                 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1320                 if (IS_ERR(ctrl->mmio))
1321                         return PTR_ERR(ctrl->mmio);
1322         }
1323
1324         if (data->sw_clk_gate_required) {
1325                 ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr");
1326                 if (IS_ERR_OR_NULL(ctrl->audio_cgcr)) {
1327                         dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1328                         ret = PTR_ERR(ctrl->audio_cgcr);
1329                         goto err_init;
1330                 }
1331         }
1332
1333         ctrl->irq = of_irq_get(dev->of_node, 0);
1334         if (ctrl->irq < 0) {
1335                 ret = ctrl->irq;
1336                 goto err_init;
1337         }
1338
1339         ctrl->hclk = devm_clk_get(dev, "iface");
1340         if (IS_ERR(ctrl->hclk)) {
1341                 ret = PTR_ERR(ctrl->hclk);
1342                 goto err_init;
1343         }
1344
1345         clk_prepare_enable(ctrl->hclk);
1346
1347         ctrl->dev = dev;
1348         dev_set_drvdata(&pdev->dev, ctrl);
1349         mutex_init(&ctrl->port_lock);
1350         init_completion(&ctrl->broadcast);
1351         init_completion(&ctrl->enumeration);
1352
1353         ctrl->bus.ops = &qcom_swrm_ops;
1354         ctrl->bus.port_ops = &qcom_swrm_port_ops;
1355         ctrl->bus.compute_params = &qcom_swrm_compute_params;
1356         ctrl->bus.clk_stop_timeout = 300;
1357
1358         ret = qcom_swrm_get_port_config(ctrl);
1359         if (ret)
1360                 goto err_clk;
1361
1362         params = &ctrl->bus.params;
1363         params->max_dr_freq = DEFAULT_CLK_FREQ;
1364         params->curr_dr_freq = DEFAULT_CLK_FREQ;
1365         params->col = data->default_cols;
1366         params->row = data->default_rows;
1367         ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1368         params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1369         params->next_bank = !params->curr_bank;
1370
1371         prop = &ctrl->bus.prop;
1372         prop->max_clk_freq = DEFAULT_CLK_FREQ;
1373         prop->num_clk_gears = 0;
1374         prop->num_clk_freq = MAX_FREQ_NUM;
1375         prop->clk_freq = &qcom_swrm_freq_tbl[0];
1376         prop->default_col = data->default_cols;
1377         prop->default_row = data->default_rows;
1378
1379         ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1380
1381         ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1382                                         qcom_swrm_irq_handler,
1383                                         IRQF_TRIGGER_RISING |
1384                                         IRQF_ONESHOT,
1385                                         "soundwire", ctrl);
1386         if (ret) {
1387                 dev_err(dev, "Failed to request soundwire irq\n");
1388                 goto err_clk;
1389         }
1390
1391         ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1392         if (ctrl->wake_irq > 0) {
1393                 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1394                                                 qcom_swrm_wake_irq_handler,
1395                                                 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1396                                                 "swr_wake_irq", ctrl);
1397                 if (ret) {
1398                         dev_err(dev, "Failed to request soundwire wake irq\n");
1399                         goto err_init;
1400                 }
1401         }
1402
1403         ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1404         if (ret) {
1405                 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1406                         ret);
1407                 goto err_clk;
1408         }
1409
1410         qcom_swrm_init(ctrl);
1411         wait_for_completion_timeout(&ctrl->enumeration,
1412                                     msecs_to_jiffies(TIMEOUT_MS));
1413         ret = qcom_swrm_register_dais(ctrl);
1414         if (ret)
1415                 goto err_master_add;
1416
1417         dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1418                  (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1419                  ctrl->version & 0xffff);
1420
1421         pm_runtime_set_autosuspend_delay(dev, 3000);
1422         pm_runtime_use_autosuspend(dev);
1423         pm_runtime_mark_last_busy(dev);
1424         pm_runtime_set_active(dev);
1425         pm_runtime_enable(dev);
1426
1427         /* Clk stop is not supported on WSA Soundwire masters */
1428         if (ctrl->version <= 0x01030000) {
1429                 ctrl->clock_stop_not_supported = true;
1430         } else {
1431                 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1432                 if (val == MASTER_ID_WSA)
1433                         ctrl->clock_stop_not_supported = true;
1434         }
1435
1436 #ifdef CONFIG_DEBUG_FS
1437         ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1438         debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1439                             &swrm_reg_fops);
1440 #endif
1441
1442         return 0;
1443
1444 err_master_add:
1445         sdw_bus_master_delete(&ctrl->bus);
1446 err_clk:
1447         clk_disable_unprepare(ctrl->hclk);
1448 err_init:
1449         return ret;
1450 }
1451
1452 static int qcom_swrm_remove(struct platform_device *pdev)
1453 {
1454         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1455
1456         sdw_bus_master_delete(&ctrl->bus);
1457         clk_disable_unprepare(ctrl->hclk);
1458
1459         return 0;
1460 }
1461
1462 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
1463 {
1464         int retry = SWRM_LINK_STATUS_RETRY_CNT;
1465         int comp_sts;
1466
1467         do {
1468                 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
1469
1470                 if (comp_sts & SWRM_FRM_GEN_ENABLED)
1471                         return true;
1472
1473                 usleep_range(500, 510);
1474         } while (retry--);
1475
1476         dev_err(swrm->dev, "%s: link status not %s\n", __func__,
1477                 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1478
1479         return false;
1480 }
1481
1482 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1483 {
1484         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1485         int ret;
1486
1487         if (ctrl->wake_irq > 0) {
1488                 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1489                         disable_irq_nosync(ctrl->wake_irq);
1490         }
1491
1492         clk_prepare_enable(ctrl->hclk);
1493
1494         if (ctrl->clock_stop_not_supported) {
1495                 reinit_completion(&ctrl->enumeration);
1496                 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1497                 usleep_range(100, 105);
1498
1499                 qcom_swrm_init(ctrl);
1500
1501                 usleep_range(100, 105);
1502                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1503                         dev_err(ctrl->dev, "link failed to connect\n");
1504
1505                 /* wait for hw enumeration to complete */
1506                 wait_for_completion_timeout(&ctrl->enumeration,
1507                                             msecs_to_jiffies(TIMEOUT_MS));
1508                 qcom_swrm_get_device_status(ctrl);
1509                 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1510         } else {
1511                 reset_control_reset(ctrl->audio_cgcr);
1512
1513                 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1514                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1515                         SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1516
1517                 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1518                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1519                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1520
1521                 usleep_range(100, 105);
1522                 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1523                         dev_err(ctrl->dev, "link failed to connect\n");
1524
1525                 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1526                 if (ret < 0)
1527                         dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1528         }
1529
1530         return 0;
1531 }
1532
1533 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1534 {
1535         struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1536         int ret;
1537
1538         if (!ctrl->clock_stop_not_supported) {
1539                 /* Mask bus clash interrupt */
1540                 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1541                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1542                 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1543                 /* Prepare slaves for clock stop */
1544                 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1545                 if (ret < 0 && ret != -ENODATA) {
1546                         dev_err(dev, "prepare clock stop failed %d", ret);
1547                         return ret;
1548                 }
1549
1550                 ret = sdw_bus_clk_stop(&ctrl->bus);
1551                 if (ret < 0 && ret != -ENODATA) {
1552                         dev_err(dev, "bus clock stop failed %d", ret);
1553                         return ret;
1554                 }
1555         }
1556
1557         clk_disable_unprepare(ctrl->hclk);
1558
1559         usleep_range(300, 305);
1560
1561         if (ctrl->wake_irq > 0) {
1562                 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1563                         enable_irq(ctrl->wake_irq);
1564         }
1565
1566         return 0;
1567 }
1568
1569 static const struct dev_pm_ops swrm_dev_pm_ops = {
1570         SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1571 };
1572
1573 static const struct of_device_id qcom_swrm_of_match[] = {
1574         { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1575         { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1576         { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1577         {/* sentinel */},
1578 };
1579
1580 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1581
1582 static struct platform_driver qcom_swrm_driver = {
1583         .probe  = &qcom_swrm_probe,
1584         .remove = &qcom_swrm_remove,
1585         .driver = {
1586                 .name   = "qcom-soundwire",
1587                 .of_match_table = qcom_swrm_of_match,
1588                 .pm = &swrm_dev_pm_ops,
1589         }
1590 };
1591 module_platform_driver(qcom_swrm_driver);
1592
1593 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1594 MODULE_LICENSE("GPL v2");