drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "amdgpu_dm_psr.h"
  27 #include "dc.h"
  28 #include "dm_helpers.h"
  29 #include "amdgpu_dm.h"
  30 #include "modules/power/power_helpers.h"
  31
  32 static bool link_supports_psrsu(struct dc_link *link)
  33 {
  34         struct dc *dc = link->ctx->dc;
  35
  36         if (!dc->caps.dmcub_support)
  37                 return false;
  38
  39         if (dc->ctx->dce_version < DCN_VERSION_3_1)
  40                 return false;
  41
  42         if (!is_psr_su_specific_panel(link))
  43                 return false;
  44
  45         if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
  46             !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
  47                 return false;
  48
  49         if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&
  50             !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
  51                 return false;
  52
  53         return true;
  54 }
  55
  56 /*
  57  * amdgpu_dm_set_psr_caps() - set link psr capabilities
  58  * @link: link
  59  *
  60  */
  61 void amdgpu_dm_set_psr_caps(struct dc_link *link)
  62 {
  63         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
  64                 return;
  65
  66         if (link->type == dc_connection_none)
  67                 return;
  68
  69         if (link->dpcd_caps.psr_info.psr_version == 0) {
  70                 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
  71                 link->psr_settings.psr_feature_enabled = false;
  72
  73         } else {
  74                 if (link_supports_psrsu(link))
  75                         link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
  76                 else
  77                         link->psr_settings.psr_version = DC_PSR_VERSION_1;
  78
  79                 link->psr_settings.psr_feature_enabled = true;
  80         }
  81
  82         DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
  83                 link->psr_settings.psr_feature_enabled,
  84                 link->psr_settings.psr_version,
  85                 link->dpcd_caps.psr_info.psr_version,
  86                 link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
  87                 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap);
  88
  89 }
  90
  91 /*
  92  * amdgpu_dm_link_setup_psr() - configure psr link
  93  * @stream: stream state
  94  *
  95  * Return: true if success
  96  */
  97 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
  98 {
  99         struct dc_link *link = NULL;
 100         struct psr_config psr_config = {0};
 101         struct psr_context psr_context = {0};
 102         struct dc *dc = NULL;
 103         bool ret = false;
 104
 105         if (stream == NULL)
 106                 return false;
 107
 108         link = stream->link;
 109         dc = link->ctx->dc;
 110
 111         if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
 112                 mod_power_calc_psr_configs(&psr_config, link, stream);
 113
 114                 /* linux DM specific updating for psr config fields */
 115                 psr_config.allow_smu_optimizations =
 116                         (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
 117                         mod_power_only_edp(dc->current_state, stream);
 118                 psr_config.allow_multi_disp_optimizations =
 119                         (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
 120
 121                 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
 122
 123         }
 124         DRM_DEBUG_DRIVER("PSR link: %d\n",      link->psr_settings.psr_feature_enabled);
 125
 126         return ret;
 127 }
 128
 129 /*
 130  * amdgpu_dm_psr_enable() - enable psr f/w
 131  * @stream: stream state
 132  *
 133  * Return: true if success
 134  */
 135 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
 136 {
 137         struct dc_link *link = stream->link;
 138         unsigned int vsync_rate_hz = 0;
 139         struct dc_static_screen_params params = {0};
 140         /* Calculate number of static frames before generating interrupt to
 141          * enter PSR.
 142          */
 143         // Init fail safe of 2 frames static
 144         unsigned int num_frames_static = 2;
 145         unsigned int power_opt = 0;
 146         bool psr_enable = true;
 147
 148         DRM_DEBUG_DRIVER("Enabling psr...\n");
 149
 150         vsync_rate_hz = div64_u64(div64_u64((
 151                         stream->timing.pix_clk_100hz * 100),
 152                         stream->timing.v_total),
 153                         stream->timing.h_total);
 154
 155         /* Round up
 156          * Calculate number of frames such that at least 30 ms of time has
 157          * passed.
 158          */
 159         if (vsync_rate_hz != 0) {
 160                 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
 161                 num_frames_static = (30000 / frame_time_microsec) + 1;
 162         }
 163
 164         params.triggers.cursor_update = true;
 165         params.triggers.overlay_update = true;
 166         params.triggers.surface_update = true;
 167         params.num_frames = num_frames_static;
 168
 169         dc_stream_set_static_screen_params(link->ctx->dc,
 170                                            &stream, 1,
 171                                            &params);
 172
 173         power_opt |= psr_power_opt_z10_static_screen;
 174
 175         return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
 176 }
 177
 178 /*
 179  * amdgpu_dm_psr_disable() - disable psr f/w
 180  * @stream:  stream state
 181  *
 182  * Return: true if success
 183  */
 184 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
 185 {
 186         unsigned int power_opt = 0;
 187         bool psr_enable = false;
 188
 189         DRM_DEBUG_DRIVER("Disabling psr...\n");
 190
 191         return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);
 192 }
 193
 194 /*
 195  * amdgpu_dm_psr_disable() - disable psr f/w
 196  * if psr is enabled on any stream
 197  *
 198  * Return: true if success
 199  */
 200 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
 201 {
 202         DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
 203         return dc_set_psr_allow_active(dm->dc, false);
 204 }
 205