drivers/mailbox/imx-mailbox.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 Pengutronix, Oleksij Rempel <[email protected]>
   4  * Copyright 2022 NXP, Peng Fan <[email protected]>
   5  */
   6
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/firmware/imx/ipc.h>
  10 #include <linux/firmware/imx/s4.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/jiffies.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mailbox_controller.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/suspend.h>
  23 #include <linux/slab.h>
  24 #include <linux/workqueue.h>
  25
  26 #include "mailbox.h"
  27
  28 #define IMX_MU_CHANS            24
  29 /* TX0/RX0/RXDB[0-3] */
  30 #define IMX_MU_SCU_CHANS        6
  31 /* TX0/RX0 */
  32 #define IMX_MU_S4_CHANS         2
  33 #define IMX_MU_CHAN_NAME_SIZE   20
  34
  35 #define IMX_MU_V2_PAR_OFF       0x4
  36 #define IMX_MU_V2_TR_MASK       GENMASK(7, 0)
  37 #define IMX_MU_V2_RR_MASK       GENMASK(15, 8)
  38
  39 #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
  40 #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
  41
  42 /* Please not change TX & RX */
  43 enum imx_mu_chan_type {
  44         IMX_MU_TYPE_TX          = 0, /* Tx */
  45         IMX_MU_TYPE_RX          = 1, /* Rx */
  46         IMX_MU_TYPE_TXDB        = 2, /* Tx doorbell */
  47         IMX_MU_TYPE_RXDB        = 3, /* Rx doorbell */
  48         IMX_MU_TYPE_RST         = 4, /* Reset */
  49         IMX_MU_TYPE_TXDB_V2     = 5, /* Tx doorbell with S/W ACK */
  50 };
  51
  52 enum imx_mu_xcr {
  53         IMX_MU_CR,
  54         IMX_MU_GIER,
  55         IMX_MU_GCR,
  56         IMX_MU_TCR,
  57         IMX_MU_RCR,
  58         IMX_MU_xCR_MAX,
  59 };
  60
  61 enum imx_mu_xsr {
  62         IMX_MU_SR,
  63         IMX_MU_GSR,
  64         IMX_MU_TSR,
  65         IMX_MU_RSR,
  66         IMX_MU_xSR_MAX,
  67 };
  68
  69 struct imx_sc_rpc_msg_max {
  70         struct imx_sc_rpc_msg hdr;
  71         u32 data[30];
  72 };
  73
  74 struct imx_s4_rpc_msg_max {
  75         struct imx_s4_rpc_msg hdr;
  76         u32 data[254];
  77 };
  78
  79 struct imx_mu_con_priv {
  80         unsigned int            idx;
  81         char                    irq_desc[IMX_MU_CHAN_NAME_SIZE];
  82         enum imx_mu_chan_type   type;
  83         struct mbox_chan        *chan;
  84         struct work_struct      txdb_work;
  85 };
  86
  87 struct imx_mu_priv {
  88         struct device           *dev;
  89         void __iomem            *base;
  90         void                    *msg;
  91         spinlock_t              xcr_lock; /* control register lock */
  92
  93         struct mbox_controller  mbox;
  94         struct mbox_chan        mbox_chans[IMX_MU_CHANS];
  95
  96         struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
  97         const struct imx_mu_dcfg        *dcfg;
  98         struct clk              *clk;
  99         int                     irq[IMX_MU_CHANS];
 100         bool                    suspend;
 101         bool                    side_b;
 102
 103         u32                     xcr[IMX_MU_xCR_MAX];
 104         u32                     num_tr;
 105         u32                     num_rr;
 106 };
 107
 108 enum imx_mu_type {
 109         IMX_MU_V1,
 110         IMX_MU_V2 = BIT(1),
 111         IMX_MU_V2_S4 = BIT(15),
 112         IMX_MU_V2_IRQ = BIT(16),
 113 };
 114
 115 struct imx_mu_dcfg {
 116         int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
 117         int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
 118         int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
 119         int (*init)(struct imx_mu_priv *priv);
 120         enum imx_mu_type type;
 121         u32     xTR;            /* Transmit Register0 */
 122         u32     xRR;            /* Receive Register0 */
 123         u32     xSR[IMX_MU_xSR_MAX];    /* Status Registers */
 124         u32     xCR[IMX_MU_xCR_MAX];    /* Control Registers */
 125 };
 126
 127 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
 128 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
 129 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
 130
 131 /* General Purpose Interrupt Enable */
 132 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
 133 /* Receive Interrupt Enable */
 134 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
 135 /* Transmit Interrupt Enable */
 136 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
 137 /* General Purpose Interrupt Request */
 138 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
 139 /* MU reset */
 140 #define IMX_MU_xCR_RST(type)    (type & IMX_MU_V2 ? BIT(0) : BIT(5))
 141 #define IMX_MU_xSR_RST(type)    (type & IMX_MU_V2 ? BIT(0) : BIT(7))
 142
 143
 144 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
 145 {
 146         return container_of(mbox, struct imx_mu_priv, mbox);
 147 }
 148
 149 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
 150 {
 151         iowrite32(val, priv->base + offs);
 152 }
 153
 154 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
 155 {
 156         return ioread32(priv->base + offs);
 157 }
 158
 159 static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
 160 {
 161         u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;
 162         u32 status;
 163         u32 can_write;
 164
 165         dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
 166
 167         do {
 168                 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
 169                 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
 170         } while (!can_write && time_is_after_jiffies64(timeout_time));
 171
 172         if (!can_write) {
 173                 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
 174                         val, idx, status);
 175                 return -ETIME;
 176         }
 177
 178         imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
 179
 180         return 0;
 181 }
 182
 183 static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
 184 {
 185         u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;
 186         u32 status;
 187         u32 can_read;
 188
 189         dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
 190
 191         do {
 192                 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
 193                 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
 194         } while (!can_read && time_is_after_jiffies64(timeout_time));
 195
 196         if (!can_read) {
 197                 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
 198                         idx, status);
 199                 return -ETIME;
 200         }
 201
 202         *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
 203         dev_dbg(priv->dev, "Read %.8x\n", *val);
 204
 205         return 0;
 206 }
 207
 208 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
 209 {
 210         unsigned long flags;
 211         u32 val;
 212
 213         spin_lock_irqsave(&priv->xcr_lock, flags);
 214         val = imx_mu_read(priv, priv->dcfg->xCR[type]);
 215         val &= ~clr;
 216         val |= set;
 217         imx_mu_write(priv, val, priv->dcfg->xCR[type]);
 218         spin_unlock_irqrestore(&priv->xcr_lock, flags);
 219
 220         return val;
 221 }
 222
 223 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
 224                              struct imx_mu_con_priv *cp,
 225                              void *data)
 226 {
 227         u32 *arg = data;
 228
 229         switch (cp->type) {
 230         case IMX_MU_TYPE_TX:
 231                 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
 232                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
 233                 break;
 234         case IMX_MU_TYPE_TXDB:
 235                 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
 236                 queue_work(system_bh_wq, &cp->txdb_work);
 237                 break;
 238         case IMX_MU_TYPE_TXDB_V2:
 239                 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
 240                 break;
 241         default:
 242                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 243                 return -EINVAL;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
 250                              struct imx_mu_con_priv *cp)
 251 {
 252         u32 dat;
 253
 254         dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
 255         mbox_chan_received_data(cp->chan, (void *)&dat);
 256
 257         return 0;
 258 }
 259
 260 static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
 261                                struct imx_mu_con_priv *cp)
 262 {
 263         imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
 264                      priv->dcfg->xSR[IMX_MU_GSR]);
 265         mbox_chan_received_data(cp->chan, NULL);
 266
 267         return 0;
 268 }
 269
 270 static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
 271 {
 272         u32 *arg = data;
 273         u32 num_tr = priv->num_tr;
 274         int i, ret;
 275         u32 xsr;
 276         u32 size, max_size;
 277
 278         if (priv->dcfg->type & IMX_MU_V2_S4) {
 279                 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
 280                 max_size = sizeof(struct imx_s4_rpc_msg_max);
 281         } else {
 282                 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
 283                 max_size = sizeof(struct imx_sc_rpc_msg_max);
 284         }
 285
 286         switch (cp->type) {
 287         case IMX_MU_TYPE_TX:
 288                 /*
 289                  * msg->hdr.size specifies the number of u32 words while
 290                  * sizeof yields bytes.
 291                  */
 292
 293                 if (size > max_size / 4) {
 294                         /*
 295                          * The real message size can be different to
 296                          * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size
 297                          */
 298                         dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
 299                         return -EINVAL;
 300                 }
 301
 302                 for (i = 0; i < num_tr && i < size; i++)
 303                         imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
 304                 for (; i < size; i++) {
 305                         ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
 306                                                  xsr,
 307                                                  xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
 308                                                  0, 5 * USEC_PER_SEC);
 309                         if (ret) {
 310                                 dev_err(priv->dev, "Send data index: %d timeout\n", i);
 311                                 return ret;
 312                         }
 313                         imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
 314                 }
 315
 316                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
 317                 break;
 318         default:
 319                 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
 320                 return -EINVAL;
 321         }
 322
 323         return 0;
 324 }
 325
 326 static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
 327 {
 328         u32 *data;
 329         int i, ret;
 330         u32 xsr;
 331         u32 size, max_size;
 332         u32 num_rr = priv->num_rr;
 333
 334         data = (u32 *)priv->msg;
 335
 336         imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
 337         *data++ = imx_mu_read(priv, priv->dcfg->xRR);
 338
 339         if (priv->dcfg->type & IMX_MU_V2_S4) {
 340                 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
 341                 max_size = sizeof(struct imx_s4_rpc_msg_max);
 342         } else {
 343                 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
 344                 max_size = sizeof(struct imx_sc_rpc_msg_max);
 345         }
 346
 347         if (size > max_size / 4) {
 348                 dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
 349                 return -EINVAL;
 350         }
 351
 352         for (i = 1; i < size; i++) {
 353                 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
 354                                          xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0,
 355                                          5 * USEC_PER_SEC);
 356                 if (ret) {
 357                         dev_err(priv->dev, "timeout read idx %d\n", i);
 358                         return ret;
 359                 }
 360                 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
 361         }
 362
 363         imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
 364         mbox_chan_received_data(cp->chan, (void *)priv->msg);
 365
 366         return 0;
 367 }
 368
 369 static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
 370                           void *data)
 371 {
 372         struct imx_sc_rpc_msg_max *msg = data;
 373         u32 *arg = data;
 374         u32 byte_size;
 375         int err;
 376         int i;
 377
 378         dev_dbg(priv->dev, "Sending message\n");
 379
 380         switch (cp->type) {
 381         case IMX_MU_TYPE_TXDB:
 382                 byte_size = msg->hdr.size * sizeof(u32);
 383                 if (byte_size > sizeof(*msg)) {
 384                         /*
 385                          * The real message size can be different to
 386                          * struct imx_sc_rpc_msg_max size
 387                          */
 388                         dev_err(priv->dev,
 389                                 "Exceed max msg size (%zu) on TX, got: %i\n",
 390                                 sizeof(*msg), byte_size);
 391                         return -EINVAL;
 392                 }
 393
 394                 print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4,
 395                                      data, byte_size, false);
 396
 397                 /* Send first word */
 398                 dev_dbg(priv->dev, "Sending header\n");
 399                 imx_mu_write(priv, *arg++, priv->dcfg->xTR);
 400
 401                 /* Send signaling */
 402                 dev_dbg(priv->dev, "Sending signaling\n");
 403                 imx_mu_xcr_rmw(priv, IMX_MU_GCR,
 404                                IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
 405
 406                 /* Send words to fill the mailbox */
 407                 for (i = 1; i < 4 && i < msg->hdr.size; i++) {
 408                         dev_dbg(priv->dev, "Sending word %d\n", i);
 409                         imx_mu_write(priv, *arg++,
 410                                      priv->dcfg->xTR + (i % 4) * 4);
 411                 }
 412
 413                 /* Send rest of message waiting for remote read */
 414                 for (; i < msg->hdr.size; i++) {
 415                         dev_dbg(priv->dev, "Sending word %d\n", i);
 416                         err = imx_mu_tx_waiting_write(priv, *arg++, i);
 417                         if (err) {
 418                                 dev_err(priv->dev, "Timeout tx %d\n", i);
 419                                 return err;
 420                         }
 421                 }
 422
 423                 /* Simulate hack for mbox framework */
 424                 queue_work(system_bh_wq, &cp->txdb_work);
 425
 426                 break;
 427         default:
 428                 dev_warn_ratelimited(priv->dev,
 429                                      "Send data on wrong channel type: %d\n",
 430                                      cp->type);
 431                 return -EINVAL;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
 438 {
 439         struct imx_sc_rpc_msg_max msg;
 440         u32 *data = (u32 *)&msg;
 441         u32 byte_size;
 442         int err = 0;
 443         int i;
 444
 445         dev_dbg(priv->dev, "Receiving message\n");
 446
 447         /* Read header */
 448         dev_dbg(priv->dev, "Receiving header\n");
 449         *data++ = imx_mu_read(priv, priv->dcfg->xRR);
 450         byte_size = msg.hdr.size * sizeof(u32);
 451         if (byte_size > sizeof(msg)) {
 452                 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
 453                         sizeof(msg), byte_size);
 454                 err = -EINVAL;
 455                 goto error;
 456         }
 457
 458         /* Read message waiting they are written */
 459         for (i = 1; i < msg.hdr.size; i++) {
 460                 dev_dbg(priv->dev, "Receiving word %d\n", i);
 461                 err = imx_mu_rx_waiting_read(priv, data++, i);
 462                 if (err) {
 463                         dev_err(priv->dev, "Timeout rx %d\n", i);
 464                         goto error;
 465                 }
 466         }
 467
 468         /* Clear GIP */
 469         imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
 470                      priv->dcfg->xSR[IMX_MU_GSR]);
 471
 472         print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4,
 473                              &msg, byte_size, false);
 474
 475         /* send data to client */
 476         dev_dbg(priv->dev, "Sending message to client\n");
 477         mbox_chan_received_data(cp->chan, (void *)&msg);
 478
 479         goto exit;
 480
 481 error:
 482         mbox_chan_received_data(cp->chan, ERR_PTR(err));
 483
 484 exit:
 485         return err;
 486 }
 487
 488 static void imx_mu_txdb_work(struct work_struct *t)
 489 {
 490         struct imx_mu_con_priv *cp = from_work(cp, t, txdb_work);
 491
 492         mbox_chan_txdone(cp->chan, 0);
 493 }
 494
 495 static irqreturn_t imx_mu_isr(int irq, void *p)
 496 {
 497         struct mbox_chan *chan = p;
 498         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 499         struct imx_mu_con_priv *cp = chan->con_priv;
 500         u32 val, ctrl;
 501
 502         switch (cp->type) {
 503         case IMX_MU_TYPE_TX:
 504                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
 505                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
 506                 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
 507                         (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 508                 break;
 509         case IMX_MU_TYPE_RX:
 510                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
 511                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
 512                 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
 513                         (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
 514                 break;
 515         case IMX_MU_TYPE_RXDB:
 516                 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
 517                 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
 518                 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
 519                         (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
 520                 break;
 521         case IMX_MU_TYPE_RST:
 522                 return IRQ_NONE;
 523         default:
 524                 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
 525                                      cp->type);
 526                 return IRQ_NONE;
 527         }
 528
 529         if (!val)
 530                 return IRQ_NONE;
 531
 532         if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
 533             (cp->type == IMX_MU_TYPE_TX)) {
 534                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 535                 mbox_chan_txdone(chan, 0);
 536         } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
 537                    (cp->type == IMX_MU_TYPE_RX)) {
 538                 priv->dcfg->rx(priv, cp);
 539         } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
 540                    (cp->type == IMX_MU_TYPE_RXDB)) {
 541                 priv->dcfg->rxdb(priv, cp);
 542         } else {
 543                 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
 544                 return IRQ_NONE;
 545         }
 546
 547         if (priv->suspend)
 548                 pm_system_wakeup();
 549
 550         return IRQ_HANDLED;
 551 }
 552
 553 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
 554 {
 555         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 556         struct imx_mu_con_priv *cp = chan->con_priv;
 557
 558         return priv->dcfg->tx(priv, cp, data);
 559 }
 560
 561 static int imx_mu_startup(struct mbox_chan *chan)
 562 {
 563         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 564         struct imx_mu_con_priv *cp = chan->con_priv;
 565         unsigned long irq_flag = 0;
 566         int ret;
 567
 568         pm_runtime_get_sync(priv->dev);
 569         if (cp->type == IMX_MU_TYPE_TXDB_V2)
 570                 return 0;
 571
 572         if (cp->type == IMX_MU_TYPE_TXDB) {
 573                 /* Tx doorbell don't have ACK support */
 574                 INIT_WORK(&cp->txdb_work, imx_mu_txdb_work);
 575                 return 0;
 576         }
 577
 578         /* IPC MU should be with IRQF_NO_SUSPEND set */
 579         if (!priv->dev->pm_domain)
 580                 irq_flag |= IRQF_NO_SUSPEND;
 581
 582         if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
 583                 irq_flag |= IRQF_SHARED;
 584
 585         ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);
 586         if (ret) {
 587                 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);
 588                 return ret;
 589         }
 590
 591         switch (cp->type) {
 592         case IMX_MU_TYPE_RX:
 593                 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
 594                 break;
 595         case IMX_MU_TYPE_RXDB:
 596                 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
 597                 break;
 598         default:
 599                 break;
 600         }
 601
 602         return 0;
 603 }
 604
 605 static void imx_mu_shutdown(struct mbox_chan *chan)
 606 {
 607         struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
 608         struct imx_mu_con_priv *cp = chan->con_priv;
 609         int ret;
 610         u32 sr;
 611
 612         if (cp->type == IMX_MU_TYPE_TXDB_V2) {
 613                 pm_runtime_put_sync(priv->dev);
 614                 return;
 615         }
 616
 617         if (cp->type == IMX_MU_TYPE_TXDB) {
 618                 cancel_work_sync(&cp->txdb_work);
 619                 pm_runtime_put_sync(priv->dev);
 620                 return;
 621         }
 622
 623         switch (cp->type) {
 624         case IMX_MU_TYPE_TX:
 625                 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
 626                 break;
 627         case IMX_MU_TYPE_RX:
 628                 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
 629                 break;
 630         case IMX_MU_TYPE_RXDB:
 631                 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
 632                 break;
 633         case IMX_MU_TYPE_RST:
 634                 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
 635                 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
 636                                          !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
 637                 if (ret)
 638                         dev_warn(priv->dev, "RST channel timeout\n");
 639                 break;
 640         default:
 641                 break;
 642         }
 643
 644         free_irq(priv->irq[cp->type], chan);
 645         pm_runtime_put_sync(priv->dev);
 646 }
 647
 648 static const struct mbox_chan_ops imx_mu_ops = {
 649         .send_data = imx_mu_send_data,
 650         .startup = imx_mu_startup,
 651         .shutdown = imx_mu_shutdown,
 652 };
 653
 654 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
 655                                                const struct of_phandle_args *sp)
 656 {
 657         u32 type, idx, chan;
 658
 659         if (sp->args_count != 2) {
 660                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 661                 return ERR_PTR(-EINVAL);
 662         }
 663
 664         type = sp->args[0]; /* channel type */
 665         idx = sp->args[1]; /* index */
 666
 667         switch (type) {
 668         case IMX_MU_TYPE_TX:
 669         case IMX_MU_TYPE_RX:
 670                 if (idx != 0)
 671                         dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
 672                 chan = type;
 673                 break;
 674         case IMX_MU_TYPE_RXDB:
 675                 chan = 2 + idx;
 676                 break;
 677         default:
 678                 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
 679                 return ERR_PTR(-EINVAL);
 680         }
 681
 682         if (chan >= mbox->num_chans) {
 683                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 684                 return ERR_PTR(-EINVAL);
 685         }
 686
 687         return &mbox->chans[chan];
 688 }
 689
 690 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
 691                                        const struct of_phandle_args *sp)
 692 {
 693         struct mbox_chan *p_chan;
 694         u32 type, idx, chan;
 695
 696         if (sp->args_count != 2) {
 697                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 698                 return ERR_PTR(-EINVAL);
 699         }
 700
 701         type = sp->args[0]; /* channel type */
 702         idx = sp->args[1]; /* index */
 703
 704         /* RST only supports 1 channel */
 705         if ((type == IMX_MU_TYPE_RST) && idx) {
 706                 dev_err(mbox->dev, "Invalid RST channel %d\n", idx);
 707                 return ERR_PTR(-EINVAL);
 708         }
 709
 710         chan = type * 4 + idx;
 711         if (chan >= mbox->num_chans) {
 712                 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
 713                 return ERR_PTR(-EINVAL);
 714         }
 715
 716         p_chan = &mbox->chans[chan];
 717
 718         if (type == IMX_MU_TYPE_TXDB_V2)
 719                 p_chan->txdone_method = TXDONE_BY_ACK;
 720
 721         return p_chan;
 722 }
 723
 724 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
 725                                            const struct of_phandle_args *sp)
 726 {
 727         u32 type;
 728
 729         if (sp->args_count < 1) {
 730                 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
 731                 return ERR_PTR(-EINVAL);
 732         }
 733
 734         type = sp->args[0]; /* channel type */
 735
 736         /* Only supports TXDB and RXDB */
 737         if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
 738                 dev_err(mbox->dev, "Invalid type: %d\n", type);
 739                 return ERR_PTR(-EINVAL);
 740         }
 741
 742         return imx_mu_xlate(mbox, sp);
 743 }
 744
 745 static void imx_mu_get_tr_rr(struct imx_mu_priv *priv)
 746 {
 747         u32 val;
 748
 749         if (priv->dcfg->type & IMX_MU_V2) {
 750                 val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF);
 751                 priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
 752                 priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
 753         } else {
 754                 priv->num_tr = 4;
 755                 priv->num_rr = 4;
 756         }
 757 }
 758
 759 static int imx_mu_init_generic(struct imx_mu_priv *priv)
 760 {
 761         unsigned int i;
 762         unsigned int val;
 763
 764         if (priv->num_rr > 4 || priv->num_tr > 4) {
 765                 WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
 766                 return -EOPNOTSUPP;
 767         }
 768
 769         for (i = 0; i < IMX_MU_CHANS; i++) {
 770                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 771
 772                 cp->idx = i % 4;
 773                 cp->type = i >> 2;
 774                 cp->chan = &priv->mbox_chans[i];
 775                 priv->mbox_chans[i].con_priv = cp;
 776                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 777                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 778         }
 779
 780         priv->mbox.num_chans = IMX_MU_CHANS;
 781         priv->mbox.of_xlate = imx_mu_xlate;
 782
 783         if (priv->side_b)
 784                 return 0;
 785
 786         /* Set default MU configuration */
 787         for (i = 0; i < IMX_MU_xCR_MAX; i++)
 788                 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
 789
 790         /* Clear any pending GIP */
 791         val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
 792         imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
 793
 794         /* Clear any pending RSR */
 795         for (i = 0; i < priv->num_rr; i++)
 796                 imx_mu_read(priv, priv->dcfg->xRR + i * 4);
 797
 798         return 0;
 799 }
 800
 801 static int imx_mu_init_specific(struct imx_mu_priv *priv)
 802 {
 803         unsigned int i;
 804         int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
 805
 806         for (i = 0; i < num_chans; i++) {
 807                 struct imx_mu_con_priv *cp = &priv->con_priv[i];
 808
 809                 cp->idx = i < 2 ? 0 : i - 2;
 810                 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
 811                 cp->chan = &priv->mbox_chans[i];
 812                 priv->mbox_chans[i].con_priv = cp;
 813                 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
 814                          "imx_mu_chan[%i-%i]", cp->type, cp->idx);
 815         }
 816
 817         priv->mbox.num_chans = num_chans;
 818         priv->mbox.of_xlate = imx_mu_specific_xlate;
 819
 820         /* Set default MU configuration */
 821         for (i = 0; i < IMX_MU_xCR_MAX; i++)
 822                 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
 823
 824         return 0;
 825 }
 826
 827 static int imx_mu_init_seco(struct imx_mu_priv *priv)
 828 {
 829         int ret;
 830
 831         ret = imx_mu_init_generic(priv);
 832         if (ret)
 833                 return ret;
 834         priv->mbox.of_xlate = imx_mu_seco_xlate;
 835
 836         return 0;
 837 }
 838
 839 static int imx_mu_probe(struct platform_device *pdev)
 840 {
 841         struct device *dev = &pdev->dev;
 842         struct device_node *np = dev->of_node;
 843         struct imx_mu_priv *priv;
 844         const struct imx_mu_dcfg *dcfg;
 845         int i, ret;
 846         u32 size;
 847
 848         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 849         if (!priv)
 850                 return -ENOMEM;
 851
 852         priv->dev = dev;
 853
 854         priv->base = devm_platform_ioremap_resource(pdev, 0);
 855         if (IS_ERR(priv->base))
 856                 return PTR_ERR(priv->base);
 857
 858         dcfg = of_device_get_match_data(dev);
 859         if (!dcfg)
 860                 return -EINVAL;
 861         priv->dcfg = dcfg;
 862         if (priv->dcfg->type & IMX_MU_V2_IRQ) {
 863                 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx");
 864                 if (priv->irq[IMX_MU_TYPE_TX] < 0)
 865                         return priv->irq[IMX_MU_TYPE_TX];
 866                 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx");
 867                 if (priv->irq[IMX_MU_TYPE_RX] < 0)
 868                         return priv->irq[IMX_MU_TYPE_RX];
 869         } else {
 870                 ret = platform_get_irq(pdev, 0);
 871                 if (ret < 0)
 872                         return ret;
 873
 874                 for (i = 0; i < IMX_MU_CHANS; i++)
 875                         priv->irq[i] = ret;
 876         }
 877
 878         if (priv->dcfg->type & IMX_MU_V2_S4)
 879                 size = sizeof(struct imx_s4_rpc_msg_max);
 880         else
 881                 size = sizeof(struct imx_sc_rpc_msg_max);
 882
 883         priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
 884         if (!priv->msg)
 885                 return -ENOMEM;
 886
 887         priv->clk = devm_clk_get(dev, NULL);
 888         if (IS_ERR(priv->clk)) {
 889                 if (PTR_ERR(priv->clk) != -ENOENT)
 890                         return PTR_ERR(priv->clk);
 891
 892                 priv->clk = NULL;
 893         }
 894
 895         ret = clk_prepare_enable(priv->clk);
 896         if (ret) {
 897                 dev_err(dev, "Failed to enable clock\n");
 898                 return ret;
 899         }
 900
 901         imx_mu_get_tr_rr(priv);
 902
 903         priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
 904
 905         ret = priv->dcfg->init(priv);
 906         if (ret) {
 907                 dev_err(dev, "Failed to init MU\n");
 908                 goto disable_clk;
 909         }
 910
 911         spin_lock_init(&priv->xcr_lock);
 912
 913         priv->mbox.dev = dev;
 914         priv->mbox.ops = &imx_mu_ops;
 915         priv->mbox.chans = priv->mbox_chans;
 916         priv->mbox.txdone_irq = true;
 917
 918         platform_set_drvdata(pdev, priv);
 919
 920         ret = devm_mbox_controller_register(dev, &priv->mbox);
 921         if (ret)
 922                 goto disable_clk;
 923
 924         of_platform_populate(dev->of_node, NULL, NULL, dev);
 925
 926         pm_runtime_enable(dev);
 927
 928         ret = pm_runtime_resume_and_get(dev);
 929         if (ret < 0)
 930                 goto disable_runtime_pm;
 931
 932         ret = pm_runtime_put_sync(dev);
 933         if (ret < 0)
 934                 goto disable_runtime_pm;
 935
 936         clk_disable_unprepare(priv->clk);
 937
 938         return 0;
 939
 940 disable_runtime_pm:
 941         pm_runtime_disable(dev);
 942 disable_clk:
 943         clk_disable_unprepare(priv->clk);
 944         return ret;
 945 }
 946
 947 static void imx_mu_remove(struct platform_device *pdev)
 948 {
 949         struct imx_mu_priv *priv = platform_get_drvdata(pdev);
 950
 951         pm_runtime_disable(priv->dev);
 952 }
 953
 954 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
 955         .tx     = imx_mu_generic_tx,
 956         .rx     = imx_mu_generic_rx,
 957         .rxdb   = imx_mu_generic_rxdb,
 958         .init   = imx_mu_init_generic,
 959         .xTR    = 0x0,
 960         .xRR    = 0x10,
 961         .xSR    = {0x20, 0x20, 0x20, 0x20},
 962         .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},
 963 };
 964
 965 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
 966         .tx     = imx_mu_generic_tx,
 967         .rx     = imx_mu_generic_rx,
 968         .rxdb   = imx_mu_generic_rxdb,
 969         .init   = imx_mu_init_generic,
 970         .xTR    = 0x20,
 971         .xRR    = 0x40,
 972         .xSR    = {0x60, 0x60, 0x60, 0x60},
 973         .xCR    = {0x64, 0x64, 0x64, 0x64, 0x64},
 974 };
 975
 976 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
 977         .tx     = imx_mu_generic_tx,
 978         .rx     = imx_mu_generic_rx,
 979         .rxdb   = imx_mu_generic_rxdb,
 980         .init   = imx_mu_init_generic,
 981         .type   = IMX_MU_V2,
 982         .xTR    = 0x200,
 983         .xRR    = 0x280,
 984         .xSR    = {0xC, 0x118, 0x124, 0x12C},
 985         .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},
 986 };
 987
 988 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
 989         .tx     = imx_mu_specific_tx,
 990         .rx     = imx_mu_specific_rx,
 991         .init   = imx_mu_init_specific,
 992         .type   = IMX_MU_V2 | IMX_MU_V2_S4,
 993         .xTR    = 0x200,
 994         .xRR    = 0x280,
 995         .xSR    = {0xC, 0x118, 0x124, 0x12C},
 996         .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},
 997 };
 998
 999 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
1000         .tx     = imx_mu_specific_tx,
1001         .rx     = imx_mu_specific_rx,
1002         .init   = imx_mu_init_specific,
1003         .type   = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ,
1004         .xTR    = 0x200,
1005         .xRR    = 0x280,
1006         .xSR    = {0xC, 0x118, 0x124, 0x12C},
1007         .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},
1008 };
1009
1010 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
1011         .tx     = imx_mu_specific_tx,
1012         .rx     = imx_mu_specific_rx,
1013         .init   = imx_mu_init_specific,
1014         .rxdb   = imx_mu_generic_rxdb,
1015         .xTR    = 0x0,
1016         .xRR    = 0x10,
1017         .xSR    = {0x20, 0x20, 0x20, 0x20},
1018         .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},
1019 };
1020
1021 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
1022         .tx     = imx_mu_seco_tx,
1023         .rx     = imx_mu_generic_rx,
1024         .rxdb   = imx_mu_seco_rxdb,
1025         .init   = imx_mu_init_seco,
1026         .xTR    = 0x0,
1027         .xRR    = 0x10,
1028         .xSR    = {0x20, 0x20, 0x20, 0x20},
1029         .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},
1030 };
1031
1032 static const struct of_device_id imx_mu_dt_ids[] = {
1033         { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
1034         { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
1035         { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
1036         { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
1037         { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
1038         { .compatible = "fsl,imx95-mu", .data = &imx_mu_cfg_imx8ulp },
1039         { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 },
1040         { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 },
1041         { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
1042         { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
1043         { },
1044 };
1045 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
1046
1047 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
1048 {
1049         struct imx_mu_priv *priv = dev_get_drvdata(dev);
1050         int i;
1051
1052         if (!priv->clk) {
1053                 for (i = 0; i < IMX_MU_xCR_MAX; i++)
1054                         priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
1055         }
1056
1057         priv->suspend = true;
1058
1059         return 0;
1060 }
1061
1062 static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
1063 {
1064         struct imx_mu_priv *priv = dev_get_drvdata(dev);
1065         int i;
1066
1067         /*
1068          * ONLY restore MU when context lost, the TIE could
1069          * be set during noirq resume as there is MU data
1070          * communication going on, and restore the saved
1071          * value will overwrite the TIE and cause MU data
1072          * send failed, may lead to system freeze. This issue
1073          * is observed by testing freeze mode suspend.
1074          */
1075         if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
1076                 for (i = 0; i < IMX_MU_xCR_MAX; i++)
1077                         imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
1078         }
1079
1080         priv->suspend = false;
1081
1082         return 0;
1083 }
1084
1085 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
1086 {
1087         struct imx_mu_priv *priv = dev_get_drvdata(dev);
1088
1089         clk_disable_unprepare(priv->clk);
1090
1091         return 0;
1092 }
1093
1094 static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
1095 {
1096         struct imx_mu_priv *priv = dev_get_drvdata(dev);
1097         int ret;
1098
1099         ret = clk_prepare_enable(priv->clk);
1100         if (ret)
1101                 dev_err(dev, "failed to enable clock\n");
1102
1103         return ret;
1104 }
1105
1106 static const struct dev_pm_ops imx_mu_pm_ops = {
1107         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
1108                                       imx_mu_resume_noirq)
1109         SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
1110                            imx_mu_runtime_resume, NULL)
1111 };
1112
1113 static struct platform_driver imx_mu_driver = {
1114         .probe          = imx_mu_probe,
1115         .remove_new     = imx_mu_remove,
1116         .driver = {
1117                 .name   = "imx_mu",
1118                 .of_match_table = imx_mu_dt_ids,
1119                 .pm = &imx_mu_pm_ops,
1120         },
1121 };
1122 module_platform_driver(imx_mu_driver);
1123
1124 MODULE_AUTHOR("Oleksij Rempel <[email protected]>");
1125 MODULE_DESCRIPTION("Message Unit driver for i.MX");
1126 MODULE_LICENSE("GPL v2");