drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dce/dce_8_0_d.h"
  29 #include "dce/dce_8_0_sh_mask.h"
  30
  31 #include "dm_services.h"
  32
  33 #include "link_encoder.h"
  34 #include "stream_encoder.h"
  35
  36 #include "resource.h"
  37 #include "include/irq_service_interface.h"
  38 #include "irq/dce80/irq_service_dce80.h"
  39 #include "dce110/dce110_timing_generator.h"
  40 #include "dce110/dce110_resource.h"
  41 #include "dce80/dce80_timing_generator.h"
  42 #include "dce/dce_mem_input.h"
  43 #include "dce/dce_link_encoder.h"
  44 #include "dce/dce_stream_encoder.h"
  45 #include "dce/dce_ipp.h"
  46 #include "dce/dce_transform.h"
  47 #include "dce/dce_opp.h"
  48 #include "dce/dce_clock_source.h"
  49 #include "dce/dce_audio.h"
  50 #include "dce/dce_hwseq.h"
  51 #include "dce80/dce80_hw_sequencer.h"
  52 #include "dce100/dce100_resource.h"
  53 #include "dce/dce_panel_cntl.h"
  54
  55 #include "reg_helper.h"
  56
  57 #include "dce/dce_dmcu.h"
  58 #include "dce/dce_aux.h"
  59 #include "dce/dce_abm.h"
  60 #include "dce/dce_i2c.h"
  61 /* TODO remove this include */
  62
  63 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  64 #include "gmc/gmc_7_1_d.h"
  65 #include "gmc/gmc_7_1_sh_mask.h"
  66 #endif
  67
  68 #ifndef mmDP_DPHY_INTERNAL_CTRL
  69 #define mmDP_DPHY_INTERNAL_CTRL                         0x1CDE
  70 #define mmDP0_DP_DPHY_INTERNAL_CTRL                     0x1CDE
  71 #define mmDP1_DP_DPHY_INTERNAL_CTRL                     0x1FDE
  72 #define mmDP2_DP_DPHY_INTERNAL_CTRL                     0x42DE
  73 #define mmDP3_DP_DPHY_INTERNAL_CTRL                     0x45DE
  74 #define mmDP4_DP_DPHY_INTERNAL_CTRL                     0x48DE
  75 #define mmDP5_DP_DPHY_INTERNAL_CTRL                     0x4BDE
  76 #define mmDP6_DP_DPHY_INTERNAL_CTRL                     0x4EDE
  77 #endif
  78
  79
  80 #ifndef mmBIOS_SCRATCH_2
  81         #define mmBIOS_SCRATCH_2 0x05CB
  82         #define mmBIOS_SCRATCH_3 0x05CC
  83         #define mmBIOS_SCRATCH_6 0x05CF
  84 #endif
  85
  86 #ifndef mmDP_DPHY_FAST_TRAINING
  87         #define mmDP_DPHY_FAST_TRAINING                         0x1CCE
  88         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x1CCE
  89         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x1FCE
  90         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x42CE
  91         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x45CE
  92         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x48CE
  93         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4BCE
  94         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x4ECE
  95 #endif
  96
  97
  98 #ifndef mmHPD_DC_HPD_CONTROL
  99         #define mmHPD_DC_HPD_CONTROL                            0x189A
 100         #define mmHPD0_DC_HPD_CONTROL                           0x189A
 101         #define mmHPD1_DC_HPD_CONTROL                           0x18A2
 102         #define mmHPD2_DC_HPD_CONTROL                           0x18AA
 103         #define mmHPD3_DC_HPD_CONTROL                           0x18B2
 104         #define mmHPD4_DC_HPD_CONTROL                           0x18BA
 105         #define mmHPD5_DC_HPD_CONTROL                           0x18C2
 106 #endif
 107
 108 #define DCE11_DIG_FE_CNTL 0x4a00
 109 #define DCE11_DIG_BE_CNTL 0x4a47
 110 #define DCE11_DP_SEC 0x4ac3
 111
 112 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
 113                 {
 114                         .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 115                         .dcp =  (mmGRPH_CONTROL - mmGRPH_CONTROL),
 116                         .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
 117                                         - mmDPG_WATERMARK_MASK_CONTROL),
 118                 },
 119                 {
 120                         .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 121                         .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 122                         .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
 123                                         - mmDPG_WATERMARK_MASK_CONTROL),
 124                 },
 125                 {
 126                         .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 127                         .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 128                         .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
 129                                         - mmDPG_WATERMARK_MASK_CONTROL),
 130                 },
 131                 {
 132                         .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 133                         .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 134                         .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
 135                                         - mmDPG_WATERMARK_MASK_CONTROL),
 136                 },
 137                 {
 138                         .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 139                         .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 140                         .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
 141                                         - mmDPG_WATERMARK_MASK_CONTROL),
 142                 },
 143                 {
 144                         .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 145                         .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 146                         .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
 147                                         - mmDPG_WATERMARK_MASK_CONTROL),
 148                 }
 149 };
 150
 151 /* set register offset */
 152 #define SR(reg_name)\
 153         .reg_name = mm ## reg_name
 154
 155 /* set register offset with instance */
 156 #define SRI(reg_name, block, id)\
 157         .reg_name = mm ## block ## id ## _ ## reg_name
 158
 159 #define ipp_regs(id)\
 160 [id] = {\
 161                 IPP_COMMON_REG_LIST_DCE_BASE(id)\
 162 }
 163
 164 static const struct dce_ipp_registers ipp_regs[] = {
 165                 ipp_regs(0),
 166                 ipp_regs(1),
 167                 ipp_regs(2),
 168                 ipp_regs(3),
 169                 ipp_regs(4),
 170                 ipp_regs(5)
 171 };
 172
 173 static const struct dce_ipp_shift ipp_shift = {
 174                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 175 };
 176
 177 static const struct dce_ipp_mask ipp_mask = {
 178                 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 179 };
 180
 181 #define transform_regs(id)\
 182 [id] = {\
 183                 XFM_COMMON_REG_LIST_DCE80(id)\
 184 }
 185
 186 static const struct dce_transform_registers xfm_regs[] = {
 187                 transform_regs(0),
 188                 transform_regs(1),
 189                 transform_regs(2),
 190                 transform_regs(3),
 191                 transform_regs(4),
 192                 transform_regs(5)
 193 };
 194
 195 static const struct dce_transform_shift xfm_shift = {
 196                 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
 197 };
 198
 199 static const struct dce_transform_mask xfm_mask = {
 200                 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
 201 };
 202
 203 #define aux_regs(id)\
 204 [id] = {\
 205         AUX_REG_LIST(id)\
 206 }
 207
 208 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 209         aux_regs(0),
 210         aux_regs(1),
 211         aux_regs(2),
 212         aux_regs(3),
 213         aux_regs(4),
 214         aux_regs(5)
 215 };
 216
 217 #define hpd_regs(id)\
 218 [id] = {\
 219         HPD_REG_LIST(id)\
 220 }
 221
 222 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 223                 hpd_regs(0),
 224                 hpd_regs(1),
 225                 hpd_regs(2),
 226                 hpd_regs(3),
 227                 hpd_regs(4),
 228                 hpd_regs(5)
 229 };
 230
 231 #define link_regs(id)\
 232 [id] = {\
 233         LE_DCE80_REG_LIST(id)\
 234 }
 235
 236 static const struct dce110_link_enc_registers link_enc_regs[] = {
 237         link_regs(0),
 238         link_regs(1),
 239         link_regs(2),
 240         link_regs(3),
 241         link_regs(4),
 242         link_regs(5),
 243         link_regs(6),
 244 };
 245
 246 #define stream_enc_regs(id)\
 247 [id] = {\
 248         SE_COMMON_REG_LIST_DCE_BASE(id),\
 249         .AFMT_CNTL = 0,\
 250 }
 251
 252 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 253         stream_enc_regs(0),
 254         stream_enc_regs(1),
 255         stream_enc_regs(2),
 256         stream_enc_regs(3),
 257         stream_enc_regs(4),
 258         stream_enc_regs(5),
 259         stream_enc_regs(6)
 260 };
 261
 262 static const struct dce_stream_encoder_shift se_shift = {
 263                 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
 264 };
 265
 266 static const struct dce_stream_encoder_mask se_mask = {
 267                 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
 268 };
 269
 270 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 271         { DCE_PANEL_CNTL_REG_LIST() }
 272 };
 273
 274 static const struct dce_panel_cntl_shift panel_cntl_shift = {
 275         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 276 };
 277
 278 static const struct dce_panel_cntl_mask panel_cntl_mask = {
 279         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 280 };
 281
 282 #define opp_regs(id)\
 283 [id] = {\
 284         OPP_DCE_80_REG_LIST(id),\
 285 }
 286
 287 static const struct dce_opp_registers opp_regs[] = {
 288         opp_regs(0),
 289         opp_regs(1),
 290         opp_regs(2),
 291         opp_regs(3),
 292         opp_regs(4),
 293         opp_regs(5)
 294 };
 295
 296 static const struct dce_opp_shift opp_shift = {
 297         OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
 298 };
 299
 300 static const struct dce_opp_mask opp_mask = {
 301         OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
 302 };
 303
 304 static const struct dce110_aux_registers_shift aux_shift = {
 305         DCE10_AUX_MASK_SH_LIST(__SHIFT)
 306 };
 307
 308 static const struct dce110_aux_registers_mask aux_mask = {
 309         DCE10_AUX_MASK_SH_LIST(_MASK)
 310 };
 311
 312 #define aux_engine_regs(id)\
 313 [id] = {\
 314         AUX_COMMON_REG_LIST(id), \
 315         .AUX_RESET_MASK = 0 \
 316 }
 317
 318 static const struct dce110_aux_registers aux_engine_regs[] = {
 319                 aux_engine_regs(0),
 320                 aux_engine_regs(1),
 321                 aux_engine_regs(2),
 322                 aux_engine_regs(3),
 323                 aux_engine_regs(4),
 324                 aux_engine_regs(5)
 325 };
 326
 327 #define audio_regs(id)\
 328 [id] = {\
 329         AUD_COMMON_REG_LIST(id)\
 330 }
 331
 332 static const struct dce_audio_registers audio_regs[] = {
 333         audio_regs(0),
 334         audio_regs(1),
 335         audio_regs(2),
 336         audio_regs(3),
 337         audio_regs(4),
 338         audio_regs(5),
 339         audio_regs(6),
 340 };
 341
 342 static const struct dce_audio_shift audio_shift = {
 343                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 344 };
 345
 346 static const struct dce_audio_mask audio_mask = {
 347                 AUD_COMMON_MASK_SH_LIST(_MASK)
 348 };
 349
 350 #define clk_src_regs(id)\
 351 [id] = {\
 352         CS_COMMON_REG_LIST_DCE_80(id),\
 353 }
 354
 355
 356 static const struct dce110_clk_src_regs clk_src_regs[] = {
 357         clk_src_regs(0),
 358         clk_src_regs(1),
 359         clk_src_regs(2)
 360 };
 361
 362 static const struct dce110_clk_src_shift cs_shift = {
 363                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 364 };
 365
 366 static const struct dce110_clk_src_mask cs_mask = {
 367                 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 368 };
 369
 370 static const struct bios_registers bios_regs = {
 371         .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
 372         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 373 };
 374
 375 static const struct resource_caps res_cap = {
 376                 .num_timing_generator = 6,
 377                 .num_audio = 6,
 378                 .num_stream_encoder = 6,
 379                 .num_pll = 3,
 380                 .num_ddc = 6,
 381 };
 382
 383 static const struct resource_caps res_cap_81 = {
 384                 .num_timing_generator = 4,
 385                 .num_audio = 7,
 386                 .num_stream_encoder = 7,
 387                 .num_pll = 3,
 388                 .num_ddc = 6,
 389 };
 390
 391 static const struct resource_caps res_cap_83 = {
 392                 .num_timing_generator = 2,
 393                 .num_audio = 6,
 394                 .num_stream_encoder = 6,
 395                 .num_pll = 2,
 396                 .num_ddc = 2,
 397 };
 398
 399 static const struct dc_plane_cap plane_cap = {
 400         .type = DC_PLANE_TYPE_DCE_RGB,
 401
 402         .pixel_format_support = {
 403                         .argb8888 = true,
 404                         .nv12 = false,
 405                         .fp16 = false
 406         },
 407
 408         .max_upscale_factor = {
 409                         .argb8888 = 16000,
 410                         .nv12 = 1,
 411                         .fp16 = 1
 412         },
 413
 414         .max_downscale_factor = {
 415                         .argb8888 = 250,
 416                         .nv12 = 1,
 417                         .fp16 = 1
 418         }
 419 };
 420
 421 static const struct dce_dmcu_registers dmcu_regs = {
 422                 DMCU_DCE80_REG_LIST()
 423 };
 424
 425 static const struct dce_dmcu_shift dmcu_shift = {
 426                 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
 427 };
 428
 429 static const struct dce_dmcu_mask dmcu_mask = {
 430                 DMCU_MASK_SH_LIST_DCE80(_MASK)
 431 };
 432 static const struct dce_abm_registers abm_regs = {
 433                 ABM_DCE110_COMMON_REG_LIST()
 434 };
 435
 436 static const struct dce_abm_shift abm_shift = {
 437                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 438 };
 439
 440 static const struct dce_abm_mask abm_mask = {
 441                 ABM_MASK_SH_LIST_DCE110(_MASK)
 442 };
 443
 444 #define CTX  ctx
 445 #define REG(reg) mm ## reg
 446
 447 #ifndef mmCC_DC_HDMI_STRAPS
 448 #define mmCC_DC_HDMI_STRAPS 0x1918
 449 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 450 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 451 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 452 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 453 #endif
 454
 455 static int map_transmitter_id_to_phy_instance(
 456         enum transmitter transmitter)
 457 {
 458         switch (transmitter) {
 459         case TRANSMITTER_UNIPHY_A:
 460                 return 0;
 461         case TRANSMITTER_UNIPHY_B:
 462                 return 1;
 463         case TRANSMITTER_UNIPHY_C:
 464                 return 2;
 465         case TRANSMITTER_UNIPHY_D:
 466                 return 3;
 467         case TRANSMITTER_UNIPHY_E:
 468                 return 4;
 469         case TRANSMITTER_UNIPHY_F:
 470                 return 5;
 471         case TRANSMITTER_UNIPHY_G:
 472                 return 6;
 473         default:
 474                 ASSERT(0);
 475                 return 0;
 476         }
 477 }
 478
 479 static void read_dce_straps(
 480         struct dc_context *ctx,
 481         struct resource_straps *straps)
 482 {
 483         REG_GET_2(CC_DC_HDMI_STRAPS,
 484                         HDMI_DISABLE, &straps->hdmi_disable,
 485                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 486
 487         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 488 }
 489
 490 static struct audio *create_audio(
 491                 struct dc_context *ctx, unsigned int inst)
 492 {
 493         return dce_audio_create(ctx, inst,
 494                         &audio_regs[inst], &audio_shift, &audio_mask);
 495 }
 496
 497 static struct timing_generator *dce80_timing_generator_create(
 498                 struct dc_context *ctx,
 499                 uint32_t instance,
 500                 const struct dce110_timing_generator_offsets *offsets)
 501 {
 502         struct dce110_timing_generator *tg110 =
 503                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 504
 505         if (!tg110)
 506                 return NULL;
 507
 508         dce80_timing_generator_construct(tg110, ctx, instance, offsets);
 509         return &tg110->base;
 510 }
 511
 512 static struct output_pixel_processor *dce80_opp_create(
 513         struct dc_context *ctx,
 514         uint32_t inst)
 515 {
 516         struct dce110_opp *opp =
 517                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 518
 519         if (!opp)
 520                 return NULL;
 521
 522         dce110_opp_construct(opp,
 523                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 524         return &opp->base;
 525 }
 526
 527 struct dce_aux *dce80_aux_engine_create(
 528         struct dc_context *ctx,
 529         uint32_t inst)
 530 {
 531         struct aux_engine_dce110 *aux_engine =
 532                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 533
 534         if (!aux_engine)
 535                 return NULL;
 536
 537         dce110_aux_engine_construct(aux_engine, ctx, inst,
 538                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 539                                     &aux_engine_regs[inst],
 540                                         &aux_mask,
 541                                         &aux_shift,
 542                                         ctx->dc->caps.extended_aux_timeout_support);
 543
 544         return &aux_engine->base;
 545 }
 546 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 547
 548 static const struct dce_i2c_registers i2c_hw_regs[] = {
 549                 i2c_inst_regs(1),
 550                 i2c_inst_regs(2),
 551                 i2c_inst_regs(3),
 552                 i2c_inst_regs(4),
 553                 i2c_inst_regs(5),
 554                 i2c_inst_regs(6),
 555 };
 556
 557 static const struct dce_i2c_shift i2c_shifts = {
 558                 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 559 };
 560
 561 static const struct dce_i2c_mask i2c_masks = {
 562                 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 563 };
 564
 565 struct dce_i2c_hw *dce80_i2c_hw_create(
 566         struct dc_context *ctx,
 567         uint32_t inst)
 568 {
 569         struct dce_i2c_hw *dce_i2c_hw =
 570                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 571
 572         if (!dce_i2c_hw)
 573                 return NULL;
 574
 575         dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 576                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 577
 578         return dce_i2c_hw;
 579 }
 580
 581 struct dce_i2c_sw *dce80_i2c_sw_create(
 582         struct dc_context *ctx)
 583 {
 584         struct dce_i2c_sw *dce_i2c_sw =
 585                 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
 586
 587         if (!dce_i2c_sw)
 588                 return NULL;
 589
 590         dce_i2c_sw_construct(dce_i2c_sw, ctx);
 591
 592         return dce_i2c_sw;
 593 }
 594 static struct stream_encoder *dce80_stream_encoder_create(
 595         enum engine_id eng_id,
 596         struct dc_context *ctx)
 597 {
 598         struct dce110_stream_encoder *enc110 =
 599                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 600
 601         if (!enc110)
 602                 return NULL;
 603
 604         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 605                                         &stream_enc_regs[eng_id],
 606                                         &se_shift, &se_mask);
 607         return &enc110->base;
 608 }
 609
 610 #define SRII(reg_name, block, id)\
 611         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 612
 613 static const struct dce_hwseq_registers hwseq_reg = {
 614                 HWSEQ_DCE8_REG_LIST()
 615 };
 616
 617 static const struct dce_hwseq_shift hwseq_shift = {
 618                 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
 619 };
 620
 621 static const struct dce_hwseq_mask hwseq_mask = {
 622                 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
 623 };
 624
 625 static struct dce_hwseq *dce80_hwseq_create(
 626         struct dc_context *ctx)
 627 {
 628         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 629
 630         if (hws) {
 631                 hws->ctx = ctx;
 632                 hws->regs = &hwseq_reg;
 633                 hws->shifts = &hwseq_shift;
 634                 hws->masks = &hwseq_mask;
 635         }
 636         return hws;
 637 }
 638
 639 static const struct resource_create_funcs res_create_funcs = {
 640         .read_dce_straps = read_dce_straps,
 641         .create_audio = create_audio,
 642         .create_stream_encoder = dce80_stream_encoder_create,
 643         .create_hwseq = dce80_hwseq_create,
 644 };
 645
 646 #define mi_inst_regs(id) { \
 647         MI_DCE8_REG_LIST(id), \
 648         .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
 649 }
 650 static const struct dce_mem_input_registers mi_regs[] = {
 651                 mi_inst_regs(0),
 652                 mi_inst_regs(1),
 653                 mi_inst_regs(2),
 654                 mi_inst_regs(3),
 655                 mi_inst_regs(4),
 656                 mi_inst_regs(5),
 657 };
 658
 659 static const struct dce_mem_input_shift mi_shifts = {
 660                 MI_DCE8_MASK_SH_LIST(__SHIFT),
 661                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
 662 };
 663
 664 static const struct dce_mem_input_mask mi_masks = {
 665                 MI_DCE8_MASK_SH_LIST(_MASK),
 666                 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
 667 };
 668
 669 static struct mem_input *dce80_mem_input_create(
 670         struct dc_context *ctx,
 671         uint32_t inst)
 672 {
 673         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 674                                                GFP_KERNEL);
 675
 676         if (!dce_mi) {
 677                 BREAK_TO_DEBUGGER();
 678                 return NULL;
 679         }
 680
 681         dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 682         dce_mi->wa.single_head_rdreq_dmif_limit = 2;
 683         return &dce_mi->base;
 684 }
 685
 686 static void dce80_transform_destroy(struct transform **xfm)
 687 {
 688         kfree(TO_DCE_TRANSFORM(*xfm));
 689         *xfm = NULL;
 690 }
 691
 692 static struct transform *dce80_transform_create(
 693         struct dc_context *ctx,
 694         uint32_t inst)
 695 {
 696         struct dce_transform *transform =
 697                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 698
 699         if (!transform)
 700                 return NULL;
 701
 702         dce_transform_construct(transform, ctx, inst,
 703                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 704         transform->prescaler_on = false;
 705         return &transform->base;
 706 }
 707
 708 static const struct encoder_feature_support link_enc_feature = {
 709                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 710                 .max_hdmi_pixel_clock = 297000,
 711                 .flags.bits.IS_HBR2_CAPABLE = true,
 712                 .flags.bits.IS_TPS3_CAPABLE = true
 713 };
 714
 715 struct link_encoder *dce80_link_encoder_create(
 716         const struct encoder_init_data *enc_init_data)
 717 {
 718         struct dce110_link_encoder *enc110 =
 719                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 720         int link_regs_id;
 721
 722         if (!enc110)
 723                 return NULL;
 724
 725         link_regs_id =
 726                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
 727
 728         dce110_link_encoder_construct(enc110,
 729                                       enc_init_data,
 730                                       &link_enc_feature,
 731                                       &link_enc_regs[link_regs_id],
 732                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 733                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 734         return &enc110->base;
 735 }
 736
 737 static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
 738 {
 739         struct dce_panel_cntl *panel_cntl =
 740                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
 741
 742         if (!panel_cntl)
 743                 return NULL;
 744
 745         dce_panel_cntl_construct(panel_cntl,
 746                         init_data,
 747                         &panel_cntl_regs[init_data->inst],
 748                         &panel_cntl_shift,
 749                         &panel_cntl_mask);
 750
 751         return &panel_cntl->base;
 752 }
 753
 754 struct clock_source *dce80_clock_source_create(
 755         struct dc_context *ctx,
 756         struct dc_bios *bios,
 757         enum clock_source_id id,
 758         const struct dce110_clk_src_regs *regs,
 759         bool dp_clk_src)
 760 {
 761         struct dce110_clk_src *clk_src =
 762                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 763
 764         if (!clk_src)
 765                 return NULL;
 766
 767         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 768                         regs, &cs_shift, &cs_mask)) {
 769                 clk_src->base.dp_clk_src = dp_clk_src;
 770                 return &clk_src->base;
 771         }
 772
 773         kfree(clk_src);
 774         BREAK_TO_DEBUGGER();
 775         return NULL;
 776 }
 777
 778 void dce80_clock_source_destroy(struct clock_source **clk_src)
 779 {
 780         kfree(TO_DCE110_CLK_SRC(*clk_src));
 781         *clk_src = NULL;
 782 }
 783
 784 static struct input_pixel_processor *dce80_ipp_create(
 785         struct dc_context *ctx, uint32_t inst)
 786 {
 787         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 788
 789         if (!ipp) {
 790                 BREAK_TO_DEBUGGER();
 791                 return NULL;
 792         }
 793
 794         dce_ipp_construct(ipp, ctx, inst,
 795                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 796         return &ipp->base;
 797 }
 798
 799 static void dce80_resource_destruct(struct dce110_resource_pool *pool)
 800 {
 801         unsigned int i;
 802
 803         for (i = 0; i < pool->base.pipe_count; i++) {
 804                 if (pool->base.opps[i] != NULL)
 805                         dce110_opp_destroy(&pool->base.opps[i]);
 806
 807                 if (pool->base.transforms[i] != NULL)
 808                         dce80_transform_destroy(&pool->base.transforms[i]);
 809
 810                 if (pool->base.ipps[i] != NULL)
 811                         dce_ipp_destroy(&pool->base.ipps[i]);
 812
 813                 if (pool->base.mis[i] != NULL) {
 814                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 815                         pool->base.mis[i] = NULL;
 816                 }
 817
 818                 if (pool->base.timing_generators[i] != NULL)    {
 819                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 820                         pool->base.timing_generators[i] = NULL;
 821                 }
 822         }
 823
 824         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 825                 if (pool->base.engines[i] != NULL)
 826                         dce110_engine_destroy(&pool->base.engines[i]);
 827                 if (pool->base.hw_i2cs[i] != NULL) {
 828                         kfree(pool->base.hw_i2cs[i]);
 829                         pool->base.hw_i2cs[i] = NULL;
 830                 }
 831                 if (pool->base.sw_i2cs[i] != NULL) {
 832                         kfree(pool->base.sw_i2cs[i]);
 833                         pool->base.sw_i2cs[i] = NULL;
 834                 }
 835         }
 836
 837         for (i = 0; i < pool->base.stream_enc_count; i++) {
 838                 if (pool->base.stream_enc[i] != NULL)
 839                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 840         }
 841
 842         for (i = 0; i < pool->base.clk_src_count; i++) {
 843                 if (pool->base.clock_sources[i] != NULL) {
 844                         dce80_clock_source_destroy(&pool->base.clock_sources[i]);
 845                 }
 846         }
 847
 848         if (pool->base.abm != NULL)
 849                         dce_abm_destroy(&pool->base.abm);
 850
 851         if (pool->base.dmcu != NULL)
 852                         dce_dmcu_destroy(&pool->base.dmcu);
 853
 854         if (pool->base.dp_clock_source != NULL)
 855                 dce80_clock_source_destroy(&pool->base.dp_clock_source);
 856
 857         for (i = 0; i < pool->base.audio_count; i++)    {
 858                 if (pool->base.audios[i] != NULL) {
 859                         dce_aud_destroy(&pool->base.audios[i]);
 860                 }
 861         }
 862
 863         if (pool->base.irqs != NULL) {
 864                 dal_irq_service_destroy(&pool->base.irqs);
 865         }
 866 }
 867
 868 bool dce80_validate_bandwidth(
 869         struct dc *dc,
 870         struct dc_state *context,
 871         bool fast_validate)
 872 {
 873         int i;
 874         bool at_least_one_pipe = false;
 875
 876         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 877                 if (context->res_ctx.pipe_ctx[i].stream)
 878                         at_least_one_pipe = true;
 879         }
 880
 881         if (at_least_one_pipe) {
 882                 /* TODO implement when needed but for now hardcode max value*/
 883                 context->bw_ctx.bw.dce.dispclk_khz = 681000;
 884                 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
 885         } else {
 886                 context->bw_ctx.bw.dce.dispclk_khz = 0;
 887                 context->bw_ctx.bw.dce.yclk_khz = 0;
 888         }
 889
 890         return true;
 891 }
 892
 893 static bool dce80_validate_surface_sets(
 894                 struct dc_state *context)
 895 {
 896         int i;
 897
 898         for (i = 0; i < context->stream_count; i++) {
 899                 if (context->stream_status[i].plane_count == 0)
 900                         continue;
 901
 902                 if (context->stream_status[i].plane_count > 1)
 903                         return false;
 904
 905                 if (context->stream_status[i].plane_states[0]->format
 906                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 907                         return false;
 908         }
 909
 910         return true;
 911 }
 912
 913 enum dc_status dce80_validate_global(
 914                 struct dc *dc,
 915                 struct dc_state *context)
 916 {
 917         if (!dce80_validate_surface_sets(context))
 918                 return DC_FAIL_SURFACE_VALIDATE;
 919
 920         return DC_OK;
 921 }
 922
 923 static void dce80_destroy_resource_pool(struct resource_pool **pool)
 924 {
 925         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 926
 927         dce80_resource_destruct(dce110_pool);
 928         kfree(dce110_pool);
 929         *pool = NULL;
 930 }
 931
 932 static const struct resource_funcs dce80_res_pool_funcs = {
 933         .destroy = dce80_destroy_resource_pool,
 934         .link_enc_create = dce80_link_encoder_create,
 935         .panel_cntl_create = dce80_panel_cntl_create,
 936         .validate_bandwidth = dce80_validate_bandwidth,
 937         .validate_plane = dce100_validate_plane,
 938         .add_stream_to_ctx = dce100_add_stream_to_ctx,
 939         .validate_global = dce80_validate_global,
 940         .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
 941 };
 942
 943 static bool dce80_construct(
 944         uint8_t num_virtual_links,
 945         struct dc *dc,
 946         struct dce110_resource_pool *pool)
 947 {
 948         unsigned int i;
 949         struct dc_context *ctx = dc->ctx;
 950         struct dc_bios *bp;
 951
 952         ctx->dc_bios->regs = &bios_regs;
 953
 954         pool->base.res_cap = &res_cap;
 955         pool->base.funcs = &dce80_res_pool_funcs;
 956
 957
 958         /*************************************************
 959          *  Resource + asic cap harcoding                *
 960          *************************************************/
 961         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
 962         pool->base.pipe_count = res_cap.num_timing_generator;
 963         pool->base.timing_generator_count = res_cap.num_timing_generator;
 964         dc->caps.max_downscale_ratio = 200;
 965         dc->caps.i2c_speed_in_khz = 40;
 966         dc->caps.i2c_speed_in_khz_hdcp = 40;
 967         dc->caps.max_cursor_size = 128;
 968         dc->caps.min_horizontal_blanking_period = 80;
 969         dc->caps.dual_link_dvi = true;
 970         dc->caps.extended_aux_timeout_support = false;
 971
 972         /*************************************************
 973          *  Create resources                             *
 974          *************************************************/
 975
 976         bp = ctx->dc_bios;
 977
 978         if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
 979                 pool->base.dp_clock_source =
 980                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
 981
 982                 pool->base.clock_sources[0] =
 983                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
 984                 pool->base.clock_sources[1] =
 985                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 986                 pool->base.clock_sources[2] =
 987                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 988                 pool->base.clk_src_count = 3;
 989
 990         } else {
 991                 pool->base.dp_clock_source =
 992                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
 993
 994                 pool->base.clock_sources[0] =
 995                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
 996                 pool->base.clock_sources[1] =
 997                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
 998                 pool->base.clk_src_count = 2;
 999         }
1000
1001         if (pool->base.dp_clock_source == NULL) {
1002                 dm_error("DC: failed to create dp clock source!\n");
1003                 BREAK_TO_DEBUGGER();
1004                 goto res_create_fail;
1005         }
1006
1007         for (i = 0; i < pool->base.clk_src_count; i++) {
1008                 if (pool->base.clock_sources[i] == NULL) {
1009                         dm_error("DC: failed to create clock sources!\n");
1010                         BREAK_TO_DEBUGGER();
1011                         goto res_create_fail;
1012                 }
1013         }
1014
1015         pool->base.dmcu = dce_dmcu_create(ctx,
1016                         &dmcu_regs,
1017                         &dmcu_shift,
1018                         &dmcu_mask);
1019         if (pool->base.dmcu == NULL) {
1020                 dm_error("DC: failed to create dmcu!\n");
1021                 BREAK_TO_DEBUGGER();
1022                 goto res_create_fail;
1023         }
1024
1025         pool->base.abm = dce_abm_create(ctx,
1026                         &abm_regs,
1027                         &abm_shift,
1028                         &abm_mask);
1029         if (pool->base.abm == NULL) {
1030                 dm_error("DC: failed to create abm!\n");
1031                 BREAK_TO_DEBUGGER();
1032                 goto res_create_fail;
1033         }
1034
1035         {
1036                 struct irq_service_init_data init_data;
1037                 init_data.ctx = dc->ctx;
1038                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1039                 if (!pool->base.irqs)
1040                         goto res_create_fail;
1041         }
1042
1043         for (i = 0; i < pool->base.pipe_count; i++) {
1044                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1045                                 ctx, i, &dce80_tg_offsets[i]);
1046                 if (pool->base.timing_generators[i] == NULL) {
1047                         BREAK_TO_DEBUGGER();
1048                         dm_error("DC: failed to create tg!\n");
1049                         goto res_create_fail;
1050                 }
1051
1052                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1053                 if (pool->base.mis[i] == NULL) {
1054                         BREAK_TO_DEBUGGER();
1055                         dm_error("DC: failed to create memory input!\n");
1056                         goto res_create_fail;
1057                 }
1058
1059                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1060                 if (pool->base.ipps[i] == NULL) {
1061                         BREAK_TO_DEBUGGER();
1062                         dm_error("DC: failed to create input pixel processor!\n");
1063                         goto res_create_fail;
1064                 }
1065
1066                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1067                 if (pool->base.transforms[i] == NULL) {
1068                         BREAK_TO_DEBUGGER();
1069                         dm_error("DC: failed to create transform!\n");
1070                         goto res_create_fail;
1071                 }
1072
1073                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1074                 if (pool->base.opps[i] == NULL) {
1075                         BREAK_TO_DEBUGGER();
1076                         dm_error("DC: failed to create output pixel processor!\n");
1077                         goto res_create_fail;
1078                 }
1079         }
1080
1081         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1082                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1083                 if (pool->base.engines[i] == NULL) {
1084                         BREAK_TO_DEBUGGER();
1085                         dm_error(
1086                                 "DC:failed to create aux engine!!\n");
1087                         goto res_create_fail;
1088                 }
1089                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1090                 if (pool->base.hw_i2cs[i] == NULL) {
1091                         BREAK_TO_DEBUGGER();
1092                         dm_error(
1093                                 "DC:failed to create i2c engine!!\n");
1094                         goto res_create_fail;
1095                 }
1096                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1097                 if (pool->base.sw_i2cs[i] == NULL) {
1098                         BREAK_TO_DEBUGGER();
1099                         dm_error(
1100                                 "DC:failed to create sw i2c!!\n");
1101                         goto res_create_fail;
1102                 }
1103         }
1104
1105         dc->caps.max_planes =  pool->base.pipe_count;
1106
1107         for (i = 0; i < dc->caps.max_planes; ++i)
1108                 dc->caps.planes[i] = plane_cap;
1109
1110         dc->caps.disable_dp_clk_share = true;
1111
1112         if (!resource_construct(num_virtual_links, dc, &pool->base,
1113                         &res_create_funcs))
1114                 goto res_create_fail;
1115
1116         /* Create hardware sequencer */
1117         dce80_hw_sequencer_construct(dc);
1118
1119         return true;
1120
1121 res_create_fail:
1122         dce80_resource_destruct(pool);
1123         return false;
1124 }
1125
1126 struct resource_pool *dce80_create_resource_pool(
1127         uint8_t num_virtual_links,
1128         struct dc *dc)
1129 {
1130         struct dce110_resource_pool *pool =
1131                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1132
1133         if (!pool)
1134                 return NULL;
1135
1136         if (dce80_construct(num_virtual_links, dc, pool))
1137                 return &pool->base;
1138
1139         BREAK_TO_DEBUGGER();
1140         return NULL;
1141 }
1142
1143 static bool dce81_construct(
1144         uint8_t num_virtual_links,
1145         struct dc *dc,
1146         struct dce110_resource_pool *pool)
1147 {
1148         unsigned int i;
1149         struct dc_context *ctx = dc->ctx;
1150         struct dc_bios *bp;
1151
1152         ctx->dc_bios->regs = &bios_regs;
1153
1154         pool->base.res_cap = &res_cap_81;
1155         pool->base.funcs = &dce80_res_pool_funcs;
1156
1157
1158         /*************************************************
1159          *  Resource + asic cap harcoding                *
1160          *************************************************/
1161         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1162         pool->base.pipe_count = res_cap_81.num_timing_generator;
1163         pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1164         dc->caps.max_downscale_ratio = 200;
1165         dc->caps.i2c_speed_in_khz = 40;
1166         dc->caps.i2c_speed_in_khz_hdcp = 40;
1167         dc->caps.max_cursor_size = 128;
1168         dc->caps.min_horizontal_blanking_period = 80;
1169         dc->caps.is_apu = true;
1170
1171         /*************************************************
1172          *  Create resources                             *
1173          *************************************************/
1174
1175         bp = ctx->dc_bios;
1176
1177         if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1178                 pool->base.dp_clock_source =
1179                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1180
1181                 pool->base.clock_sources[0] =
1182                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1183                 pool->base.clock_sources[1] =
1184                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1185                 pool->base.clock_sources[2] =
1186                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1187                 pool->base.clk_src_count = 3;
1188
1189         } else {
1190                 pool->base.dp_clock_source =
1191                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1192
1193                 pool->base.clock_sources[0] =
1194                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1195                 pool->base.clock_sources[1] =
1196                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1197                 pool->base.clk_src_count = 2;
1198         }
1199
1200         if (pool->base.dp_clock_source == NULL) {
1201                 dm_error("DC: failed to create dp clock source!\n");
1202                 BREAK_TO_DEBUGGER();
1203                 goto res_create_fail;
1204         }
1205
1206         for (i = 0; i < pool->base.clk_src_count; i++) {
1207                 if (pool->base.clock_sources[i] == NULL) {
1208                         dm_error("DC: failed to create clock sources!\n");
1209                         BREAK_TO_DEBUGGER();
1210                         goto res_create_fail;
1211                 }
1212         }
1213
1214         pool->base.dmcu = dce_dmcu_create(ctx,
1215                         &dmcu_regs,
1216                         &dmcu_shift,
1217                         &dmcu_mask);
1218         if (pool->base.dmcu == NULL) {
1219                 dm_error("DC: failed to create dmcu!\n");
1220                 BREAK_TO_DEBUGGER();
1221                 goto res_create_fail;
1222         }
1223
1224         pool->base.abm = dce_abm_create(ctx,
1225                         &abm_regs,
1226                         &abm_shift,
1227                         &abm_mask);
1228         if (pool->base.abm == NULL) {
1229                 dm_error("DC: failed to create abm!\n");
1230                 BREAK_TO_DEBUGGER();
1231                 goto res_create_fail;
1232         }
1233
1234         {
1235                 struct irq_service_init_data init_data;
1236                 init_data.ctx = dc->ctx;
1237                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1238                 if (!pool->base.irqs)
1239                         goto res_create_fail;
1240         }
1241
1242         for (i = 0; i < pool->base.pipe_count; i++) {
1243                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1244                                 ctx, i, &dce80_tg_offsets[i]);
1245                 if (pool->base.timing_generators[i] == NULL) {
1246                         BREAK_TO_DEBUGGER();
1247                         dm_error("DC: failed to create tg!\n");
1248                         goto res_create_fail;
1249                 }
1250
1251                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1252                 if (pool->base.mis[i] == NULL) {
1253                         BREAK_TO_DEBUGGER();
1254                         dm_error("DC: failed to create memory input!\n");
1255                         goto res_create_fail;
1256                 }
1257
1258                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1259                 if (pool->base.ipps[i] == NULL) {
1260                         BREAK_TO_DEBUGGER();
1261                         dm_error("DC: failed to create input pixel processor!\n");
1262                         goto res_create_fail;
1263                 }
1264
1265                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1266                 if (pool->base.transforms[i] == NULL) {
1267                         BREAK_TO_DEBUGGER();
1268                         dm_error("DC: failed to create transform!\n");
1269                         goto res_create_fail;
1270                 }
1271
1272                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1273                 if (pool->base.opps[i] == NULL) {
1274                         BREAK_TO_DEBUGGER();
1275                         dm_error("DC: failed to create output pixel processor!\n");
1276                         goto res_create_fail;
1277                 }
1278         }
1279
1280         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1281                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1282                 if (pool->base.engines[i] == NULL) {
1283                         BREAK_TO_DEBUGGER();
1284                         dm_error(
1285                                 "DC:failed to create aux engine!!\n");
1286                         goto res_create_fail;
1287                 }
1288                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1289                 if (pool->base.hw_i2cs[i] == NULL) {
1290                         BREAK_TO_DEBUGGER();
1291                         dm_error(
1292                                 "DC:failed to create i2c engine!!\n");
1293                         goto res_create_fail;
1294                 }
1295                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1296                 if (pool->base.sw_i2cs[i] == NULL) {
1297                         BREAK_TO_DEBUGGER();
1298                         dm_error(
1299                                 "DC:failed to create sw i2c!!\n");
1300                         goto res_create_fail;
1301                 }
1302         }
1303
1304         dc->caps.max_planes =  pool->base.pipe_count;
1305
1306         for (i = 0; i < dc->caps.max_planes; ++i)
1307                 dc->caps.planes[i] = plane_cap;
1308
1309         dc->caps.disable_dp_clk_share = true;
1310
1311         if (!resource_construct(num_virtual_links, dc, &pool->base,
1312                         &res_create_funcs))
1313                 goto res_create_fail;
1314
1315         /* Create hardware sequencer */
1316         dce80_hw_sequencer_construct(dc);
1317
1318         return true;
1319
1320 res_create_fail:
1321         dce80_resource_destruct(pool);
1322         return false;
1323 }
1324
1325 struct resource_pool *dce81_create_resource_pool(
1326         uint8_t num_virtual_links,
1327         struct dc *dc)
1328 {
1329         struct dce110_resource_pool *pool =
1330                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1331
1332         if (!pool)
1333                 return NULL;
1334
1335         if (dce81_construct(num_virtual_links, dc, pool))
1336                 return &pool->base;
1337
1338         BREAK_TO_DEBUGGER();
1339         return NULL;
1340 }
1341
1342 static bool dce83_construct(
1343         uint8_t num_virtual_links,
1344         struct dc *dc,
1345         struct dce110_resource_pool *pool)
1346 {
1347         unsigned int i;
1348         struct dc_context *ctx = dc->ctx;
1349         struct dc_bios *bp;
1350
1351         ctx->dc_bios->regs = &bios_regs;
1352
1353         pool->base.res_cap = &res_cap_83;
1354         pool->base.funcs = &dce80_res_pool_funcs;
1355
1356
1357         /*************************************************
1358          *  Resource + asic cap harcoding                *
1359          *************************************************/
1360         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1361         pool->base.pipe_count = res_cap_83.num_timing_generator;
1362         pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1363         dc->caps.max_downscale_ratio = 200;
1364         dc->caps.i2c_speed_in_khz = 40;
1365         dc->caps.i2c_speed_in_khz_hdcp = 40;
1366         dc->caps.max_cursor_size = 128;
1367         dc->caps.min_horizontal_blanking_period = 80;
1368         dc->caps.is_apu = true;
1369
1370         /*************************************************
1371          *  Create resources                             *
1372          *************************************************/
1373
1374         bp = ctx->dc_bios;
1375
1376         if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1377                 pool->base.dp_clock_source =
1378                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1379
1380                 pool->base.clock_sources[0] =
1381                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1382                 pool->base.clock_sources[1] =
1383                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1384                 pool->base.clk_src_count = 2;
1385
1386         } else {
1387                 pool->base.dp_clock_source =
1388                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1389
1390                 pool->base.clock_sources[0] =
1391                                 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1392                 pool->base.clk_src_count = 1;
1393         }
1394
1395         if (pool->base.dp_clock_source == NULL) {
1396                 dm_error("DC: failed to create dp clock source!\n");
1397                 BREAK_TO_DEBUGGER();
1398                 goto res_create_fail;
1399         }
1400
1401         for (i = 0; i < pool->base.clk_src_count; i++) {
1402                 if (pool->base.clock_sources[i] == NULL) {
1403                         dm_error("DC: failed to create clock sources!\n");
1404                         BREAK_TO_DEBUGGER();
1405                         goto res_create_fail;
1406                 }
1407         }
1408
1409         pool->base.dmcu = dce_dmcu_create(ctx,
1410                         &dmcu_regs,
1411                         &dmcu_shift,
1412                         &dmcu_mask);
1413         if (pool->base.dmcu == NULL) {
1414                 dm_error("DC: failed to create dmcu!\n");
1415                 BREAK_TO_DEBUGGER();
1416                 goto res_create_fail;
1417         }
1418
1419         pool->base.abm = dce_abm_create(ctx,
1420                         &abm_regs,
1421                         &abm_shift,
1422                         &abm_mask);
1423         if (pool->base.abm == NULL) {
1424                 dm_error("DC: failed to create abm!\n");
1425                 BREAK_TO_DEBUGGER();
1426                 goto res_create_fail;
1427         }
1428
1429         {
1430                 struct irq_service_init_data init_data;
1431                 init_data.ctx = dc->ctx;
1432                 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1433                 if (!pool->base.irqs)
1434                         goto res_create_fail;
1435         }
1436
1437         for (i = 0; i < pool->base.pipe_count; i++) {
1438                 pool->base.timing_generators[i] = dce80_timing_generator_create(
1439                                 ctx, i, &dce80_tg_offsets[i]);
1440                 if (pool->base.timing_generators[i] == NULL) {
1441                         BREAK_TO_DEBUGGER();
1442                         dm_error("DC: failed to create tg!\n");
1443                         goto res_create_fail;
1444                 }
1445
1446                 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1447                 if (pool->base.mis[i] == NULL) {
1448                         BREAK_TO_DEBUGGER();
1449                         dm_error("DC: failed to create memory input!\n");
1450                         goto res_create_fail;
1451                 }
1452
1453                 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1454                 if (pool->base.ipps[i] == NULL) {
1455                         BREAK_TO_DEBUGGER();
1456                         dm_error("DC: failed to create input pixel processor!\n");
1457                         goto res_create_fail;
1458                 }
1459
1460                 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1461                 if (pool->base.transforms[i] == NULL) {
1462                         BREAK_TO_DEBUGGER();
1463                         dm_error("DC: failed to create transform!\n");
1464                         goto res_create_fail;
1465                 }
1466
1467                 pool->base.opps[i] = dce80_opp_create(ctx, i);
1468                 if (pool->base.opps[i] == NULL) {
1469                         BREAK_TO_DEBUGGER();
1470                         dm_error("DC: failed to create output pixel processor!\n");
1471                         goto res_create_fail;
1472                 }
1473         }
1474
1475         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1476                 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1477                 if (pool->base.engines[i] == NULL) {
1478                         BREAK_TO_DEBUGGER();
1479                         dm_error(
1480                                 "DC:failed to create aux engine!!\n");
1481                         goto res_create_fail;
1482                 }
1483                 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1484                 if (pool->base.hw_i2cs[i] == NULL) {
1485                         BREAK_TO_DEBUGGER();
1486                         dm_error(
1487                                 "DC:failed to create i2c engine!!\n");
1488                         goto res_create_fail;
1489                 }
1490                 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1491                 if (pool->base.sw_i2cs[i] == NULL) {
1492                         BREAK_TO_DEBUGGER();
1493                         dm_error(
1494                                 "DC:failed to create sw i2c!!\n");
1495                         goto res_create_fail;
1496                 }
1497         }
1498
1499         dc->caps.max_planes =  pool->base.pipe_count;
1500
1501         for (i = 0; i < dc->caps.max_planes; ++i)
1502                 dc->caps.planes[i] = plane_cap;
1503
1504         dc->caps.disable_dp_clk_share = true;
1505
1506         if (!resource_construct(num_virtual_links, dc, &pool->base,
1507                         &res_create_funcs))
1508                 goto res_create_fail;
1509
1510         /* Create hardware sequencer */
1511         dce80_hw_sequencer_construct(dc);
1512
1513         return true;
1514
1515 res_create_fail:
1516         dce80_resource_destruct(pool);
1517         return false;
1518 }
1519
1520 struct resource_pool *dce83_create_resource_pool(
1521         uint8_t num_virtual_links,
1522         struct dc *dc)
1523 {
1524         struct dce110_resource_pool *pool =
1525                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1526
1527         if (!pool)
1528                 return NULL;
1529
1530         if (dce83_construct(num_virtual_links, dc, pool))
1531                 return &pool->base;
1532
1533         BREAK_TO_DEBUGGER();
1534         return NULL;
1535 }