drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* For display hotplug interrupt */
  41 static void
  42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  43 {
  44         if ((dev_priv->irq_mask & mask) != 0) {
  45                 dev_priv->irq_mask &= ~mask;
  46                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  47                 POSTING_READ(DEIMR);
  48         }
  49 }
  50
  51 static inline void
  52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  53 {
  54         if ((dev_priv->irq_mask & mask) != mask) {
  55                 dev_priv->irq_mask |= mask;
  56                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  57                 POSTING_READ(DEIMR);
  58         }
  59 }
  60
  61 void
  62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  63 {
  64         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  65                 u32 reg = PIPESTAT(pipe);
  66
  67                 dev_priv->pipestat[pipe] |= mask;
  68                 /* Enable the interrupt, clear any pending status */
  69                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  70                 POSTING_READ(reg);
  71         }
  72 }
  73
  74 void
  75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  76 {
  77         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  78                 u32 reg = PIPESTAT(pipe);
  79
  80                 dev_priv->pipestat[pipe] &= ~mask;
  81                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  82                 POSTING_READ(reg);
  83         }
  84 }
  85
  86 /**
  87  * intel_enable_asle - enable ASLE interrupt for OpRegion
  88  */
  89 void intel_enable_asle(struct drm_device *dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         unsigned long irqflags;
  93
  94         /* FIXME: opregion/asle for VLV */
  95         if (IS_VALLEYVIEW(dev))
  96                 return;
  97
  98         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  99
 100         if (HAS_PCH_SPLIT(dev))
 101                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 102         else {
 103                 i915_enable_pipestat(dev_priv, 1,
 104                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 105                 if (INTEL_INFO(dev)->gen >= 4)
 106                         i915_enable_pipestat(dev_priv, 0,
 107                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 108         }
 109
 110         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 111 }
 112
 113 /**
 114  * i915_pipe_enabled - check if a pipe is enabled
 115  * @dev: DRM device
 116  * @pipe: pipe to check
 117  *
 118  * Reading certain registers when the pipe is disabled can hang the chip.
 119  * Use this routine to make sure the PLL is running and the pipe is active
 120  * before reading such registers if unsure.
 121  */
 122 static int
 123 i915_pipe_enabled(struct drm_device *dev, int pipe)
 124 {
 125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 126         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 127 }
 128
 129 /* Called from drm generic code, passed a 'crtc', which
 130  * we use as a pipe index
 131  */
 132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 133 {
 134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 135         unsigned long high_frame;
 136         unsigned long low_frame;
 137         u32 high1, high2, low;
 138
 139         if (!i915_pipe_enabled(dev, pipe)) {
 140                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 141                                 "pipe %c\n", pipe_name(pipe));
 142                 return 0;
 143         }
 144
 145         high_frame = PIPEFRAME(pipe);
 146         low_frame = PIPEFRAMEPIXEL(pipe);
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 155                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 156                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157         } while (high1 != high2);
 158
 159         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 160         low >>= PIPE_FRAME_LOW_SHIFT;
 161         return (high1 << 8) | low;
 162 }
 163
 164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 165 {
 166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 167         int reg = PIPE_FRMCOUNT_GM45(pipe);
 168
 169         if (!i915_pipe_enabled(dev, pipe)) {
 170                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 171                                  "pipe %c\n", pipe_name(pipe));
 172                 return 0;
 173         }
 174
 175         return I915_READ(reg);
 176 }
 177
 178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 179                              int *vpos, int *hpos)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         u32 vbl = 0, position = 0;
 183         int vbl_start, vbl_end, htotal, vtotal;
 184         bool in_vbl = true;
 185         int ret = 0;
 186
 187         if (!i915_pipe_enabled(dev, pipe)) {
 188                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 189                                  "pipe %c\n", pipe_name(pipe));
 190                 return 0;
 191         }
 192
 193         /* Get vtotal. */
 194         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 195
 196         if (INTEL_INFO(dev)->gen >= 4) {
 197                 /* No obvious pixelcount register. Only query vertical
 198                  * scanout position from Display scan line register.
 199                  */
 200                 position = I915_READ(PIPEDSL(pipe));
 201
 202                 /* Decode into vertical scanout position. Don't have
 203                  * horizontal scanout position.
 204                  */
 205                 *vpos = position & 0x1fff;
 206                 *hpos = 0;
 207         } else {
 208                 /* Have access to pixelcount since start of frame.
 209                  * We can split this into vertical and horizontal
 210                  * scanout position.
 211                  */
 212                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 213
 214                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 215                 *vpos = position / htotal;
 216                 *hpos = position - (*vpos * htotal);
 217         }
 218
 219         /* Query vblank area. */
 220         vbl = I915_READ(VBLANK(pipe));
 221
 222         /* Test position against vblank region. */
 223         vbl_start = vbl & 0x1fff;
 224         vbl_end = (vbl >> 16) & 0x1fff;
 225
 226         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 227                 in_vbl = false;
 228
 229         /* Inside "upper part" of vblank area? Apply corrective offset: */
 230         if (in_vbl && (*vpos >= vbl_start))
 231                 *vpos = *vpos - vtotal;
 232
 233         /* Readouts valid? */
 234         if (vbl > 0)
 235                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 236
 237         /* In vblank? */
 238         if (in_vbl)
 239                 ret |= DRM_SCANOUTPOS_INVBL;
 240
 241         return ret;
 242 }
 243
 244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 245                               int *max_error,
 246                               struct timeval *vblank_time,
 247                               unsigned flags)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         struct drm_crtc *crtc;
 251
 252         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 253                 DRM_ERROR("Invalid crtc %d\n", pipe);
 254                 return -EINVAL;
 255         }
 256
 257         /* Get drm_crtc to timestamp: */
 258         crtc = intel_get_crtc_for_pipe(dev, pipe);
 259         if (crtc == NULL) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         if (!crtc->enabled) {
 265                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 266                 return -EBUSY;
 267         }
 268
 269         /* Helper routine in DRM core does all the work: */
 270         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 271                                                      vblank_time, flags,
 272                                                      crtc);
 273 }
 274
 275 /*
 276  * Handle hotplug events outside the interrupt handler proper.
 277  */
 278 static void i915_hotplug_work_func(struct work_struct *work)
 279 {
 280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 281                                                     hotplug_work);
 282         struct drm_device *dev = dev_priv->dev;
 283         struct drm_mode_config *mode_config = &dev->mode_config;
 284         struct intel_encoder *encoder;
 285
 286         mutex_lock(&mode_config->mutex);
 287         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 288
 289         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 290                 if (encoder->hot_plug)
 291                         encoder->hot_plug(encoder);
 292
 293         mutex_unlock(&mode_config->mutex);
 294
 295         /* Just fire off a uevent and let userspace tell us what to do */
 296         drm_helper_hpd_irq_event(dev);
 297 }
 298
 299 /* defined intel_pm.c */
 300 extern spinlock_t mchdev_lock;
 301
 302 static void ironlake_handle_rps_change(struct drm_device *dev)
 303 {
 304         drm_i915_private_t *dev_priv = dev->dev_private;
 305         u32 busy_up, busy_down, max_avg, min_avg;
 306         u8 new_delay;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&mchdev_lock, flags);
 310
 311         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 312
 313         new_delay = dev_priv->ips.cur_delay;
 314
 315         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 316         busy_up = I915_READ(RCPREVBSYTUPAVG);
 317         busy_down = I915_READ(RCPREVBSYTDNAVG);
 318         max_avg = I915_READ(RCBMAXAVG);
 319         min_avg = I915_READ(RCBMINAVG);
 320
 321         /* Handle RCS change request from hw */
 322         if (busy_up > max_avg) {
 323                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 324                         new_delay = dev_priv->ips.cur_delay - 1;
 325                 if (new_delay < dev_priv->ips.max_delay)
 326                         new_delay = dev_priv->ips.max_delay;
 327         } else if (busy_down < min_avg) {
 328                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 329                         new_delay = dev_priv->ips.cur_delay + 1;
 330                 if (new_delay > dev_priv->ips.min_delay)
 331                         new_delay = dev_priv->ips.min_delay;
 332         }
 333
 334         if (ironlake_set_drps(dev, new_delay))
 335                 dev_priv->ips.cur_delay = new_delay;
 336
 337         spin_unlock_irqrestore(&mchdev_lock, flags);
 338
 339         return;
 340 }
 341
 342 static void notify_ring(struct drm_device *dev,
 343                         struct intel_ring_buffer *ring)
 344 {
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346
 347         if (ring->obj == NULL)
 348                 return;
 349
 350         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 351
 352         wake_up_all(&ring->irq_queue);
 353         if (i915_enable_hangcheck) {
 354                 dev_priv->hangcheck_count = 0;
 355                 mod_timer(&dev_priv->hangcheck_timer,
 356                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 357         }
 358 }
 359
 360 static void gen6_pm_rps_work(struct work_struct *work)
 361 {
 362         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 363                                                     rps.work);
 364         u32 pm_iir, pm_imr;
 365         u8 new_delay;
 366
 367         spin_lock_irq(&dev_priv->rps.lock);
 368         pm_iir = dev_priv->rps.pm_iir;
 369         dev_priv->rps.pm_iir = 0;
 370         pm_imr = I915_READ(GEN6_PMIMR);
 371         I915_WRITE(GEN6_PMIMR, 0);
 372         spin_unlock_irq(&dev_priv->rps.lock);
 373
 374         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 375                 return;
 376
 377         mutex_lock(&dev_priv->dev->struct_mutex);
 378
 379         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 380                 new_delay = dev_priv->rps.cur_delay + 1;
 381         else
 382                 new_delay = dev_priv->rps.cur_delay - 1;
 383
 384         /* sysfs frequency interfaces may have snuck in while servicing the
 385          * interrupt
 386          */
 387         if (!(new_delay > dev_priv->rps.max_delay ||
 388               new_delay < dev_priv->rps.min_delay)) {
 389                 gen6_set_rps(dev_priv->dev, new_delay);
 390         }
 391
 392         mutex_unlock(&dev_priv->dev->struct_mutex);
 393 }
 394
 395
 396 /**
 397  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 398  * occurred.
 399  * @work: workqueue struct
 400  *
 401  * Doesn't actually do anything except notify userspace. As a consequence of
 402  * this event, userspace should try to remap the bad rows since statistically
 403  * it is likely the same row is more likely to go bad again.
 404  */
 405 static void ivybridge_parity_work(struct work_struct *work)
 406 {
 407         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 408                                                     parity_error_work);
 409         u32 error_status, row, bank, subbank;
 410         char *parity_event[5];
 411         uint32_t misccpctl;
 412         unsigned long flags;
 413
 414         /* We must turn off DOP level clock gating to access the L3 registers.
 415          * In order to prevent a get/put style interface, acquire struct mutex
 416          * any time we access those registers.
 417          */
 418         mutex_lock(&dev_priv->dev->struct_mutex);
 419
 420         misccpctl = I915_READ(GEN7_MISCCPCTL);
 421         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 422         POSTING_READ(GEN7_MISCCPCTL);
 423
 424         error_status = I915_READ(GEN7_L3CDERRST1);
 425         row = GEN7_PARITY_ERROR_ROW(error_status);
 426         bank = GEN7_PARITY_ERROR_BANK(error_status);
 427         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 428
 429         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 430                                     GEN7_L3CDERRST1_ENABLE);
 431         POSTING_READ(GEN7_L3CDERRST1);
 432
 433         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 434
 435         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 436         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 437         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 438         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 439
 440         mutex_unlock(&dev_priv->dev->struct_mutex);
 441
 442         parity_event[0] = "L3_PARITY_ERROR=1";
 443         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 444         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 445         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 446         parity_event[4] = NULL;
 447
 448         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 449                            KOBJ_CHANGE, parity_event);
 450
 451         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 452                   row, bank, subbank);
 453
 454         kfree(parity_event[3]);
 455         kfree(parity_event[2]);
 456         kfree(parity_event[1]);
 457 }
 458
 459 static void ivybridge_handle_parity_error(struct drm_device *dev)
 460 {
 461         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 462         unsigned long flags;
 463
 464         if (!HAS_L3_GPU_CACHE(dev))
 465                 return;
 466
 467         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 468         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 469         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 470         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 471
 472         queue_work(dev_priv->wq, &dev_priv->parity_error_work);
 473 }
 474
 475 static void snb_gt_irq_handler(struct drm_device *dev,
 476                                struct drm_i915_private *dev_priv,
 477                                u32 gt_iir)
 478 {
 479
 480         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 481                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 482                 notify_ring(dev, &dev_priv->ring[RCS]);
 483         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 484                 notify_ring(dev, &dev_priv->ring[VCS]);
 485         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 486                 notify_ring(dev, &dev_priv->ring[BCS]);
 487
 488         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 489                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 490                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 491                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 492                 i915_handle_error(dev, false);
 493         }
 494
 495         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 496                 ivybridge_handle_parity_error(dev);
 497 }
 498
 499 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 500                                 u32 pm_iir)
 501 {
 502         unsigned long flags;
 503
 504         /*
 505          * IIR bits should never already be set because IMR should
 506          * prevent an interrupt from being shown in IIR. The warning
 507          * displays a case where we've unsafely cleared
 508          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 509          * type is not a problem, it displays a problem in the logic.
 510          *
 511          * The mask bit in IMR is cleared by dev_priv->rps.work.
 512          */
 513
 514         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 515         dev_priv->rps.pm_iir |= pm_iir;
 516         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 517         POSTING_READ(GEN6_PMIMR);
 518         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 519
 520         queue_work(dev_priv->wq, &dev_priv->rps.work);
 521 }
 522
 523 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 524 {
 525         struct drm_device *dev = (struct drm_device *) arg;
 526         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 527         u32 iir, gt_iir, pm_iir;
 528         irqreturn_t ret = IRQ_NONE;
 529         unsigned long irqflags;
 530         int pipe;
 531         u32 pipe_stats[I915_MAX_PIPES];
 532         bool blc_event;
 533
 534         atomic_inc(&dev_priv->irq_received);
 535
 536         while (true) {
 537                 iir = I915_READ(VLV_IIR);
 538                 gt_iir = I915_READ(GTIIR);
 539                 pm_iir = I915_READ(GEN6_PMIIR);
 540
 541                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 542                         goto out;
 543
 544                 ret = IRQ_HANDLED;
 545
 546                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 547
 548                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 549                 for_each_pipe(pipe) {
 550                         int reg = PIPESTAT(pipe);
 551                         pipe_stats[pipe] = I915_READ(reg);
 552
 553                         /*
 554                          * Clear the PIPE*STAT regs before the IIR
 555                          */
 556                         if (pipe_stats[pipe] & 0x8000ffff) {
 557                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 558                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 559                                                          pipe_name(pipe));
 560                                 I915_WRITE(reg, pipe_stats[pipe]);
 561                         }
 562                 }
 563                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 564
 565                 for_each_pipe(pipe) {
 566                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 567                                 drm_handle_vblank(dev, pipe);
 568
 569                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 570                                 intel_prepare_page_flip(dev, pipe);
 571                                 intel_finish_page_flip(dev, pipe);
 572                         }
 573                 }
 574
 575                 /* Consume port.  Then clear IIR or we'll miss events */
 576                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 577                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 578
 579                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 580                                          hotplug_status);
 581                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 582                                 queue_work(dev_priv->wq,
 583                                            &dev_priv->hotplug_work);
 584
 585                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 586                         I915_READ(PORT_HOTPLUG_STAT);
 587                 }
 588
 589                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 590                         blc_event = true;
 591
 592                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 593                         gen6_queue_rps_work(dev_priv, pm_iir);
 594
 595                 I915_WRITE(GTIIR, gt_iir);
 596                 I915_WRITE(GEN6_PMIIR, pm_iir);
 597                 I915_WRITE(VLV_IIR, iir);
 598         }
 599
 600 out:
 601         return ret;
 602 }
 603
 604 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 605 {
 606         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 607         int pipe;
 608
 609         if (pch_iir & SDE_HOTPLUG_MASK)
 610                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 611
 612         if (pch_iir & SDE_AUDIO_POWER_MASK)
 613                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 614                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 615                                  SDE_AUDIO_POWER_SHIFT);
 616
 617         if (pch_iir & SDE_GMBUS)
 618                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 619
 620         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 621                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 622
 623         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 624                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 625
 626         if (pch_iir & SDE_POISON)
 627                 DRM_ERROR("PCH poison interrupt\n");
 628
 629         if (pch_iir & SDE_FDI_MASK)
 630                 for_each_pipe(pipe)
 631                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 632                                          pipe_name(pipe),
 633                                          I915_READ(FDI_RX_IIR(pipe)));
 634
 635         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 636                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 637
 638         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 639                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 640
 641         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 642                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 643         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 644                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 645 }
 646
 647 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 648 {
 649         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 650         int pipe;
 651
 652         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 653                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 654
 655         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 656                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 657                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 658                                  SDE_AUDIO_POWER_SHIFT_CPT);
 659
 660         if (pch_iir & SDE_AUX_MASK_CPT)
 661                 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 662
 663         if (pch_iir & SDE_GMBUS_CPT)
 664                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 665
 666         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 667                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 668
 669         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 670                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 671
 672         if (pch_iir & SDE_FDI_MASK_CPT)
 673                 for_each_pipe(pipe)
 674                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 675                                          pipe_name(pipe),
 676                                          I915_READ(FDI_RX_IIR(pipe)));
 677 }
 678
 679 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 680 {
 681         struct drm_device *dev = (struct drm_device *) arg;
 682         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 683         u32 de_iir, gt_iir, de_ier, pm_iir;
 684         irqreturn_t ret = IRQ_NONE;
 685         int i;
 686
 687         atomic_inc(&dev_priv->irq_received);
 688
 689         /* disable master interrupt before clearing iir  */
 690         de_ier = I915_READ(DEIER);
 691         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 692
 693         gt_iir = I915_READ(GTIIR);
 694         if (gt_iir) {
 695                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 696                 I915_WRITE(GTIIR, gt_iir);
 697                 ret = IRQ_HANDLED;
 698         }
 699
 700         de_iir = I915_READ(DEIIR);
 701         if (de_iir) {
 702                 if (de_iir & DE_GSE_IVB)
 703                         intel_opregion_gse_intr(dev);
 704
 705                 for (i = 0; i < 3; i++) {
 706                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 707                                 intel_prepare_page_flip(dev, i);
 708                                 intel_finish_page_flip_plane(dev, i);
 709                         }
 710                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 711                                 drm_handle_vblank(dev, i);
 712                 }
 713
 714                 /* check event from PCH */
 715                 if (de_iir & DE_PCH_EVENT_IVB) {
 716                         u32 pch_iir = I915_READ(SDEIIR);
 717
 718                         cpt_irq_handler(dev, pch_iir);
 719
 720                         /* clear PCH hotplug event before clear CPU irq */
 721                         I915_WRITE(SDEIIR, pch_iir);
 722                 }
 723
 724                 I915_WRITE(DEIIR, de_iir);
 725                 ret = IRQ_HANDLED;
 726         }
 727
 728         pm_iir = I915_READ(GEN6_PMIIR);
 729         if (pm_iir) {
 730                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 731                         gen6_queue_rps_work(dev_priv, pm_iir);
 732                 I915_WRITE(GEN6_PMIIR, pm_iir);
 733                 ret = IRQ_HANDLED;
 734         }
 735
 736         I915_WRITE(DEIER, de_ier);
 737         POSTING_READ(DEIER);
 738
 739         return ret;
 740 }
 741
 742 static void ilk_gt_irq_handler(struct drm_device *dev,
 743                                struct drm_i915_private *dev_priv,
 744                                u32 gt_iir)
 745 {
 746         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 747                 notify_ring(dev, &dev_priv->ring[RCS]);
 748         if (gt_iir & GT_BSD_USER_INTERRUPT)
 749                 notify_ring(dev, &dev_priv->ring[VCS]);
 750 }
 751
 752 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 753 {
 754         struct drm_device *dev = (struct drm_device *) arg;
 755         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 756         int ret = IRQ_NONE;
 757         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 758
 759         atomic_inc(&dev_priv->irq_received);
 760
 761         /* disable master interrupt before clearing iir  */
 762         de_ier = I915_READ(DEIER);
 763         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 764         POSTING_READ(DEIER);
 765
 766         de_iir = I915_READ(DEIIR);
 767         gt_iir = I915_READ(GTIIR);
 768         pch_iir = I915_READ(SDEIIR);
 769         pm_iir = I915_READ(GEN6_PMIIR);
 770
 771         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 772             (!IS_GEN6(dev) || pm_iir == 0))
 773                 goto done;
 774
 775         ret = IRQ_HANDLED;
 776
 777         if (IS_GEN5(dev))
 778                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 779         else
 780                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 781
 782         if (de_iir & DE_GSE)
 783                 intel_opregion_gse_intr(dev);
 784
 785         if (de_iir & DE_PLANEA_FLIP_DONE) {
 786                 intel_prepare_page_flip(dev, 0);
 787                 intel_finish_page_flip_plane(dev, 0);
 788         }
 789
 790         if (de_iir & DE_PLANEB_FLIP_DONE) {
 791                 intel_prepare_page_flip(dev, 1);
 792                 intel_finish_page_flip_plane(dev, 1);
 793         }
 794
 795         if (de_iir & DE_PIPEA_VBLANK)
 796                 drm_handle_vblank(dev, 0);
 797
 798         if (de_iir & DE_PIPEB_VBLANK)
 799                 drm_handle_vblank(dev, 1);
 800
 801         /* check event from PCH */
 802         if (de_iir & DE_PCH_EVENT) {
 803                 if (HAS_PCH_CPT(dev))
 804                         cpt_irq_handler(dev, pch_iir);
 805                 else
 806                         ibx_irq_handler(dev, pch_iir);
 807         }
 808
 809         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 810                 ironlake_handle_rps_change(dev);
 811
 812         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 813                 gen6_queue_rps_work(dev_priv, pm_iir);
 814
 815         /* should clear PCH hotplug event before clear CPU irq */
 816         I915_WRITE(SDEIIR, pch_iir);
 817         I915_WRITE(GTIIR, gt_iir);
 818         I915_WRITE(DEIIR, de_iir);
 819         I915_WRITE(GEN6_PMIIR, pm_iir);
 820
 821 done:
 822         I915_WRITE(DEIER, de_ier);
 823         POSTING_READ(DEIER);
 824
 825         return ret;
 826 }
 827
 828 /**
 829  * i915_error_work_func - do process context error handling work
 830  * @work: work struct
 831  *
 832  * Fire an error uevent so userspace can see that a hang or error
 833  * was detected.
 834  */
 835 static void i915_error_work_func(struct work_struct *work)
 836 {
 837         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 838                                                     error_work);
 839         struct drm_device *dev = dev_priv->dev;
 840         char *error_event[] = { "ERROR=1", NULL };
 841         char *reset_event[] = { "RESET=1", NULL };
 842         char *reset_done_event[] = { "ERROR=0", NULL };
 843
 844         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 845
 846         if (atomic_read(&dev_priv->mm.wedged)) {
 847                 DRM_DEBUG_DRIVER("resetting chip\n");
 848                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 849                 if (!i915_reset(dev)) {
 850                         atomic_set(&dev_priv->mm.wedged, 0);
 851                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 852                 }
 853                 complete_all(&dev_priv->error_completion);
 854         }
 855 }
 856
 857 /* NB: please notice the memset */
 858 static void i915_get_extra_instdone(struct drm_device *dev,
 859                                     uint32_t *instdone)
 860 {
 861         struct drm_i915_private *dev_priv = dev->dev_private;
 862         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 863
 864         switch(INTEL_INFO(dev)->gen) {
 865         case 2:
 866         case 3:
 867                 instdone[0] = I915_READ(INSTDONE);
 868                 break;
 869         case 4:
 870         case 5:
 871         case 6:
 872                 instdone[0] = I915_READ(INSTDONE_I965);
 873                 instdone[1] = I915_READ(INSTDONE1);
 874                 break;
 875         default:
 876                 WARN_ONCE(1, "Unsupported platform\n");
 877         case 7:
 878                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
 879                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 880                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
 881                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
 882                 break;
 883         }
 884 }
 885
 886 #ifdef CONFIG_DEBUG_FS
 887 static struct drm_i915_error_object *
 888 i915_error_object_create(struct drm_i915_private *dev_priv,
 889                          struct drm_i915_gem_object *src)
 890 {
 891         struct drm_i915_error_object *dst;
 892         int i, count;
 893         u32 reloc_offset;
 894
 895         if (src == NULL || src->pages == NULL)
 896                 return NULL;
 897
 898         count = src->base.size / PAGE_SIZE;
 899
 900         dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
 901         if (dst == NULL)
 902                 return NULL;
 903
 904         reloc_offset = src->gtt_offset;
 905         for (i = 0; i < count; i++) {
 906                 unsigned long flags;
 907                 void *d;
 908
 909                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 910                 if (d == NULL)
 911                         goto unwind;
 912
 913                 local_irq_save(flags);
 914                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 915                     src->has_global_gtt_mapping) {
 916                         void __iomem *s;
 917
 918                         /* Simply ignore tiling or any overlapping fence.
 919                          * It's part of the error state, and this hopefully
 920                          * captures what the GPU read.
 921                          */
 922
 923                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 924                                                      reloc_offset);
 925                         memcpy_fromio(d, s, PAGE_SIZE);
 926                         io_mapping_unmap_atomic(s);
 927                 } else {
 928                         struct page *page;
 929                         void *s;
 930
 931                         page = i915_gem_object_get_page(src, i);
 932
 933                         drm_clflush_pages(&page, 1);
 934
 935                         s = kmap_atomic(page);
 936                         memcpy(d, s, PAGE_SIZE);
 937                         kunmap_atomic(s);
 938
 939                         drm_clflush_pages(&page, 1);
 940                 }
 941                 local_irq_restore(flags);
 942
 943                 dst->pages[i] = d;
 944
 945                 reloc_offset += PAGE_SIZE;
 946         }
 947         dst->page_count = count;
 948         dst->gtt_offset = src->gtt_offset;
 949
 950         return dst;
 951
 952 unwind:
 953         while (i--)
 954                 kfree(dst->pages[i]);
 955         kfree(dst);
 956         return NULL;
 957 }
 958
 959 static void
 960 i915_error_object_free(struct drm_i915_error_object *obj)
 961 {
 962         int page;
 963
 964         if (obj == NULL)
 965                 return;
 966
 967         for (page = 0; page < obj->page_count; page++)
 968                 kfree(obj->pages[page]);
 969
 970         kfree(obj);
 971 }
 972
 973 void
 974 i915_error_state_free(struct kref *error_ref)
 975 {
 976         struct drm_i915_error_state *error = container_of(error_ref,
 977                                                           typeof(*error), ref);
 978         int i;
 979
 980         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 981                 i915_error_object_free(error->ring[i].batchbuffer);
 982                 i915_error_object_free(error->ring[i].ringbuffer);
 983                 kfree(error->ring[i].requests);
 984         }
 985
 986         kfree(error->active_bo);
 987         kfree(error->overlay);
 988         kfree(error);
 989 }
 990 static void capture_bo(struct drm_i915_error_buffer *err,
 991                        struct drm_i915_gem_object *obj)
 992 {
 993         err->size = obj->base.size;
 994         err->name = obj->base.name;
 995         err->rseqno = obj->last_read_seqno;
 996         err->wseqno = obj->last_write_seqno;
 997         err->gtt_offset = obj->gtt_offset;
 998         err->read_domains = obj->base.read_domains;
 999         err->write_domain = obj->base.write_domain;
1000         err->fence_reg = obj->fence_reg;
1001         err->pinned = 0;
1002         if (obj->pin_count > 0)
1003                 err->pinned = 1;
1004         if (obj->user_pin_count > 0)
1005                 err->pinned = -1;
1006         err->tiling = obj->tiling_mode;
1007         err->dirty = obj->dirty;
1008         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1009         err->ring = obj->ring ? obj->ring->id : -1;
1010         err->cache_level = obj->cache_level;
1011 }
1012
1013 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1014                              int count, struct list_head *head)
1015 {
1016         struct drm_i915_gem_object *obj;
1017         int i = 0;
1018
1019         list_for_each_entry(obj, head, mm_list) {
1020                 capture_bo(err++, obj);
1021                 if (++i == count)
1022                         break;
1023         }
1024
1025         return i;
1026 }
1027
1028 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1029                              int count, struct list_head *head)
1030 {
1031         struct drm_i915_gem_object *obj;
1032         int i = 0;
1033
1034         list_for_each_entry(obj, head, gtt_list) {
1035                 if (obj->pin_count == 0)
1036                         continue;
1037
1038                 capture_bo(err++, obj);
1039                 if (++i == count)
1040                         break;
1041         }
1042
1043         return i;
1044 }
1045
1046 static void i915_gem_record_fences(struct drm_device *dev,
1047                                    struct drm_i915_error_state *error)
1048 {
1049         struct drm_i915_private *dev_priv = dev->dev_private;
1050         int i;
1051
1052         /* Fences */
1053         switch (INTEL_INFO(dev)->gen) {
1054         case 7:
1055         case 6:
1056                 for (i = 0; i < 16; i++)
1057                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1058                 break;
1059         case 5:
1060         case 4:
1061                 for (i = 0; i < 16; i++)
1062                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1063                 break;
1064         case 3:
1065                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1066                         for (i = 0; i < 8; i++)
1067                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1068         case 2:
1069                 for (i = 0; i < 8; i++)
1070                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1071                 break;
1072
1073         }
1074 }
1075
1076 static struct drm_i915_error_object *
1077 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1078                              struct intel_ring_buffer *ring)
1079 {
1080         struct drm_i915_gem_object *obj;
1081         u32 seqno;
1082
1083         if (!ring->get_seqno)
1084                 return NULL;
1085
1086         seqno = ring->get_seqno(ring, false);
1087         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1088                 if (obj->ring != ring)
1089                         continue;
1090
1091                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1092                         continue;
1093
1094                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1095                         continue;
1096
1097                 /* We need to copy these to an anonymous buffer as the simplest
1098                  * method to avoid being overwritten by userspace.
1099                  */
1100                 return i915_error_object_create(dev_priv, obj);
1101         }
1102
1103         return NULL;
1104 }
1105
1106 static void i915_record_ring_state(struct drm_device *dev,
1107                                    struct drm_i915_error_state *error,
1108                                    struct intel_ring_buffer *ring)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111
1112         if (INTEL_INFO(dev)->gen >= 6) {
1113                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1114                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1115                 error->semaphore_mboxes[ring->id][0]
1116                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1117                 error->semaphore_mboxes[ring->id][1]
1118                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1119         }
1120
1121         if (INTEL_INFO(dev)->gen >= 4) {
1122                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1123                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1124                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1125                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1126                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1127                 if (ring->id == RCS)
1128                         error->bbaddr = I915_READ64(BB_ADDR);
1129         } else {
1130                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1131                 error->ipeir[ring->id] = I915_READ(IPEIR);
1132                 error->ipehr[ring->id] = I915_READ(IPEHR);
1133                 error->instdone[ring->id] = I915_READ(INSTDONE);
1134         }
1135
1136         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1137         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1138         error->seqno[ring->id] = ring->get_seqno(ring, false);
1139         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1140         error->head[ring->id] = I915_READ_HEAD(ring);
1141         error->tail[ring->id] = I915_READ_TAIL(ring);
1142
1143         error->cpu_ring_head[ring->id] = ring->head;
1144         error->cpu_ring_tail[ring->id] = ring->tail;
1145 }
1146
1147 static void i915_gem_record_rings(struct drm_device *dev,
1148                                   struct drm_i915_error_state *error)
1149 {
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         struct intel_ring_buffer *ring;
1152         struct drm_i915_gem_request *request;
1153         int i, count;
1154
1155         for_each_ring(ring, dev_priv, i) {
1156                 i915_record_ring_state(dev, error, ring);
1157
1158                 error->ring[i].batchbuffer =
1159                         i915_error_first_batchbuffer(dev_priv, ring);
1160
1161                 error->ring[i].ringbuffer =
1162                         i915_error_object_create(dev_priv, ring->obj);
1163
1164                 count = 0;
1165                 list_for_each_entry(request, &ring->request_list, list)
1166                         count++;
1167
1168                 error->ring[i].num_requests = count;
1169                 error->ring[i].requests =
1170                         kmalloc(count*sizeof(struct drm_i915_error_request),
1171                                 GFP_ATOMIC);
1172                 if (error->ring[i].requests == NULL) {
1173                         error->ring[i].num_requests = 0;
1174                         continue;
1175                 }
1176
1177                 count = 0;
1178                 list_for_each_entry(request, &ring->request_list, list) {
1179                         struct drm_i915_error_request *erq;
1180
1181                         erq = &error->ring[i].requests[count++];
1182                         erq->seqno = request->seqno;
1183                         erq->jiffies = request->emitted_jiffies;
1184                         erq->tail = request->tail;
1185                 }
1186         }
1187 }
1188
1189 /**
1190  * i915_capture_error_state - capture an error record for later analysis
1191  * @dev: drm device
1192  *
1193  * Should be called when an error is detected (either a hang or an error
1194  * interrupt) to capture error state from the time of the error.  Fills
1195  * out a structure which becomes available in debugfs for user level tools
1196  * to pick up.
1197  */
1198 static void i915_capture_error_state(struct drm_device *dev)
1199 {
1200         struct drm_i915_private *dev_priv = dev->dev_private;
1201         struct drm_i915_gem_object *obj;
1202         struct drm_i915_error_state *error;
1203         unsigned long flags;
1204         int i, pipe;
1205
1206         spin_lock_irqsave(&dev_priv->error_lock, flags);
1207         error = dev_priv->first_error;
1208         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1209         if (error)
1210                 return;
1211
1212         /* Account for pipe specific data like PIPE*STAT */
1213         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1214         if (!error) {
1215                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1216                 return;
1217         }
1218
1219         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1220                  dev->primary->index);
1221
1222         kref_init(&error->ref);
1223         error->eir = I915_READ(EIR);
1224         error->pgtbl_er = I915_READ(PGTBL_ER);
1225         error->ccid = I915_READ(CCID);
1226
1227         if (HAS_PCH_SPLIT(dev))
1228                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1229         else if (IS_VALLEYVIEW(dev))
1230                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1231         else if (IS_GEN2(dev))
1232                 error->ier = I915_READ16(IER);
1233         else
1234                 error->ier = I915_READ(IER);
1235
1236         for_each_pipe(pipe)
1237                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1238
1239         if (INTEL_INFO(dev)->gen >= 6) {
1240                 error->error = I915_READ(ERROR_GEN6);
1241                 error->done_reg = I915_READ(DONE_REG);
1242         }
1243
1244         if (INTEL_INFO(dev)->gen == 7)
1245                 error->err_int = I915_READ(GEN7_ERR_INT);
1246
1247         i915_get_extra_instdone(dev, error->extra_instdone);
1248
1249         i915_gem_record_fences(dev, error);
1250         i915_gem_record_rings(dev, error);
1251
1252         /* Record buffers on the active and pinned lists. */
1253         error->active_bo = NULL;
1254         error->pinned_bo = NULL;
1255
1256         i = 0;
1257         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1258                 i++;
1259         error->active_bo_count = i;
1260         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1261                 if (obj->pin_count)
1262                         i++;
1263         error->pinned_bo_count = i - error->active_bo_count;
1264
1265         error->active_bo = NULL;
1266         error->pinned_bo = NULL;
1267         if (i) {
1268                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1269                                            GFP_ATOMIC);
1270                 if (error->active_bo)
1271                         error->pinned_bo =
1272                                 error->active_bo + error->active_bo_count;
1273         }
1274
1275         if (error->active_bo)
1276                 error->active_bo_count =
1277                         capture_active_bo(error->active_bo,
1278                                           error->active_bo_count,
1279                                           &dev_priv->mm.active_list);
1280
1281         if (error->pinned_bo)
1282                 error->pinned_bo_count =
1283                         capture_pinned_bo(error->pinned_bo,
1284                                           error->pinned_bo_count,
1285                                           &dev_priv->mm.bound_list);
1286
1287         do_gettimeofday(&error->time);
1288
1289         error->overlay = intel_overlay_capture_error_state(dev);
1290         error->display = intel_display_capture_error_state(dev);
1291
1292         spin_lock_irqsave(&dev_priv->error_lock, flags);
1293         if (dev_priv->first_error == NULL) {
1294                 dev_priv->first_error = error;
1295                 error = NULL;
1296         }
1297         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1298
1299         if (error)
1300                 i915_error_state_free(&error->ref);
1301 }
1302
1303 void i915_destroy_error_state(struct drm_device *dev)
1304 {
1305         struct drm_i915_private *dev_priv = dev->dev_private;
1306         struct drm_i915_error_state *error;
1307         unsigned long flags;
1308
1309         spin_lock_irqsave(&dev_priv->error_lock, flags);
1310         error = dev_priv->first_error;
1311         dev_priv->first_error = NULL;
1312         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1313
1314         if (error)
1315                 kref_put(&error->ref, i915_error_state_free);
1316 }
1317 #else
1318 #define i915_capture_error_state(x)
1319 #endif
1320
1321 static void i915_report_and_clear_eir(struct drm_device *dev)
1322 {
1323         struct drm_i915_private *dev_priv = dev->dev_private;
1324         uint32_t instdone[I915_NUM_INSTDONE_REG];
1325         u32 eir = I915_READ(EIR);
1326         int pipe, i;
1327
1328         if (!eir)
1329                 return;
1330
1331         pr_err("render error detected, EIR: 0x%08x\n", eir);
1332
1333         i915_get_extra_instdone(dev, instdone);
1334
1335         if (IS_G4X(dev)) {
1336                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1337                         u32 ipeir = I915_READ(IPEIR_I965);
1338
1339                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1340                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1341                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1342                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1343                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1344                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1345                         I915_WRITE(IPEIR_I965, ipeir);
1346                         POSTING_READ(IPEIR_I965);
1347                 }
1348                 if (eir & GM45_ERROR_PAGE_TABLE) {
1349                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1350                         pr_err("page table error\n");
1351                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1352                         I915_WRITE(PGTBL_ER, pgtbl_err);
1353                         POSTING_READ(PGTBL_ER);
1354                 }
1355         }
1356
1357         if (!IS_GEN2(dev)) {
1358                 if (eir & I915_ERROR_PAGE_TABLE) {
1359                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1360                         pr_err("page table error\n");
1361                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1362                         I915_WRITE(PGTBL_ER, pgtbl_err);
1363                         POSTING_READ(PGTBL_ER);
1364                 }
1365         }
1366
1367         if (eir & I915_ERROR_MEMORY_REFRESH) {
1368                 pr_err("memory refresh error:\n");
1369                 for_each_pipe(pipe)
1370                         pr_err("pipe %c stat: 0x%08x\n",
1371                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1372                 /* pipestat has already been acked */
1373         }
1374         if (eir & I915_ERROR_INSTRUCTION) {
1375                 pr_err("instruction error\n");
1376                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1377                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1378                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1379                 if (INTEL_INFO(dev)->gen < 4) {
1380                         u32 ipeir = I915_READ(IPEIR);
1381
1382                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1383                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1384                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1385                         I915_WRITE(IPEIR, ipeir);
1386                         POSTING_READ(IPEIR);
1387                 } else {
1388                         u32 ipeir = I915_READ(IPEIR_I965);
1389
1390                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1391                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1392                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1393                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1394                         I915_WRITE(IPEIR_I965, ipeir);
1395                         POSTING_READ(IPEIR_I965);
1396                 }
1397         }
1398
1399         I915_WRITE(EIR, eir);
1400         POSTING_READ(EIR);
1401         eir = I915_READ(EIR);
1402         if (eir) {
1403                 /*
1404                  * some errors might have become stuck,
1405                  * mask them.
1406                  */
1407                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1408                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1409                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1410         }
1411 }
1412
1413 /**
1414  * i915_handle_error - handle an error interrupt
1415  * @dev: drm device
1416  *
1417  * Do some basic checking of regsiter state at error interrupt time and
1418  * dump it to the syslog.  Also call i915_capture_error_state() to make
1419  * sure we get a record and make it available in debugfs.  Fire a uevent
1420  * so userspace knows something bad happened (should trigger collection
1421  * of a ring dump etc.).
1422  */
1423 void i915_handle_error(struct drm_device *dev, bool wedged)
1424 {
1425         struct drm_i915_private *dev_priv = dev->dev_private;
1426         struct intel_ring_buffer *ring;
1427         int i;
1428
1429         i915_capture_error_state(dev);
1430         i915_report_and_clear_eir(dev);
1431
1432         if (wedged) {
1433                 INIT_COMPLETION(dev_priv->error_completion);
1434                 atomic_set(&dev_priv->mm.wedged, 1);
1435
1436                 /*
1437                  * Wakeup waiting processes so they don't hang
1438                  */
1439                 for_each_ring(ring, dev_priv, i)
1440                         wake_up_all(&ring->irq_queue);
1441         }
1442
1443         queue_work(dev_priv->wq, &dev_priv->error_work);
1444 }
1445
1446 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1447 {
1448         drm_i915_private_t *dev_priv = dev->dev_private;
1449         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1451         struct drm_i915_gem_object *obj;
1452         struct intel_unpin_work *work;
1453         unsigned long flags;
1454         bool stall_detected;
1455
1456         /* Ignore early vblank irqs */
1457         if (intel_crtc == NULL)
1458                 return;
1459
1460         spin_lock_irqsave(&dev->event_lock, flags);
1461         work = intel_crtc->unpin_work;
1462
1463         if (work == NULL || work->pending || !work->enable_stall_check) {
1464                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1465                 spin_unlock_irqrestore(&dev->event_lock, flags);
1466                 return;
1467         }
1468
1469         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1470         obj = work->pending_flip_obj;
1471         if (INTEL_INFO(dev)->gen >= 4) {
1472                 int dspsurf = DSPSURF(intel_crtc->plane);
1473                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1474                                         obj->gtt_offset;
1475         } else {
1476                 int dspaddr = DSPADDR(intel_crtc->plane);
1477                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1478                                                         crtc->y * crtc->fb->pitches[0] +
1479                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1480         }
1481
1482         spin_unlock_irqrestore(&dev->event_lock, flags);
1483
1484         if (stall_detected) {
1485                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1486                 intel_prepare_page_flip(dev, intel_crtc->plane);
1487         }
1488 }
1489
1490 /* Called from drm generic code, passed 'crtc' which
1491  * we use as a pipe index
1492  */
1493 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1494 {
1495         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1496         unsigned long irqflags;
1497
1498         if (!i915_pipe_enabled(dev, pipe))
1499                 return -EINVAL;
1500
1501         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1502         if (INTEL_INFO(dev)->gen >= 4)
1503                 i915_enable_pipestat(dev_priv, pipe,
1504                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1505         else
1506                 i915_enable_pipestat(dev_priv, pipe,
1507                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1508
1509         /* maintain vblank delivery even in deep C-states */
1510         if (dev_priv->info->gen == 3)
1511                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1512         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1513
1514         return 0;
1515 }
1516
1517 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1518 {
1519         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1520         unsigned long irqflags;
1521
1522         if (!i915_pipe_enabled(dev, pipe))
1523                 return -EINVAL;
1524
1525         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1526         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1527                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1528         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1529
1530         return 0;
1531 }
1532
1533 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1534 {
1535         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1536         unsigned long irqflags;
1537
1538         if (!i915_pipe_enabled(dev, pipe))
1539                 return -EINVAL;
1540
1541         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1542         ironlake_enable_display_irq(dev_priv,
1543                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1544         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1545
1546         return 0;
1547 }
1548
1549 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1550 {
1551         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1552         unsigned long irqflags;
1553         u32 imr;
1554
1555         if (!i915_pipe_enabled(dev, pipe))
1556                 return -EINVAL;
1557
1558         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1559         imr = I915_READ(VLV_IMR);
1560         if (pipe == 0)
1561                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1562         else
1563                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1564         I915_WRITE(VLV_IMR, imr);
1565         i915_enable_pipestat(dev_priv, pipe,
1566                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1567         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1568
1569         return 0;
1570 }
1571
1572 /* Called from drm generic code, passed 'crtc' which
1573  * we use as a pipe index
1574  */
1575 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1576 {
1577         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1578         unsigned long irqflags;
1579
1580         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1581         if (dev_priv->info->gen == 3)
1582                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1583
1584         i915_disable_pipestat(dev_priv, pipe,
1585                               PIPE_VBLANK_INTERRUPT_ENABLE |
1586                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1587         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1588 }
1589
1590 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1591 {
1592         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1593         unsigned long irqflags;
1594
1595         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1596         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1597                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1598         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1599 }
1600
1601 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1602 {
1603         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1604         unsigned long irqflags;
1605
1606         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1607         ironlake_disable_display_irq(dev_priv,
1608                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1609         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1610 }
1611
1612 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1613 {
1614         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1615         unsigned long irqflags;
1616         u32 imr;
1617
1618         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1619         i915_disable_pipestat(dev_priv, pipe,
1620                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1621         imr = I915_READ(VLV_IMR);
1622         if (pipe == 0)
1623                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1624         else
1625                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1626         I915_WRITE(VLV_IMR, imr);
1627         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1628 }
1629
1630 static u32
1631 ring_last_seqno(struct intel_ring_buffer *ring)
1632 {
1633         return list_entry(ring->request_list.prev,
1634                           struct drm_i915_gem_request, list)->seqno;
1635 }
1636
1637 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1638 {
1639         if (list_empty(&ring->request_list) ||
1640             i915_seqno_passed(ring->get_seqno(ring, false),
1641                               ring_last_seqno(ring))) {
1642                 /* Issue a wake-up to catch stuck h/w. */
1643                 if (waitqueue_active(&ring->irq_queue)) {
1644                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1645                                   ring->name);
1646                         wake_up_all(&ring->irq_queue);
1647                         *err = true;
1648                 }
1649                 return true;
1650         }
1651         return false;
1652 }
1653
1654 static bool kick_ring(struct intel_ring_buffer *ring)
1655 {
1656         struct drm_device *dev = ring->dev;
1657         struct drm_i915_private *dev_priv = dev->dev_private;
1658         u32 tmp = I915_READ_CTL(ring);
1659         if (tmp & RING_WAIT) {
1660                 DRM_ERROR("Kicking stuck wait on %s\n",
1661                           ring->name);
1662                 I915_WRITE_CTL(ring, tmp);
1663                 return true;
1664         }
1665         return false;
1666 }
1667
1668 static bool i915_hangcheck_hung(struct drm_device *dev)
1669 {
1670         drm_i915_private_t *dev_priv = dev->dev_private;
1671
1672         if (dev_priv->hangcheck_count++ > 1) {
1673                 bool hung = true;
1674
1675                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1676                 i915_handle_error(dev, true);
1677
1678                 if (!IS_GEN2(dev)) {
1679                         struct intel_ring_buffer *ring;
1680                         int i;
1681
1682                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1683                          * If so we can simply poke the RB_WAIT bit
1684                          * and break the hang. This should work on
1685                          * all but the second generation chipsets.
1686                          */
1687                         for_each_ring(ring, dev_priv, i)
1688                                 hung &= !kick_ring(ring);
1689                 }
1690
1691                 return hung;
1692         }
1693
1694         return false;
1695 }
1696
1697 /**
1698  * This is called when the chip hasn't reported back with completed
1699  * batchbuffers in a long time. The first time this is called we simply record
1700  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1701  * again, we assume the chip is wedged and try to fix it.
1702  */
1703 void i915_hangcheck_elapsed(unsigned long data)
1704 {
1705         struct drm_device *dev = (struct drm_device *)data;
1706         drm_i915_private_t *dev_priv = dev->dev_private;
1707         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1708         struct intel_ring_buffer *ring;
1709         bool err = false, idle;
1710         int i;
1711
1712         if (!i915_enable_hangcheck)
1713                 return;
1714
1715         memset(acthd, 0, sizeof(acthd));
1716         idle = true;
1717         for_each_ring(ring, dev_priv, i) {
1718             idle &= i915_hangcheck_ring_idle(ring, &err);
1719             acthd[i] = intel_ring_get_active_head(ring);
1720         }
1721
1722         /* If all work is done then ACTHD clearly hasn't advanced. */
1723         if (idle) {
1724                 if (err) {
1725                         if (i915_hangcheck_hung(dev))
1726                                 return;
1727
1728                         goto repeat;
1729                 }
1730
1731                 dev_priv->hangcheck_count = 0;
1732                 return;
1733         }
1734
1735         i915_get_extra_instdone(dev, instdone);
1736         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1737             memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
1738                 if (i915_hangcheck_hung(dev))
1739                         return;
1740         } else {
1741                 dev_priv->hangcheck_count = 0;
1742
1743                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1744                 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
1745         }
1746
1747 repeat:
1748         /* Reset timer case chip hangs without another request being added */
1749         mod_timer(&dev_priv->hangcheck_timer,
1750                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1751 }
1752
1753 /* drm_dma.h hooks
1754 */
1755 static void ironlake_irq_preinstall(struct drm_device *dev)
1756 {
1757         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1758
1759         atomic_set(&dev_priv->irq_received, 0);
1760
1761         I915_WRITE(HWSTAM, 0xeffe);
1762
1763         /* XXX hotplug from PCH */
1764
1765         I915_WRITE(DEIMR, 0xffffffff);
1766         I915_WRITE(DEIER, 0x0);
1767         POSTING_READ(DEIER);
1768
1769         /* and GT */
1770         I915_WRITE(GTIMR, 0xffffffff);
1771         I915_WRITE(GTIER, 0x0);
1772         POSTING_READ(GTIER);
1773
1774         /* south display irq */
1775         I915_WRITE(SDEIMR, 0xffffffff);
1776         I915_WRITE(SDEIER, 0x0);
1777         POSTING_READ(SDEIER);
1778 }
1779
1780 static void valleyview_irq_preinstall(struct drm_device *dev)
1781 {
1782         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1783         int pipe;
1784
1785         atomic_set(&dev_priv->irq_received, 0);
1786
1787         /* VLV magic */
1788         I915_WRITE(VLV_IMR, 0);
1789         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1790         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1791         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1792
1793         /* and GT */
1794         I915_WRITE(GTIIR, I915_READ(GTIIR));
1795         I915_WRITE(GTIIR, I915_READ(GTIIR));
1796         I915_WRITE(GTIMR, 0xffffffff);
1797         I915_WRITE(GTIER, 0x0);
1798         POSTING_READ(GTIER);
1799
1800         I915_WRITE(DPINVGTT, 0xff);
1801
1802         I915_WRITE(PORT_HOTPLUG_EN, 0);
1803         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1804         for_each_pipe(pipe)
1805                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1806         I915_WRITE(VLV_IIR, 0xffffffff);
1807         I915_WRITE(VLV_IMR, 0xffffffff);
1808         I915_WRITE(VLV_IER, 0x0);
1809         POSTING_READ(VLV_IER);
1810 }
1811
1812 /*
1813  * Enable digital hotplug on the PCH, and configure the DP short pulse
1814  * duration to 2ms (which is the minimum in the Display Port spec)
1815  *
1816  * This register is the same on all known PCH chips.
1817  */
1818
1819 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1820 {
1821         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1822         u32     hotplug;
1823
1824         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1825         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1826         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1827         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1828         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1829         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1830 }
1831
1832 static int ironlake_irq_postinstall(struct drm_device *dev)
1833 {
1834         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1835         /* enable kind of interrupts always enabled */
1836         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1837                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1838         u32 render_irqs;
1839         u32 hotplug_mask;
1840
1841         dev_priv->irq_mask = ~display_mask;
1842
1843         /* should always can generate irq */
1844         I915_WRITE(DEIIR, I915_READ(DEIIR));
1845         I915_WRITE(DEIMR, dev_priv->irq_mask);
1846         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1847         POSTING_READ(DEIER);
1848
1849         dev_priv->gt_irq_mask = ~0;
1850
1851         I915_WRITE(GTIIR, I915_READ(GTIIR));
1852         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1853
1854         if (IS_GEN6(dev))
1855                 render_irqs =
1856                         GT_USER_INTERRUPT |
1857                         GEN6_BSD_USER_INTERRUPT |
1858                         GEN6_BLITTER_USER_INTERRUPT;
1859         else
1860                 render_irqs =
1861                         GT_USER_INTERRUPT |
1862                         GT_PIPE_NOTIFY |
1863                         GT_BSD_USER_INTERRUPT;
1864         I915_WRITE(GTIER, render_irqs);
1865         POSTING_READ(GTIER);
1866
1867         if (HAS_PCH_CPT(dev)) {
1868                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1869                                 SDE_PORTB_HOTPLUG_CPT |
1870                                 SDE_PORTC_HOTPLUG_CPT |
1871                                 SDE_PORTD_HOTPLUG_CPT);
1872         } else {
1873                 hotplug_mask = (SDE_CRT_HOTPLUG |
1874                                 SDE_PORTB_HOTPLUG |
1875                                 SDE_PORTC_HOTPLUG |
1876                                 SDE_PORTD_HOTPLUG |
1877                                 SDE_AUX_MASK);
1878         }
1879
1880         dev_priv->pch_irq_mask = ~hotplug_mask;
1881
1882         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1883         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1884         I915_WRITE(SDEIER, hotplug_mask);
1885         POSTING_READ(SDEIER);
1886
1887         ironlake_enable_pch_hotplug(dev);
1888
1889         if (IS_IRONLAKE_M(dev)) {
1890                 /* Clear & enable PCU event interrupts */
1891                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1892                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1893                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1894         }
1895
1896         return 0;
1897 }
1898
1899 static int ivybridge_irq_postinstall(struct drm_device *dev)
1900 {
1901         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1902         /* enable kind of interrupts always enabled */
1903         u32 display_mask =
1904                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1905                 DE_PLANEC_FLIP_DONE_IVB |
1906                 DE_PLANEB_FLIP_DONE_IVB |
1907                 DE_PLANEA_FLIP_DONE_IVB;
1908         u32 render_irqs;
1909         u32 hotplug_mask;
1910
1911         dev_priv->irq_mask = ~display_mask;
1912
1913         /* should always can generate irq */
1914         I915_WRITE(DEIIR, I915_READ(DEIIR));
1915         I915_WRITE(DEIMR, dev_priv->irq_mask);
1916         I915_WRITE(DEIER,
1917                    display_mask |
1918                    DE_PIPEC_VBLANK_IVB |
1919                    DE_PIPEB_VBLANK_IVB |
1920                    DE_PIPEA_VBLANK_IVB);
1921         POSTING_READ(DEIER);
1922
1923         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1924
1925         I915_WRITE(GTIIR, I915_READ(GTIIR));
1926         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1927
1928         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1929                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1930         I915_WRITE(GTIER, render_irqs);
1931         POSTING_READ(GTIER);
1932
1933         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1934                         SDE_PORTB_HOTPLUG_CPT |
1935                         SDE_PORTC_HOTPLUG_CPT |
1936                         SDE_PORTD_HOTPLUG_CPT);
1937         dev_priv->pch_irq_mask = ~hotplug_mask;
1938
1939         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1940         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1941         I915_WRITE(SDEIER, hotplug_mask);
1942         POSTING_READ(SDEIER);
1943
1944         ironlake_enable_pch_hotplug(dev);
1945
1946         return 0;
1947 }
1948
1949 static int valleyview_irq_postinstall(struct drm_device *dev)
1950 {
1951         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1952         u32 enable_mask;
1953         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1954         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
1955         u32 render_irqs;
1956         u16 msid;
1957
1958         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1959         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1960                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1961                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1962                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1963
1964         /*
1965          *Leave vblank interrupts masked initially.  enable/disable will
1966          * toggle them based on usage.
1967          */
1968         dev_priv->irq_mask = (~enable_mask) |
1969                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1970                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1971
1972         dev_priv->pipestat[0] = 0;
1973         dev_priv->pipestat[1] = 0;
1974
1975         /* Hack for broken MSIs on VLV */
1976         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1977         pci_read_config_word(dev->pdev, 0x98, &msid);
1978         msid &= 0xff; /* mask out delivery bits */
1979         msid |= (1<<14);
1980         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1981
1982         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1983         I915_WRITE(VLV_IER, enable_mask);
1984         I915_WRITE(VLV_IIR, 0xffffffff);
1985         I915_WRITE(PIPESTAT(0), 0xffff);
1986         I915_WRITE(PIPESTAT(1), 0xffff);
1987         POSTING_READ(VLV_IER);
1988
1989         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1990         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1991
1992         I915_WRITE(VLV_IIR, 0xffffffff);
1993         I915_WRITE(VLV_IIR, 0xffffffff);
1994
1995         I915_WRITE(GTIIR, I915_READ(GTIIR));
1996         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1997
1998         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1999                 GEN6_BLITTER_USER_INTERRUPT;
2000         I915_WRITE(GTIER, render_irqs);
2001         POSTING_READ(GTIER);
2002
2003         /* ack & enable invalid PTE error interrupts */
2004 #if 0 /* FIXME: add support to irq handler for checking these bits */
2005         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2006         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2007 #endif
2008
2009         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2010         /* Note HDMI and DP share bits */
2011         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2012                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2013         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2014                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2015         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2016                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2017         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2018                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2019         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2020                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2021         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2022                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2023                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2024         }
2025
2026         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2027
2028         return 0;
2029 }
2030
2031 static void valleyview_irq_uninstall(struct drm_device *dev)
2032 {
2033         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2034         int pipe;
2035
2036         if (!dev_priv)
2037                 return;
2038
2039         for_each_pipe(pipe)
2040                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2041
2042         I915_WRITE(HWSTAM, 0xffffffff);
2043         I915_WRITE(PORT_HOTPLUG_EN, 0);
2044         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2045         for_each_pipe(pipe)
2046                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2047         I915_WRITE(VLV_IIR, 0xffffffff);
2048         I915_WRITE(VLV_IMR, 0xffffffff);
2049         I915_WRITE(VLV_IER, 0x0);
2050         POSTING_READ(VLV_IER);
2051 }
2052
2053 static void ironlake_irq_uninstall(struct drm_device *dev)
2054 {
2055         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2056
2057         if (!dev_priv)
2058                 return;
2059
2060         I915_WRITE(HWSTAM, 0xffffffff);
2061
2062         I915_WRITE(DEIMR, 0xffffffff);
2063         I915_WRITE(DEIER, 0x0);
2064         I915_WRITE(DEIIR, I915_READ(DEIIR));
2065
2066         I915_WRITE(GTIMR, 0xffffffff);
2067         I915_WRITE(GTIER, 0x0);
2068         I915_WRITE(GTIIR, I915_READ(GTIIR));
2069
2070         I915_WRITE(SDEIMR, 0xffffffff);
2071         I915_WRITE(SDEIER, 0x0);
2072         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2073 }
2074
2075 static void i8xx_irq_preinstall(struct drm_device * dev)
2076 {
2077         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2078         int pipe;
2079
2080         atomic_set(&dev_priv->irq_received, 0);
2081
2082         for_each_pipe(pipe)
2083                 I915_WRITE(PIPESTAT(pipe), 0);
2084         I915_WRITE16(IMR, 0xffff);
2085         I915_WRITE16(IER, 0x0);
2086         POSTING_READ16(IER);
2087 }
2088
2089 static int i8xx_irq_postinstall(struct drm_device *dev)
2090 {
2091         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2092
2093         dev_priv->pipestat[0] = 0;
2094         dev_priv->pipestat[1] = 0;
2095
2096         I915_WRITE16(EMR,
2097                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2098
2099         /* Unmask the interrupts that we always want on. */
2100         dev_priv->irq_mask =
2101                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2102                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2103                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2104                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2105                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2106         I915_WRITE16(IMR, dev_priv->irq_mask);
2107
2108         I915_WRITE16(IER,
2109                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2110                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2111                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2112                      I915_USER_INTERRUPT);
2113         POSTING_READ16(IER);
2114
2115         return 0;
2116 }
2117
2118 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2119 {
2120         struct drm_device *dev = (struct drm_device *) arg;
2121         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2122         u16 iir, new_iir;
2123         u32 pipe_stats[2];
2124         unsigned long irqflags;
2125         int irq_received;
2126         int pipe;
2127         u16 flip_mask =
2128                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2129                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2130
2131         atomic_inc(&dev_priv->irq_received);
2132
2133         iir = I915_READ16(IIR);
2134         if (iir == 0)
2135                 return IRQ_NONE;
2136
2137         while (iir & ~flip_mask) {
2138                 /* Can't rely on pipestat interrupt bit in iir as it might
2139                  * have been cleared after the pipestat interrupt was received.
2140                  * It doesn't set the bit in iir again, but it still produces
2141                  * interrupts (for non-MSI).
2142                  */
2143                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2144                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2145                         i915_handle_error(dev, false);
2146
2147                 for_each_pipe(pipe) {
2148                         int reg = PIPESTAT(pipe);
2149                         pipe_stats[pipe] = I915_READ(reg);
2150
2151                         /*
2152                          * Clear the PIPE*STAT regs before the IIR
2153                          */
2154                         if (pipe_stats[pipe] & 0x8000ffff) {
2155                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2156                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2157                                                          pipe_name(pipe));
2158                                 I915_WRITE(reg, pipe_stats[pipe]);
2159                                 irq_received = 1;
2160                         }
2161                 }
2162                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2163
2164                 I915_WRITE16(IIR, iir & ~flip_mask);
2165                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2166
2167                 i915_update_dri1_breadcrumb(dev);
2168
2169                 if (iir & I915_USER_INTERRUPT)
2170                         notify_ring(dev, &dev_priv->ring[RCS]);
2171
2172                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2173                     drm_handle_vblank(dev, 0)) {
2174                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2175                                 intel_prepare_page_flip(dev, 0);
2176                                 intel_finish_page_flip(dev, 0);
2177                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2178                         }
2179                 }
2180
2181                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2182                     drm_handle_vblank(dev, 1)) {
2183                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2184                                 intel_prepare_page_flip(dev, 1);
2185                                 intel_finish_page_flip(dev, 1);
2186                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2187                         }
2188                 }
2189
2190                 iir = new_iir;
2191         }
2192
2193         return IRQ_HANDLED;
2194 }
2195
2196 static void i8xx_irq_uninstall(struct drm_device * dev)
2197 {
2198         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2199         int pipe;
2200
2201         for_each_pipe(pipe) {
2202                 /* Clear enable bits; then clear status bits */
2203                 I915_WRITE(PIPESTAT(pipe), 0);
2204                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2205         }
2206         I915_WRITE16(IMR, 0xffff);
2207         I915_WRITE16(IER, 0x0);
2208         I915_WRITE16(IIR, I915_READ16(IIR));
2209 }
2210
2211 static void i915_irq_preinstall(struct drm_device * dev)
2212 {
2213         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2214         int pipe;
2215
2216         atomic_set(&dev_priv->irq_received, 0);
2217
2218         if (I915_HAS_HOTPLUG(dev)) {
2219                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2220                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2221         }
2222
2223         I915_WRITE16(HWSTAM, 0xeffe);
2224         for_each_pipe(pipe)
2225                 I915_WRITE(PIPESTAT(pipe), 0);
2226         I915_WRITE(IMR, 0xffffffff);
2227         I915_WRITE(IER, 0x0);
2228         POSTING_READ(IER);
2229 }
2230
2231 static int i915_irq_postinstall(struct drm_device *dev)
2232 {
2233         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2234         u32 enable_mask;
2235
2236         dev_priv->pipestat[0] = 0;
2237         dev_priv->pipestat[1] = 0;
2238
2239         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2240
2241         /* Unmask the interrupts that we always want on. */
2242         dev_priv->irq_mask =
2243                 ~(I915_ASLE_INTERRUPT |
2244                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2245                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2246                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2247                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2248                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2249
2250         enable_mask =
2251                 I915_ASLE_INTERRUPT |
2252                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2253                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2254                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2255                 I915_USER_INTERRUPT;
2256
2257         if (I915_HAS_HOTPLUG(dev)) {
2258                 /* Enable in IER... */
2259                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2260                 /* and unmask in IMR */
2261                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2262         }
2263
2264         I915_WRITE(IMR, dev_priv->irq_mask);
2265         I915_WRITE(IER, enable_mask);
2266         POSTING_READ(IER);
2267
2268         if (I915_HAS_HOTPLUG(dev)) {
2269                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2270
2271                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2272                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2273                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2274                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2275                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2276                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2277                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2278                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2279                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2280                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2281                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2282                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2283                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2284                 }
2285
2286                 /* Ignore TV since it's buggy */
2287
2288                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2289         }
2290
2291         intel_opregion_enable_asle(dev);
2292
2293         return 0;
2294 }
2295
2296 static irqreturn_t i915_irq_handler(int irq, void *arg)
2297 {
2298         struct drm_device *dev = (struct drm_device *) arg;
2299         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2300         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2301         unsigned long irqflags;
2302         u32 flip_mask =
2303                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2304                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2305         u32 flip[2] = {
2306                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2307                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2308         };
2309         int pipe, ret = IRQ_NONE;
2310
2311         atomic_inc(&dev_priv->irq_received);
2312
2313         iir = I915_READ(IIR);
2314         do {
2315                 bool irq_received = (iir & ~flip_mask) != 0;
2316                 bool blc_event = false;
2317
2318                 /* Can't rely on pipestat interrupt bit in iir as it might
2319                  * have been cleared after the pipestat interrupt was received.
2320                  * It doesn't set the bit in iir again, but it still produces
2321                  * interrupts (for non-MSI).
2322                  */
2323                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2324                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2325                         i915_handle_error(dev, false);
2326
2327                 for_each_pipe(pipe) {
2328                         int reg = PIPESTAT(pipe);
2329                         pipe_stats[pipe] = I915_READ(reg);
2330
2331                         /* Clear the PIPE*STAT regs before the IIR */
2332                         if (pipe_stats[pipe] & 0x8000ffff) {
2333                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2334                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2335                                                          pipe_name(pipe));
2336                                 I915_WRITE(reg, pipe_stats[pipe]);
2337                                 irq_received = true;
2338                         }
2339                 }
2340                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2341
2342                 if (!irq_received)
2343                         break;
2344
2345                 /* Consume port.  Then clear IIR or we'll miss events */
2346                 if ((I915_HAS_HOTPLUG(dev)) &&
2347                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2348                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2349
2350                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2351                                   hotplug_status);
2352                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2353                                 queue_work(dev_priv->wq,
2354                                            &dev_priv->hotplug_work);
2355
2356                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2357                         POSTING_READ(PORT_HOTPLUG_STAT);
2358                 }
2359
2360                 I915_WRITE(IIR, iir & ~flip_mask);
2361                 new_iir = I915_READ(IIR); /* Flush posted writes */
2362
2363                 if (iir & I915_USER_INTERRUPT)
2364                         notify_ring(dev, &dev_priv->ring[RCS]);
2365
2366                 for_each_pipe(pipe) {
2367                         int plane = pipe;
2368                         if (IS_MOBILE(dev))
2369                                 plane = !plane;
2370                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2371                             drm_handle_vblank(dev, pipe)) {
2372                                 if (iir & flip[plane]) {
2373                                         intel_prepare_page_flip(dev, plane);
2374                                         intel_finish_page_flip(dev, pipe);
2375                                         flip_mask &= ~flip[plane];
2376                                 }
2377                         }
2378
2379                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2380                                 blc_event = true;
2381                 }
2382
2383                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2384                         intel_opregion_asle_intr(dev);
2385
2386                 /* With MSI, interrupts are only generated when iir
2387                  * transitions from zero to nonzero.  If another bit got
2388                  * set while we were handling the existing iir bits, then
2389                  * we would never get another interrupt.
2390                  *
2391                  * This is fine on non-MSI as well, as if we hit this path
2392                  * we avoid exiting the interrupt handler only to generate
2393                  * another one.
2394                  *
2395                  * Note that for MSI this could cause a stray interrupt report
2396                  * if an interrupt landed in the time between writing IIR and
2397                  * the posting read.  This should be rare enough to never
2398                  * trigger the 99% of 100,000 interrupts test for disabling
2399                  * stray interrupts.
2400                  */
2401                 ret = IRQ_HANDLED;
2402                 iir = new_iir;
2403         } while (iir & ~flip_mask);
2404
2405         i915_update_dri1_breadcrumb(dev);
2406
2407         return ret;
2408 }
2409
2410 static void i915_irq_uninstall(struct drm_device * dev)
2411 {
2412         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2413         int pipe;
2414
2415         if (I915_HAS_HOTPLUG(dev)) {
2416                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2417                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2418         }
2419
2420         I915_WRITE16(HWSTAM, 0xffff);
2421         for_each_pipe(pipe) {
2422                 /* Clear enable bits; then clear status bits */
2423                 I915_WRITE(PIPESTAT(pipe), 0);
2424                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2425         }
2426         I915_WRITE(IMR, 0xffffffff);
2427         I915_WRITE(IER, 0x0);
2428
2429         I915_WRITE(IIR, I915_READ(IIR));
2430 }
2431
2432 static void i965_irq_preinstall(struct drm_device * dev)
2433 {
2434         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2435         int pipe;
2436
2437         atomic_set(&dev_priv->irq_received, 0);
2438
2439         I915_WRITE(PORT_HOTPLUG_EN, 0);
2440         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2441
2442         I915_WRITE(HWSTAM, 0xeffe);
2443         for_each_pipe(pipe)
2444                 I915_WRITE(PIPESTAT(pipe), 0);
2445         I915_WRITE(IMR, 0xffffffff);
2446         I915_WRITE(IER, 0x0);
2447         POSTING_READ(IER);
2448 }
2449
2450 static int i965_irq_postinstall(struct drm_device *dev)
2451 {
2452         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2453         u32 hotplug_en;
2454         u32 enable_mask;
2455         u32 error_mask;
2456
2457         /* Unmask the interrupts that we always want on. */
2458         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2459                                I915_DISPLAY_PORT_INTERRUPT |
2460                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2461                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2462                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2463                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2464                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2465
2466         enable_mask = ~dev_priv->irq_mask;
2467         enable_mask |= I915_USER_INTERRUPT;
2468
2469         if (IS_G4X(dev))
2470                 enable_mask |= I915_BSD_USER_INTERRUPT;
2471
2472         dev_priv->pipestat[0] = 0;
2473         dev_priv->pipestat[1] = 0;
2474
2475         /*
2476          * Enable some error detection, note the instruction error mask
2477          * bit is reserved, so we leave it masked.
2478          */
2479         if (IS_G4X(dev)) {
2480                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2481                                GM45_ERROR_MEM_PRIV |
2482                                GM45_ERROR_CP_PRIV |
2483                                I915_ERROR_MEMORY_REFRESH);
2484         } else {
2485                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2486                                I915_ERROR_MEMORY_REFRESH);
2487         }
2488         I915_WRITE(EMR, error_mask);
2489
2490         I915_WRITE(IMR, dev_priv->irq_mask);
2491         I915_WRITE(IER, enable_mask);
2492         POSTING_READ(IER);
2493
2494         /* Note HDMI and DP share hotplug bits */
2495         hotplug_en = 0;
2496         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2497                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2498         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2499                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2500         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2501                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2502         if (IS_G4X(dev)) {
2503                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2504                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2505                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2506                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2507         } else {
2508                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2509                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2510                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2511                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2512         }
2513         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2514                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2515
2516                 /* Programming the CRT detection parameters tends
2517                    to generate a spurious hotplug event about three
2518                    seconds later.  So just do it once.
2519                    */
2520                 if (IS_G4X(dev))
2521                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2522                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2523         }
2524
2525         /* Ignore TV since it's buggy */
2526
2527         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2528
2529         intel_opregion_enable_asle(dev);
2530
2531         return 0;
2532 }
2533
2534 static irqreturn_t i965_irq_handler(int irq, void *arg)
2535 {
2536         struct drm_device *dev = (struct drm_device *) arg;
2537         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2538         u32 iir, new_iir;
2539         u32 pipe_stats[I915_MAX_PIPES];
2540         unsigned long irqflags;
2541         int irq_received;
2542         int ret = IRQ_NONE, pipe;
2543
2544         atomic_inc(&dev_priv->irq_received);
2545
2546         iir = I915_READ(IIR);
2547
2548         for (;;) {
2549                 bool blc_event = false;
2550
2551                 irq_received = iir != 0;
2552
2553                 /* Can't rely on pipestat interrupt bit in iir as it might
2554                  * have been cleared after the pipestat interrupt was received.
2555                  * It doesn't set the bit in iir again, but it still produces
2556                  * interrupts (for non-MSI).
2557                  */
2558                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2559                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2560                         i915_handle_error(dev, false);
2561
2562                 for_each_pipe(pipe) {
2563                         int reg = PIPESTAT(pipe);
2564                         pipe_stats[pipe] = I915_READ(reg);
2565
2566                         /*
2567                          * Clear the PIPE*STAT regs before the IIR
2568                          */
2569                         if (pipe_stats[pipe] & 0x8000ffff) {
2570                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2571                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2572                                                          pipe_name(pipe));
2573                                 I915_WRITE(reg, pipe_stats[pipe]);
2574                                 irq_received = 1;
2575                         }
2576                 }
2577                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2578
2579                 if (!irq_received)
2580                         break;
2581
2582                 ret = IRQ_HANDLED;
2583
2584                 /* Consume port.  Then clear IIR or we'll miss events */
2585                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2586                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2587
2588                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2589                                   hotplug_status);
2590                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2591                                 queue_work(dev_priv->wq,
2592                                            &dev_priv->hotplug_work);
2593
2594                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2595                         I915_READ(PORT_HOTPLUG_STAT);
2596                 }
2597
2598                 I915_WRITE(IIR, iir);
2599                 new_iir = I915_READ(IIR); /* Flush posted writes */
2600
2601                 if (iir & I915_USER_INTERRUPT)
2602                         notify_ring(dev, &dev_priv->ring[RCS]);
2603                 if (iir & I915_BSD_USER_INTERRUPT)
2604                         notify_ring(dev, &dev_priv->ring[VCS]);
2605
2606                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2607                         intel_prepare_page_flip(dev, 0);
2608
2609                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2610                         intel_prepare_page_flip(dev, 1);
2611
2612                 for_each_pipe(pipe) {
2613                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2614                             drm_handle_vblank(dev, pipe)) {
2615                                 i915_pageflip_stall_check(dev, pipe);
2616                                 intel_finish_page_flip(dev, pipe);
2617                         }
2618
2619                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2620                                 blc_event = true;
2621                 }
2622
2623
2624                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2625                         intel_opregion_asle_intr(dev);
2626
2627                 /* With MSI, interrupts are only generated when iir
2628                  * transitions from zero to nonzero.  If another bit got
2629                  * set while we were handling the existing iir bits, then
2630                  * we would never get another interrupt.
2631                  *
2632                  * This is fine on non-MSI as well, as if we hit this path
2633                  * we avoid exiting the interrupt handler only to generate
2634                  * another one.
2635                  *
2636                  * Note that for MSI this could cause a stray interrupt report
2637                  * if an interrupt landed in the time between writing IIR and
2638                  * the posting read.  This should be rare enough to never
2639                  * trigger the 99% of 100,000 interrupts test for disabling
2640                  * stray interrupts.
2641                  */
2642                 iir = new_iir;
2643         }
2644
2645         i915_update_dri1_breadcrumb(dev);
2646
2647         return ret;
2648 }
2649
2650 static void i965_irq_uninstall(struct drm_device * dev)
2651 {
2652         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2653         int pipe;
2654
2655         if (!dev_priv)
2656                 return;
2657
2658         I915_WRITE(PORT_HOTPLUG_EN, 0);
2659         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2660
2661         I915_WRITE(HWSTAM, 0xffffffff);
2662         for_each_pipe(pipe)
2663                 I915_WRITE(PIPESTAT(pipe), 0);
2664         I915_WRITE(IMR, 0xffffffff);
2665         I915_WRITE(IER, 0x0);
2666
2667         for_each_pipe(pipe)
2668                 I915_WRITE(PIPESTAT(pipe),
2669                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2670         I915_WRITE(IIR, I915_READ(IIR));
2671 }
2672
2673 void intel_irq_init(struct drm_device *dev)
2674 {
2675         struct drm_i915_private *dev_priv = dev->dev_private;
2676
2677         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2678         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2679         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2680         INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
2681
2682         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2683         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2684         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2685                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2686                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2687         }
2688
2689         if (drm_core_check_feature(dev, DRIVER_MODESET))
2690                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2691         else
2692                 dev->driver->get_vblank_timestamp = NULL;
2693         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2694
2695         if (IS_VALLEYVIEW(dev)) {
2696                 dev->driver->irq_handler = valleyview_irq_handler;
2697                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2698                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2699                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2700                 dev->driver->enable_vblank = valleyview_enable_vblank;
2701                 dev->driver->disable_vblank = valleyview_disable_vblank;
2702         } else if (IS_IVYBRIDGE(dev)) {
2703                 /* Share pre & uninstall handlers with ILK/SNB */
2704                 dev->driver->irq_handler = ivybridge_irq_handler;
2705                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2706                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2707                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2708                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2709                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2710         } else if (IS_HASWELL(dev)) {
2711                 /* Share interrupts handling with IVB */
2712                 dev->driver->irq_handler = ivybridge_irq_handler;
2713                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2714                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2715                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2716                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2717                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2718         } else if (HAS_PCH_SPLIT(dev)) {
2719                 dev->driver->irq_handler = ironlake_irq_handler;
2720                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2721                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2722                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2723                 dev->driver->enable_vblank = ironlake_enable_vblank;
2724                 dev->driver->disable_vblank = ironlake_disable_vblank;
2725         } else {
2726                 if (INTEL_INFO(dev)->gen == 2) {
2727                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2728                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2729                         dev->driver->irq_handler = i8xx_irq_handler;
2730                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2731                 } else if (INTEL_INFO(dev)->gen == 3) {
2732                         dev->driver->irq_preinstall = i915_irq_preinstall;
2733                         dev->driver->irq_postinstall = i915_irq_postinstall;
2734                         dev->driver->irq_uninstall = i915_irq_uninstall;
2735                         dev->driver->irq_handler = i915_irq_handler;
2736                 } else {
2737                         dev->driver->irq_preinstall = i965_irq_preinstall;
2738                         dev->driver->irq_postinstall = i965_irq_postinstall;
2739                         dev->driver->irq_uninstall = i965_irq_uninstall;
2740                         dev->driver->irq_handler = i965_irq_handler;
2741                 }
2742                 dev->driver->enable_vblank = i915_enable_vblank;
2743                 dev->driver->disable_vblank = i915_disable_vblank;
2744         }
2745 }