drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "dce/dce_10_0_d.h"
  39 #include "dce/dce_10_0_sh_mask.h"
  40
  41 #include "vid.h"
  42 #include "vi.h"
  43
  44 #include "amdgpu_atombios.h"
  45
  46
  47 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  48 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  49 static int gmc_v8_0_wait_for_idle(void *handle);
  50
  51 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  52 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  53 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  54 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  55
  56 static const u32 golden_settings_tonga_a11[] =
  57 {
  58         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  59         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  60         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  61         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  62         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  63         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65 };
  66
  67 static const u32 tonga_mgcg_cgcg_init[] =
  68 {
  69         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  70 };
  71
  72 static const u32 golden_settings_fiji_a10[] =
  73 {
  74         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  75         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  76         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  77         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  78 };
  79
  80 static const u32 fiji_mgcg_cgcg_init[] =
  81 {
  82         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  83 };
  84
  85 static const u32 golden_settings_polaris11_a11[] =
  86 {
  87         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  88         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  89         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  90         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  91 };
  92
  93 static const u32 golden_settings_polaris10_a11[] =
  94 {
  95         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  96         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  97         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  98         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  99         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 100 };
 101
 102 static const u32 cz_mgcg_cgcg_init[] =
 103 {
 104         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 105 };
 106
 107 static const u32 stoney_mgcg_cgcg_init[] =
 108 {
 109         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 110         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 111 };
 112
 113 static const u32 golden_settings_stoney_common[] =
 114 {
 115         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 116         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 117 };
 118
 119 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 120 {
 121         switch (adev->asic_type) {
 122         case CHIP_FIJI:
 123                 amdgpu_program_register_sequence(adev,
 124                                                  fiji_mgcg_cgcg_init,
 125                                                  ARRAY_SIZE(fiji_mgcg_cgcg_init));
 126                 amdgpu_program_register_sequence(adev,
 127                                                  golden_settings_fiji_a10,
 128                                                  ARRAY_SIZE(golden_settings_fiji_a10));
 129                 break;
 130         case CHIP_TONGA:
 131                 amdgpu_program_register_sequence(adev,
 132                                                  tonga_mgcg_cgcg_init,
 133                                                  ARRAY_SIZE(tonga_mgcg_cgcg_init));
 134                 amdgpu_program_register_sequence(adev,
 135                                                  golden_settings_tonga_a11,
 136                                                  ARRAY_SIZE(golden_settings_tonga_a11));
 137                 break;
 138         case CHIP_POLARIS11:
 139         case CHIP_POLARIS12:
 140                 amdgpu_program_register_sequence(adev,
 141                                                  golden_settings_polaris11_a11,
 142                                                  ARRAY_SIZE(golden_settings_polaris11_a11));
 143                 break;
 144         case CHIP_POLARIS10:
 145                 amdgpu_program_register_sequence(adev,
 146                                                  golden_settings_polaris10_a11,
 147                                                  ARRAY_SIZE(golden_settings_polaris10_a11));
 148                 break;
 149         case CHIP_CARRIZO:
 150                 amdgpu_program_register_sequence(adev,
 151                                                  cz_mgcg_cgcg_init,
 152                                                  ARRAY_SIZE(cz_mgcg_cgcg_init));
 153                 break;
 154         case CHIP_STONEY:
 155                 amdgpu_program_register_sequence(adev,
 156                                                  stoney_mgcg_cgcg_init,
 157                                                  ARRAY_SIZE(stoney_mgcg_cgcg_init));
 158                 amdgpu_program_register_sequence(adev,
 159                                                  golden_settings_stoney_common,
 160                                                  ARRAY_SIZE(golden_settings_stoney_common));
 161                 break;
 162         default:
 163                 break;
 164         }
 165 }
 166
 167 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 168 {
 169         u32 blackout;
 170
 171         gmc_v8_0_wait_for_idle(adev);
 172
 173         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 174         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 175                 /* Block CPU access */
 176                 WREG32(mmBIF_FB_EN, 0);
 177                 /* blackout the MC */
 178                 blackout = REG_SET_FIELD(blackout,
 179                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 180                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 181         }
 182         /* wait for the MC to settle */
 183         udelay(100);
 184 }
 185
 186 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 187 {
 188         u32 tmp;
 189
 190         /* unblackout the MC */
 191         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 192         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 193         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 194         /* allow CPU access */
 195         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 196         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 197         WREG32(mmBIF_FB_EN, tmp);
 198 }
 199
 200 /**
 201  * gmc_v8_0_init_microcode - load ucode images from disk
 202  *
 203  * @adev: amdgpu_device pointer
 204  *
 205  * Use the firmware interface to load the ucode images into
 206  * the driver (not loaded into hw).
 207  * Returns 0 on success, error on failure.
 208  */
 209 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 210 {
 211         const char *chip_name;
 212         char fw_name[30];
 213         int err;
 214
 215         DRM_DEBUG("\n");
 216
 217         switch (adev->asic_type) {
 218         case CHIP_TONGA:
 219                 chip_name = "tonga";
 220                 break;
 221         case CHIP_POLARIS11:
 222                 chip_name = "polaris11";
 223                 break;
 224         case CHIP_POLARIS10:
 225                 chip_name = "polaris10";
 226                 break;
 227         case CHIP_POLARIS12:
 228                 chip_name = "polaris12";
 229                 break;
 230         case CHIP_FIJI:
 231         case CHIP_CARRIZO:
 232         case CHIP_STONEY:
 233                 return 0;
 234         default: BUG();
 235         }
 236
 237         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 238         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 239         if (err)
 240                 goto out;
 241         err = amdgpu_ucode_validate(adev->mc.fw);
 242
 243 out:
 244         if (err) {
 245                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 246                 release_firmware(adev->mc.fw);
 247                 adev->mc.fw = NULL;
 248         }
 249         return err;
 250 }
 251
 252 /**
 253  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 254  *
 255  * @adev: amdgpu_device pointer
 256  *
 257  * Load the GDDR MC ucode into the hw (CIK).
 258  * Returns 0 on success, error on failure.
 259  */
 260 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 261 {
 262         const struct mc_firmware_header_v1_0 *hdr;
 263         const __le32 *fw_data = NULL;
 264         const __le32 *io_mc_regs = NULL;
 265         u32 running;
 266         int i, ucode_size, regs_size;
 267
 268         /* Skip MC ucode loading on SR-IOV capable boards.
 269          * vbios does this for us in asic_init in that case.
 270          * Skip MC ucode loading on VF, because hypervisor will do that
 271          * for this adaptor.
 272          */
 273         if (amdgpu_sriov_bios(adev))
 274                 return 0;
 275
 276         if (!adev->mc.fw)
 277                 return -EINVAL;
 278
 279         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 280         amdgpu_ucode_print_mc_hdr(&hdr->header);
 281
 282         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 283         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 284         io_mc_regs = (const __le32 *)
 285                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 286         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 287         fw_data = (const __le32 *)
 288                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 289
 290         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 291
 292         if (running == 0) {
 293                 /* reset the engine and set to writable */
 294                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 295                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 296
 297                 /* load mc io regs */
 298                 for (i = 0; i < regs_size; i++) {
 299                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 300                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 301                 }
 302                 /* load the MC ucode */
 303                 for (i = 0; i < ucode_size; i++)
 304                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 305
 306                 /* put the engine back into the active state */
 307                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 308                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 309                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 310
 311                 /* wait for training to complete */
 312                 for (i = 0; i < adev->usec_timeout; i++) {
 313                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 314                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 315                                 break;
 316                         udelay(1);
 317                 }
 318                 for (i = 0; i < adev->usec_timeout; i++) {
 319                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 320                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 321                                 break;
 322                         udelay(1);
 323                 }
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 330 {
 331         const struct mc_firmware_header_v1_0 *hdr;
 332         const __le32 *fw_data = NULL;
 333         const __le32 *io_mc_regs = NULL;
 334         u32 data, vbios_version;
 335         int i, ucode_size, regs_size;
 336
 337         /* Skip MC ucode loading on SR-IOV capable boards.
 338          * vbios does this for us in asic_init in that case.
 339          * Skip MC ucode loading on VF, because hypervisor will do that
 340          * for this adaptor.
 341          */
 342         if (amdgpu_sriov_bios(adev))
 343                 return 0;
 344
 345         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 346         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 347         vbios_version = data & 0xf;
 348
 349         if (vbios_version == 0)
 350                 return 0;
 351
 352         if (!adev->mc.fw)
 353                 return -EINVAL;
 354
 355         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 356         amdgpu_ucode_print_mc_hdr(&hdr->header);
 357
 358         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 359         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 360         io_mc_regs = (const __le32 *)
 361                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 362         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 363         fw_data = (const __le32 *)
 364                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 365
 366         data = RREG32(mmMC_SEQ_MISC0);
 367         data &= ~(0x40);
 368         WREG32(mmMC_SEQ_MISC0, data);
 369
 370         /* load mc io regs */
 371         for (i = 0; i < regs_size; i++) {
 372                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 373                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 374         }
 375
 376         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 377         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 378
 379         /* load the MC ucode */
 380         for (i = 0; i < ucode_size; i++)
 381                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 382
 383         /* put the engine back into the active state */
 384         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 385         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 386         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 387
 388         /* wait for training to complete */
 389         for (i = 0; i < adev->usec_timeout; i++) {
 390                 data = RREG32(mmMC_SEQ_MISC0);
 391                 if (data & 0x80)
 392                         break;
 393                 udelay(1);
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 400                                        struct amdgpu_mc *mc)
 401 {
 402         u64 base = 0;
 403
 404         if (!amdgpu_sriov_vf(adev))
 405                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 406         base <<= 24;
 407
 408         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 409                 /* leave room for at least 1024M GTT */
 410                 dev_warn(adev->dev, "limiting VRAM\n");
 411                 mc->real_vram_size = 0xFFC0000000ULL;
 412                 mc->mc_vram_size = 0xFFC0000000ULL;
 413         }
 414         amdgpu_vram_location(adev, &adev->mc, base);
 415         amdgpu_gart_location(adev, mc);
 416 }
 417
 418 /**
 419  * gmc_v8_0_mc_program - program the GPU memory controller
 420  *
 421  * @adev: amdgpu_device pointer
 422  *
 423  * Set the location of vram, gart, and AGP in the GPU's
 424  * physical address space (CIK).
 425  */
 426 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 427 {
 428         u32 tmp;
 429         int i, j;
 430
 431         /* Initialize HDP */
 432         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 433                 WREG32((0xb05 + j), 0x00000000);
 434                 WREG32((0xb06 + j), 0x00000000);
 435                 WREG32((0xb07 + j), 0x00000000);
 436                 WREG32((0xb08 + j), 0x00000000);
 437                 WREG32((0xb09 + j), 0x00000000);
 438         }
 439         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 440
 441         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 442                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 443         }
 444         if (adev->mode_info.num_crtc) {
 445                 /* Lockout access through VGA aperture*/
 446                 tmp = RREG32(mmVGA_HDP_CONTROL);
 447                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 448                 WREG32(mmVGA_HDP_CONTROL, tmp);
 449
 450                 /* disable VGA render */
 451                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 452                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 453                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 454         }
 455         /* Update configuration */
 456         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 457                adev->mc.vram_start >> 12);
 458         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 459                adev->mc.vram_end >> 12);
 460         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 461                adev->vram_scratch.gpu_addr >> 12);
 462
 463         if (amdgpu_sriov_vf(adev)) {
 464                 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 465                 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 466                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 467                 /* XXX double check these! */
 468                 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 469                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 470                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 471         }
 472
 473         WREG32(mmMC_VM_AGP_BASE, 0);
 474         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 475         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 476         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 477                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 478         }
 479
 480         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 481
 482         tmp = RREG32(mmHDP_MISC_CNTL);
 483         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 484         WREG32(mmHDP_MISC_CNTL, tmp);
 485
 486         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 487         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 488 }
 489
 490 /**
 491  * gmc_v8_0_mc_init - initialize the memory controller driver params
 492  *
 493  * @adev: amdgpu_device pointer
 494  *
 495  * Look up the amount of vram, vram width, and decide how to place
 496  * vram and gart within the GPU's physical address space (CIK).
 497  * Returns 0 for success.
 498  */
 499 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 500 {
 501         int r;
 502
 503         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 504         if (!adev->mc.vram_width) {
 505                 u32 tmp;
 506                 int chansize, numchan;
 507
 508                 /* Get VRAM informations */
 509                 tmp = RREG32(mmMC_ARB_RAMCFG);
 510                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 511                         chansize = 64;
 512                 } else {
 513                         chansize = 32;
 514                 }
 515                 tmp = RREG32(mmMC_SHARED_CHMAP);
 516                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 517                 case 0:
 518                 default:
 519                         numchan = 1;
 520                         break;
 521                 case 1:
 522                         numchan = 2;
 523                         break;
 524                 case 2:
 525                         numchan = 4;
 526                         break;
 527                 case 3:
 528                         numchan = 8;
 529                         break;
 530                 case 4:
 531                         numchan = 3;
 532                         break;
 533                 case 5:
 534                         numchan = 6;
 535                         break;
 536                 case 6:
 537                         numchan = 10;
 538                         break;
 539                 case 7:
 540                         numchan = 12;
 541                         break;
 542                 case 8:
 543                         numchan = 16;
 544                         break;
 545                 }
 546                 adev->mc.vram_width = numchan * chansize;
 547         }
 548         /* size in MB on si */
 549         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 550         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 551
 552         if (!(adev->flags & AMD_IS_APU)) {
 553                 r = amdgpu_device_resize_fb_bar(adev);
 554                 if (r)
 555                         return r;
 556         }
 557         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 558         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 559
 560 #ifdef CONFIG_X86_64
 561         if (adev->flags & AMD_IS_APU) {
 562                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 563                 adev->mc.aper_size = adev->mc.real_vram_size;
 564         }
 565 #endif
 566
 567         /* In case the PCI BAR is larger than the actual amount of vram */
 568         adev->mc.visible_vram_size = adev->mc.aper_size;
 569         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 570                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 571
 572         /* set the gart size */
 573         if (amdgpu_gart_size == -1) {
 574                 switch (adev->asic_type) {
 575                 case CHIP_POLARIS11: /* all engines support GPUVM */
 576                 case CHIP_POLARIS10: /* all engines support GPUVM */
 577                 case CHIP_POLARIS12: /* all engines support GPUVM */
 578                 default:
 579                         adev->mc.gart_size = 256ULL << 20;
 580                         break;
 581                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 582                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 583                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 584                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 585                         adev->mc.gart_size = 1024ULL << 20;
 586                         break;
 587                 }
 588         } else {
 589                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 590         }
 591
 592         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 593
 594         return 0;
 595 }
 596
 597 /*
 598  * GART
 599  * VMID 0 is the physical GPU addresses as used by the kernel.
 600  * VMIDs 1-15 are used for userspace clients and are handled
 601  * by the amdgpu vm/hsa code.
 602  */
 603
 604 /**
 605  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 606  *
 607  * @adev: amdgpu_device pointer
 608  * @vmid: vm instance to flush
 609  *
 610  * Flush the TLB for the requested page table (CIK).
 611  */
 612 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 613                                         uint32_t vmid)
 614 {
 615         /* flush hdp cache */
 616         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 617
 618         /* bits 0-15 are the VM contexts0-15 */
 619         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 620 }
 621
 622 /**
 623  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 624  *
 625  * @adev: amdgpu_device pointer
 626  * @cpu_pt_addr: cpu address of the page table
 627  * @gpu_page_idx: entry in the page table to update
 628  * @addr: dst addr to write into pte/pde
 629  * @flags: access flags
 630  *
 631  * Update the page tables using the CPU.
 632  */
 633 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 634                                      void *cpu_pt_addr,
 635                                      uint32_t gpu_page_idx,
 636                                      uint64_t addr,
 637                                      uint64_t flags)
 638 {
 639         void __iomem *ptr = (void *)cpu_pt_addr;
 640         uint64_t value;
 641
 642         /*
 643          * PTE format on VI:
 644          * 63:40 reserved
 645          * 39:12 4k physical page base address
 646          * 11:7 fragment
 647          * 6 write
 648          * 5 read
 649          * 4 exe
 650          * 3 reserved
 651          * 2 snooped
 652          * 1 system
 653          * 0 valid
 654          *
 655          * PDE format on VI:
 656          * 63:59 block fragment size
 657          * 58:40 reserved
 658          * 39:1 physical base address of PTE
 659          * bits 5:1 must be 0.
 660          * 0 valid
 661          */
 662         value = addr & 0x000000FFFFFFF000ULL;
 663         value |= flags;
 664         writeq(value, ptr + (gpu_page_idx * 8));
 665
 666         return 0;
 667 }
 668
 669 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 670                                           uint32_t flags)
 671 {
 672         uint64_t pte_flag = 0;
 673
 674         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 675                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 676         if (flags & AMDGPU_VM_PAGE_READABLE)
 677                 pte_flag |= AMDGPU_PTE_READABLE;
 678         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 679                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 680         if (flags & AMDGPU_VM_PAGE_PRT)
 681                 pte_flag |= AMDGPU_PTE_PRT;
 682
 683         return pte_flag;
 684 }
 685
 686 static uint64_t gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, uint64_t addr)
 687 {
 688         BUG_ON(addr & 0xFFFFFF0000000FFFULL);
 689         return addr;
 690 }
 691
 692 /**
 693  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 694  *
 695  * @adev: amdgpu_device pointer
 696  * @value: true redirects VM faults to the default page
 697  */
 698 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 699                                               bool value)
 700 {
 701         u32 tmp;
 702
 703         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 704         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 705                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 706         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 707                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 708         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 709                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 710         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 711                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 712         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 713                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 714         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 715                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 716         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 717                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 718         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 719 }
 720
 721 /**
 722  * gmc_v8_0_set_prt - set PRT VM fault
 723  *
 724  * @adev: amdgpu_device pointer
 725  * @enable: enable/disable VM fault handling for PRT
 726 */
 727 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 728 {
 729         u32 tmp;
 730
 731         if (enable && !adev->mc.prt_warning) {
 732                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 733                 adev->mc.prt_warning = true;
 734         }
 735
 736         tmp = RREG32(mmVM_PRT_CNTL);
 737         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 738                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 739         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 740                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 741         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 742                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 743         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 744                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 745         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 746                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 747         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 748                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 749         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 750                             MASK_PDE0_FAULT, enable);
 751         WREG32(mmVM_PRT_CNTL, tmp);
 752
 753         if (enable) {
 754                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 755                 uint32_t high = adev->vm_manager.max_pfn;
 756
 757                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 758                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 759                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 760                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 761                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 762                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 763                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 764                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 765         } else {
 766                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 767                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 768                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 769                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 770                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 771                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 772                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 773                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 774         }
 775 }
 776
 777 /**
 778  * gmc_v8_0_gart_enable - gart enable
 779  *
 780  * @adev: amdgpu_device pointer
 781  *
 782  * This sets up the TLBs, programs the page tables for VMID0,
 783  * sets up the hw for VMIDs 1-15 which are allocated on
 784  * demand, and sets up the global locations for the LDS, GDS,
 785  * and GPUVM for FSA64 clients (CIK).
 786  * Returns 0 for success, errors for failure.
 787  */
 788 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 789 {
 790         int r, i;
 791         u32 tmp, field;
 792
 793         if (adev->gart.robj == NULL) {
 794                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 795                 return -EINVAL;
 796         }
 797         r = amdgpu_gart_table_vram_pin(adev);
 798         if (r)
 799                 return r;
 800         /* Setup TLB control */
 801         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 802         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 803         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 804         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 805         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 806         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 807         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 808         /* Setup L2 cache */
 809         tmp = RREG32(mmVM_L2_CNTL);
 810         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 811         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 812         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 813         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 814         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 815         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 816         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 817         WREG32(mmVM_L2_CNTL, tmp);
 818         tmp = RREG32(mmVM_L2_CNTL2);
 819         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 820         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 821         WREG32(mmVM_L2_CNTL2, tmp);
 822
 823         field = adev->vm_manager.fragment_size;
 824         tmp = RREG32(mmVM_L2_CNTL3);
 825         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 826         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 827         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 828         WREG32(mmVM_L2_CNTL3, tmp);
 829         /* XXX: set to enable PTE/PDE in system memory */
 830         tmp = RREG32(mmVM_L2_CNTL4);
 831         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 832         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 833         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 834         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 835         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 836         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 837         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 838         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 839         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 840         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 841         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 842         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 843         WREG32(mmVM_L2_CNTL4, tmp);
 844         /* setup context0 */
 845         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 846         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 847         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 848         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 849                         (u32)(adev->dummy_page.addr >> 12));
 850         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 851         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 852         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 853         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 854         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 855         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 856
 857         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 858         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 859         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 860
 861         /* empty context1-15 */
 862         /* FIXME start with 4G, once using 2 level pt switch to full
 863          * vm size space
 864          */
 865         /* set vm size, must be a multiple of 4 */
 866         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 867         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 868         for (i = 1; i < 16; i++) {
 869                 if (i < 8)
 870                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 871                                adev->gart.table_addr >> 12);
 872                 else
 873                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 874                                adev->gart.table_addr >> 12);
 875         }
 876
 877         /* enable context1-15 */
 878         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 879                (u32)(adev->dummy_page.addr >> 12));
 880         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 881         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 882         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 883         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 884         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 885         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 886         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 887         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 888         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 889         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 890         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 891         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 892                             adev->vm_manager.block_size - 9);
 893         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 894         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 895                 gmc_v8_0_set_fault_enable_default(adev, false);
 896         else
 897                 gmc_v8_0_set_fault_enable_default(adev, true);
 898
 899         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 900         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 901                  (unsigned)(adev->mc.gart_size >> 20),
 902                  (unsigned long long)adev->gart.table_addr);
 903         adev->gart.ready = true;
 904         return 0;
 905 }
 906
 907 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 908 {
 909         int r;
 910
 911         if (adev->gart.robj) {
 912                 WARN(1, "R600 PCIE GART already initialized\n");
 913                 return 0;
 914         }
 915         /* Initialize common gart structure */
 916         r = amdgpu_gart_init(adev);
 917         if (r)
 918                 return r;
 919         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 920         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 921         return amdgpu_gart_table_vram_alloc(adev);
 922 }
 923
 924 /**
 925  * gmc_v8_0_gart_disable - gart disable
 926  *
 927  * @adev: amdgpu_device pointer
 928  *
 929  * This disables all VM page table (CIK).
 930  */
 931 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 932 {
 933         u32 tmp;
 934
 935         /* Disable all tables */
 936         WREG32(mmVM_CONTEXT0_CNTL, 0);
 937         WREG32(mmVM_CONTEXT1_CNTL, 0);
 938         /* Setup TLB control */
 939         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 940         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 941         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 942         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 943         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 944         /* Setup L2 cache */
 945         tmp = RREG32(mmVM_L2_CNTL);
 946         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 947         WREG32(mmVM_L2_CNTL, tmp);
 948         WREG32(mmVM_L2_CNTL2, 0);
 949         amdgpu_gart_table_vram_unpin(adev);
 950 }
 951
 952 /**
 953  * gmc_v8_0_gart_fini - vm fini callback
 954  *
 955  * @adev: amdgpu_device pointer
 956  *
 957  * Tears down the driver GART/VM setup (CIK).
 958  */
 959 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 960 {
 961         amdgpu_gart_table_vram_free(adev);
 962         amdgpu_gart_fini(adev);
 963 }
 964
 965 /**
 966  * gmc_v8_0_vm_decode_fault - print human readable fault info
 967  *
 968  * @adev: amdgpu_device pointer
 969  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 970  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 971  *
 972  * Print human readable fault information (CIK).
 973  */
 974 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 975                                      u32 status, u32 addr, u32 mc_client)
 976 {
 977         u32 mc_id;
 978         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 979         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 980                                         PROTECTIONS);
 981         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 982                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 983
 984         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 985                               MEMORY_CLIENT_ID);
 986
 987         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 988                protections, vmid, addr,
 989                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 990                              MEMORY_CLIENT_RW) ?
 991                "write" : "read", block, mc_client, mc_id);
 992 }
 993
 994 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 995 {
 996         switch (mc_seq_vram_type) {
 997         case MC_SEQ_MISC0__MT__GDDR1:
 998                 return AMDGPU_VRAM_TYPE_GDDR1;
 999         case MC_SEQ_MISC0__MT__DDR2:
1000                 return AMDGPU_VRAM_TYPE_DDR2;
1001         case MC_SEQ_MISC0__MT__GDDR3:
1002                 return AMDGPU_VRAM_TYPE_GDDR3;
1003         case MC_SEQ_MISC0__MT__GDDR4:
1004                 return AMDGPU_VRAM_TYPE_GDDR4;
1005         case MC_SEQ_MISC0__MT__GDDR5:
1006                 return AMDGPU_VRAM_TYPE_GDDR5;
1007         case MC_SEQ_MISC0__MT__HBM:
1008                 return AMDGPU_VRAM_TYPE_HBM;
1009         case MC_SEQ_MISC0__MT__DDR3:
1010                 return AMDGPU_VRAM_TYPE_DDR3;
1011         default:
1012                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1013         }
1014 }
1015
1016 static int gmc_v8_0_early_init(void *handle)
1017 {
1018         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1019
1020         gmc_v8_0_set_gart_funcs(adev);
1021         gmc_v8_0_set_irq_funcs(adev);
1022
1023         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
1024         adev->mc.shared_aperture_end =
1025                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
1026         adev->mc.private_aperture_start =
1027                 adev->mc.shared_aperture_end + 1;
1028         adev->mc.private_aperture_end =
1029                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
1030
1031         return 0;
1032 }
1033
1034 static int gmc_v8_0_late_init(void *handle)
1035 {
1036         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1037
1038         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1039                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
1040         else
1041                 return 0;
1042 }
1043
1044 #define mmMC_SEQ_MISC0_FIJI 0xA71
1045
1046 static int gmc_v8_0_sw_init(void *handle)
1047 {
1048         int r;
1049         int dma_bits;
1050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1051
1052         if (adev->flags & AMD_IS_APU) {
1053                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1054         } else {
1055                 u32 tmp;
1056
1057                 if (adev->asic_type == CHIP_FIJI)
1058                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1059                 else
1060                         tmp = RREG32(mmMC_SEQ_MISC0);
1061                 tmp &= MC_SEQ_MISC0__MT__MASK;
1062                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1063         }
1064
1065         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
1066         if (r)
1067                 return r;
1068
1069         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
1070         if (r)
1071                 return r;
1072
1073         /* Adjust VM size here.
1074          * Currently set to 4GB ((1 << 20) 4k pages).
1075          * Max GPUVM size for cayman and SI is 40 bits.
1076          */
1077         amdgpu_vm_adjust_size(adev, 64, 9);
1078
1079         /* Set the internal MC address mask
1080          * This is the max address of the GPU's
1081          * internal address space.
1082          */
1083         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1084
1085         adev->mc.stolen_size = 256 * 1024;
1086
1087         /* set DMA mask + need_dma32 flags.
1088          * PCIE - can handle 40-bits.
1089          * IGP - can handle 40-bits
1090          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1091          */
1092         adev->need_dma32 = false;
1093         dma_bits = adev->need_dma32 ? 32 : 40;
1094         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1095         if (r) {
1096                 adev->need_dma32 = true;
1097                 dma_bits = 32;
1098                 pr_warn("amdgpu: No suitable DMA available\n");
1099         }
1100         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1101         if (r) {
1102                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1103                 pr_warn("amdgpu: No coherent DMA available\n");
1104         }
1105
1106         r = gmc_v8_0_init_microcode(adev);
1107         if (r) {
1108                 DRM_ERROR("Failed to load mc firmware!\n");
1109                 return r;
1110         }
1111
1112         r = gmc_v8_0_mc_init(adev);
1113         if (r)
1114                 return r;
1115
1116         /* Memory manager */
1117         r = amdgpu_bo_init(adev);
1118         if (r)
1119                 return r;
1120
1121         r = gmc_v8_0_gart_init(adev);
1122         if (r)
1123                 return r;
1124
1125         /*
1126          * number of VMs
1127          * VMID 0 is reserved for System
1128          * amdgpu graphics/compute will use VMIDs 1-7
1129          * amdkfd will use VMIDs 8-15
1130          */
1131         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1132         adev->vm_manager.num_level = 1;
1133         amdgpu_vm_manager_init(adev);
1134
1135         /* base offset of vram pages */
1136         if (adev->flags & AMD_IS_APU) {
1137                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1138
1139                 tmp <<= 22;
1140                 adev->vm_manager.vram_base_offset = tmp;
1141         } else {
1142                 adev->vm_manager.vram_base_offset = 0;
1143         }
1144
1145         return 0;
1146 }
1147
1148 static int gmc_v8_0_sw_fini(void *handle)
1149 {
1150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1151
1152         amdgpu_vm_manager_fini(adev);
1153         gmc_v8_0_gart_fini(adev);
1154         amdgpu_gem_force_release(adev);
1155         amdgpu_bo_fini(adev);
1156         release_firmware(adev->mc.fw);
1157         adev->mc.fw = NULL;
1158
1159         return 0;
1160 }
1161
1162 static int gmc_v8_0_hw_init(void *handle)
1163 {
1164         int r;
1165         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1166
1167         gmc_v8_0_init_golden_registers(adev);
1168
1169         gmc_v8_0_mc_program(adev);
1170
1171         if (adev->asic_type == CHIP_TONGA) {
1172                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1173                 if (r) {
1174                         DRM_ERROR("Failed to load MC firmware!\n");
1175                         return r;
1176                 }
1177         } else if (adev->asic_type == CHIP_POLARIS11 ||
1178                         adev->asic_type == CHIP_POLARIS10 ||
1179                         adev->asic_type == CHIP_POLARIS12) {
1180                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1181                 if (r) {
1182                         DRM_ERROR("Failed to load MC firmware!\n");
1183                         return r;
1184                 }
1185         }
1186
1187         r = gmc_v8_0_gart_enable(adev);
1188         if (r)
1189                 return r;
1190
1191         return r;
1192 }
1193
1194 static int gmc_v8_0_hw_fini(void *handle)
1195 {
1196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1197
1198         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1199         gmc_v8_0_gart_disable(adev);
1200
1201         return 0;
1202 }
1203
1204 static int gmc_v8_0_suspend(void *handle)
1205 {
1206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207
1208         gmc_v8_0_hw_fini(adev);
1209
1210         return 0;
1211 }
1212
1213 static int gmc_v8_0_resume(void *handle)
1214 {
1215         int r;
1216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217
1218         r = gmc_v8_0_hw_init(adev);
1219         if (r)
1220                 return r;
1221
1222         amdgpu_vm_reset_all_ids(adev);
1223
1224         return 0;
1225 }
1226
1227 static bool gmc_v8_0_is_idle(void *handle)
1228 {
1229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1230         u32 tmp = RREG32(mmSRBM_STATUS);
1231
1232         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1233                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1234                 return false;
1235
1236         return true;
1237 }
1238
1239 static int gmc_v8_0_wait_for_idle(void *handle)
1240 {
1241         unsigned i;
1242         u32 tmp;
1243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244
1245         for (i = 0; i < adev->usec_timeout; i++) {
1246                 /* read MC_STATUS */
1247                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1248                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1249                                                SRBM_STATUS__MCC_BUSY_MASK |
1250                                                SRBM_STATUS__MCD_BUSY_MASK |
1251                                                SRBM_STATUS__VMC_BUSY_MASK |
1252                                                SRBM_STATUS__VMC1_BUSY_MASK);
1253                 if (!tmp)
1254                         return 0;
1255                 udelay(1);
1256         }
1257         return -ETIMEDOUT;
1258
1259 }
1260
1261 static bool gmc_v8_0_check_soft_reset(void *handle)
1262 {
1263         u32 srbm_soft_reset = 0;
1264         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265         u32 tmp = RREG32(mmSRBM_STATUS);
1266
1267         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1268                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1269                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1270
1271         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1272                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1273                 if (!(adev->flags & AMD_IS_APU))
1274                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1275                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1276         }
1277         if (srbm_soft_reset) {
1278                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1279                 return true;
1280         } else {
1281                 adev->mc.srbm_soft_reset = 0;
1282                 return false;
1283         }
1284 }
1285
1286 static int gmc_v8_0_pre_soft_reset(void *handle)
1287 {
1288         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1289
1290         if (!adev->mc.srbm_soft_reset)
1291                 return 0;
1292
1293         gmc_v8_0_mc_stop(adev);
1294         if (gmc_v8_0_wait_for_idle(adev)) {
1295                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int gmc_v8_0_soft_reset(void *handle)
1302 {
1303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304         u32 srbm_soft_reset;
1305
1306         if (!adev->mc.srbm_soft_reset)
1307                 return 0;
1308         srbm_soft_reset = adev->mc.srbm_soft_reset;
1309
1310         if (srbm_soft_reset) {
1311                 u32 tmp;
1312
1313                 tmp = RREG32(mmSRBM_SOFT_RESET);
1314                 tmp |= srbm_soft_reset;
1315                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1316                 WREG32(mmSRBM_SOFT_RESET, tmp);
1317                 tmp = RREG32(mmSRBM_SOFT_RESET);
1318
1319                 udelay(50);
1320
1321                 tmp &= ~srbm_soft_reset;
1322                 WREG32(mmSRBM_SOFT_RESET, tmp);
1323                 tmp = RREG32(mmSRBM_SOFT_RESET);
1324
1325                 /* Wait a little for things to settle down */
1326                 udelay(50);
1327         }
1328
1329         return 0;
1330 }
1331
1332 static int gmc_v8_0_post_soft_reset(void *handle)
1333 {
1334         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335
1336         if (!adev->mc.srbm_soft_reset)
1337                 return 0;
1338
1339         gmc_v8_0_mc_resume(adev);
1340         return 0;
1341 }
1342
1343 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1344                                              struct amdgpu_irq_src *src,
1345                                              unsigned type,
1346                                              enum amdgpu_interrupt_state state)
1347 {
1348         u32 tmp;
1349         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1350                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1351                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1352                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1353                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1354                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1355                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1356
1357         switch (state) {
1358         case AMDGPU_IRQ_STATE_DISABLE:
1359                 /* system context */
1360                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1361                 tmp &= ~bits;
1362                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1363                 /* VMs */
1364                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1365                 tmp &= ~bits;
1366                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1367                 break;
1368         case AMDGPU_IRQ_STATE_ENABLE:
1369                 /* system context */
1370                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1371                 tmp |= bits;
1372                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1373                 /* VMs */
1374                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1375                 tmp |= bits;
1376                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1377                 break;
1378         default:
1379                 break;
1380         }
1381
1382         return 0;
1383 }
1384
1385 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1386                                       struct amdgpu_irq_src *source,
1387                                       struct amdgpu_iv_entry *entry)
1388 {
1389         u32 addr, status, mc_client;
1390
1391         if (amdgpu_sriov_vf(adev)) {
1392                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1393                         entry->src_id, entry->src_data[0]);
1394                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1395                 return 0;
1396         }
1397
1398         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1399         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1400         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1401         /* reset addr and status */
1402         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1403
1404         if (!addr && !status)
1405                 return 0;
1406
1407         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1408                 gmc_v8_0_set_fault_enable_default(adev, false);
1409
1410         if (printk_ratelimit()) {
1411                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1412                         entry->src_id, entry->src_data[0]);
1413                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1414                         addr);
1415                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1416                         status);
1417                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1418         }
1419
1420         return 0;
1421 }
1422
1423 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1424                                                      bool enable)
1425 {
1426         uint32_t data;
1427
1428         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1429                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1430                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1431                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1432
1433                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1434                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1435                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1436
1437                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1438                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1439                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1440
1441                 data = RREG32(mmMC_XPB_CLK_GAT);
1442                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1443                 WREG32(mmMC_XPB_CLK_GAT, data);
1444
1445                 data = RREG32(mmATC_MISC_CG);
1446                 data |= ATC_MISC_CG__ENABLE_MASK;
1447                 WREG32(mmATC_MISC_CG, data);
1448
1449                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1450                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1451                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1452
1453                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1454                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1455                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1456
1457                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1458                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1459                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1460
1461                 data = RREG32(mmVM_L2_CG);
1462                 data |= VM_L2_CG__ENABLE_MASK;
1463                 WREG32(mmVM_L2_CG, data);
1464         } else {
1465                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1466                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1467                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1468
1469                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1470                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1471                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1472
1473                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1474                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1475                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1476
1477                 data = RREG32(mmMC_XPB_CLK_GAT);
1478                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1479                 WREG32(mmMC_XPB_CLK_GAT, data);
1480
1481                 data = RREG32(mmATC_MISC_CG);
1482                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1483                 WREG32(mmATC_MISC_CG, data);
1484
1485                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1486                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1487                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1488
1489                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1490                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1491                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1492
1493                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1494                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1495                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1496
1497                 data = RREG32(mmVM_L2_CG);
1498                 data &= ~VM_L2_CG__ENABLE_MASK;
1499                 WREG32(mmVM_L2_CG, data);
1500         }
1501 }
1502
1503 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1504                                        bool enable)
1505 {
1506         uint32_t data;
1507
1508         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1509                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1510                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1511                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1512
1513                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1514                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1515                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1516
1517                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1518                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1519                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1520
1521                 data = RREG32(mmMC_XPB_CLK_GAT);
1522                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1523                 WREG32(mmMC_XPB_CLK_GAT, data);
1524
1525                 data = RREG32(mmATC_MISC_CG);
1526                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1527                 WREG32(mmATC_MISC_CG, data);
1528
1529                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1530                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1531                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1532
1533                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1534                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1535                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1536
1537                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1538                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1539                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1540
1541                 data = RREG32(mmVM_L2_CG);
1542                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1543                 WREG32(mmVM_L2_CG, data);
1544         } else {
1545                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1546                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1547                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1548
1549                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1550                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1551                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1552
1553                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1554                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1555                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1556
1557                 data = RREG32(mmMC_XPB_CLK_GAT);
1558                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1559                 WREG32(mmMC_XPB_CLK_GAT, data);
1560
1561                 data = RREG32(mmATC_MISC_CG);
1562                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1563                 WREG32(mmATC_MISC_CG, data);
1564
1565                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1566                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1567                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1568
1569                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1570                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1571                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1572
1573                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1574                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1575                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1576
1577                 data = RREG32(mmVM_L2_CG);
1578                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1579                 WREG32(mmVM_L2_CG, data);
1580         }
1581 }
1582
1583 static int gmc_v8_0_set_clockgating_state(void *handle,
1584                                           enum amd_clockgating_state state)
1585 {
1586         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1587
1588         if (amdgpu_sriov_vf(adev))
1589                 return 0;
1590
1591         switch (adev->asic_type) {
1592         case CHIP_FIJI:
1593                 fiji_update_mc_medium_grain_clock_gating(adev,
1594                                 state == AMD_CG_STATE_GATE);
1595                 fiji_update_mc_light_sleep(adev,
1596                                 state == AMD_CG_STATE_GATE);
1597                 break;
1598         default:
1599                 break;
1600         }
1601         return 0;
1602 }
1603
1604 static int gmc_v8_0_set_powergating_state(void *handle,
1605                                           enum amd_powergating_state state)
1606 {
1607         return 0;
1608 }
1609
1610 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1611 {
1612         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1613         int data;
1614
1615         if (amdgpu_sriov_vf(adev))
1616                 *flags = 0;
1617
1618         /* AMD_CG_SUPPORT_MC_MGCG */
1619         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1620         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1621                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1622
1623         /* AMD_CG_SUPPORT_MC_LS */
1624         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1625                 *flags |= AMD_CG_SUPPORT_MC_LS;
1626 }
1627
1628 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1629         .name = "gmc_v8_0",
1630         .early_init = gmc_v8_0_early_init,
1631         .late_init = gmc_v8_0_late_init,
1632         .sw_init = gmc_v8_0_sw_init,
1633         .sw_fini = gmc_v8_0_sw_fini,
1634         .hw_init = gmc_v8_0_hw_init,
1635         .hw_fini = gmc_v8_0_hw_fini,
1636         .suspend = gmc_v8_0_suspend,
1637         .resume = gmc_v8_0_resume,
1638         .is_idle = gmc_v8_0_is_idle,
1639         .wait_for_idle = gmc_v8_0_wait_for_idle,
1640         .check_soft_reset = gmc_v8_0_check_soft_reset,
1641         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1642         .soft_reset = gmc_v8_0_soft_reset,
1643         .post_soft_reset = gmc_v8_0_post_soft_reset,
1644         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1645         .set_powergating_state = gmc_v8_0_set_powergating_state,
1646         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1647 };
1648
1649 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1650         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1651         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1652         .set_prt = gmc_v8_0_set_prt,
1653         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1654         .get_vm_pde = gmc_v8_0_get_vm_pde
1655 };
1656
1657 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1658         .set = gmc_v8_0_vm_fault_interrupt_state,
1659         .process = gmc_v8_0_process_interrupt,
1660 };
1661
1662 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1663 {
1664         if (adev->gart.gart_funcs == NULL)
1665                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1666 }
1667
1668 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1669 {
1670         adev->mc.vm_fault.num_types = 1;
1671         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1672 }
1673
1674 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1675 {
1676         .type = AMD_IP_BLOCK_TYPE_GMC,
1677         .major = 8,
1678         .minor = 0,
1679         .rev = 0,
1680         .funcs = &gmc_v8_0_ip_funcs,
1681 };
1682
1683 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1684 {
1685         .type = AMD_IP_BLOCK_TYPE_GMC,
1686         .major = 8,
1687         .minor = 1,
1688         .rev = 0,
1689         .funcs = &gmc_v8_0_ip_funcs,
1690 };
1691
1692 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1693 {
1694         .type = AMD_IP_BLOCK_TYPE_GMC,
1695         .major = 8,
1696         .minor = 5,
1697         .rev = 0,
1698         .funcs = &gmc_v8_0_ip_funcs,
1699 };