drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <linux/sync_file.h>
  29 #include <drm/drmP.h>
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_syncobj.h>
  32 #include "amdgpu.h"
  33 #include "amdgpu_trace.h"
  34
  35 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  36                                       struct drm_amdgpu_cs_chunk_fence *data,
  37                                       uint32_t *offset)
  38 {
  39         struct drm_gem_object *gobj;
  40         unsigned long size;
  41
  42         gobj = drm_gem_object_lookup(p->filp, data->handle);
  43         if (gobj == NULL)
  44                 return -EINVAL;
  45
  46         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  47         p->uf_entry.priority = 0;
  48         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  49         p->uf_entry.tv.shared = true;
  50         p->uf_entry.user_pages = NULL;
  51
  52         size = amdgpu_bo_size(p->uf_entry.robj);
  53         if (size != PAGE_SIZE || (data->offset + 8) > size)
  54                 return -EINVAL;
  55
  56         *offset = data->offset;
  57
  58         drm_gem_object_put_unlocked(gobj);
  59
  60         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  61                 amdgpu_bo_unref(&p->uf_entry.robj);
  62                 return -EINVAL;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
  69 {
  70         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  71         struct amdgpu_vm *vm = &fpriv->vm;
  72         union drm_amdgpu_cs *cs = data;
  73         uint64_t *chunk_array_user;
  74         uint64_t *chunk_array;
  75         unsigned size, num_ibs = 0;
  76         uint32_t uf_offset = 0;
  77         int i;
  78         int ret;
  79
  80         if (cs->in.num_chunks == 0)
  81                 return 0;
  82
  83         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
  84         if (!chunk_array)
  85                 return -ENOMEM;
  86
  87         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  88         if (!p->ctx) {
  89                 ret = -EINVAL;
  90                 goto free_chunk;
  91         }
  92
  93         /* skip guilty context job */
  94         if (atomic_read(&p->ctx->guilty) == 1) {
  95                 ret = -ECANCELED;
  96                 goto free_chunk;
  97         }
  98
  99         mutex_lock(&p->ctx->lock);
 100
 101         /* get chunks */
 102         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 103         if (copy_from_user(chunk_array, chunk_array_user,
 104                            sizeof(uint64_t)*cs->in.num_chunks)) {
 105                 ret = -EFAULT;
 106                 goto free_chunk;
 107         }
 108
 109         p->nchunks = cs->in.num_chunks;
 110         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 111                             GFP_KERNEL);
 112         if (!p->chunks) {
 113                 ret = -ENOMEM;
 114                 goto free_chunk;
 115         }
 116
 117         for (i = 0; i < p->nchunks; i++) {
 118                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 119                 struct drm_amdgpu_cs_chunk user_chunk;
 120                 uint32_t __user *cdata;
 121
 122                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 123                 if (copy_from_user(&user_chunk, chunk_ptr,
 124                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 125                         ret = -EFAULT;
 126                         i--;
 127                         goto free_partial_kdata;
 128                 }
 129                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 130                 p->chunks[i].length_dw = user_chunk.length_dw;
 131
 132                 size = p->chunks[i].length_dw;
 133                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 134
 135                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 136                 if (p->chunks[i].kdata == NULL) {
 137                         ret = -ENOMEM;
 138                         i--;
 139                         goto free_partial_kdata;
 140                 }
 141                 size *= sizeof(uint32_t);
 142                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 143                         ret = -EFAULT;
 144                         goto free_partial_kdata;
 145                 }
 146
 147                 switch (p->chunks[i].chunk_id) {
 148                 case AMDGPU_CHUNK_ID_IB:
 149                         ++num_ibs;
 150                         break;
 151
 152                 case AMDGPU_CHUNK_ID_FENCE:
 153                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 154                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 155                                 ret = -EINVAL;
 156                                 goto free_partial_kdata;
 157                         }
 158
 159                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 160                                                          &uf_offset);
 161                         if (ret)
 162                                 goto free_partial_kdata;
 163
 164                         break;
 165
 166                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 167                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 168                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 169                         break;
 170
 171                 default:
 172                         ret = -EINVAL;
 173                         goto free_partial_kdata;
 174                 }
 175         }
 176
 177         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 178         if (ret)
 179                 goto free_all_kdata;
 180
 181         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 182                 ret = -ECANCELED;
 183                 goto free_all_kdata;
 184         }
 185
 186         if (p->uf_entry.robj)
 187                 p->job->uf_addr = uf_offset;
 188         kfree(chunk_array);
 189         return 0;
 190
 191 free_all_kdata:
 192         i = p->nchunks - 1;
 193 free_partial_kdata:
 194         for (; i >= 0; i--)
 195                 kvfree(p->chunks[i].kdata);
 196         kfree(p->chunks);
 197         p->chunks = NULL;
 198         p->nchunks = 0;
 199 free_chunk:
 200         kfree(chunk_array);
 201
 202         return ret;
 203 }
 204
 205 /* Convert microseconds to bytes. */
 206 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 207 {
 208         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 209                 return 0;
 210
 211         /* Since accum_us is incremented by a million per second, just
 212          * multiply it by the number of MB/s to get the number of bytes.
 213          */
 214         return us << adev->mm_stats.log2_max_MBps;
 215 }
 216
 217 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 218 {
 219         if (!adev->mm_stats.log2_max_MBps)
 220                 return 0;
 221
 222         return bytes >> adev->mm_stats.log2_max_MBps;
 223 }
 224
 225 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 226  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 227  * which means it can go over the threshold once. If that happens, the driver
 228  * will be in debt and no other buffer migrations can be done until that debt
 229  * is repaid.
 230  *
 231  * This approach allows moving a buffer of any size (it's important to allow
 232  * that).
 233  *
 234  * The currency is simply time in microseconds and it increases as the clock
 235  * ticks. The accumulated microseconds (us) are converted to bytes and
 236  * returned.
 237  */
 238 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 239                                               u64 *max_bytes,
 240                                               u64 *max_vis_bytes)
 241 {
 242         s64 time_us, increment_us;
 243         u64 free_vram, total_vram, used_vram;
 244
 245         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 246          * throttling.
 247          *
 248          * It means that in order to get full max MBps, at least 5 IBs per
 249          * second must be submitted and not more than 200ms apart from each
 250          * other.
 251          */
 252         const s64 us_upper_bound = 200000;
 253
 254         if (!adev->mm_stats.log2_max_MBps) {
 255                 *max_bytes = 0;
 256                 *max_vis_bytes = 0;
 257                 return;
 258         }
 259
 260         total_vram = adev->gmc.real_vram_size - adev->vram_pin_size;
 261         used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 262         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 263
 264         spin_lock(&adev->mm_stats.lock);
 265
 266         /* Increase the amount of accumulated us. */
 267         time_us = ktime_to_us(ktime_get());
 268         increment_us = time_us - adev->mm_stats.last_update_us;
 269         adev->mm_stats.last_update_us = time_us;
 270         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 271                                       us_upper_bound);
 272
 273         /* This prevents the short period of low performance when the VRAM
 274          * usage is low and the driver is in debt or doesn't have enough
 275          * accumulated us to fill VRAM quickly.
 276          *
 277          * The situation can occur in these cases:
 278          * - a lot of VRAM is freed by userspace
 279          * - the presence of a big buffer causes a lot of evictions
 280          *   (solution: split buffers into smaller ones)
 281          *
 282          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 283          * accum_us to a positive number.
 284          */
 285         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 286                 s64 min_us;
 287
 288                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 289                  * VRAM now.
 290                  */
 291                 if (!(adev->flags & AMD_IS_APU))
 292                         min_us = bytes_to_us(adev, free_vram / 4);
 293                 else
 294                         min_us = 0; /* Reset accum_us on APUs. */
 295
 296                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 297         }
 298
 299         /* This is set to 0 if the driver is in debt to disallow (optional)
 300          * buffer moves.
 301          */
 302         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 303
 304         /* Do the same for visible VRAM if half of it is free */
 305         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size) {
 306                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 307                 u64 used_vis_vram =
 308                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 309
 310                 if (used_vis_vram < total_vis_vram) {
 311                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 312                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 313                                                           increment_us, us_upper_bound);
 314
 315                         if (free_vis_vram >= total_vis_vram / 2)
 316                                 adev->mm_stats.accum_us_vis =
 317                                         max(bytes_to_us(adev, free_vis_vram / 2),
 318                                             adev->mm_stats.accum_us_vis);
 319                 }
 320
 321                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 322         } else {
 323                 *max_vis_bytes = 0;
 324         }
 325
 326         spin_unlock(&adev->mm_stats.lock);
 327 }
 328
 329 /* Report how many bytes have really been moved for the last command
 330  * submission. This can result in a debt that can stop buffer migrations
 331  * temporarily.
 332  */
 333 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 334                                   u64 num_vis_bytes)
 335 {
 336         spin_lock(&adev->mm_stats.lock);
 337         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 338         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 339         spin_unlock(&adev->mm_stats.lock);
 340 }
 341
 342 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 343                                  struct amdgpu_bo *bo)
 344 {
 345         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 346         struct ttm_operation_ctx ctx = {
 347                 .interruptible = true,
 348                 .no_wait_gpu = false,
 349                 .resv = bo->tbo.resv,
 350                 .flags = 0
 351         };
 352         uint32_t domain;
 353         int r;
 354
 355         if (bo->pin_count)
 356                 return 0;
 357
 358         /* Don't move this buffer if we have depleted our allowance
 359          * to move it. Don't move anything if the threshold is zero.
 360          */
 361         if (p->bytes_moved < p->bytes_moved_threshold) {
 362                 if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 363                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 364                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 365                          * visible VRAM if we've depleted our allowance to do
 366                          * that.
 367                          */
 368                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 369                                 domain = bo->preferred_domains;
 370                         else
 371                                 domain = bo->allowed_domains;
 372                 } else {
 373                         domain = bo->preferred_domains;
 374                 }
 375         } else {
 376                 domain = bo->allowed_domains;
 377         }
 378
 379 retry:
 380         amdgpu_ttm_placement_from_domain(bo, domain);
 381         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 382
 383         p->bytes_moved += ctx.bytes_moved;
 384         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 385             amdgpu_bo_in_cpu_visible_vram(bo))
 386                 p->bytes_moved_vis += ctx.bytes_moved;
 387
 388         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 389                 domain = bo->allowed_domains;
 390                 goto retry;
 391         }
 392
 393         return r;
 394 }
 395
 396 /* Last resort, try to evict something from the current working set */
 397 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 398                                 struct amdgpu_bo *validated)
 399 {
 400         uint32_t domain = validated->allowed_domains;
 401         struct ttm_operation_ctx ctx = { true, false };
 402         int r;
 403
 404         if (!p->evictable)
 405                 return false;
 406
 407         for (;&p->evictable->tv.head != &p->validated;
 408              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 409
 410                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 411                 struct amdgpu_bo *bo = candidate->robj;
 412                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 413                 bool update_bytes_moved_vis;
 414                 uint32_t other;
 415
 416                 /* If we reached our current BO we can forget it */
 417                 if (candidate->robj == validated)
 418                         break;
 419
 420                 /* We can't move pinned BOs here */
 421                 if (bo->pin_count)
 422                         continue;
 423
 424                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 425
 426                 /* Check if this BO is in one of the domains we need space for */
 427                 if (!(other & domain))
 428                         continue;
 429
 430                 /* Check if we can move this BO somewhere else */
 431                 other = bo->allowed_domains & ~domain;
 432                 if (!other)
 433                         continue;
 434
 435                 /* Good we can try to move this BO somewhere else */
 436                 update_bytes_moved_vis =
 437                         adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 438                         amdgpu_bo_in_cpu_visible_vram(bo);
 439                 amdgpu_ttm_placement_from_domain(bo, other);
 440                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 441                 p->bytes_moved += ctx.bytes_moved;
 442                 if (update_bytes_moved_vis)
 443                         p->bytes_moved_vis += ctx.bytes_moved;
 444
 445                 if (unlikely(r))
 446                         break;
 447
 448                 p->evictable = list_prev_entry(p->evictable, tv.head);
 449                 list_move(&candidate->tv.head, &p->validated);
 450
 451                 return true;
 452         }
 453
 454         return false;
 455 }
 456
 457 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 458 {
 459         struct amdgpu_cs_parser *p = param;
 460         int r;
 461
 462         do {
 463                 r = amdgpu_cs_bo_validate(p, bo);
 464         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 465         if (r)
 466                 return r;
 467
 468         if (bo->shadow)
 469                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 470
 471         return r;
 472 }
 473
 474 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 475                             struct list_head *validated)
 476 {
 477         struct ttm_operation_ctx ctx = { true, false };
 478         struct amdgpu_bo_list_entry *lobj;
 479         int r;
 480
 481         list_for_each_entry(lobj, validated, tv.head) {
 482                 struct amdgpu_bo *bo = lobj->robj;
 483                 bool binding_userptr = false;
 484                 struct mm_struct *usermm;
 485
 486                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 487                 if (usermm && usermm != current->mm)
 488                         return -EPERM;
 489
 490                 /* Check if we have user pages and nobody bound the BO already */
 491                 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 492                     lobj->user_pages) {
 493                         amdgpu_ttm_placement_from_domain(bo,
 494                                                          AMDGPU_GEM_DOMAIN_CPU);
 495                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 496                         if (r)
 497                                 return r;
 498                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 499                                                      lobj->user_pages);
 500                         binding_userptr = true;
 501                 }
 502
 503                 if (p->evictable == lobj)
 504                         p->evictable = NULL;
 505
 506                 r = amdgpu_cs_validate(p, bo);
 507                 if (r)
 508                         return r;
 509
 510                 if (binding_userptr) {
 511                         kvfree(lobj->user_pages);
 512                         lobj->user_pages = NULL;
 513                 }
 514         }
 515         return 0;
 516 }
 517
 518 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 519                                 union drm_amdgpu_cs *cs)
 520 {
 521         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 522         struct amdgpu_bo_list_entry *e;
 523         struct list_head duplicates;
 524         unsigned i, tries = 10;
 525         struct amdgpu_bo *gds;
 526         struct amdgpu_bo *gws;
 527         struct amdgpu_bo *oa;
 528         int r;
 529
 530         INIT_LIST_HEAD(&p->validated);
 531
 532         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 533         if (p->bo_list) {
 534                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 535                 if (p->bo_list->first_userptr != p->bo_list->num_entries)
 536                         p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
 537         }
 538
 539         INIT_LIST_HEAD(&duplicates);
 540         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 541
 542         if (p->uf_entry.robj && !p->uf_entry.robj->parent)
 543                 list_add(&p->uf_entry.tv.head, &p->validated);
 544
 545         while (1) {
 546                 struct list_head need_pages;
 547                 unsigned i;
 548
 549                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 550                                            &duplicates);
 551                 if (unlikely(r != 0)) {
 552                         if (r != -ERESTARTSYS)
 553                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 554                         goto error_free_pages;
 555                 }
 556
 557                 /* Without a BO list we don't have userptr BOs */
 558                 if (!p->bo_list)
 559                         break;
 560
 561                 INIT_LIST_HEAD(&need_pages);
 562                 for (i = p->bo_list->first_userptr;
 563                      i < p->bo_list->num_entries; ++i) {
 564                         struct amdgpu_bo *bo;
 565
 566                         e = &p->bo_list->array[i];
 567                         bo = e->robj;
 568
 569                         if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
 570                                  &e->user_invalidated) && e->user_pages) {
 571
 572                                 /* We acquired a page array, but somebody
 573                                  * invalidated it. Free it and try again
 574                                  */
 575                                 release_pages(e->user_pages,
 576                                               bo->tbo.ttm->num_pages);
 577                                 kvfree(e->user_pages);
 578                                 e->user_pages = NULL;
 579                         }
 580
 581                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
 582                             !e->user_pages) {
 583                                 list_del(&e->tv.head);
 584                                 list_add(&e->tv.head, &need_pages);
 585
 586                                 amdgpu_bo_unreserve(e->robj);
 587                         }
 588                 }
 589
 590                 if (list_empty(&need_pages))
 591                         break;
 592
 593                 /* Unreserve everything again. */
 594                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 595
 596                 /* We tried too many times, just abort */
 597                 if (!--tries) {
 598                         r = -EDEADLK;
 599                         DRM_ERROR("deadlock in %s\n", __func__);
 600                         goto error_free_pages;
 601                 }
 602
 603                 /* Fill the page arrays for all userptrs. */
 604                 list_for_each_entry(e, &need_pages, tv.head) {
 605                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 606
 607                         e->user_pages = kvmalloc_array(ttm->num_pages,
 608                                                          sizeof(struct page*),
 609                                                          GFP_KERNEL | __GFP_ZERO);
 610                         if (!e->user_pages) {
 611                                 r = -ENOMEM;
 612                                 DRM_ERROR("calloc failure in %s\n", __func__);
 613                                 goto error_free_pages;
 614                         }
 615
 616                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 617                         if (r) {
 618                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 619                                 kvfree(e->user_pages);
 620                                 e->user_pages = NULL;
 621                                 goto error_free_pages;
 622                         }
 623                 }
 624
 625                 /* And try again. */
 626                 list_splice(&need_pages, &p->validated);
 627         }
 628
 629         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 630                                           &p->bytes_moved_vis_threshold);
 631         p->bytes_moved = 0;
 632         p->bytes_moved_vis = 0;
 633         p->evictable = list_last_entry(&p->validated,
 634                                        struct amdgpu_bo_list_entry,
 635                                        tv.head);
 636
 637         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 638                                       amdgpu_cs_validate, p);
 639         if (r) {
 640                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 641                 goto error_validate;
 642         }
 643
 644         r = amdgpu_cs_list_validate(p, &duplicates);
 645         if (r) {
 646                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 647                 goto error_validate;
 648         }
 649
 650         r = amdgpu_cs_list_validate(p, &p->validated);
 651         if (r) {
 652                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 653                 goto error_validate;
 654         }
 655
 656         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 657                                      p->bytes_moved_vis);
 658
 659         if (p->bo_list) {
 660                 struct amdgpu_vm *vm = &fpriv->vm;
 661                 unsigned i;
 662
 663                 gds = p->bo_list->gds_obj;
 664                 gws = p->bo_list->gws_obj;
 665                 oa = p->bo_list->oa_obj;
 666                 for (i = 0; i < p->bo_list->num_entries; i++) {
 667                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 668
 669                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 670                 }
 671         } else {
 672                 gds = p->adev->gds.gds_gfx_bo;
 673                 gws = p->adev->gds.gws_gfx_bo;
 674                 oa = p->adev->gds.oa_gfx_bo;
 675         }
 676
 677         if (gds) {
 678                 p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 679                 p->job->gds_size = amdgpu_bo_size(gds);
 680         }
 681         if (gws) {
 682                 p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 683                 p->job->gws_size = amdgpu_bo_size(gws);
 684         }
 685         if (oa) {
 686                 p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 687                 p->job->oa_size = amdgpu_bo_size(oa);
 688         }
 689
 690         if (!r && p->uf_entry.robj) {
 691                 struct amdgpu_bo *uf = p->uf_entry.robj;
 692
 693                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 694                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 695         }
 696
 697 error_validate:
 698         if (r)
 699                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 700
 701 error_free_pages:
 702
 703         if (p->bo_list) {
 704                 for (i = p->bo_list->first_userptr;
 705                      i < p->bo_list->num_entries; ++i) {
 706                         e = &p->bo_list->array[i];
 707
 708                         if (!e->user_pages)
 709                                 continue;
 710
 711                         release_pages(e->user_pages,
 712                                       e->robj->tbo.ttm->num_pages);
 713                         kvfree(e->user_pages);
 714                 }
 715         }
 716
 717         return r;
 718 }
 719
 720 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 721 {
 722         struct amdgpu_bo_list_entry *e;
 723         int r;
 724
 725         list_for_each_entry(e, &p->validated, tv.head) {
 726                 struct reservation_object *resv = e->robj->tbo.resv;
 727                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
 728                                      amdgpu_bo_explicit_sync(e->robj));
 729
 730                 if (r)
 731                         return r;
 732         }
 733         return 0;
 734 }
 735
 736 /**
 737  * cs_parser_fini() - clean parser states
 738  * @parser:     parser structure holding parsing context.
 739  * @error:      error number
 740  *
 741  * If error is set than unvalidate buffer, otherwise just free memory
 742  * used by parsing context.
 743  **/
 744 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 745                                   bool backoff)
 746 {
 747         unsigned i;
 748
 749         if (error && backoff)
 750                 ttm_eu_backoff_reservation(&parser->ticket,
 751                                            &parser->validated);
 752
 753         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 754                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 755         kfree(parser->post_dep_syncobjs);
 756
 757         dma_fence_put(parser->fence);
 758
 759         if (parser->ctx) {
 760                 mutex_unlock(&parser->ctx->lock);
 761                 amdgpu_ctx_put(parser->ctx);
 762         }
 763         if (parser->bo_list)
 764                 amdgpu_bo_list_put(parser->bo_list);
 765
 766         for (i = 0; i < parser->nchunks; i++)
 767                 kvfree(parser->chunks[i].kdata);
 768         kfree(parser->chunks);
 769         if (parser->job)
 770                 amdgpu_job_free(parser->job);
 771         amdgpu_bo_unref(&parser->uf_entry.robj);
 772 }
 773
 774 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 775 {
 776         struct amdgpu_device *adev = p->adev;
 777         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 778         struct amdgpu_vm *vm = &fpriv->vm;
 779         struct amdgpu_bo_va *bo_va;
 780         struct amdgpu_bo *bo;
 781         int i, r;
 782
 783         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 784         if (r)
 785                 return r;
 786
 787         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 788         if (r)
 789                 return r;
 790
 791         r = amdgpu_sync_fence(adev, &p->job->sync,
 792                               fpriv->prt_va->last_pt_update, false);
 793         if (r)
 794                 return r;
 795
 796         if (amdgpu_sriov_vf(adev)) {
 797                 struct dma_fence *f;
 798
 799                 bo_va = fpriv->csa_va;
 800                 BUG_ON(!bo_va);
 801                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 802                 if (r)
 803                         return r;
 804
 805                 f = bo_va->last_pt_update;
 806                 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 807                 if (r)
 808                         return r;
 809         }
 810
 811         if (p->bo_list) {
 812                 for (i = 0; i < p->bo_list->num_entries; i++) {
 813                         struct dma_fence *f;
 814
 815                         /* ignore duplicates */
 816                         bo = p->bo_list->array[i].robj;
 817                         if (!bo)
 818                                 continue;
 819
 820                         bo_va = p->bo_list->array[i].bo_va;
 821                         if (bo_va == NULL)
 822                                 continue;
 823
 824                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 825                         if (r)
 826                                 return r;
 827
 828                         f = bo_va->last_pt_update;
 829                         r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
 830                         if (r)
 831                                 return r;
 832                 }
 833
 834         }
 835
 836         r = amdgpu_vm_handle_moved(adev, vm);
 837         if (r)
 838                 return r;
 839
 840         r = amdgpu_vm_update_directories(adev, vm);
 841         if (r)
 842                 return r;
 843
 844         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
 845         if (r)
 846                 return r;
 847
 848         if (amdgpu_vm_debug && p->bo_list) {
 849                 /* Invalidate all BOs to test for userspace bugs */
 850                 for (i = 0; i < p->bo_list->num_entries; i++) {
 851                         /* ignore duplicates */
 852                         bo = p->bo_list->array[i].robj;
 853                         if (!bo)
 854                                 continue;
 855
 856                         amdgpu_vm_bo_invalidate(adev, bo, false);
 857                 }
 858         }
 859
 860         return r;
 861 }
 862
 863 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 864                                  struct amdgpu_cs_parser *p)
 865 {
 866         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 867         struct amdgpu_vm *vm = &fpriv->vm;
 868         struct amdgpu_ring *ring = p->job->ring;
 869         int r;
 870
 871         /* Only for UVD/VCE VM emulation */
 872         if (p->job->ring->funcs->parse_cs) {
 873                 unsigned i, j;
 874
 875                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 876                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 877                         struct amdgpu_bo_va_mapping *m;
 878                         struct amdgpu_bo *aobj = NULL;
 879                         struct amdgpu_cs_chunk *chunk;
 880                         uint64_t offset, va_start;
 881                         struct amdgpu_ib *ib;
 882                         uint8_t *kptr;
 883
 884                         chunk = &p->chunks[i];
 885                         ib = &p->job->ibs[j];
 886                         chunk_ib = chunk->kdata;
 887
 888                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 889                                 continue;
 890
 891                         va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
 892                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 893                         if (r) {
 894                                 DRM_ERROR("IB va_start is invalid\n");
 895                                 return r;
 896                         }
 897
 898                         if ((va_start + chunk_ib->ib_bytes) >
 899                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 900                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 901                                 return -EINVAL;
 902                         }
 903
 904                         /* the IB should be reserved at this point */
 905                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 906                         if (r) {
 907                                 return r;
 908                         }
 909
 910                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 911                         kptr += va_start - offset;
 912
 913                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 914                         amdgpu_bo_kunmap(aobj);
 915
 916                         r = amdgpu_ring_parse_cs(ring, p, j);
 917                         if (r)
 918                                 return r;
 919
 920                         j++;
 921                 }
 922         }
 923
 924         if (p->job->vm) {
 925                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
 926
 927                 r = amdgpu_bo_vm_update_pte(p);
 928                 if (r)
 929                         return r;
 930         }
 931
 932         return amdgpu_cs_sync_rings(p);
 933 }
 934
 935 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 936                              struct amdgpu_cs_parser *parser)
 937 {
 938         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 939         struct amdgpu_vm *vm = &fpriv->vm;
 940         int i, j;
 941         int r, ce_preempt = 0, de_preempt = 0;
 942
 943         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 944                 struct amdgpu_cs_chunk *chunk;
 945                 struct amdgpu_ib *ib;
 946                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 947                 struct amdgpu_ring *ring;
 948
 949                 chunk = &parser->chunks[i];
 950                 ib = &parser->job->ibs[j];
 951                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 952
 953                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 954                         continue;
 955
 956                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 957                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 958                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 959                                         ce_preempt++;
 960                                 else
 961                                         de_preempt++;
 962                         }
 963
 964                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 965                         if (ce_preempt > 1 || de_preempt > 1)
 966                                 return -EINVAL;
 967                 }
 968
 969                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
 970                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
 971                 if (r)
 972                         return r;
 973
 974                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 975                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 976                         if (!parser->ctx->preamble_presented) {
 977                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 978                                 parser->ctx->preamble_presented = true;
 979                         }
 980                 }
 981
 982                 if (parser->job->ring && parser->job->ring != ring)
 983                         return -EINVAL;
 984
 985                 parser->job->ring = ring;
 986
 987                 r =  amdgpu_ib_get(adev, vm,
 988                                         ring->funcs->parse_cs ? chunk_ib->ib_bytes : 0,
 989                                         ib);
 990                 if (r) {
 991                         DRM_ERROR("Failed to get ib !\n");
 992                         return r;
 993                 }
 994
 995                 ib->gpu_addr = chunk_ib->va_start;
 996                 ib->length_dw = chunk_ib->ib_bytes / 4;
 997                 ib->flags = chunk_ib->flags;
 998
 999                 j++;
1000         }
1001
1002         /* UVD & VCE fw doesn't support user fences */
1003         if (parser->job->uf_addr && (
1004             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
1005             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1006                 return -EINVAL;
1007
1008         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->job->ring->idx);
1009 }
1010
1011 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1012                                        struct amdgpu_cs_chunk *chunk)
1013 {
1014         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1015         unsigned num_deps;
1016         int i, r;
1017         struct drm_amdgpu_cs_chunk_dep *deps;
1018
1019         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1020         num_deps = chunk->length_dw * 4 /
1021                 sizeof(struct drm_amdgpu_cs_chunk_dep);
1022
1023         for (i = 0; i < num_deps; ++i) {
1024                 struct amdgpu_ring *ring;
1025                 struct amdgpu_ctx *ctx;
1026                 struct dma_fence *fence;
1027
1028                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1029                 if (ctx == NULL)
1030                         return -EINVAL;
1031
1032                 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1033                                          deps[i].ip_type,
1034                                          deps[i].ip_instance,
1035                                          deps[i].ring, &ring);
1036                 if (r) {
1037                         amdgpu_ctx_put(ctx);
1038                         return r;
1039                 }
1040
1041                 fence = amdgpu_ctx_get_fence(ctx, ring,
1042                                              deps[i].handle);
1043                 if (IS_ERR(fence)) {
1044                         r = PTR_ERR(fence);
1045                         amdgpu_ctx_put(ctx);
1046                         return r;
1047                 } else if (fence) {
1048                         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1049                                         true);
1050                         dma_fence_put(fence);
1051                         amdgpu_ctx_put(ctx);
1052                         if (r)
1053                                 return r;
1054                 }
1055         }
1056         return 0;
1057 }
1058
1059 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1060                                                  uint32_t handle)
1061 {
1062         int r;
1063         struct dma_fence *fence;
1064         r = drm_syncobj_find_fence(p->filp, handle, &fence);
1065         if (r)
1066                 return r;
1067
1068         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1069         dma_fence_put(fence);
1070
1071         return r;
1072 }
1073
1074 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1075                                             struct amdgpu_cs_chunk *chunk)
1076 {
1077         unsigned num_deps;
1078         int i, r;
1079         struct drm_amdgpu_cs_chunk_sem *deps;
1080
1081         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1082         num_deps = chunk->length_dw * 4 /
1083                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1084
1085         for (i = 0; i < num_deps; ++i) {
1086                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1087                 if (r)
1088                         return r;
1089         }
1090         return 0;
1091 }
1092
1093 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1094                                              struct amdgpu_cs_chunk *chunk)
1095 {
1096         unsigned num_deps;
1097         int i;
1098         struct drm_amdgpu_cs_chunk_sem *deps;
1099         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1100         num_deps = chunk->length_dw * 4 /
1101                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1102
1103         p->post_dep_syncobjs = kmalloc_array(num_deps,
1104                                              sizeof(struct drm_syncobj *),
1105                                              GFP_KERNEL);
1106         p->num_post_dep_syncobjs = 0;
1107
1108         if (!p->post_dep_syncobjs)
1109                 return -ENOMEM;
1110
1111         for (i = 0; i < num_deps; ++i) {
1112                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1113                 if (!p->post_dep_syncobjs[i])
1114                         return -EINVAL;
1115                 p->num_post_dep_syncobjs++;
1116         }
1117         return 0;
1118 }
1119
1120 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1121                                   struct amdgpu_cs_parser *p)
1122 {
1123         int i, r;
1124
1125         for (i = 0; i < p->nchunks; ++i) {
1126                 struct amdgpu_cs_chunk *chunk;
1127
1128                 chunk = &p->chunks[i];
1129
1130                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1131                         r = amdgpu_cs_process_fence_dep(p, chunk);
1132                         if (r)
1133                                 return r;
1134                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1135                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1136                         if (r)
1137                                 return r;
1138                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1139                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1140                         if (r)
1141                                 return r;
1142                 }
1143         }
1144
1145         return 0;
1146 }
1147
1148 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1149 {
1150         int i;
1151
1152         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1153                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1154 }
1155
1156 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1157                             union drm_amdgpu_cs *cs)
1158 {
1159         struct amdgpu_ring *ring = p->job->ring;
1160         struct drm_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1161         struct amdgpu_job *job;
1162         unsigned i;
1163         uint64_t seq;
1164
1165         int r;
1166
1167         amdgpu_mn_lock(p->mn);
1168         if (p->bo_list) {
1169                 for (i = p->bo_list->first_userptr;
1170                      i < p->bo_list->num_entries; ++i) {
1171                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
1172
1173                         if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1174                                 amdgpu_mn_unlock(p->mn);
1175                                 return -ERESTARTSYS;
1176                         }
1177                 }
1178         }
1179
1180         job = p->job;
1181         p->job = NULL;
1182
1183         r = drm_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1184         if (r) {
1185                 amdgpu_job_free(job);
1186                 amdgpu_mn_unlock(p->mn);
1187                 return r;
1188         }
1189
1190         job->owner = p->filp;
1191         job->fence_ctx = entity->fence_context;
1192         p->fence = dma_fence_get(&job->base.s_fence->finished);
1193
1194         r = amdgpu_ctx_add_fence(p->ctx, ring, p->fence, &seq);
1195         if (r) {
1196                 dma_fence_put(p->fence);
1197                 dma_fence_put(&job->base.s_fence->finished);
1198                 amdgpu_job_free(job);
1199                 amdgpu_mn_unlock(p->mn);
1200                 return r;
1201         }
1202
1203         amdgpu_cs_post_dependencies(p);
1204
1205         cs->out.handle = seq;
1206         job->uf_sequence = seq;
1207
1208         amdgpu_job_free_resources(job);
1209         amdgpu_ring_priority_get(job->ring, job->base.s_priority);
1210
1211         trace_amdgpu_cs_ioctl(job);
1212         drm_sched_entity_push_job(&job->base, entity);
1213
1214         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1215         amdgpu_mn_unlock(p->mn);
1216
1217         return 0;
1218 }
1219
1220 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1221 {
1222         struct amdgpu_device *adev = dev->dev_private;
1223         union drm_amdgpu_cs *cs = data;
1224         struct amdgpu_cs_parser parser = {};
1225         bool reserved_buffers = false;
1226         int i, r;
1227
1228         if (!adev->accel_working)
1229                 return -EBUSY;
1230
1231         parser.adev = adev;
1232         parser.filp = filp;
1233
1234         r = amdgpu_cs_parser_init(&parser, data);
1235         if (r) {
1236                 DRM_ERROR("Failed to initialize parser !\n");
1237                 goto out;
1238         }
1239
1240         r = amdgpu_cs_ib_fill(adev, &parser);
1241         if (r)
1242                 goto out;
1243
1244         r = amdgpu_cs_parser_bos(&parser, data);
1245         if (r) {
1246                 if (r == -ENOMEM)
1247                         DRM_ERROR("Not enough memory for command submission!\n");
1248                 else if (r != -ERESTARTSYS)
1249                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1250                 goto out;
1251         }
1252
1253         reserved_buffers = true;
1254
1255         r = amdgpu_cs_dependencies(adev, &parser);
1256         if (r) {
1257                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1258                 goto out;
1259         }
1260
1261         for (i = 0; i < parser.job->num_ibs; i++)
1262                 trace_amdgpu_cs(&parser, i);
1263
1264         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1265         if (r)
1266                 goto out;
1267
1268         r = amdgpu_cs_submit(&parser, cs);
1269
1270 out:
1271         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1272         return r;
1273 }
1274
1275 /**
1276  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1277  *
1278  * @dev: drm device
1279  * @data: data from userspace
1280  * @filp: file private
1281  *
1282  * Wait for the command submission identified by handle to finish.
1283  */
1284 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1285                          struct drm_file *filp)
1286 {
1287         union drm_amdgpu_wait_cs *wait = data;
1288         struct amdgpu_device *adev = dev->dev_private;
1289         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1290         struct amdgpu_ring *ring = NULL;
1291         struct amdgpu_ctx *ctx;
1292         struct dma_fence *fence;
1293         long r;
1294
1295         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1296         if (ctx == NULL)
1297                 return -EINVAL;
1298
1299         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1300                                  wait->in.ip_type, wait->in.ip_instance,
1301                                  wait->in.ring, &ring);
1302         if (r) {
1303                 amdgpu_ctx_put(ctx);
1304                 return r;
1305         }
1306
1307         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1308         if (IS_ERR(fence))
1309                 r = PTR_ERR(fence);
1310         else if (fence) {
1311                 r = dma_fence_wait_timeout(fence, true, timeout);
1312                 if (r > 0 && fence->error)
1313                         r = fence->error;
1314                 dma_fence_put(fence);
1315         } else
1316                 r = 1;
1317
1318         amdgpu_ctx_put(ctx);
1319         if (r < 0)
1320                 return r;
1321
1322         memset(wait, 0, sizeof(*wait));
1323         wait->out.status = (r == 0);
1324
1325         return 0;
1326 }
1327
1328 /**
1329  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1330  *
1331  * @adev: amdgpu device
1332  * @filp: file private
1333  * @user: drm_amdgpu_fence copied from user space
1334  */
1335 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1336                                              struct drm_file *filp,
1337                                              struct drm_amdgpu_fence *user)
1338 {
1339         struct amdgpu_ring *ring;
1340         struct amdgpu_ctx *ctx;
1341         struct dma_fence *fence;
1342         int r;
1343
1344         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1345         if (ctx == NULL)
1346                 return ERR_PTR(-EINVAL);
1347
1348         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1349                                  user->ip_instance, user->ring, &ring);
1350         if (r) {
1351                 amdgpu_ctx_put(ctx);
1352                 return ERR_PTR(r);
1353         }
1354
1355         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1356         amdgpu_ctx_put(ctx);
1357
1358         return fence;
1359 }
1360
1361 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1362                                     struct drm_file *filp)
1363 {
1364         struct amdgpu_device *adev = dev->dev_private;
1365         union drm_amdgpu_fence_to_handle *info = data;
1366         struct dma_fence *fence;
1367         struct drm_syncobj *syncobj;
1368         struct sync_file *sync_file;
1369         int fd, r;
1370
1371         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1372         if (IS_ERR(fence))
1373                 return PTR_ERR(fence);
1374
1375         switch (info->in.what) {
1376         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1377                 r = drm_syncobj_create(&syncobj, 0, fence);
1378                 dma_fence_put(fence);
1379                 if (r)
1380                         return r;
1381                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1382                 drm_syncobj_put(syncobj);
1383                 return r;
1384
1385         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1386                 r = drm_syncobj_create(&syncobj, 0, fence);
1387                 dma_fence_put(fence);
1388                 if (r)
1389                         return r;
1390                 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1391                 drm_syncobj_put(syncobj);
1392                 return r;
1393
1394         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1395                 fd = get_unused_fd_flags(O_CLOEXEC);
1396                 if (fd < 0) {
1397                         dma_fence_put(fence);
1398                         return fd;
1399                 }
1400
1401                 sync_file = sync_file_create(fence);
1402                 dma_fence_put(fence);
1403                 if (!sync_file) {
1404                         put_unused_fd(fd);
1405                         return -ENOMEM;
1406                 }
1407
1408                 fd_install(fd, sync_file->file);
1409                 info->out.handle = fd;
1410                 return 0;
1411
1412         default:
1413                 return -EINVAL;
1414         }
1415 }
1416
1417 /**
1418  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1419  *
1420  * @adev: amdgpu device
1421  * @filp: file private
1422  * @wait: wait parameters
1423  * @fences: array of drm_amdgpu_fence
1424  */
1425 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1426                                      struct drm_file *filp,
1427                                      union drm_amdgpu_wait_fences *wait,
1428                                      struct drm_amdgpu_fence *fences)
1429 {
1430         uint32_t fence_count = wait->in.fence_count;
1431         unsigned int i;
1432         long r = 1;
1433
1434         for (i = 0; i < fence_count; i++) {
1435                 struct dma_fence *fence;
1436                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1437
1438                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1439                 if (IS_ERR(fence))
1440                         return PTR_ERR(fence);
1441                 else if (!fence)
1442                         continue;
1443
1444                 r = dma_fence_wait_timeout(fence, true, timeout);
1445                 dma_fence_put(fence);
1446                 if (r < 0)
1447                         return r;
1448
1449                 if (r == 0)
1450                         break;
1451
1452                 if (fence->error)
1453                         return fence->error;
1454         }
1455
1456         memset(wait, 0, sizeof(*wait));
1457         wait->out.status = (r > 0);
1458
1459         return 0;
1460 }
1461
1462 /**
1463  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1464  *
1465  * @adev: amdgpu device
1466  * @filp: file private
1467  * @wait: wait parameters
1468  * @fences: array of drm_amdgpu_fence
1469  */
1470 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1471                                     struct drm_file *filp,
1472                                     union drm_amdgpu_wait_fences *wait,
1473                                     struct drm_amdgpu_fence *fences)
1474 {
1475         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1476         uint32_t fence_count = wait->in.fence_count;
1477         uint32_t first = ~0;
1478         struct dma_fence **array;
1479         unsigned int i;
1480         long r;
1481
1482         /* Prepare the fence array */
1483         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1484
1485         if (array == NULL)
1486                 return -ENOMEM;
1487
1488         for (i = 0; i < fence_count; i++) {
1489                 struct dma_fence *fence;
1490
1491                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1492                 if (IS_ERR(fence)) {
1493                         r = PTR_ERR(fence);
1494                         goto err_free_fence_array;
1495                 } else if (fence) {
1496                         array[i] = fence;
1497                 } else { /* NULL, the fence has been already signaled */
1498                         r = 1;
1499                         first = i;
1500                         goto out;
1501                 }
1502         }
1503
1504         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1505                                        &first);
1506         if (r < 0)
1507                 goto err_free_fence_array;
1508
1509 out:
1510         memset(wait, 0, sizeof(*wait));
1511         wait->out.status = (r > 0);
1512         wait->out.first_signaled = first;
1513
1514         if (first < fence_count && array[first])
1515                 r = array[first]->error;
1516         else
1517                 r = 0;
1518
1519 err_free_fence_array:
1520         for (i = 0; i < fence_count; i++)
1521                 dma_fence_put(array[i]);
1522         kfree(array);
1523
1524         return r;
1525 }
1526
1527 /**
1528  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1529  *
1530  * @dev: drm device
1531  * @data: data from userspace
1532  * @filp: file private
1533  */
1534 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1535                                 struct drm_file *filp)
1536 {
1537         struct amdgpu_device *adev = dev->dev_private;
1538         union drm_amdgpu_wait_fences *wait = data;
1539         uint32_t fence_count = wait->in.fence_count;
1540         struct drm_amdgpu_fence *fences_user;
1541         struct drm_amdgpu_fence *fences;
1542         int r;
1543
1544         /* Get the fences from userspace */
1545         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1546                         GFP_KERNEL);
1547         if (fences == NULL)
1548                 return -ENOMEM;
1549
1550         fences_user = u64_to_user_ptr(wait->in.fences);
1551         if (copy_from_user(fences, fences_user,
1552                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1553                 r = -EFAULT;
1554                 goto err_free_fences;
1555         }
1556
1557         if (wait->in.wait_all)
1558                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1559         else
1560                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1561
1562 err_free_fences:
1563         kfree(fences);
1564
1565         return r;
1566 }
1567
1568 /**
1569  * amdgpu_cs_find_bo_va - find bo_va for VM address
1570  *
1571  * @parser: command submission parser context
1572  * @addr: VM address
1573  * @bo: resulting BO of the mapping found
1574  *
1575  * Search the buffer objects in the command submission context for a certain
1576  * virtual memory address. Returns allocation structure when found, NULL
1577  * otherwise.
1578  */
1579 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1580                            uint64_t addr, struct amdgpu_bo **bo,
1581                            struct amdgpu_bo_va_mapping **map)
1582 {
1583         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1584         struct ttm_operation_ctx ctx = { false, false };
1585         struct amdgpu_vm *vm = &fpriv->vm;
1586         struct amdgpu_bo_va_mapping *mapping;
1587         int r;
1588
1589         addr /= AMDGPU_GPU_PAGE_SIZE;
1590
1591         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1592         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1593                 return -EINVAL;
1594
1595         *bo = mapping->bo_va->base.bo;
1596         *map = mapping;
1597
1598         /* Double check that the BO is reserved by this CS */
1599         if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1600                 return -EINVAL;
1601
1602         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1603                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1604                 amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
1605                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1606                 if (r)
1607                         return r;
1608         }
1609
1610         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1611 }