drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <linux/pci.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/gcd.h>
  30
  31 #include <asm/div64.h>
  32
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_device.h>
  35 #include <drm/drm_drv.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_fourcc.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_plane_helper.h>
  41 #include <drm/drm_probe_helper.h>
  42 #include <drm/drm_vblank.h>
  43 #include <drm/radeon_drm.h>
  44
  45 #include "atom.h"
  46 #include "radeon.h"
  47
  48 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
  49 int radeon_enable_vblank_kms(struct drm_crtc *crtc);
  50 void radeon_disable_vblank_kms(struct drm_crtc *crtc);
  51
  52 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  53 {
  54         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  55         struct drm_device *dev = crtc->dev;
  56         struct radeon_device *rdev = dev->dev_private;
  57         u16 *r, *g, *b;
  58         int i;
  59
  60         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  61         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  62
  63         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  64         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  65         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  66
  67         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  68         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  69         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  70
  71         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  72         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  73         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  74
  75         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  76         r = crtc->gamma_store;
  77         g = r + crtc->gamma_size;
  78         b = g + crtc->gamma_size;
  79         for (i = 0; i < 256; i++) {
  80                 WREG32(AVIVO_DC_LUT_30_COLOR,
  81                        ((*r++ & 0xffc0) << 14) |
  82                        ((*g++ & 0xffc0) << 4) |
  83                        (*b++ >> 6));
  84         }
  85
  86         /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
  87         WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);
  88 }
  89
  90 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  91 {
  92         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  93         struct drm_device *dev = crtc->dev;
  94         struct radeon_device *rdev = dev->dev_private;
  95         u16 *r, *g, *b;
  96         int i;
  97
  98         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  99         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 100
 101         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 102         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 103         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 104
 105         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 106         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 107         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 108
 109         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 110         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 111
 112         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 113         r = crtc->gamma_store;
 114         g = r + crtc->gamma_size;
 115         b = g + crtc->gamma_size;
 116         for (i = 0; i < 256; i++) {
 117                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 118                        ((*r++ & 0xffc0) << 14) |
 119                        ((*g++ & 0xffc0) << 4) |
 120                        (*b++ >> 6));
 121         }
 122 }
 123
 124 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 125 {
 126         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 127         struct drm_device *dev = crtc->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129         u16 *r, *g, *b;
 130         int i;
 131
 132         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 133
 134         msleep(10);
 135
 136         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 137                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 138                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 139         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 140                NI_GRPH_PRESCALE_BYPASS);
 141         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 142                NI_OVL_PRESCALE_BYPASS);
 143         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 144                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 145                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 146
 147         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 148
 149         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 150         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 151         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 152
 153         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 154         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 155         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 156
 157         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 158         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 159
 160         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 161         r = crtc->gamma_store;
 162         g = r + crtc->gamma_size;
 163         b = g + crtc->gamma_size;
 164         for (i = 0; i < 256; i++) {
 165                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 166                        ((*r++ & 0xffc0) << 14) |
 167                        ((*g++ & 0xffc0) << 4) |
 168                        (*b++ >> 6));
 169         }
 170
 171         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 172                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 173                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 174                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 175                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 176         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 177                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 178                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 179         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 180                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 181                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 182         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 183                (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |
 184                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 185         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 186         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 187         if (ASIC_IS_DCE8(rdev)) {
 188                 /* XXX this only needs to be programmed once per crtc at startup,
 189                  * not sure where the best place for it is
 190                  */
 191                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 192                        CIK_CURSOR_ALPHA_BLND_ENA);
 193         }
 194 }
 195
 196 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 197 {
 198         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 199         struct drm_device *dev = crtc->dev;
 200         struct radeon_device *rdev = dev->dev_private;
 201         u16 *r, *g, *b;
 202         int i;
 203         uint32_t dac2_cntl;
 204
 205         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 206         if (radeon_crtc->crtc_id == 0)
 207                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 208         else
 209                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 210         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 211
 212         WREG8(RADEON_PALETTE_INDEX, 0);
 213         r = crtc->gamma_store;
 214         g = r + crtc->gamma_size;
 215         b = g + crtc->gamma_size;
 216         for (i = 0; i < 256; i++) {
 217                 WREG32(RADEON_PALETTE_30_DATA,
 218                        ((*r++ & 0xffc0) << 14) |
 219                        ((*g++ & 0xffc0) << 4) |
 220                        (*b++ >> 6));
 221         }
 222 }
 223
 224 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 225 {
 226         struct drm_device *dev = crtc->dev;
 227         struct radeon_device *rdev = dev->dev_private;
 228
 229         if (!crtc->enabled)
 230                 return;
 231
 232         if (ASIC_IS_DCE5(rdev))
 233                 dce5_crtc_load_lut(crtc);
 234         else if (ASIC_IS_DCE4(rdev))
 235                 dce4_crtc_load_lut(crtc);
 236         else if (ASIC_IS_AVIVO(rdev))
 237                 avivo_crtc_load_lut(crtc);
 238         else
 239                 legacy_crtc_load_lut(crtc);
 240 }
 241
 242 static int radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 243                                  u16 *blue, uint32_t size,
 244                                  struct drm_modeset_acquire_ctx *ctx)
 245 {
 246         radeon_crtc_load_lut(crtc);
 247
 248         return 0;
 249 }
 250
 251 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 252 {
 253         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 254
 255         drm_crtc_cleanup(crtc);
 256         destroy_workqueue(radeon_crtc->flip_queue);
 257         kfree(radeon_crtc);
 258 }
 259
 260 /**
 261  * radeon_unpin_work_func - unpin old buffer object
 262  *
 263  * @__work - kernel work item
 264  *
 265  * Unpin the old frame buffer object outside of the interrupt handler
 266  */
 267 static void radeon_unpin_work_func(struct work_struct *__work)
 268 {
 269         struct radeon_flip_work *work =
 270                 container_of(__work, struct radeon_flip_work, unpin_work);
 271         int r;
 272
 273         /* unpin of the old buffer */
 274         r = radeon_bo_reserve(work->old_rbo, false);
 275         if (likely(r == 0)) {
 276                 r = radeon_bo_unpin(work->old_rbo);
 277                 if (unlikely(r != 0)) {
 278                         DRM_ERROR("failed to unpin buffer after flip\n");
 279                 }
 280                 radeon_bo_unreserve(work->old_rbo);
 281         } else
 282                 DRM_ERROR("failed to reserve buffer after flip\n");
 283
 284         drm_gem_object_put_unlocked(&work->old_rbo->tbo.base);
 285         kfree(work);
 286 }
 287
 288 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id)
 289 {
 290         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 291         unsigned long flags;
 292         u32 update_pending;
 293         int vpos, hpos;
 294
 295         /* can happen during initialization */
 296         if (radeon_crtc == NULL)
 297                 return;
 298
 299         /* Skip the pageflip completion check below (based on polling) on
 300          * asics which reliably support hw pageflip completion irqs. pflip
 301          * irqs are a reliable and race-free method of handling pageflip
 302          * completion detection. A use_pflipirq module parameter < 2 allows
 303          * to override this in case of asics with faulty pflip irqs.
 304          * A module parameter of 0 would only use this polling based path,
 305          * a parameter of 1 would use pflip irq only as a backup to this
 306          * path, as in Linux 3.16.
 307          */
 308         if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev))
 309                 return;
 310
 311         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 312         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 313                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 314                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 315                                  radeon_crtc->flip_status,
 316                                  RADEON_FLIP_SUBMITTED);
 317                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 318                 return;
 319         }
 320
 321         update_pending = radeon_page_flip_pending(rdev, crtc_id);
 322
 323         /* Has the pageflip already completed in crtc, or is it certain
 324          * to complete in this vblank? GET_DISTANCE_TO_VBLANKSTART provides
 325          * distance to start of "fudged earlier" vblank in vpos, distance to
 326          * start of real vblank in hpos. vpos >= 0 && hpos < 0 means we are in
 327          * the last few scanlines before start of real vblank, where the vblank
 328          * irq can fire, so we have sampled update_pending a bit too early and
 329          * know the flip will complete at leading edge of the upcoming real
 330          * vblank. On pre-AVIVO hardware, flips also complete inside the real
 331          * vblank, not only at leading edge, so if update_pending for hpos >= 0
 332          *  == inside real vblank, the flip will complete almost immediately.
 333          * Note that this method of completion handling is still not 100% race
 334          * free, as we could execute before the radeon_flip_work_func managed
 335          * to run and set the RADEON_FLIP_SUBMITTED status, thereby we no-op,
 336          * but the flip still gets programmed into hw and completed during
 337          * vblank, leading to a delayed emission of the flip completion event.
 338          * This applies at least to pre-AVIVO hardware, where flips are always
 339          * completing inside vblank, not only at leading edge of vblank.
 340          */
 341         if (update_pending &&
 342             (DRM_SCANOUTPOS_VALID &
 343              radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 344                                         GET_DISTANCE_TO_VBLANKSTART,
 345                                         &vpos, &hpos, NULL, NULL,
 346                                         &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) &&
 347             ((vpos >= 0 && hpos < 0) || (hpos >= 0 && !ASIC_IS_AVIVO(rdev)))) {
 348                 /* crtc didn't flip in this target vblank interval,
 349                  * but flip is pending in crtc. Based on the current
 350                  * scanout position we know that the current frame is
 351                  * (nearly) complete and the flip will (likely)
 352                  * complete before the start of the next frame.
 353                  */
 354                 update_pending = 0;
 355         }
 356         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 357         if (!update_pending)
 358                 radeon_crtc_handle_flip(rdev, crtc_id);
 359 }
 360
 361 /**
 362  * radeon_crtc_handle_flip - page flip completed
 363  *
 364  * @rdev: radeon device pointer
 365  * @crtc_id: crtc number this event is for
 366  *
 367  * Called when we are sure that a page flip for this crtc is completed.
 368  */
 369 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 370 {
 371         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 372         struct radeon_flip_work *work;
 373         unsigned long flags;
 374
 375         /* this can happen at init */
 376         if (radeon_crtc == NULL)
 377                 return;
 378
 379         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 380         work = radeon_crtc->flip_work;
 381         if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {
 382                 DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != "
 383                                  "RADEON_FLIP_SUBMITTED(%d)\n",
 384                                  radeon_crtc->flip_status,
 385                                  RADEON_FLIP_SUBMITTED);
 386                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 387                 return;
 388         }
 389
 390         /* Pageflip completed. Clean up. */
 391         radeon_crtc->flip_status = RADEON_FLIP_NONE;
 392         radeon_crtc->flip_work = NULL;
 393
 394         /* wakeup userspace */
 395         if (work->event)
 396                 drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);
 397
 398         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 399
 400         drm_crtc_vblank_put(&radeon_crtc->base);
 401         radeon_irq_kms_pflip_irq_put(rdev, work->crtc_id);
 402         queue_work(radeon_crtc->flip_queue, &work->unpin_work);
 403 }
 404
 405 /**
 406  * radeon_flip_work_func - page flip framebuffer
 407  *
 408  * @work - kernel work item
 409  *
 410  * Wait for the buffer object to become idle and do the actual page flip
 411  */
 412 static void radeon_flip_work_func(struct work_struct *__work)
 413 {
 414         struct radeon_flip_work *work =
 415                 container_of(__work, struct radeon_flip_work, flip_work);
 416         struct radeon_device *rdev = work->rdev;
 417         struct drm_device *dev = rdev->ddev;
 418         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];
 419
 420         struct drm_crtc *crtc = &radeon_crtc->base;
 421         unsigned long flags;
 422         int r;
 423         int vpos, hpos;
 424
 425         down_read(&rdev->exclusive_lock);
 426         if (work->fence) {
 427                 struct radeon_fence *fence;
 428
 429                 fence = to_radeon_fence(work->fence);
 430                 if (fence && fence->rdev == rdev) {
 431                         r = radeon_fence_wait(fence, false);
 432                         if (r == -EDEADLK) {
 433                                 up_read(&rdev->exclusive_lock);
 434                                 do {
 435                                         r = radeon_gpu_reset(rdev);
 436                                 } while (r == -EAGAIN);
 437                                 down_read(&rdev->exclusive_lock);
 438                         }
 439                 } else
 440                         r = dma_fence_wait(work->fence, false);
 441
 442                 if (r)
 443                         DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
 444
 445                 /* We continue with the page flip even if we failed to wait on
 446                  * the fence, otherwise the DRM core and userspace will be
 447                  * confused about which BO the CRTC is scanning out
 448                  */
 449
 450                 dma_fence_put(work->fence);
 451                 work->fence = NULL;
 452         }
 453
 454         /* Wait until we're out of the vertical blank period before the one
 455          * targeted by the flip. Always wait on pre DCE4 to avoid races with
 456          * flip completion handling from vblank irq, as these old asics don't
 457          * have reliable pageflip completion interrupts.
 458          */
 459         while (radeon_crtc->enabled &&
 460                 (radeon_get_crtc_scanoutpos(dev, work->crtc_id, 0,
 461                                             &vpos, &hpos, NULL, NULL,
 462                                             &crtc->hwmode)
 463                 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 464                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 465                 (!ASIC_IS_AVIVO(rdev) ||
 466                 ((int) (work->target_vblank -
 467                 crtc->funcs->get_vblank_counter(crtc)) > 0)))
 468                 usleep_range(1000, 2000);
 469
 470         /* We borrow the event spin lock for protecting flip_status */
 471         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 472
 473         /* set the proper interrupt */
 474         radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);
 475
 476         /* do the flip (mmio) */
 477         radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);
 478
 479         radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;
 480         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 481         up_read(&rdev->exclusive_lock);
 482 }
 483
 484 static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
 485                                         struct drm_framebuffer *fb,
 486                                         struct drm_pending_vblank_event *event,
 487                                         uint32_t page_flip_flags,
 488                                         uint32_t target,
 489                                         struct drm_modeset_acquire_ctx *ctx)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         struct radeon_device *rdev = dev->dev_private;
 493         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 494         struct drm_gem_object *obj;
 495         struct radeon_flip_work *work;
 496         struct radeon_bo *new_rbo;
 497         uint32_t tiling_flags, pitch_pixels;
 498         uint64_t base;
 499         unsigned long flags;
 500         int r;
 501
 502         work = kzalloc(sizeof *work, GFP_KERNEL);
 503         if (work == NULL)
 504                 return -ENOMEM;
 505
 506         INIT_WORK(&work->flip_work, radeon_flip_work_func);
 507         INIT_WORK(&work->unpin_work, radeon_unpin_work_func);
 508
 509         work->rdev = rdev;
 510         work->crtc_id = radeon_crtc->crtc_id;
 511         work->event = event;
 512         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 513
 514         /* schedule unpin of the old buffer */
 515         obj = crtc->primary->fb->obj[0];
 516
 517         /* take a reference to the old object */
 518         drm_gem_object_get(obj);
 519         work->old_rbo = gem_to_radeon_bo(obj);
 520
 521         obj = fb->obj[0];
 522         new_rbo = gem_to_radeon_bo(obj);
 523
 524         /* pin the new buffer */
 525         DRM_DEBUG_DRIVER("flip-ioctl() cur_rbo = %p, new_rbo = %p\n",
 526                          work->old_rbo, new_rbo);
 527
 528         r = radeon_bo_reserve(new_rbo, false);
 529         if (unlikely(r != 0)) {
 530                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 531                 goto cleanup;
 532         }
 533         /* Only 27 bit offset for legacy CRTC */
 534         r = radeon_bo_pin_restricted(new_rbo, RADEON_GEM_DOMAIN_VRAM,
 535                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 536         if (unlikely(r != 0)) {
 537                 radeon_bo_unreserve(new_rbo);
 538                 r = -EINVAL;
 539                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 540                 goto cleanup;
 541         }
 542         work->fence = dma_fence_get(dma_resv_get_excl(new_rbo->tbo.base.resv));
 543         radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
 544         radeon_bo_unreserve(new_rbo);
 545
 546         if (!ASIC_IS_AVIVO(rdev)) {
 547                 /* crtc offset is from display base addr not FB location */
 548                 base -= radeon_crtc->legacy_display_base_addr;
 549                 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
 550
 551                 if (tiling_flags & RADEON_TILING_MACRO) {
 552                         if (ASIC_IS_R300(rdev)) {
 553                                 base &= ~0x7ff;
 554                         } else {
 555                                 int byteshift = fb->format->cpp[0] * 8 >> 4;
 556                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 557                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 558                         }
 559                 } else {
 560                         int offset = crtc->y * pitch_pixels + crtc->x;
 561                         switch (fb->format->cpp[0] * 8) {
 562                         case 8:
 563                         default:
 564                                 offset *= 1;
 565                                 break;
 566                         case 15:
 567                         case 16:
 568                                 offset *= 2;
 569                                 break;
 570                         case 24:
 571                                 offset *= 3;
 572                                 break;
 573                         case 32:
 574                                 offset *= 4;
 575                                 break;
 576                         }
 577                         base += offset;
 578                 }
 579                 base &= ~7;
 580         }
 581         work->base = base;
 582         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 583                 crtc->funcs->get_vblank_counter(crtc);
 584
 585         /* We borrow the event spin lock for protecting flip_work */
 586         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 587
 588         if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {
 589                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 590                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 591                 r = -EBUSY;
 592                 goto pflip_cleanup;
 593         }
 594         radeon_crtc->flip_status = RADEON_FLIP_PENDING;
 595         radeon_crtc->flip_work = work;
 596
 597         /* update crtc fb */
 598         crtc->primary->fb = fb;
 599
 600         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 601
 602         queue_work(radeon_crtc->flip_queue, &work->flip_work);
 603         return 0;
 604
 605 pflip_cleanup:
 606         if (unlikely(radeon_bo_reserve(new_rbo, false) != 0)) {
 607                 DRM_ERROR("failed to reserve new rbo in error path\n");
 608                 goto cleanup;
 609         }
 610         if (unlikely(radeon_bo_unpin(new_rbo) != 0)) {
 611                 DRM_ERROR("failed to unpin new rbo in error path\n");
 612         }
 613         radeon_bo_unreserve(new_rbo);
 614
 615 cleanup:
 616         drm_gem_object_put_unlocked(&work->old_rbo->tbo.base);
 617         dma_fence_put(work->fence);
 618         kfree(work);
 619         return r;
 620 }
 621
 622 static int
 623 radeon_crtc_set_config(struct drm_mode_set *set,
 624                        struct drm_modeset_acquire_ctx *ctx)
 625 {
 626         struct drm_device *dev;
 627         struct radeon_device *rdev;
 628         struct drm_crtc *crtc;
 629         bool active = false;
 630         int ret;
 631
 632         if (!set || !set->crtc)
 633                 return -EINVAL;
 634
 635         dev = set->crtc->dev;
 636
 637         ret = pm_runtime_get_sync(dev->dev);
 638         if (ret < 0)
 639                 return ret;
 640
 641         ret = drm_crtc_helper_set_config(set, ctx);
 642
 643         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 644                 if (crtc->enabled)
 645                         active = true;
 646
 647         pm_runtime_mark_last_busy(dev->dev);
 648
 649         rdev = dev->dev_private;
 650         /* if we have active crtcs and we don't have a power ref,
 651            take the current one */
 652         if (active && !rdev->have_disp_power_ref) {
 653                 rdev->have_disp_power_ref = true;
 654                 return ret;
 655         }
 656         /* if we have no active crtcs, then drop the power ref
 657            we got before */
 658         if (!active && rdev->have_disp_power_ref) {
 659                 pm_runtime_put_autosuspend(dev->dev);
 660                 rdev->have_disp_power_ref = false;
 661         }
 662
 663         /* drop the power reference we got coming in here */
 664         pm_runtime_put_autosuspend(dev->dev);
 665         return ret;
 666 }
 667
 668 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 669         .cursor_set2 = radeon_crtc_cursor_set2,
 670         .cursor_move = radeon_crtc_cursor_move,
 671         .gamma_set = radeon_crtc_gamma_set,
 672         .set_config = radeon_crtc_set_config,
 673         .destroy = radeon_crtc_destroy,
 674         .page_flip_target = radeon_crtc_page_flip_target,
 675         .get_vblank_counter = radeon_get_vblank_counter_kms,
 676         .enable_vblank = radeon_enable_vblank_kms,
 677         .disable_vblank = radeon_disable_vblank_kms,
 678         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 679 };
 680
 681 static void radeon_crtc_init(struct drm_device *dev, int index)
 682 {
 683         struct radeon_device *rdev = dev->dev_private;
 684         struct radeon_crtc *radeon_crtc;
 685
 686         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 687         if (radeon_crtc == NULL)
 688                 return;
 689
 690         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 691
 692         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 693         radeon_crtc->crtc_id = index;
 694         radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
 695         rdev->mode_info.crtcs[index] = radeon_crtc;
 696
 697         if (rdev->family >= CHIP_BONAIRE) {
 698                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 699                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 700         } else {
 701                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 702                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 703         }
 704         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 705         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 706
 707 #if 0
 708         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 709         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 710         radeon_crtc->mode_set.num_connectors = 0;
 711 #endif
 712
 713         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 714                 radeon_atombios_init_crtc(dev, radeon_crtc);
 715         else
 716                 radeon_legacy_init_crtc(dev, radeon_crtc);
 717 }
 718
 719 static const char *encoder_names[38] = {
 720         "NONE",
 721         "INTERNAL_LVDS",
 722         "INTERNAL_TMDS1",
 723         "INTERNAL_TMDS2",
 724         "INTERNAL_DAC1",
 725         "INTERNAL_DAC2",
 726         "INTERNAL_SDVOA",
 727         "INTERNAL_SDVOB",
 728         "SI170B",
 729         "CH7303",
 730         "CH7301",
 731         "INTERNAL_DVO1",
 732         "EXTERNAL_SDVOA",
 733         "EXTERNAL_SDVOB",
 734         "TITFP513",
 735         "INTERNAL_LVTM1",
 736         "VT1623",
 737         "HDMI_SI1930",
 738         "HDMI_INTERNAL",
 739         "INTERNAL_KLDSCP_TMDS1",
 740         "INTERNAL_KLDSCP_DVO1",
 741         "INTERNAL_KLDSCP_DAC1",
 742         "INTERNAL_KLDSCP_DAC2",
 743         "SI178",
 744         "MVPU_FPGA",
 745         "INTERNAL_DDI",
 746         "VT1625",
 747         "HDMI_SI1932",
 748         "DP_AN9801",
 749         "DP_DP501",
 750         "INTERNAL_UNIPHY",
 751         "INTERNAL_KLDSCP_LVTMA",
 752         "INTERNAL_UNIPHY1",
 753         "INTERNAL_UNIPHY2",
 754         "NUTMEG",
 755         "TRAVIS",
 756         "INTERNAL_VCE",
 757         "INTERNAL_UNIPHY3",
 758 };
 759
 760 static const char *hpd_names[6] = {
 761         "HPD1",
 762         "HPD2",
 763         "HPD3",
 764         "HPD4",
 765         "HPD5",
 766         "HPD6",
 767 };
 768
 769 static void radeon_print_display_setup(struct drm_device *dev)
 770 {
 771         struct drm_connector *connector;
 772         struct radeon_connector *radeon_connector;
 773         struct drm_encoder *encoder;
 774         struct radeon_encoder *radeon_encoder;
 775         uint32_t devices;
 776         int i = 0;
 777
 778         DRM_INFO("Radeon Display Connectors\n");
 779         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 780                 radeon_connector = to_radeon_connector(connector);
 781                 DRM_INFO("Connector %d:\n", i);
 782                 DRM_INFO("  %s\n", connector->name);
 783                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 784                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 785                 if (radeon_connector->ddc_bus) {
 786                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 787                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 788                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 789                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 790                                  radeon_connector->ddc_bus->rec.a_data_reg,
 791                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 792                                  radeon_connector->ddc_bus->rec.en_data_reg,
 793                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 794                                  radeon_connector->ddc_bus->rec.y_data_reg);
 795                         if (radeon_connector->router.ddc_valid)
 796                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 797                                          radeon_connector->router.ddc_mux_control_pin,
 798                                          radeon_connector->router.ddc_mux_state);
 799                         if (radeon_connector->router.cd_valid)
 800                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 801                                          radeon_connector->router.cd_mux_control_pin,
 802                                          radeon_connector->router.cd_mux_state);
 803                 } else {
 804                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 805                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 806                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 807                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 808                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 809                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 810                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n");
 811                 }
 812                 DRM_INFO("  Encoders:\n");
 813                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 814                         radeon_encoder = to_radeon_encoder(encoder);
 815                         devices = radeon_encoder->devices & radeon_connector->devices;
 816                         if (devices) {
 817                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 818                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 819                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 820                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 821                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 822                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 823                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 824                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 825                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 826                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 827                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 828                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 829                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 830                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 831                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 832                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 833                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 834                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 835                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 836                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 837                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 838                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 839                         }
 840                 }
 841                 i++;
 842         }
 843 }
 844
 845 static bool radeon_setup_enc_conn(struct drm_device *dev)
 846 {
 847         struct radeon_device *rdev = dev->dev_private;
 848         bool ret = false;
 849
 850         if (rdev->bios) {
 851                 if (rdev->is_atom_bios) {
 852                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 853                         if (!ret)
 854                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 855                 } else {
 856                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 857                         if (!ret)
 858                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 859                 }
 860         } else {
 861                 if (!ASIC_IS_AVIVO(rdev))
 862                         ret = radeon_get_legacy_connector_info_from_table(dev);
 863         }
 864         if (ret) {
 865                 radeon_setup_encoder_clones(dev);
 866                 radeon_print_display_setup(dev);
 867         }
 868
 869         return ret;
 870 }
 871
 872 /* avivo */
 873
 874 /**
 875  * avivo_reduce_ratio - fractional number reduction
 876  *
 877  * @nom: nominator
 878  * @den: denominator
 879  * @nom_min: minimum value for nominator
 880  * @den_min: minimum value for denominator
 881  *
 882  * Find the greatest common divisor and apply it on both nominator and
 883  * denominator, but make nominator and denominator are at least as large
 884  * as their minimum values.
 885  */
 886 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 887                                unsigned nom_min, unsigned den_min)
 888 {
 889         unsigned tmp;
 890
 891         /* reduce the numbers to a simpler ratio */
 892         tmp = gcd(*nom, *den);
 893         *nom /= tmp;
 894         *den /= tmp;
 895
 896         /* make sure nominator is large enough */
 897         if (*nom < nom_min) {
 898                 tmp = DIV_ROUND_UP(nom_min, *nom);
 899                 *nom *= tmp;
 900                 *den *= tmp;
 901         }
 902
 903         /* make sure the denominator is large enough */
 904         if (*den < den_min) {
 905                 tmp = DIV_ROUND_UP(den_min, *den);
 906                 *nom *= tmp;
 907                 *den *= tmp;
 908         }
 909 }
 910
 911 /**
 912  * avivo_get_fb_ref_div - feedback and ref divider calculation
 913  *
 914  * @nom: nominator
 915  * @den: denominator
 916  * @post_div: post divider
 917  * @fb_div_max: feedback divider maximum
 918  * @ref_div_max: reference divider maximum
 919  * @fb_div: resulting feedback divider
 920  * @ref_div: resulting reference divider
 921  *
 922  * Calculate feedback and reference divider for a given post divider. Makes
 923  * sure we stay within the limits.
 924  */
 925 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 926                                  unsigned fb_div_max, unsigned ref_div_max,
 927                                  unsigned *fb_div, unsigned *ref_div)
 928 {
 929         /* limit reference * post divider to a maximum */
 930         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 931
 932         /* get matching reference and feedback divider */
 933         *ref_div = min(max(den/post_div, 1u), ref_div_max);
 934         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 935
 936         /* limit fb divider to its maximum */
 937         if (*fb_div > fb_div_max) {
 938                 *ref_div = (*ref_div * fb_div_max)/(*fb_div);
 939                 *fb_div = fb_div_max;
 940         }
 941 }
 942
 943 /**
 944  * radeon_compute_pll_avivo - compute PLL paramaters
 945  *
 946  * @pll: information about the PLL
 947  * @dot_clock_p: resulting pixel clock
 948  * fb_div_p: resulting feedback divider
 949  * frac_fb_div_p: fractional part of the feedback divider
 950  * ref_div_p: resulting reference divider
 951  * post_div_p: resulting reference divider
 952  *
 953  * Try to calculate the PLL parameters to generate the given frequency:
 954  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 955  */
 956 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 957                               u32 freq,
 958                               u32 *dot_clock_p,
 959                               u32 *fb_div_p,
 960                               u32 *frac_fb_div_p,
 961                               u32 *ref_div_p,
 962                               u32 *post_div_p)
 963 {
 964         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 965                 freq : freq / 10;
 966
 967         unsigned fb_div_min, fb_div_max, fb_div;
 968         unsigned post_div_min, post_div_max, post_div;
 969         unsigned ref_div_min, ref_div_max, ref_div;
 970         unsigned post_div_best, diff_best;
 971         unsigned nom, den;
 972
 973         /* determine allowed feedback divider range */
 974         fb_div_min = pll->min_feedback_div;
 975         fb_div_max = pll->max_feedback_div;
 976
 977         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 978                 fb_div_min *= 10;
 979                 fb_div_max *= 10;
 980         }
 981
 982         /* determine allowed ref divider range */
 983         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 984                 ref_div_min = pll->reference_div;
 985         else
 986                 ref_div_min = pll->min_ref_div;
 987
 988         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 989             pll->flags & RADEON_PLL_USE_REF_DIV)
 990                 ref_div_max = pll->reference_div;
 991         else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 992                 /* fix for problems on RS880 */
 993                 ref_div_max = min(pll->max_ref_div, 7u);
 994         else
 995                 ref_div_max = pll->max_ref_div;
 996
 997         /* determine allowed post divider range */
 998         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 999                 post_div_min = pll->post_div;
1000                 post_div_max = pll->post_div;
1001         } else {
1002                 unsigned vco_min, vco_max;
1003
1004                 if (pll->flags & RADEON_PLL_IS_LCD) {
1005                         vco_min = pll->lcd_pll_out_min;
1006                         vco_max = pll->lcd_pll_out_max;
1007                 } else {
1008                         vco_min = pll->pll_out_min;
1009                         vco_max = pll->pll_out_max;
1010                 }
1011
1012                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1013                         vco_min *= 10;
1014                         vco_max *= 10;
1015                 }
1016
1017                 post_div_min = vco_min / target_clock;
1018                 if ((target_clock * post_div_min) < vco_min)
1019                         ++post_div_min;
1020                 if (post_div_min < pll->min_post_div)
1021                         post_div_min = pll->min_post_div;
1022
1023                 post_div_max = vco_max / target_clock;
1024                 if ((target_clock * post_div_max) > vco_max)
1025                         --post_div_max;
1026                 if (post_div_max > pll->max_post_div)
1027                         post_div_max = pll->max_post_div;
1028         }
1029
1030         /* represent the searched ratio as fractional number */
1031         nom = target_clock;
1032         den = pll->reference_freq;
1033
1034         /* reduce the numbers to a simpler ratio */
1035         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
1036
1037         /* now search for a post divider */
1038         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
1039                 post_div_best = post_div_min;
1040         else
1041                 post_div_best = post_div_max;
1042         diff_best = ~0;
1043
1044         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
1045                 unsigned diff;
1046                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
1047                                      ref_div_max, &fb_div, &ref_div);
1048                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
1049                         (ref_div * post_div));
1050
1051                 if (diff < diff_best || (diff == diff_best &&
1052                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
1053
1054                         post_div_best = post_div;
1055                         diff_best = diff;
1056                 }
1057         }
1058         post_div = post_div_best;
1059
1060         /* get the feedback and reference divider for the optimal value */
1061         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
1062                              &fb_div, &ref_div);
1063
1064         /* reduce the numbers to a simpler ratio once more */
1065         /* this also makes sure that the reference divider is large enough */
1066         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
1067
1068         /* avoid high jitter with small fractional dividers */
1069         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1070                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1071                 if (fb_div < fb_div_min) {
1072                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1073                         fb_div *= tmp;
1074                         ref_div *= tmp;
1075                 }
1076         }
1077
1078         /* and finally save the result */
1079         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1080                 *fb_div_p = fb_div / 10;
1081                 *frac_fb_div_p = fb_div % 10;
1082         } else {
1083                 *fb_div_p = fb_div;
1084                 *frac_fb_div_p = 0;
1085         }
1086
1087         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1088                         (pll->reference_freq * *frac_fb_div_p)) /
1089                        (ref_div * post_div * 10);
1090         *ref_div_p = ref_div;
1091         *post_div_p = post_div;
1092
1093         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1094                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1095                       ref_div, post_div);
1096 }
1097
1098 /* pre-avivo */
1099 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1100 {
1101         uint64_t mod;
1102
1103         n += d / 2;
1104
1105         mod = do_div(n, d);
1106         return n;
1107 }
1108
1109 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1110                                uint64_t freq,
1111                                uint32_t *dot_clock_p,
1112                                uint32_t *fb_div_p,
1113                                uint32_t *frac_fb_div_p,
1114                                uint32_t *ref_div_p,
1115                                uint32_t *post_div_p)
1116 {
1117         uint32_t min_ref_div = pll->min_ref_div;
1118         uint32_t max_ref_div = pll->max_ref_div;
1119         uint32_t min_post_div = pll->min_post_div;
1120         uint32_t max_post_div = pll->max_post_div;
1121         uint32_t min_fractional_feed_div = 0;
1122         uint32_t max_fractional_feed_div = 0;
1123         uint32_t best_vco = pll->best_vco;
1124         uint32_t best_post_div = 1;
1125         uint32_t best_ref_div = 1;
1126         uint32_t best_feedback_div = 1;
1127         uint32_t best_frac_feedback_div = 0;
1128         uint32_t best_freq = -1;
1129         uint32_t best_error = 0xffffffff;
1130         uint32_t best_vco_diff = 1;
1131         uint32_t post_div;
1132         u32 pll_out_min, pll_out_max;
1133
1134         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1135         freq = freq * 1000;
1136
1137         if (pll->flags & RADEON_PLL_IS_LCD) {
1138                 pll_out_min = pll->lcd_pll_out_min;
1139                 pll_out_max = pll->lcd_pll_out_max;
1140         } else {
1141                 pll_out_min = pll->pll_out_min;
1142                 pll_out_max = pll->pll_out_max;
1143         }
1144
1145         if (pll_out_min > 64800)
1146                 pll_out_min = 64800;
1147
1148         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1149                 min_ref_div = max_ref_div = pll->reference_div;
1150         else {
1151                 while (min_ref_div < max_ref_div-1) {
1152                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1153                         uint32_t pll_in = pll->reference_freq / mid;
1154                         if (pll_in < pll->pll_in_min)
1155                                 max_ref_div = mid;
1156                         else if (pll_in > pll->pll_in_max)
1157                                 min_ref_div = mid;
1158                         else
1159                                 break;
1160                 }
1161         }
1162
1163         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1164                 min_post_div = max_post_div = pll->post_div;
1165
1166         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1167                 min_fractional_feed_div = pll->min_frac_feedback_div;
1168                 max_fractional_feed_div = pll->max_frac_feedback_div;
1169         }
1170
1171         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1172                 uint32_t ref_div;
1173
1174                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1175                         continue;
1176
1177                 /* legacy radeons only have a few post_divs */
1178                 if (pll->flags & RADEON_PLL_LEGACY) {
1179                         if ((post_div == 5) ||
1180                             (post_div == 7) ||
1181                             (post_div == 9) ||
1182                             (post_div == 10) ||
1183                             (post_div == 11) ||
1184                             (post_div == 13) ||
1185                             (post_div == 14) ||
1186                             (post_div == 15))
1187                                 continue;
1188                 }
1189
1190                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1191                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1192                         uint32_t pll_in = pll->reference_freq / ref_div;
1193                         uint32_t min_feed_div = pll->min_feedback_div;
1194                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1195
1196                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1197                                 continue;
1198
1199                         while (min_feed_div < max_feed_div) {
1200                                 uint32_t vco;
1201                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1202                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1203                                 uint32_t frac_feedback_div;
1204                                 uint64_t tmp;
1205
1206                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1207
1208                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1209                                 vco = radeon_div(tmp, ref_div);
1210
1211                                 if (vco < pll_out_min) {
1212                                         min_feed_div = feedback_div + 1;
1213                                         continue;
1214                                 } else if (vco > pll_out_max) {
1215                                         max_feed_div = feedback_div;
1216                                         continue;
1217                                 }
1218
1219                                 while (min_frac_feed_div < max_frac_feed_div) {
1220                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1221                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1222                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1223                                         current_freq = radeon_div(tmp, ref_div * post_div);
1224
1225                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1226                                                 if (freq < current_freq)
1227                                                         error = 0xffffffff;
1228                                                 else
1229                                                         error = freq - current_freq;
1230                                         } else
1231                                                 error = abs(current_freq - freq);
1232                                         vco_diff = abs(vco - best_vco);
1233
1234                                         if ((best_vco == 0 && error < best_error) ||
1235                                             (best_vco != 0 &&
1236                                              ((best_error > 100 && error < best_error - 100) ||
1237                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1238                                                 best_post_div = post_div;
1239                                                 best_ref_div = ref_div;
1240                                                 best_feedback_div = feedback_div;
1241                                                 best_frac_feedback_div = frac_feedback_div;
1242                                                 best_freq = current_freq;
1243                                                 best_error = error;
1244                                                 best_vco_diff = vco_diff;
1245                                         } else if (current_freq == freq) {
1246                                                 if (best_freq == -1) {
1247                                                         best_post_div = post_div;
1248                                                         best_ref_div = ref_div;
1249                                                         best_feedback_div = feedback_div;
1250                                                         best_frac_feedback_div = frac_feedback_div;
1251                                                         best_freq = current_freq;
1252                                                         best_error = error;
1253                                                         best_vco_diff = vco_diff;
1254                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1255                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1256                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1257                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1258                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1259                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1260                                                         best_post_div = post_div;
1261                                                         best_ref_div = ref_div;
1262                                                         best_feedback_div = feedback_div;
1263                                                         best_frac_feedback_div = frac_feedback_div;
1264                                                         best_freq = current_freq;
1265                                                         best_error = error;
1266                                                         best_vco_diff = vco_diff;
1267                                                 }
1268                                         }
1269                                         if (current_freq < freq)
1270                                                 min_frac_feed_div = frac_feedback_div + 1;
1271                                         else
1272                                                 max_frac_feed_div = frac_feedback_div;
1273                                 }
1274                                 if (current_freq < freq)
1275                                         min_feed_div = feedback_div + 1;
1276                                 else
1277                                         max_feed_div = feedback_div;
1278                         }
1279                 }
1280         }
1281
1282         *dot_clock_p = best_freq / 10000;
1283         *fb_div_p = best_feedback_div;
1284         *frac_fb_div_p = best_frac_feedback_div;
1285         *ref_div_p = best_ref_div;
1286         *post_div_p = best_post_div;
1287         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1288                       (long long)freq,
1289                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1290                       best_ref_div, best_post_div);
1291
1292 }
1293
1294 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1295         .destroy = drm_gem_fb_destroy,
1296         .create_handle = drm_gem_fb_create_handle,
1297 };
1298
1299 int
1300 radeon_framebuffer_init(struct drm_device *dev,
1301                         struct drm_framebuffer *fb,
1302                         const struct drm_mode_fb_cmd2 *mode_cmd,
1303                         struct drm_gem_object *obj)
1304 {
1305         int ret;
1306         fb->obj[0] = obj;
1307         drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd);
1308         ret = drm_framebuffer_init(dev, fb, &radeon_fb_funcs);
1309         if (ret) {
1310                 fb->obj[0] = NULL;
1311                 return ret;
1312         }
1313         return 0;
1314 }
1315
1316 static struct drm_framebuffer *
1317 radeon_user_framebuffer_create(struct drm_device *dev,
1318                                struct drm_file *file_priv,
1319                                const struct drm_mode_fb_cmd2 *mode_cmd)
1320 {
1321         struct drm_gem_object *obj;
1322         struct drm_framebuffer *fb;
1323         int ret;
1324
1325         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
1326         if (obj ==  NULL) {
1327                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1328                         "can't create framebuffer\n", mode_cmd->handles[0]);
1329                 return ERR_PTR(-ENOENT);
1330         }
1331
1332         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
1333         if (obj->import_attach) {
1334                 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
1335                 return ERR_PTR(-EINVAL);
1336         }
1337
1338         fb = kzalloc(sizeof(*fb), GFP_KERNEL);
1339         if (fb == NULL) {
1340                 drm_gem_object_put_unlocked(obj);
1341                 return ERR_PTR(-ENOMEM);
1342         }
1343
1344         ret = radeon_framebuffer_init(dev, fb, mode_cmd, obj);
1345         if (ret) {
1346                 kfree(fb);
1347                 drm_gem_object_put_unlocked(obj);
1348                 return ERR_PTR(ret);
1349         }
1350
1351         return fb;
1352 }
1353
1354 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1355         .fb_create = radeon_user_framebuffer_create,
1356         .output_poll_changed = drm_fb_helper_output_poll_changed,
1357 };
1358
1359 static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1360 {       { 0, "driver" },
1361         { 1, "bios" },
1362 };
1363
1364 static const struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1365 {       { TV_STD_NTSC, "ntsc" },
1366         { TV_STD_PAL, "pal" },
1367         { TV_STD_PAL_M, "pal-m" },
1368         { TV_STD_PAL_60, "pal-60" },
1369         { TV_STD_NTSC_J, "ntsc-j" },
1370         { TV_STD_SCART_PAL, "scart-pal" },
1371         { TV_STD_PAL_CN, "pal-cn" },
1372         { TV_STD_SECAM, "secam" },
1373 };
1374
1375 static const struct drm_prop_enum_list radeon_underscan_enum_list[] =
1376 {       { UNDERSCAN_OFF, "off" },
1377         { UNDERSCAN_ON, "on" },
1378         { UNDERSCAN_AUTO, "auto" },
1379 };
1380
1381 static const struct drm_prop_enum_list radeon_audio_enum_list[] =
1382 {       { RADEON_AUDIO_DISABLE, "off" },
1383         { RADEON_AUDIO_ENABLE, "on" },
1384         { RADEON_AUDIO_AUTO, "auto" },
1385 };
1386
1387 /* XXX support different dither options? spatial, temporal, both, etc. */
1388 static const struct drm_prop_enum_list radeon_dither_enum_list[] =
1389 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1390         { RADEON_FMT_DITHER_ENABLE, "on" },
1391 };
1392
1393 static const struct drm_prop_enum_list radeon_output_csc_enum_list[] =
1394 {       { RADEON_OUTPUT_CSC_BYPASS, "bypass" },
1395         { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" },
1396         { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" },
1397         { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" },
1398 };
1399
1400 static int radeon_modeset_create_props(struct radeon_device *rdev)
1401 {
1402         int sz;
1403
1404         if (rdev->is_atom_bios) {
1405                 rdev->mode_info.coherent_mode_property =
1406                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1407                 if (!rdev->mode_info.coherent_mode_property)
1408                         return -ENOMEM;
1409         }
1410
1411         if (!ASIC_IS_AVIVO(rdev)) {
1412                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1413                 rdev->mode_info.tmds_pll_property =
1414                         drm_property_create_enum(rdev->ddev, 0,
1415                                             "tmds_pll",
1416                                             radeon_tmds_pll_enum_list, sz);
1417         }
1418
1419         rdev->mode_info.load_detect_property =
1420                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1421         if (!rdev->mode_info.load_detect_property)
1422                 return -ENOMEM;
1423
1424         drm_mode_create_scaling_mode_property(rdev->ddev);
1425
1426         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1427         rdev->mode_info.tv_std_property =
1428                 drm_property_create_enum(rdev->ddev, 0,
1429                                     "tv standard",
1430                                     radeon_tv_std_enum_list, sz);
1431
1432         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1433         rdev->mode_info.underscan_property =
1434                 drm_property_create_enum(rdev->ddev, 0,
1435                                     "underscan",
1436                                     radeon_underscan_enum_list, sz);
1437
1438         rdev->mode_info.underscan_hborder_property =
1439                 drm_property_create_range(rdev->ddev, 0,
1440                                         "underscan hborder", 0, 128);
1441         if (!rdev->mode_info.underscan_hborder_property)
1442                 return -ENOMEM;
1443
1444         rdev->mode_info.underscan_vborder_property =
1445                 drm_property_create_range(rdev->ddev, 0,
1446                                         "underscan vborder", 0, 128);
1447         if (!rdev->mode_info.underscan_vborder_property)
1448                 return -ENOMEM;
1449
1450         sz = ARRAY_SIZE(radeon_audio_enum_list);
1451         rdev->mode_info.audio_property =
1452                 drm_property_create_enum(rdev->ddev, 0,
1453                                          "audio",
1454                                          radeon_audio_enum_list, sz);
1455
1456         sz = ARRAY_SIZE(radeon_dither_enum_list);
1457         rdev->mode_info.dither_property =
1458                 drm_property_create_enum(rdev->ddev, 0,
1459                                          "dither",
1460                                          radeon_dither_enum_list, sz);
1461
1462         sz = ARRAY_SIZE(radeon_output_csc_enum_list);
1463         rdev->mode_info.output_csc_property =
1464                 drm_property_create_enum(rdev->ddev, 0,
1465                                          "output_csc",
1466                                          radeon_output_csc_enum_list, sz);
1467
1468         return 0;
1469 }
1470
1471 void radeon_update_display_priority(struct radeon_device *rdev)
1472 {
1473         /* adjustment options for the display watermarks */
1474         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1475                 /* set display priority to high for r3xx, rv515 chips
1476                  * this avoids flickering due to underflow to the
1477                  * display controllers during heavy acceleration.
1478                  * Don't force high on rs4xx igp chips as it seems to
1479                  * affect the sound card.  See kernel bug 15982.
1480                  */
1481                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1482                     !(rdev->flags & RADEON_IS_IGP))
1483                         rdev->disp_priority = 2;
1484                 else
1485                         rdev->disp_priority = 0;
1486         } else
1487                 rdev->disp_priority = radeon_disp_priority;
1488
1489 }
1490
1491 /*
1492  * Allocate hdmi structs and determine register offsets
1493  */
1494 static void radeon_afmt_init(struct radeon_device *rdev)
1495 {
1496         int i;
1497
1498         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1499                 rdev->mode_info.afmt[i] = NULL;
1500
1501         if (ASIC_IS_NODCE(rdev)) {
1502                 /* nothing to do */
1503         } else if (ASIC_IS_DCE4(rdev)) {
1504                 static uint32_t eg_offsets[] = {
1505                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1506                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1507                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1508                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1509                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1510                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1511                         0x13830 - 0x7030,
1512                 };
1513                 int num_afmt;
1514
1515                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1516                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1517                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1518                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1519                 if (ASIC_IS_DCE8(rdev))
1520                         num_afmt = 7;
1521                 else if (ASIC_IS_DCE6(rdev))
1522                         num_afmt = 6;
1523                 else if (ASIC_IS_DCE5(rdev))
1524                         num_afmt = 6;
1525                 else if (ASIC_IS_DCE41(rdev))
1526                         num_afmt = 2;
1527                 else /* DCE4 */
1528                         num_afmt = 6;
1529
1530                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1531                 for (i = 0; i < num_afmt; i++) {
1532                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1533                         if (rdev->mode_info.afmt[i]) {
1534                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1535                                 rdev->mode_info.afmt[i]->id = i;
1536                         }
1537                 }
1538         } else if (ASIC_IS_DCE3(rdev)) {
1539                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1540                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1541                 if (rdev->mode_info.afmt[0]) {
1542                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1543                         rdev->mode_info.afmt[0]->id = 0;
1544                 }
1545                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1546                 if (rdev->mode_info.afmt[1]) {
1547                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1548                         rdev->mode_info.afmt[1]->id = 1;
1549                 }
1550         } else if (ASIC_IS_DCE2(rdev)) {
1551                 /* DCE2 has at least 1 routable audio block */
1552                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1553                 if (rdev->mode_info.afmt[0]) {
1554                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1555                         rdev->mode_info.afmt[0]->id = 0;
1556                 }
1557                 /* r6xx has 2 routable audio blocks */
1558                 if (rdev->family >= CHIP_R600) {
1559                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1560                         if (rdev->mode_info.afmt[1]) {
1561                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1562                                 rdev->mode_info.afmt[1]->id = 1;
1563                         }
1564                 }
1565         }
1566 }
1567
1568 static void radeon_afmt_fini(struct radeon_device *rdev)
1569 {
1570         int i;
1571
1572         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1573                 kfree(rdev->mode_info.afmt[i]);
1574                 rdev->mode_info.afmt[i] = NULL;
1575         }
1576 }
1577
1578 int radeon_modeset_init(struct radeon_device *rdev)
1579 {
1580         int i;
1581         int ret;
1582
1583         drm_mode_config_init(rdev->ddev);
1584         rdev->mode_info.mode_config_initialized = true;
1585
1586         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1587
1588         if (radeon_use_pflipirq == 2 && rdev->family >= CHIP_R600)
1589                 rdev->ddev->mode_config.async_page_flip = true;
1590
1591         if (ASIC_IS_DCE5(rdev)) {
1592                 rdev->ddev->mode_config.max_width = 16384;
1593                 rdev->ddev->mode_config.max_height = 16384;
1594         } else if (ASIC_IS_AVIVO(rdev)) {
1595                 rdev->ddev->mode_config.max_width = 8192;
1596                 rdev->ddev->mode_config.max_height = 8192;
1597         } else {
1598                 rdev->ddev->mode_config.max_width = 4096;
1599                 rdev->ddev->mode_config.max_height = 4096;
1600         }
1601
1602         rdev->ddev->mode_config.preferred_depth = 24;
1603         rdev->ddev->mode_config.prefer_shadow = 1;
1604
1605         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1606
1607         ret = radeon_modeset_create_props(rdev);
1608         if (ret) {
1609                 return ret;
1610         }
1611
1612         /* init i2c buses */
1613         radeon_i2c_init(rdev);
1614
1615         /* check combios for a valid hardcoded EDID - Sun servers */
1616         if (!rdev->is_atom_bios) {
1617                 /* check for hardcoded EDID in BIOS */
1618                 radeon_combios_check_hardcoded_edid(rdev);
1619         }
1620
1621         /* allocate crtcs */
1622         for (i = 0; i < rdev->num_crtc; i++) {
1623                 radeon_crtc_init(rdev->ddev, i);
1624         }
1625
1626         /* okay we should have all the bios connectors */
1627         ret = radeon_setup_enc_conn(rdev->ddev);
1628         if (!ret) {
1629                 return ret;
1630         }
1631
1632         /* init dig PHYs, disp eng pll */
1633         if (rdev->is_atom_bios) {
1634                 radeon_atom_encoder_init(rdev);
1635                 radeon_atom_disp_eng_pll_init(rdev);
1636         }
1637
1638         /* initialize hpd */
1639         radeon_hpd_init(rdev);
1640
1641         /* setup afmt */
1642         radeon_afmt_init(rdev);
1643
1644         radeon_fbdev_init(rdev);
1645         drm_kms_helper_poll_init(rdev->ddev);
1646
1647         /* do pm late init */
1648         ret = radeon_pm_late_init(rdev);
1649
1650         return 0;
1651 }
1652
1653 void radeon_modeset_fini(struct radeon_device *rdev)
1654 {
1655         if (rdev->mode_info.mode_config_initialized) {
1656                 drm_kms_helper_poll_fini(rdev->ddev);
1657                 radeon_hpd_fini(rdev);
1658                 drm_helper_force_disable_all(rdev->ddev);
1659                 radeon_fbdev_fini(rdev);
1660                 radeon_afmt_fini(rdev);
1661                 drm_mode_config_cleanup(rdev->ddev);
1662                 rdev->mode_info.mode_config_initialized = false;
1663         }
1664
1665         kfree(rdev->mode_info.bios_hardcoded_edid);
1666
1667         /* free i2c buses */
1668         radeon_i2c_fini(rdev);
1669 }
1670
1671 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1672 {
1673         /* try and guess if this is a tv or a monitor */
1674         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1675             (mode->vdisplay == 576) || /* 576p */
1676             (mode->vdisplay == 720) || /* 720p */
1677             (mode->vdisplay == 1080)) /* 1080p */
1678                 return true;
1679         else
1680                 return false;
1681 }
1682
1683 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1684                                 const struct drm_display_mode *mode,
1685                                 struct drm_display_mode *adjusted_mode)
1686 {
1687         struct drm_device *dev = crtc->dev;
1688         struct radeon_device *rdev = dev->dev_private;
1689         struct drm_encoder *encoder;
1690         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1691         struct radeon_encoder *radeon_encoder;
1692         struct drm_connector *connector;
1693         bool first = true;
1694         u32 src_v = 1, dst_v = 1;
1695         u32 src_h = 1, dst_h = 1;
1696
1697         radeon_crtc->h_border = 0;
1698         radeon_crtc->v_border = 0;
1699
1700         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1701                 if (encoder->crtc != crtc)
1702                         continue;
1703                 radeon_encoder = to_radeon_encoder(encoder);
1704                 connector = radeon_get_connector_for_encoder(encoder);
1705
1706                 if (first) {
1707                         /* set scaling */
1708                         if (radeon_encoder->rmx_type == RMX_OFF)
1709                                 radeon_crtc->rmx_type = RMX_OFF;
1710                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1711                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1712                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1713                         else
1714                                 radeon_crtc->rmx_type = RMX_OFF;
1715                         /* copy native mode */
1716                         memcpy(&radeon_crtc->native_mode,
1717                                &radeon_encoder->native_mode,
1718                                 sizeof(struct drm_display_mode));
1719                         src_v = crtc->mode.vdisplay;
1720                         dst_v = radeon_crtc->native_mode.vdisplay;
1721                         src_h = crtc->mode.hdisplay;
1722                         dst_h = radeon_crtc->native_mode.hdisplay;
1723
1724                         /* fix up for overscan on hdmi */
1725                         if (ASIC_IS_AVIVO(rdev) &&
1726                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1727                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1728                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1729                               drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
1730                               is_hdtv_mode(mode)))) {
1731                                 if (radeon_encoder->underscan_hborder != 0)
1732                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1733                                 else
1734                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1735                                 if (radeon_encoder->underscan_vborder != 0)
1736                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1737                                 else
1738                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1739                                 radeon_crtc->rmx_type = RMX_FULL;
1740                                 src_v = crtc->mode.vdisplay;
1741                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1742                                 src_h = crtc->mode.hdisplay;
1743                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1744                         }
1745                         first = false;
1746                 } else {
1747                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1748                                 /* WARNING: Right now this can't happen but
1749                                  * in the future we need to check that scaling
1750                                  * are consistent across different encoder
1751                                  * (ie all encoder can work with the same
1752                                  *  scaling).
1753                                  */
1754                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1755                                 return false;
1756                         }
1757                 }
1758         }
1759         if (radeon_crtc->rmx_type != RMX_OFF) {
1760                 fixed20_12 a, b;
1761                 a.full = dfixed_const(src_v);
1762                 b.full = dfixed_const(dst_v);
1763                 radeon_crtc->vsc.full = dfixed_div(a, b);
1764                 a.full = dfixed_const(src_h);
1765                 b.full = dfixed_const(dst_h);
1766                 radeon_crtc->hsc.full = dfixed_div(a, b);
1767         } else {
1768                 radeon_crtc->vsc.full = dfixed_const(1);
1769                 radeon_crtc->hsc.full = dfixed_const(1);
1770         }
1771         return true;
1772 }
1773
1774 /*
1775  * Retrieve current video scanout position of crtc on a given gpu, and
1776  * an optional accurate timestamp of when query happened.
1777  *
1778  * \param dev Device to query.
1779  * \param crtc Crtc to query.
1780  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1781  *              For driver internal use only also supports these flags:
1782  *
1783  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
1784  *              of a fudged earlier start of vblank.
1785  *
1786  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
1787  *              fudged earlier start of vblank in *vpos and the distance
1788  *              to true start of vblank in *hpos.
1789  *
1790  * \param *vpos Location where vertical scanout position should be stored.
1791  * \param *hpos Location where horizontal scanout position should go.
1792  * \param *stime Target location for timestamp taken immediately before
1793  *               scanout position query. Can be NULL to skip timestamp.
1794  * \param *etime Target location for timestamp taken immediately after
1795  *               scanout position query. Can be NULL to skip timestamp.
1796  *
1797  * Returns vpos as a positive number while in active scanout area.
1798  * Returns vpos as a negative number inside vblank, counting the number
1799  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1800  * until start of active scanout / end of vblank."
1801  *
1802  * \return Flags, or'ed together as follows:
1803  *
1804  * DRM_SCANOUTPOS_VALID = Query successful.
1805  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1806  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1807  * this flag means that returned position may be offset by a constant but
1808  * unknown small number of scanlines wrt. real scanout position.
1809  *
1810  */
1811 int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
1812                                unsigned int flags, int *vpos, int *hpos,
1813                                ktime_t *stime, ktime_t *etime,
1814                                const struct drm_display_mode *mode)
1815 {
1816         u32 stat_crtc = 0, vbl = 0, position = 0;
1817         int vbl_start, vbl_end, vtotal, ret = 0;
1818         bool in_vbl = true;
1819
1820         struct radeon_device *rdev = dev->dev_private;
1821
1822         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1823
1824         /* Get optional system timestamp before query. */
1825         if (stime)
1826                 *stime = ktime_get();
1827
1828         if (ASIC_IS_DCE4(rdev)) {
1829                 if (pipe == 0) {
1830                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1831                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1832                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1833                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1834                         ret |= DRM_SCANOUTPOS_VALID;
1835                 }
1836                 if (pipe == 1) {
1837                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1838                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1839                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1840                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1841                         ret |= DRM_SCANOUTPOS_VALID;
1842                 }
1843                 if (pipe == 2) {
1844                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1845                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1846                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1847                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1848                         ret |= DRM_SCANOUTPOS_VALID;
1849                 }
1850                 if (pipe == 3) {
1851                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1852                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1853                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1854                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1855                         ret |= DRM_SCANOUTPOS_VALID;
1856                 }
1857                 if (pipe == 4) {
1858                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1859                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1860                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1861                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1862                         ret |= DRM_SCANOUTPOS_VALID;
1863                 }
1864                 if (pipe == 5) {
1865                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1866                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1867                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1868                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1869                         ret |= DRM_SCANOUTPOS_VALID;
1870                 }
1871         } else if (ASIC_IS_AVIVO(rdev)) {
1872                 if (pipe == 0) {
1873                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1874                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1875                         ret |= DRM_SCANOUTPOS_VALID;
1876                 }
1877                 if (pipe == 1) {
1878                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1879                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1880                         ret |= DRM_SCANOUTPOS_VALID;
1881                 }
1882         } else {
1883                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1884                 if (pipe == 0) {
1885                         /* Assume vbl_end == 0, get vbl_start from
1886                          * upper 16 bits.
1887                          */
1888                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1889                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1890                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1891                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1892                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1893                         if (!(stat_crtc & 1))
1894                                 in_vbl = false;
1895
1896                         ret |= DRM_SCANOUTPOS_VALID;
1897                 }
1898                 if (pipe == 1) {
1899                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1900                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1901                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1902                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1903                         if (!(stat_crtc & 1))
1904                                 in_vbl = false;
1905
1906                         ret |= DRM_SCANOUTPOS_VALID;
1907                 }
1908         }
1909
1910         /* Get optional system timestamp after query. */
1911         if (etime)
1912                 *etime = ktime_get();
1913
1914         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1915
1916         /* Decode into vertical and horizontal scanout position. */
1917         *vpos = position & 0x1fff;
1918         *hpos = (position >> 16) & 0x1fff;
1919
1920         /* Valid vblank area boundaries from gpu retrieved? */
1921         if (vbl > 0) {
1922                 /* Yes: Decode. */
1923                 ret |= DRM_SCANOUTPOS_ACCURATE;
1924                 vbl_start = vbl & 0x1fff;
1925                 vbl_end = (vbl >> 16) & 0x1fff;
1926         }
1927         else {
1928                 /* No: Fake something reasonable which gives at least ok results. */
1929                 vbl_start = mode->crtc_vdisplay;
1930                 vbl_end = 0;
1931         }
1932
1933         /* Called from driver internal vblank counter query code? */
1934         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1935             /* Caller wants distance from real vbl_start in *hpos */
1936             *hpos = *vpos - vbl_start;
1937         }
1938
1939         /* Fudge vblank to start a few scanlines earlier to handle the
1940          * problem that vblank irqs fire a few scanlines before start
1941          * of vblank. Some driver internal callers need the true vblank
1942          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1943          *
1944          * The cause of the "early" vblank irq is that the irq is triggered
1945          * by the line buffer logic when the line buffer read position enters
1946          * the vblank, whereas our crtc scanout position naturally lags the
1947          * line buffer read position.
1948          */
1949         if (!(flags & USE_REAL_VBLANKSTART))
1950                 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1951
1952         /* Test scanout position against vblank region. */
1953         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1954                 in_vbl = false;
1955
1956         /* In vblank? */
1957         if (in_vbl)
1958             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1959
1960         /* Called from driver internal vblank counter query code? */
1961         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1962                 /* Caller wants distance from fudged earlier vbl_start */
1963                 *vpos -= vbl_start;
1964                 return ret;
1965         }
1966
1967         /* Check if inside vblank area and apply corrective offsets:
1968          * vpos will then be >=0 in video scanout area, but negative
1969          * within vblank area, counting down the number of lines until
1970          * start of scanout.
1971          */
1972
1973         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1974         if (in_vbl && (*vpos >= vbl_start)) {
1975                 vtotal = mode->crtc_vtotal;
1976                 *vpos = *vpos - vtotal;
1977         }
1978
1979         /* Correct for shifted end of vbl at vbl_end. */
1980         *vpos = *vpos - vbl_end;
1981
1982         return ret;
1983 }
1984
1985 bool
1986 radeon_get_crtc_scanout_position(struct drm_crtc *crtc,
1987                                  bool in_vblank_irq, int *vpos, int *hpos,
1988                                  ktime_t *stime, ktime_t *etime,
1989                                  const struct drm_display_mode *mode)
1990 {
1991         struct drm_device *dev = crtc->dev;
1992         unsigned int pipe = crtc->index;
1993
1994         return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1995                                           stime, etime, mode);
1996 }