drivers/perf/arm_spe_pmu.c

   1 /*
   2  * Perf support for the Statistical Profiling Extension, introduced as
   3  * part of ARMv8.2.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  *
  17  * Copyright (C) 2016 ARM Limited
  18  *
  19  * Author: Will Deacon <[email protected]>
  20  */
  21
  22 #define PMUNAME                                 "arm_spe"
  23 #define DRVNAME                                 PMUNAME "_pmu"
  24 #define pr_fmt(fmt)                             DRVNAME ": " fmt
  25
  26 #include <linux/bitops.h>
  27 #include <linux/bug.h>
  28 #include <linux/capability.h>
  29 #include <linux/cpuhotplug.h>
  30 #include <linux/cpumask.h>
  31 #include <linux/device.h>
  32 #include <linux/errno.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/irq.h>
  35 #include <linux/kernel.h>
  36 #include <linux/list.h>
  37 #include <linux/module.h>
  38 #include <linux/of_address.h>
  39 #include <linux/of_device.h>
  40 #include <linux/perf_event.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/printk.h>
  43 #include <linux/slab.h>
  44 #include <linux/smp.h>
  45 #include <linux/vmalloc.h>
  46
  47 #include <asm/barrier.h>
  48 #include <asm/cpufeature.h>
  49 #include <asm/mmu.h>
  50 #include <asm/sysreg.h>
  51
  52 #define ARM_SPE_BUF_PAD_BYTE                    0
  53
  54 struct arm_spe_pmu_buf {
  55         int                                     nr_pages;
  56         bool                                    snapshot;
  57         void                                    *base;
  58 };
  59
  60 struct arm_spe_pmu {
  61         struct pmu                              pmu;
  62         struct platform_device                  *pdev;
  63         cpumask_t                               supported_cpus;
  64         struct hlist_node                       hotplug_node;
  65
  66         int                                     irq; /* PPI */
  67
  68         u16                                     min_period;
  69         u16                                     counter_sz;
  70
  71 #define SPE_PMU_FEAT_FILT_EVT                   (1UL << 0)
  72 #define SPE_PMU_FEAT_FILT_TYP                   (1UL << 1)
  73 #define SPE_PMU_FEAT_FILT_LAT                   (1UL << 2)
  74 #define SPE_PMU_FEAT_ARCH_INST                  (1UL << 3)
  75 #define SPE_PMU_FEAT_LDS                        (1UL << 4)
  76 #define SPE_PMU_FEAT_ERND                       (1UL << 5)
  77 #define SPE_PMU_FEAT_DEV_PROBED                 (1UL << 63)
  78         u64                                     features;
  79
  80         u16                                     max_record_sz;
  81         u16                                     align;
  82         struct perf_output_handle __percpu      *handle;
  83 };
  84
  85 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu))
  86
  87 /* Convert a free-running index from perf into an SPE buffer offset */
  88 #define PERF_IDX2OFF(idx, buf)  ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
  89
  90 /* Keep track of our dynamic hotplug state */
  91 static enum cpuhp_state arm_spe_pmu_online;
  92
  93 enum arm_spe_pmu_buf_fault_action {
  94         SPE_PMU_BUF_FAULT_ACT_SPURIOUS,
  95         SPE_PMU_BUF_FAULT_ACT_FATAL,
  96         SPE_PMU_BUF_FAULT_ACT_OK,
  97 };
  98
  99 /* This sysfs gunk was really good fun to write. */
 100 enum arm_spe_pmu_capabilities {
 101         SPE_PMU_CAP_ARCH_INST = 0,
 102         SPE_PMU_CAP_ERND,
 103         SPE_PMU_CAP_FEAT_MAX,
 104         SPE_PMU_CAP_CNT_SZ = SPE_PMU_CAP_FEAT_MAX,
 105         SPE_PMU_CAP_MIN_IVAL,
 106 };
 107
 108 static int arm_spe_pmu_feat_caps[SPE_PMU_CAP_FEAT_MAX] = {
 109         [SPE_PMU_CAP_ARCH_INST] = SPE_PMU_FEAT_ARCH_INST,
 110         [SPE_PMU_CAP_ERND]      = SPE_PMU_FEAT_ERND,
 111 };
 112
 113 static u32 arm_spe_pmu_cap_get(struct arm_spe_pmu *spe_pmu, int cap)
 114 {
 115         if (cap < SPE_PMU_CAP_FEAT_MAX)
 116                 return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]);
 117
 118         switch (cap) {
 119         case SPE_PMU_CAP_CNT_SZ:
 120                 return spe_pmu->counter_sz;
 121         case SPE_PMU_CAP_MIN_IVAL:
 122                 return spe_pmu->min_period;
 123         default:
 124                 WARN(1, "unknown cap %d\n", cap);
 125         }
 126
 127         return 0;
 128 }
 129
 130 static ssize_t arm_spe_pmu_cap_show(struct device *dev,
 131                                     struct device_attribute *attr,
 132                                     char *buf)
 133 {
 134         struct platform_device *pdev = to_platform_device(dev);
 135         struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev);
 136         struct dev_ext_attribute *ea =
 137                 container_of(attr, struct dev_ext_attribute, attr);
 138         int cap = (long)ea->var;
 139
 140         return snprintf(buf, PAGE_SIZE, "%u\n",
 141                 arm_spe_pmu_cap_get(spe_pmu, cap));
 142 }
 143
 144 #define SPE_EXT_ATTR_ENTRY(_name, _func, _var)                          \
 145         &((struct dev_ext_attribute[]) {                                \
 146                 { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_var }   \
 147         })[0].attr.attr
 148
 149 #define SPE_CAP_EXT_ATTR_ENTRY(_name, _var)                             \
 150         SPE_EXT_ATTR_ENTRY(_name, arm_spe_pmu_cap_show, _var)
 151
 152 static struct attribute *arm_spe_pmu_cap_attr[] = {
 153         SPE_CAP_EXT_ATTR_ENTRY(arch_inst, SPE_PMU_CAP_ARCH_INST),
 154         SPE_CAP_EXT_ATTR_ENTRY(ernd, SPE_PMU_CAP_ERND),
 155         SPE_CAP_EXT_ATTR_ENTRY(count_size, SPE_PMU_CAP_CNT_SZ),
 156         SPE_CAP_EXT_ATTR_ENTRY(min_interval, SPE_PMU_CAP_MIN_IVAL),
 157         NULL,
 158 };
 159
 160 static struct attribute_group arm_spe_pmu_cap_group = {
 161         .name   = "caps",
 162         .attrs  = arm_spe_pmu_cap_attr,
 163 };
 164
 165 /* User ABI */
 166 #define ATTR_CFG_FLD_ts_enable_CFG              config  /* PMSCR_EL1.TS */
 167 #define ATTR_CFG_FLD_ts_enable_LO               0
 168 #define ATTR_CFG_FLD_ts_enable_HI               0
 169 #define ATTR_CFG_FLD_pa_enable_CFG              config  /* PMSCR_EL1.PA */
 170 #define ATTR_CFG_FLD_pa_enable_LO               1
 171 #define ATTR_CFG_FLD_pa_enable_HI               1
 172 #define ATTR_CFG_FLD_pct_enable_CFG             config  /* PMSCR_EL1.PCT */
 173 #define ATTR_CFG_FLD_pct_enable_LO              2
 174 #define ATTR_CFG_FLD_pct_enable_HI              2
 175 #define ATTR_CFG_FLD_jitter_CFG                 config  /* PMSIRR_EL1.RND */
 176 #define ATTR_CFG_FLD_jitter_LO                  16
 177 #define ATTR_CFG_FLD_jitter_HI                  16
 178 #define ATTR_CFG_FLD_branch_filter_CFG          config  /* PMSFCR_EL1.B */
 179 #define ATTR_CFG_FLD_branch_filter_LO           32
 180 #define ATTR_CFG_FLD_branch_filter_HI           32
 181 #define ATTR_CFG_FLD_load_filter_CFG            config  /* PMSFCR_EL1.LD */
 182 #define ATTR_CFG_FLD_load_filter_LO             33
 183 #define ATTR_CFG_FLD_load_filter_HI             33
 184 #define ATTR_CFG_FLD_store_filter_CFG           config  /* PMSFCR_EL1.ST */
 185 #define ATTR_CFG_FLD_store_filter_LO            34
 186 #define ATTR_CFG_FLD_store_filter_HI            34
 187
 188 #define ATTR_CFG_FLD_event_filter_CFG           config1 /* PMSEVFR_EL1 */
 189 #define ATTR_CFG_FLD_event_filter_LO            0
 190 #define ATTR_CFG_FLD_event_filter_HI            63
 191
 192 #define ATTR_CFG_FLD_min_latency_CFG            config2 /* PMSLATFR_EL1.MINLAT */
 193 #define ATTR_CFG_FLD_min_latency_LO             0
 194 #define ATTR_CFG_FLD_min_latency_HI             11
 195
 196 /* Why does everything I do descend into this? */
 197 #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)                              \
 198         (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
 199
 200 #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi)                               \
 201         __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)
 202
 203 #define GEN_PMU_FORMAT_ATTR(name)                                       \
 204         PMU_FORMAT_ATTR(name,                                           \
 205         _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG,                 \
 206                              ATTR_CFG_FLD_##name##_LO,                  \
 207                              ATTR_CFG_FLD_##name##_HI))
 208
 209 #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi)                            \
 210         ((((attr)->cfg) >> lo) & GENMASK(hi - lo, 0))
 211
 212 #define ATTR_CFG_GET_FLD(attr, name)                                    \
 213         _ATTR_CFG_GET_FLD(attr,                                         \
 214                           ATTR_CFG_FLD_##name##_CFG,                    \
 215                           ATTR_CFG_FLD_##name##_LO,                     \
 216                           ATTR_CFG_FLD_##name##_HI)
 217
 218 GEN_PMU_FORMAT_ATTR(ts_enable);
 219 GEN_PMU_FORMAT_ATTR(pa_enable);
 220 GEN_PMU_FORMAT_ATTR(pct_enable);
 221 GEN_PMU_FORMAT_ATTR(jitter);
 222 GEN_PMU_FORMAT_ATTR(branch_filter);
 223 GEN_PMU_FORMAT_ATTR(load_filter);
 224 GEN_PMU_FORMAT_ATTR(store_filter);
 225 GEN_PMU_FORMAT_ATTR(event_filter);
 226 GEN_PMU_FORMAT_ATTR(min_latency);
 227
 228 static struct attribute *arm_spe_pmu_formats_attr[] = {
 229         &format_attr_ts_enable.attr,
 230         &format_attr_pa_enable.attr,
 231         &format_attr_pct_enable.attr,
 232         &format_attr_jitter.attr,
 233         &format_attr_branch_filter.attr,
 234         &format_attr_load_filter.attr,
 235         &format_attr_store_filter.attr,
 236         &format_attr_event_filter.attr,
 237         &format_attr_min_latency.attr,
 238         NULL,
 239 };
 240
 241 static struct attribute_group arm_spe_pmu_format_group = {
 242         .name   = "format",
 243         .attrs  = arm_spe_pmu_formats_attr,
 244 };
 245
 246 static ssize_t arm_spe_pmu_get_attr_cpumask(struct device *dev,
 247                                             struct device_attribute *attr,
 248                                             char *buf)
 249 {
 250         struct platform_device *pdev = to_platform_device(dev);
 251         struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev);
 252
 253         return cpumap_print_to_pagebuf(true, buf, &spe_pmu->supported_cpus);
 254 }
 255 static DEVICE_ATTR(cpumask, S_IRUGO, arm_spe_pmu_get_attr_cpumask, NULL);
 256
 257 static struct attribute *arm_spe_pmu_attrs[] = {
 258         &dev_attr_cpumask.attr,
 259         NULL,
 260 };
 261
 262 static struct attribute_group arm_spe_pmu_group = {
 263         .attrs  = arm_spe_pmu_attrs,
 264 };
 265
 266 static const struct attribute_group *arm_spe_pmu_attr_groups[] = {
 267         &arm_spe_pmu_group,
 268         &arm_spe_pmu_cap_group,
 269         &arm_spe_pmu_format_group,
 270         NULL,
 271 };
 272
 273 /* Convert between user ABI and register values */
 274 static u64 arm_spe_event_to_pmscr(struct perf_event *event)
 275 {
 276         struct perf_event_attr *attr = &event->attr;
 277         u64 reg = 0;
 278
 279         reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT;
 280         reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT;
 281         reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT;
 282
 283         if (!attr->exclude_user)
 284                 reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT);
 285
 286         if (!attr->exclude_kernel)
 287                 reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT);
 288
 289         if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && capable(CAP_SYS_ADMIN))
 290                 reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT);
 291
 292         return reg;
 293 }
 294
 295 static void arm_spe_event_sanitise_period(struct perf_event *event)
 296 {
 297         struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
 298         u64 period = event->hw.sample_period;
 299         u64 max_period = SYS_PMSIRR_EL1_INTERVAL_MASK
 300                          << SYS_PMSIRR_EL1_INTERVAL_SHIFT;
 301
 302         if (period < spe_pmu->min_period)
 303                 period = spe_pmu->min_period;
 304         else if (period > max_period)
 305                 period = max_period;
 306         else
 307                 period &= max_period;
 308
 309         event->hw.sample_period = period;
 310 }
 311
 312 static u64 arm_spe_event_to_pmsirr(struct perf_event *event)
 313 {
 314         struct perf_event_attr *attr = &event->attr;
 315         u64 reg = 0;
 316
 317         arm_spe_event_sanitise_period(event);
 318
 319         reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT;
 320         reg |= event->hw.sample_period;
 321
 322         return reg;
 323 }
 324
 325 static u64 arm_spe_event_to_pmsfcr(struct perf_event *event)
 326 {
 327         struct perf_event_attr *attr = &event->attr;
 328         u64 reg = 0;
 329
 330         reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT;
 331         reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT;
 332         reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT;
 333
 334         if (reg)
 335                 reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT);
 336
 337         if (ATTR_CFG_GET_FLD(attr, event_filter))
 338                 reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT);
 339
 340         if (ATTR_CFG_GET_FLD(attr, min_latency))
 341                 reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT);
 342
 343         return reg;
 344 }
 345
 346 static u64 arm_spe_event_to_pmsevfr(struct perf_event *event)
 347 {
 348         struct perf_event_attr *attr = &event->attr;
 349         return ATTR_CFG_GET_FLD(attr, event_filter);
 350 }
 351
 352 static u64 arm_spe_event_to_pmslatfr(struct perf_event *event)
 353 {
 354         struct perf_event_attr *attr = &event->attr;
 355         return ATTR_CFG_GET_FLD(attr, min_latency)
 356                << SYS_PMSLATFR_EL1_MINLAT_SHIFT;
 357 }
 358
 359 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len)
 360 {
 361         struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
 362         u64 head = PERF_IDX2OFF(handle->head, buf);
 363
 364         memset(buf->base + head, ARM_SPE_BUF_PAD_BYTE, len);
 365         if (!buf->snapshot)
 366                 perf_aux_output_skip(handle, len);
 367 }
 368
 369 static u64 arm_spe_pmu_next_snapshot_off(struct perf_output_handle *handle)
 370 {
 371         struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
 372         struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
 373         u64 head = PERF_IDX2OFF(handle->head, buf);
 374         u64 limit = buf->nr_pages * PAGE_SIZE;
 375
 376         /*
 377          * The trace format isn't parseable in reverse, so clamp
 378          * the limit to half of the buffer size in snapshot mode
 379          * so that the worst case is half a buffer of records, as
 380          * opposed to a single record.
 381          */
 382         if (head < limit >> 1)
 383                 limit >>= 1;
 384
 385         /*
 386          * If we're within max_record_sz of the limit, we must
 387          * pad, move the head index and recompute the limit.
 388          */
 389         if (limit - head < spe_pmu->max_record_sz) {
 390                 arm_spe_pmu_pad_buf(handle, limit - head);
 391                 handle->head = PERF_IDX2OFF(limit, buf);
 392                 limit = ((buf->nr_pages * PAGE_SIZE) >> 1) + handle->head;
 393         }
 394
 395         return limit;
 396 }
 397
 398 static u64 __arm_spe_pmu_next_off(struct perf_output_handle *handle)
 399 {
 400         struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
 401         struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
 402         const u64 bufsize = buf->nr_pages * PAGE_SIZE;
 403         u64 limit = bufsize;
 404         u64 head, tail, wakeup;
 405
 406         /*
 407          * The head can be misaligned for two reasons:
 408          *
 409          * 1. The hardware left PMBPTR pointing to the first byte after
 410          *    a record when generating a buffer management event.
 411          *
 412          * 2. We used perf_aux_output_skip to consume handle->size bytes
 413          *    and CIRC_SPACE was used to compute the size, which always
 414          *    leaves one entry free.
 415          *
 416          * Deal with this by padding to the next alignment boundary and
 417          * moving the head index. If we run out of buffer space, we'll
 418          * reduce handle->size to zero and end up reporting truncation.
 419          */
 420         head = PERF_IDX2OFF(handle->head, buf);
 421         if (!IS_ALIGNED(head, spe_pmu->align)) {
 422                 unsigned long delta = roundup(head, spe_pmu->align) - head;
 423
 424                 delta = min(delta, handle->size);
 425                 arm_spe_pmu_pad_buf(handle, delta);
 426                 head = PERF_IDX2OFF(handle->head, buf);
 427         }
 428
 429         /* If we've run out of free space, then nothing more to do */
 430         if (!handle->size)
 431                 goto no_space;
 432
 433         /* Compute the tail and wakeup indices now that we've aligned head */
 434         tail = PERF_IDX2OFF(handle->head + handle->size, buf);
 435         wakeup = PERF_IDX2OFF(handle->wakeup, buf);
 436
 437         /*
 438          * Avoid clobbering unconsumed data. We know we have space, so
 439          * if we see head == tail we know that the buffer is empty. If
 440          * head > tail, then there's nothing to clobber prior to
 441          * wrapping.
 442          */
 443         if (head < tail)
 444                 limit = round_down(tail, PAGE_SIZE);
 445
 446         /*
 447          * Wakeup may be arbitrarily far into the future. If it's not in
 448          * the current generation, either we'll wrap before hitting it,
 449          * or it's in the past and has been handled already.
 450          *
 451          * If there's a wakeup before we wrap, arrange to be woken up by
 452          * the page boundary following it. Keep the tail boundary if
 453          * that's lower.
 454          */
 455         if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
 456                 limit = min(limit, round_up(wakeup, PAGE_SIZE));
 457
 458         if (limit > head)
 459                 return limit;
 460
 461         arm_spe_pmu_pad_buf(handle, handle->size);
 462 no_space:
 463         perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
 464         perf_aux_output_end(handle, 0);
 465         return 0;
 466 }
 467
 468 static u64 arm_spe_pmu_next_off(struct perf_output_handle *handle)
 469 {
 470         struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
 471         struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
 472         u64 limit = __arm_spe_pmu_next_off(handle);
 473         u64 head = PERF_IDX2OFF(handle->head, buf);
 474
 475         /*
 476          * If the head has come too close to the end of the buffer,
 477          * then pad to the end and recompute the limit.
 478          */
 479         if (limit && (limit - head < spe_pmu->max_record_sz)) {
 480                 arm_spe_pmu_pad_buf(handle, limit - head);
 481                 limit = __arm_spe_pmu_next_off(handle);
 482         }
 483
 484         return limit;
 485 }
 486
 487 static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle,
 488                                           struct perf_event *event)
 489 {
 490         u64 base, limit;
 491         struct arm_spe_pmu_buf *buf;
 492
 493         /* Start a new aux session */
 494         buf = perf_aux_output_begin(handle, event);
 495         if (!buf) {
 496                 event->hw.state |= PERF_HES_STOPPED;
 497                 /*
 498                  * We still need to clear the limit pointer, since the
 499                  * profiler might only be disabled by virtue of a fault.
 500                  */
 501                 limit = 0;
 502                 goto out_write_limit;
 503         }
 504
 505         limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle)
 506                               : arm_spe_pmu_next_off(handle);
 507         if (limit)
 508                 limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT);
 509
 510         limit += (u64)buf->base;
 511         base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf);
 512         write_sysreg_s(base, SYS_PMBPTR_EL1);
 513
 514 out_write_limit:
 515         write_sysreg_s(limit, SYS_PMBLIMITR_EL1);
 516 }
 517
 518 static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle)
 519 {
 520         struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
 521         u64 offset, size;
 522
 523         offset = read_sysreg_s(SYS_PMBPTR_EL1) - (u64)buf->base;
 524         size = offset - PERF_IDX2OFF(handle->head, buf);
 525
 526         if (buf->snapshot)
 527                 handle->head = offset;
 528
 529         perf_aux_output_end(handle, size);
 530 }
 531
 532 static void arm_spe_pmu_disable_and_drain_local(void)
 533 {
 534         /* Disable profiling at EL0 and EL1 */
 535         write_sysreg_s(0, SYS_PMSCR_EL1);
 536         isb();
 537
 538         /* Drain any buffered data */
 539         psb_csync();
 540         dsb(nsh);
 541
 542         /* Disable the profiling buffer */
 543         write_sysreg_s(0, SYS_PMBLIMITR_EL1);
 544         isb();
 545 }
 546
 547 /* IRQ handling */
 548 static enum arm_spe_pmu_buf_fault_action
 549 arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle)
 550 {
 551         const char *err_str;
 552         u64 pmbsr;
 553         enum arm_spe_pmu_buf_fault_action ret;
 554
 555         /*
 556          * Ensure new profiling data is visible to the CPU and any external
 557          * aborts have been resolved.
 558          */
 559         psb_csync();
 560         dsb(nsh);
 561
 562         /* Ensure hardware updates to PMBPTR_EL1 are visible */
 563         isb();
 564
 565         /* Service required? */
 566         pmbsr = read_sysreg_s(SYS_PMBSR_EL1);
 567         if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT)))
 568                 return SPE_PMU_BUF_FAULT_ACT_SPURIOUS;
 569
 570         /*
 571          * If we've lost data, disable profiling and also set the PARTIAL
 572          * flag to indicate that the last record is corrupted.
 573          */
 574         if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT))
 575                 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED |
 576                                              PERF_AUX_FLAG_PARTIAL);
 577
 578         /* Report collisions to userspace so that it can up the period */
 579         if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT))
 580                 perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION);
 581
 582         /* We only expect buffer management events */
 583         switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) {
 584         case SYS_PMBSR_EL1_EC_BUF:
 585                 /* Handled below */
 586                 break;
 587         case SYS_PMBSR_EL1_EC_FAULT_S1:
 588         case SYS_PMBSR_EL1_EC_FAULT_S2:
 589                 err_str = "Unexpected buffer fault";
 590                 goto out_err;
 591         default:
 592                 err_str = "Unknown error code";
 593                 goto out_err;
 594         }
 595
 596         /* Buffer management event */
 597         switch (pmbsr &
 598                 (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) {
 599         case SYS_PMBSR_EL1_BUF_BSC_FULL:
 600                 ret = SPE_PMU_BUF_FAULT_ACT_OK;
 601                 goto out_stop;
 602         default:
 603                 err_str = "Unknown buffer status code";
 604         }
 605
 606 out_err:
 607         pr_err_ratelimited("%s on CPU %d [PMBSR=0x%016llx, PMBPTR=0x%016llx, PMBLIMITR=0x%016llx]\n",
 608                            err_str, smp_processor_id(), pmbsr,
 609                            read_sysreg_s(SYS_PMBPTR_EL1),
 610                            read_sysreg_s(SYS_PMBLIMITR_EL1));
 611         ret = SPE_PMU_BUF_FAULT_ACT_FATAL;
 612
 613 out_stop:
 614         arm_spe_perf_aux_output_end(handle);
 615         return ret;
 616 }
 617
 618 static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev)
 619 {
 620         struct perf_output_handle *handle = dev;
 621         struct perf_event *event = handle->event;
 622         enum arm_spe_pmu_buf_fault_action act;
 623
 624         if (!perf_get_aux(handle))
 625                 return IRQ_NONE;
 626
 627         act = arm_spe_pmu_buf_get_fault_act(handle);
 628         if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
 629                 return IRQ_NONE;
 630
 631         /*
 632          * Ensure perf callbacks have completed, which may disable the
 633          * profiling buffer in response to a TRUNCATION flag.
 634          */
 635         irq_work_run();
 636
 637         switch (act) {
 638         case SPE_PMU_BUF_FAULT_ACT_FATAL:
 639                 /*
 640                  * If a fatal exception occurred then leaving the profiling
 641                  * buffer enabled is a recipe waiting to happen. Since
 642                  * fatal faults don't always imply truncation, make sure
 643                  * that the profiling buffer is disabled explicitly before
 644                  * clearing the syndrome register.
 645                  */
 646                 arm_spe_pmu_disable_and_drain_local();
 647                 break;
 648         case SPE_PMU_BUF_FAULT_ACT_OK:
 649                 /*
 650                  * We handled the fault (the buffer was full), so resume
 651                  * profiling as long as we didn't detect truncation.
 652                  * PMBPTR might be misaligned, but we'll burn that bridge
 653                  * when we get to it.
 654                  */
 655                 if (!(handle->aux_flags & PERF_AUX_FLAG_TRUNCATED)) {
 656                         arm_spe_perf_aux_output_begin(handle, event);
 657                         isb();
 658                 }
 659                 break;
 660         case SPE_PMU_BUF_FAULT_ACT_SPURIOUS:
 661                 /* We've seen you before, but GCC has the memory of a sieve. */
 662                 break;
 663         }
 664
 665         /* The buffer pointers are now sane, so resume profiling. */
 666         write_sysreg_s(0, SYS_PMBSR_EL1);
 667         return IRQ_HANDLED;
 668 }
 669
 670 /* Perf callbacks */
 671 static int arm_spe_pmu_event_init(struct perf_event *event)
 672 {
 673         u64 reg;
 674         struct perf_event_attr *attr = &event->attr;
 675         struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
 676
 677         /* This is, of course, deeply driver-specific */
 678         if (attr->type != event->pmu->type)
 679                 return -ENOENT;
 680
 681         if (event->cpu >= 0 &&
 682             !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus))
 683                 return -ENOENT;
 684
 685         if (arm_spe_event_to_pmsevfr(event) & SYS_PMSEVFR_EL1_RES0)
 686                 return -EOPNOTSUPP;
 687
 688         if (attr->exclude_idle)
 689                 return -EOPNOTSUPP;
 690
 691         /*
 692          * Feedback-directed frequency throttling doesn't work when we
 693          * have a buffer of samples. We'd need to manually count the
 694          * samples in the buffer when it fills up and adjust the event
 695          * count to reflect that. Instead, just force the user to specify
 696          * a sample period.
 697          */
 698         if (attr->freq)
 699                 return -EINVAL;
 700
 701         reg = arm_spe_event_to_pmsfcr(event);
 702         if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) &&
 703             !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT))
 704                 return -EOPNOTSUPP;
 705
 706         if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) &&
 707             !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP))
 708                 return -EOPNOTSUPP;
 709
 710         if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) &&
 711             !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT))
 712                 return -EOPNOTSUPP;
 713
 714         reg = arm_spe_event_to_pmscr(event);
 715         if (!capable(CAP_SYS_ADMIN) &&
 716             (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) |
 717                     BIT(SYS_PMSCR_EL1_CX_SHIFT) |
 718                     BIT(SYS_PMSCR_EL1_PCT_SHIFT))))
 719                 return -EACCES;
 720
 721         return 0;
 722 }
 723
 724 static void arm_spe_pmu_start(struct perf_event *event, int flags)
 725 {
 726         u64 reg;
 727         struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
 728         struct hw_perf_event *hwc = &event->hw;
 729         struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
 730
 731         hwc->state = 0;
 732         arm_spe_perf_aux_output_begin(handle, event);
 733         if (hwc->state)
 734                 return;
 735
 736         reg = arm_spe_event_to_pmsfcr(event);
 737         write_sysreg_s(reg, SYS_PMSFCR_EL1);
 738
 739         reg = arm_spe_event_to_pmsevfr(event);
 740         write_sysreg_s(reg, SYS_PMSEVFR_EL1);
 741
 742         reg = arm_spe_event_to_pmslatfr(event);
 743         write_sysreg_s(reg, SYS_PMSLATFR_EL1);
 744
 745         if (flags & PERF_EF_RELOAD) {
 746                 reg = arm_spe_event_to_pmsirr(event);
 747                 write_sysreg_s(reg, SYS_PMSIRR_EL1);
 748                 isb();
 749                 reg = local64_read(&hwc->period_left);
 750                 write_sysreg_s(reg, SYS_PMSICR_EL1);
 751         }
 752
 753         reg = arm_spe_event_to_pmscr(event);
 754         isb();
 755         write_sysreg_s(reg, SYS_PMSCR_EL1);
 756 }
 757
 758 static void arm_spe_pmu_stop(struct perf_event *event, int flags)
 759 {
 760         struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
 761         struct hw_perf_event *hwc = &event->hw;
 762         struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
 763
 764         /* If we're already stopped, then nothing to do */
 765         if (hwc->state & PERF_HES_STOPPED)
 766                 return;
 767
 768         /* Stop all trace generation */
 769         arm_spe_pmu_disable_and_drain_local();
 770
 771         if (flags & PERF_EF_UPDATE) {
 772                 /*
 773                  * If there's a fault pending then ensure we contain it
 774                  * to this buffer, since we might be on the context-switch
 775                  * path.
 776                  */
 777                 if (perf_get_aux(handle)) {
 778                         enum arm_spe_pmu_buf_fault_action act;
 779
 780                         act = arm_spe_pmu_buf_get_fault_act(handle);
 781                         if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
 782                                 arm_spe_perf_aux_output_end(handle);
 783                         else
 784                                 write_sysreg_s(0, SYS_PMBSR_EL1);
 785                 }
 786
 787                 /*
 788                  * This may also contain ECOUNT, but nobody else should
 789                  * be looking at period_left, since we forbid frequency
 790                  * based sampling.
 791                  */
 792                 local64_set(&hwc->period_left, read_sysreg_s(SYS_PMSICR_EL1));
 793                 hwc->state |= PERF_HES_UPTODATE;
 794         }
 795
 796         hwc->state |= PERF_HES_STOPPED;
 797 }
 798
 799 static int arm_spe_pmu_add(struct perf_event *event, int flags)
 800 {
 801         int ret = 0;
 802         struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
 803         struct hw_perf_event *hwc = &event->hw;
 804         int cpu = event->cpu == -1 ? smp_processor_id() : event->cpu;
 805
 806         if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
 807                 return -ENOENT;
 808
 809         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 810
 811         if (flags & PERF_EF_START) {
 812                 arm_spe_pmu_start(event, PERF_EF_RELOAD);
 813                 if (hwc->state & PERF_HES_STOPPED)
 814                         ret = -EINVAL;
 815         }
 816
 817         return ret;
 818 }
 819
 820 static void arm_spe_pmu_del(struct perf_event *event, int flags)
 821 {
 822         arm_spe_pmu_stop(event, PERF_EF_UPDATE);
 823 }
 824
 825 static void arm_spe_pmu_read(struct perf_event *event)
 826 {
 827 }
 828
 829 static void *arm_spe_pmu_setup_aux(int cpu, void **pages, int nr_pages,
 830                                    bool snapshot)
 831 {
 832         int i;
 833         struct page **pglist;
 834         struct arm_spe_pmu_buf *buf;
 835
 836         /* We need at least two pages for this to work. */
 837         if (nr_pages < 2)
 838                 return NULL;
 839
 840         /*
 841          * We require an even number of pages for snapshot mode, so that
 842          * we can effectively treat the buffer as consisting of two equal
 843          * parts and give userspace a fighting chance of getting some
 844          * useful data out of it.
 845          */
 846         if (!nr_pages || (snapshot && (nr_pages & 1)))
 847                 return NULL;
 848
 849         if (cpu == -1)
 850                 cpu = raw_smp_processor_id();
 851
 852         buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, cpu_to_node(cpu));
 853         if (!buf)
 854                 return NULL;
 855
 856         pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
 857         if (!pglist)
 858                 goto out_free_buf;
 859
 860         for (i = 0; i < nr_pages; ++i) {
 861                 struct page *page = virt_to_page(pages[i]);
 862
 863                 if (PagePrivate(page)) {
 864                         pr_warn("unexpected high-order page for auxbuf!");
 865                         goto out_free_pglist;
 866                 }
 867
 868                 pglist[i] = virt_to_page(pages[i]);
 869         }
 870
 871         buf->base = vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
 872         if (!buf->base)
 873                 goto out_free_pglist;
 874
 875         buf->nr_pages   = nr_pages;
 876         buf->snapshot   = snapshot;
 877
 878         kfree(pglist);
 879         return buf;
 880
 881 out_free_pglist:
 882         kfree(pglist);
 883 out_free_buf:
 884         kfree(buf);
 885         return NULL;
 886 }
 887
 888 static void arm_spe_pmu_free_aux(void *aux)
 889 {
 890         struct arm_spe_pmu_buf *buf = aux;
 891
 892         vunmap(buf->base);
 893         kfree(buf);
 894 }
 895
 896 /* Initialisation and teardown functions */
 897 static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu)
 898 {
 899         static atomic_t pmu_idx = ATOMIC_INIT(-1);
 900
 901         int idx;
 902         char *name;
 903         struct device *dev = &spe_pmu->pdev->dev;
 904
 905         spe_pmu->pmu = (struct pmu) {
 906                 .module = THIS_MODULE,
 907                 .capabilities   = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
 908                 .attr_groups    = arm_spe_pmu_attr_groups,
 909                 /*
 910                  * We hitch a ride on the software context here, so that
 911                  * we can support per-task profiling (which is not possible
 912                  * with the invalid context as it doesn't get sched callbacks).
 913                  * This requires that userspace either uses a dummy event for
 914                  * perf_event_open, since the aux buffer is not setup until
 915                  * a subsequent mmap, or creates the profiling event in a
 916                  * disabled state and explicitly PERF_EVENT_IOC_ENABLEs it
 917                  * once the buffer has been created.
 918                  */
 919                 .task_ctx_nr    = perf_sw_context,
 920                 .event_init     = arm_spe_pmu_event_init,
 921                 .add            = arm_spe_pmu_add,
 922                 .del            = arm_spe_pmu_del,
 923                 .start          = arm_spe_pmu_start,
 924                 .stop           = arm_spe_pmu_stop,
 925                 .read           = arm_spe_pmu_read,
 926                 .setup_aux      = arm_spe_pmu_setup_aux,
 927                 .free_aux       = arm_spe_pmu_free_aux,
 928         };
 929
 930         idx = atomic_inc_return(&pmu_idx);
 931         name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", PMUNAME, idx);
 932         return perf_pmu_register(&spe_pmu->pmu, name, -1);
 933 }
 934
 935 static void arm_spe_pmu_perf_destroy(struct arm_spe_pmu *spe_pmu)
 936 {
 937         perf_pmu_unregister(&spe_pmu->pmu);
 938 }
 939
 940 static void __arm_spe_pmu_dev_probe(void *info)
 941 {
 942         int fld;
 943         u64 reg;
 944         struct arm_spe_pmu *spe_pmu = info;
 945         struct device *dev = &spe_pmu->pdev->dev;
 946
 947         fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1),
 948                                                    ID_AA64DFR0_PMSVER_SHIFT);
 949         if (!fld) {
 950                 dev_err(dev,
 951                         "unsupported ID_AA64DFR0_EL1.PMSVer [%d] on CPU %d\n",
 952                         fld, smp_processor_id());
 953                 return;
 954         }
 955
 956         /* Read PMBIDR first to determine whether or not we have access */
 957         reg = read_sysreg_s(SYS_PMBIDR_EL1);
 958         if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) {
 959                 dev_err(dev,
 960                         "profiling buffer owned by higher exception level\n");
 961                 return;
 962         }
 963
 964         /* Minimum alignment. If it's out-of-range, then fail the probe */
 965         fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK;
 966         spe_pmu->align = 1 << fld;
 967         if (spe_pmu->align > SZ_2K) {
 968                 dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n",
 969                         fld, smp_processor_id());
 970                 return;
 971         }
 972
 973         /* It's now safe to read PMSIDR and figure out what we've got */
 974         reg = read_sysreg_s(SYS_PMSIDR_EL1);
 975         if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT))
 976                 spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT;
 977
 978         if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT))
 979                 spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP;
 980
 981         if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT))
 982                 spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT;
 983
 984         if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT))
 985                 spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST;
 986
 987         if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT))
 988                 spe_pmu->features |= SPE_PMU_FEAT_LDS;
 989
 990         if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT))
 991                 spe_pmu->features |= SPE_PMU_FEAT_ERND;
 992
 993         /* This field has a spaced out encoding, so just use a look-up */
 994         fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK;
 995         switch (fld) {
 996         case 0:
 997                 spe_pmu->min_period = 256;
 998                 break;
 999         case 2:
1000                 spe_pmu->min_period = 512;
1001                 break;
1002         case 3:
1003                 spe_pmu->min_period = 768;
1004                 break;
1005         case 4:
1006                 spe_pmu->min_period = 1024;
1007                 break;
1008         case 5:
1009                 spe_pmu->min_period = 1536;
1010                 break;
1011         case 6:
1012                 spe_pmu->min_period = 2048;
1013                 break;
1014         case 7:
1015                 spe_pmu->min_period = 3072;
1016                 break;
1017         default:
1018                 dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n",
1019                          fld);
1020                 /* Fallthrough */
1021         case 8:
1022                 spe_pmu->min_period = 4096;
1023         }
1024
1025         /* Maximum record size. If it's out-of-range, then fail the probe */
1026         fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK;
1027         spe_pmu->max_record_sz = 1 << fld;
1028         if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) {
1029                 dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n",
1030                         fld, smp_processor_id());
1031                 return;
1032         }
1033
1034         fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK;
1035         switch (fld) {
1036         default:
1037                 dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n",
1038                          fld);
1039                 /* Fallthrough */
1040         case 2:
1041                 spe_pmu->counter_sz = 12;
1042         }
1043
1044         dev_info(dev,
1045                  "probed for CPUs %*pbl [max_record_sz %u, align %u, features 0x%llx]\n",
1046                  cpumask_pr_args(&spe_pmu->supported_cpus),
1047                  spe_pmu->max_record_sz, spe_pmu->align, spe_pmu->features);
1048
1049         spe_pmu->features |= SPE_PMU_FEAT_DEV_PROBED;
1050         return;
1051 }
1052
1053 static void __arm_spe_pmu_reset_local(void)
1054 {
1055         /*
1056          * This is probably overkill, as we have no idea where we're
1057          * draining any buffered data to...
1058          */
1059         arm_spe_pmu_disable_and_drain_local();
1060
1061         /* Reset the buffer base pointer */
1062         write_sysreg_s(0, SYS_PMBPTR_EL1);
1063         isb();
1064
1065         /* Clear any pending management interrupts */
1066         write_sysreg_s(0, SYS_PMBSR_EL1);
1067         isb();
1068 }
1069
1070 static void __arm_spe_pmu_setup_one(void *info)
1071 {
1072         struct arm_spe_pmu *spe_pmu = info;
1073
1074         __arm_spe_pmu_reset_local();
1075         enable_percpu_irq(spe_pmu->irq, IRQ_TYPE_NONE);
1076 }
1077
1078 static void __arm_spe_pmu_stop_one(void *info)
1079 {
1080         struct arm_spe_pmu *spe_pmu = info;
1081
1082         disable_percpu_irq(spe_pmu->irq);
1083         __arm_spe_pmu_reset_local();
1084 }
1085
1086 static int arm_spe_pmu_cpu_startup(unsigned int cpu, struct hlist_node *node)
1087 {
1088         struct arm_spe_pmu *spe_pmu;
1089
1090         spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
1091         if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
1092                 return 0;
1093
1094         __arm_spe_pmu_setup_one(spe_pmu);
1095         return 0;
1096 }
1097
1098 static int arm_spe_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node)
1099 {
1100         struct arm_spe_pmu *spe_pmu;
1101
1102         spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
1103         if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
1104                 return 0;
1105
1106         __arm_spe_pmu_stop_one(spe_pmu);
1107         return 0;
1108 }
1109
1110 static int arm_spe_pmu_dev_init(struct arm_spe_pmu *spe_pmu)
1111 {
1112         int ret;
1113         cpumask_t *mask = &spe_pmu->supported_cpus;
1114
1115         /* Make sure we probe the hardware on a relevant CPU */
1116         ret = smp_call_function_any(mask,  __arm_spe_pmu_dev_probe, spe_pmu, 1);
1117         if (ret || !(spe_pmu->features & SPE_PMU_FEAT_DEV_PROBED))
1118                 return -ENXIO;
1119
1120         /* Request our PPIs (note that the IRQ is still disabled) */
1121         ret = request_percpu_irq(spe_pmu->irq, arm_spe_pmu_irq_handler, DRVNAME,
1122                                  spe_pmu->handle);
1123         if (ret)
1124                 return ret;
1125
1126         /*
1127          * Register our hotplug notifier now so we don't miss any events.
1128          * This will enable the IRQ for any supported CPUs that are already
1129          * up.
1130          */
1131         ret = cpuhp_state_add_instance(arm_spe_pmu_online,
1132                                        &spe_pmu->hotplug_node);
1133         if (ret)
1134                 free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
1135
1136         return ret;
1137 }
1138
1139 static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu)
1140 {
1141         cpuhp_state_remove_instance(arm_spe_pmu_online, &spe_pmu->hotplug_node);
1142         free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
1143 }
1144
1145 /* Driver and device probing */
1146 static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu)
1147 {
1148         struct platform_device *pdev = spe_pmu->pdev;
1149         int irq = platform_get_irq(pdev, 0);
1150
1151         if (irq < 0) {
1152                 dev_err(&pdev->dev, "failed to get IRQ (%d)\n", irq);
1153                 return -ENXIO;
1154         }
1155
1156         if (!irq_is_percpu(irq)) {
1157                 dev_err(&pdev->dev, "expected PPI but got SPI (%d)\n", irq);
1158                 return -EINVAL;
1159         }
1160
1161         if (irq_get_percpu_devid_partition(irq, &spe_pmu->supported_cpus)) {
1162                 dev_err(&pdev->dev, "failed to get PPI partition (%d)\n", irq);
1163                 return -EINVAL;
1164         }
1165
1166         spe_pmu->irq = irq;
1167         return 0;
1168 }
1169
1170 static const struct of_device_id arm_spe_pmu_of_match[] = {
1171         { .compatible = "arm,statistical-profiling-extension-v1", .data = (void *)1 },
1172         { /* Sentinel */ },
1173 };
1174
1175 static int arm_spe_pmu_device_dt_probe(struct platform_device *pdev)
1176 {
1177         int ret;
1178         struct arm_spe_pmu *spe_pmu;
1179         struct device *dev = &pdev->dev;
1180
1181         /*
1182          * If kernelspace is unmapped when running at EL0, then the SPE
1183          * buffer will fault and prematurely terminate the AUX session.
1184          */
1185         if (arm64_kernel_unmapped_at_el0()) {
1186                 dev_warn_once(dev, "profiling buffer inaccessible. Try passing \"kpti=off\" on the kernel command line\n");
1187                 return -EPERM;
1188         }
1189
1190         spe_pmu = devm_kzalloc(dev, sizeof(*spe_pmu), GFP_KERNEL);
1191         if (!spe_pmu) {
1192                 dev_err(dev, "failed to allocate spe_pmu\n");
1193                 return -ENOMEM;
1194         }
1195
1196         spe_pmu->handle = alloc_percpu(typeof(*spe_pmu->handle));
1197         if (!spe_pmu->handle)
1198                 return -ENOMEM;
1199
1200         spe_pmu->pdev = pdev;
1201         platform_set_drvdata(pdev, spe_pmu);
1202
1203         ret = arm_spe_pmu_irq_probe(spe_pmu);
1204         if (ret)
1205                 goto out_free_handle;
1206
1207         ret = arm_spe_pmu_dev_init(spe_pmu);
1208         if (ret)
1209                 goto out_free_handle;
1210
1211         ret = arm_spe_pmu_perf_init(spe_pmu);
1212         if (ret)
1213                 goto out_teardown_dev;
1214
1215         return 0;
1216
1217 out_teardown_dev:
1218         arm_spe_pmu_dev_teardown(spe_pmu);
1219 out_free_handle:
1220         free_percpu(spe_pmu->handle);
1221         return ret;
1222 }
1223
1224 static int arm_spe_pmu_device_remove(struct platform_device *pdev)
1225 {
1226         struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev);
1227
1228         arm_spe_pmu_perf_destroy(spe_pmu);
1229         arm_spe_pmu_dev_teardown(spe_pmu);
1230         free_percpu(spe_pmu->handle);
1231         return 0;
1232 }
1233
1234 static struct platform_driver arm_spe_pmu_driver = {
1235         .driver = {
1236                 .name           = DRVNAME,
1237                 .of_match_table = of_match_ptr(arm_spe_pmu_of_match),
1238         },
1239         .probe  = arm_spe_pmu_device_dt_probe,
1240         .remove = arm_spe_pmu_device_remove,
1241 };
1242
1243 static int __init arm_spe_pmu_init(void)
1244 {
1245         int ret;
1246
1247         ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
1248                                       arm_spe_pmu_cpu_startup,
1249                                       arm_spe_pmu_cpu_teardown);
1250         if (ret < 0)
1251                 return ret;
1252         arm_spe_pmu_online = ret;
1253
1254         ret = platform_driver_register(&arm_spe_pmu_driver);
1255         if (ret)
1256                 cpuhp_remove_multi_state(arm_spe_pmu_online);
1257
1258         return ret;
1259 }
1260
1261 static void __exit arm_spe_pmu_exit(void)
1262 {
1263         platform_driver_unregister(&arm_spe_pmu_driver);
1264         cpuhp_remove_multi_state(arm_spe_pmu_online);
1265 }
1266
1267 module_init(arm_spe_pmu_init);
1268 module_exit(arm_spe_pmu_exit);
1269
1270 MODULE_DESCRIPTION("Perf driver for the ARMv8.2 Statistical Profiling Extension");
1271 MODULE_AUTHOR("Will Deacon <[email protected]>");
1272 MODULE_LICENSE("GPL v2");