drivers/gpu/drm/sun4i/sun4i_backend.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <drm/drm_fb_cma_helper.h>
  19 #include <drm/drm_gem_cma_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/component.h>
  23 #include <linux/list.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_graph.h>
  26 #include <linux/reset.h>
  27
  28 #include "sun4i_backend.h"
  29 #include "sun4i_drv.h"
  30 #include "sun4i_frontend.h"
  31 #include "sun4i_layer.h"
  32 #include "sunxi_engine.h"
  33
  34 struct sun4i_backend_quirks {
  35         /* backend <-> TCON muxing selection done in backend */
  36         bool needs_output_muxing;
  37 };
  38
  39 static const u32 sunxi_rgb2yuv_coef[12] = {
  40         0x00000107, 0x00000204, 0x00000064, 0x00000108,
  41         0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  42         0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  43 };
  44
  45 /*
  46  * These coefficients are taken from the A33 BSP from Allwinner.
  47  *
  48  * The formula is for each component, each coefficient being multiplied by
  49  * 1024 and each constant being multiplied by 16:
  50  * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
  51  * R = 1.164 * Y + 1.596 * V - 222
  52  * B = 1.164 * Y + 2.018 * U + 276
  53  *
  54  * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255],
  55  * following the BT601 spec.
  56  */
  57 static const u32 sunxi_bt601_yuv2rgb_coef[12] = {
  58         0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877,
  59         0x000004a7, 0x00000000, 0x00000662, 0x00003211,
  60         0x000004a7, 0x00000812, 0x00000000, 0x00002eb1,
  61 };
  62
  63 static inline bool sun4i_backend_format_is_planar_yuv(uint32_t format)
  64 {
  65         switch (format) {
  66         case DRM_FORMAT_YUV411:
  67         case DRM_FORMAT_YUV422:
  68         case DRM_FORMAT_YUV444:
  69                 return true;
  70         default:
  71                 return false;
  72         }
  73 }
  74
  75 static inline bool sun4i_backend_format_is_packed_yuv422(uint32_t format)
  76 {
  77         switch (format) {
  78         case DRM_FORMAT_YUYV:
  79         case DRM_FORMAT_YVYU:
  80         case DRM_FORMAT_UYVY:
  81         case DRM_FORMAT_VYUY:
  82                 return true;
  83
  84         default:
  85                 return false;
  86         }
  87 }
  88
  89 static inline bool sun4i_backend_format_is_yuv(uint32_t format)
  90 {
  91         return sun4i_backend_format_is_planar_yuv(format) ||
  92                 sun4i_backend_format_is_packed_yuv422(format);
  93 }
  94
  95 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
  96 {
  97         int i;
  98
  99         DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
 100
 101         /* Set color correction */
 102         regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
 103                      SUN4I_BACKEND_OCCTL_ENABLE);
 104
 105         for (i = 0; i < 12; i++)
 106                 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
 107                              sunxi_rgb2yuv_coef[i]);
 108 }
 109
 110 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
 111 {
 112         DRM_DEBUG_DRIVER("Disabling color correction\n");
 113
 114         /* Disable color correction */
 115         regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
 116                            SUN4I_BACKEND_OCCTL_ENABLE, 0);
 117 }
 118
 119 static void sun4i_backend_commit(struct sunxi_engine *engine)
 120 {
 121         DRM_DEBUG_DRIVER("Committing changes\n");
 122
 123         regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 124                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
 125                      SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
 126 }
 127
 128 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
 129                                 int layer, bool enable)
 130 {
 131         u32 val;
 132
 133         DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
 134                          layer);
 135
 136         if (enable)
 137                 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
 138         else
 139                 val = 0;
 140
 141         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 142                            SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
 143 }
 144
 145 static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode)
 146 {
 147         switch (format) {
 148         case DRM_FORMAT_ARGB8888:
 149                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
 150                 break;
 151
 152         case DRM_FORMAT_ARGB4444:
 153                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
 154                 break;
 155
 156         case DRM_FORMAT_ARGB1555:
 157                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
 158                 break;
 159
 160         case DRM_FORMAT_RGBA5551:
 161                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
 162                 break;
 163
 164         case DRM_FORMAT_RGBA4444:
 165                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
 166                 break;
 167
 168         case DRM_FORMAT_XRGB8888:
 169                 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
 170                 break;
 171
 172         case DRM_FORMAT_RGB888:
 173                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
 174                 break;
 175
 176         case DRM_FORMAT_RGB565:
 177                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
 178                 break;
 179
 180         default:
 181                 return -EINVAL;
 182         }
 183
 184         return 0;
 185 }
 186
 187 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
 188                                      int layer, struct drm_plane *plane)
 189 {
 190         struct drm_plane_state *state = plane->state;
 191
 192         DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
 193
 194         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 195                 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
 196                                  state->crtc_w, state->crtc_h);
 197                 regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG,
 198                              SUN4I_BACKEND_DISSIZE(state->crtc_w,
 199                                                    state->crtc_h));
 200         }
 201
 202         /* Set height and width */
 203         DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
 204                          state->crtc_w, state->crtc_h);
 205         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
 206                      SUN4I_BACKEND_LAYSIZE(state->crtc_w,
 207                                            state->crtc_h));
 208
 209         /* Set base coordinates */
 210         DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
 211                          state->crtc_x, state->crtc_y);
 212         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
 213                      SUN4I_BACKEND_LAYCOOR(state->crtc_x,
 214                                            state->crtc_y));
 215
 216         return 0;
 217 }
 218
 219 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
 220                                            int layer, struct drm_plane *plane)
 221 {
 222         struct drm_plane_state *state = plane->state;
 223         struct drm_framebuffer *fb = state->fb;
 224         uint32_t format = fb->format->format;
 225         u32 val = SUN4I_BACKEND_IYUVCTL_EN;
 226         int i;
 227
 228         for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
 229                 regmap_write(backend->engine.regs,
 230                              SUN4I_BACKEND_YGCOEF_REG(i),
 231                              sunxi_bt601_yuv2rgb_coef[i]);
 232
 233         /*
 234          * We should do that only for a single plane, but the
 235          * framebuffer's atomic_check has our back on this.
 236          */
 237         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 238                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN,
 239                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN);
 240
 241         /* TODO: Add support for the multi-planar YUV formats */
 242         if (sun4i_backend_format_is_packed_yuv422(format))
 243                 val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422;
 244         else
 245                 DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", format);
 246
 247         /*
 248          * Allwinner seems to list the pixel sequence from right to left, while
 249          * DRM lists it from left to right.
 250          */
 251         switch (format) {
 252         case DRM_FORMAT_YUYV:
 253                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY;
 254                 break;
 255         case DRM_FORMAT_YVYU:
 256                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY;
 257                 break;
 258         case DRM_FORMAT_UYVY:
 259                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU;
 260                 break;
 261         case DRM_FORMAT_VYUY:
 262                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV;
 263                 break;
 264         default:
 265                 DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n",
 266                                  format);
 267         }
 268
 269         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
 270
 271         return 0;
 272 }
 273
 274 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
 275                                        int layer, struct drm_plane *plane)
 276 {
 277         struct drm_plane_state *state = plane->state;
 278         struct drm_framebuffer *fb = state->fb;
 279         bool interlaced = false;
 280         u32 val;
 281         int ret;
 282
 283         /* Clear the YUV mode */
 284         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 285                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
 286
 287         if (plane->state->crtc)
 288                 interlaced = plane->state->crtc->state->adjusted_mode.flags
 289                         & DRM_MODE_FLAG_INTERLACE;
 290
 291         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 292                            SUN4I_BACKEND_MODCTL_ITLMOD_EN,
 293                            interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
 294
 295         DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
 296                          interlaced ? "on" : "off");
 297
 298         val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8);
 299         if (state->alpha != DRM_BLEND_ALPHA_OPAQUE)
 300                 val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN;
 301         regmap_update_bits(backend->engine.regs,
 302                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 303                            SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK |
 304                            SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN,
 305                            val);
 306
 307         if (sun4i_backend_format_is_yuv(fb->format->format))
 308                 return sun4i_backend_update_yuv_format(backend, layer, plane);
 309
 310         ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val);
 311         if (ret) {
 312                 DRM_DEBUG_DRIVER("Invalid format\n");
 313                 return ret;
 314         }
 315
 316         regmap_update_bits(backend->engine.regs,
 317                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 318                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 319
 320         return 0;
 321 }
 322
 323 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
 324                                         int layer, uint32_t fmt)
 325 {
 326         u32 val;
 327         int ret;
 328
 329         ret = sun4i_backend_drm_format_to_layer(fmt, &val);
 330         if (ret) {
 331                 DRM_DEBUG_DRIVER("Invalid format\n");
 332                 return ret;
 333         }
 334
 335         regmap_update_bits(backend->engine.regs,
 336                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 337                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN,
 338                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN);
 339
 340         regmap_update_bits(backend->engine.regs,
 341                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 342                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 343
 344         return 0;
 345 }
 346
 347 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
 348                                            struct drm_framebuffer *fb,
 349                                            dma_addr_t paddr)
 350 {
 351         /* TODO: Add support for the multi-planar YUV formats */
 352         DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr);
 353         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
 354
 355         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 356         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
 357                      fb->pitches[0] * 8);
 358
 359         return 0;
 360 }
 361
 362 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 363                                       int layer, struct drm_plane *plane)
 364 {
 365         struct drm_plane_state *state = plane->state;
 366         struct drm_framebuffer *fb = state->fb;
 367         u32 lo_paddr, hi_paddr;
 368         dma_addr_t paddr;
 369
 370         /* Set the line width */
 371         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 372         regmap_write(backend->engine.regs,
 373                      SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
 374                      fb->pitches[0] * 8);
 375
 376         /* Get the start of the displayed memory */
 377         paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
 378         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 379
 380         /*
 381          * backend DMA accesses DRAM directly, bypassing the system
 382          * bus. As such, the address range is different and the buffer
 383          * address needs to be corrected.
 384          */
 385         paddr -= PHYS_OFFSET;
 386
 387         if (sun4i_backend_format_is_yuv(fb->format->format))
 388                 return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
 389
 390         /* Write the 32 lower bits of the address (in bits) */
 391         lo_paddr = paddr << 3;
 392         DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
 393         regmap_write(backend->engine.regs,
 394                      SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
 395                      lo_paddr);
 396
 397         /* And the upper bits */
 398         hi_paddr = paddr >> 29;
 399         DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
 400         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
 401                            SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
 402                            SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
 403
 404         return 0;
 405 }
 406
 407 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
 408                                     struct drm_plane *plane)
 409 {
 410         struct drm_plane_state *state = plane->state;
 411         struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state);
 412         unsigned int priority = state->normalized_zpos;
 413         unsigned int pipe = p_state->pipe;
 414
 415         DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n",
 416                          layer, priority, pipe);
 417         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 418                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK |
 419                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK,
 420                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) |
 421                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority));
 422
 423         return 0;
 424 }
 425
 426 static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state)
 427 {
 428         u16 src_h = state->src_h >> 16;
 429         u16 src_w = state->src_w >> 16;
 430
 431         DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n",
 432                          src_w, src_h, state->crtc_w, state->crtc_h);
 433
 434         if ((state->crtc_h != src_h) || (state->crtc_w != src_w))
 435                 return true;
 436
 437         return false;
 438 }
 439
 440 static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state)
 441 {
 442         struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane);
 443         struct sun4i_backend *backend = layer->backend;
 444
 445         if (IS_ERR(backend->frontend))
 446                 return false;
 447
 448         return sun4i_backend_plane_uses_scaler(state);
 449 }
 450
 451 static void sun4i_backend_atomic_begin(struct sunxi_engine *engine,
 452                                        struct drm_crtc_state *old_state)
 453 {
 454         u32 val;
 455
 456         WARN_ON(regmap_read_poll_timeout(engine->regs,
 457                                          SUN4I_BACKEND_REGBUFFCTL_REG,
 458                                          val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL),
 459                                          100, 50000));
 460 }
 461
 462 static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
 463                                       struct drm_crtc_state *crtc_state)
 464 {
 465         struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 };
 466         struct drm_atomic_state *state = crtc_state->state;
 467         struct drm_device *drm = state->dev;
 468         struct drm_plane *plane;
 469         unsigned int num_planes = 0;
 470         unsigned int num_alpha_planes = 0;
 471         unsigned int num_frontend_planes = 0;
 472         unsigned int num_yuv_planes = 0;
 473         unsigned int current_pipe = 0;
 474         unsigned int i;
 475
 476         DRM_DEBUG_DRIVER("Starting checking our planes\n");
 477
 478         if (!crtc_state->planes_changed)
 479                 return 0;
 480
 481         drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) {
 482                 struct drm_plane_state *plane_state =
 483                         drm_atomic_get_plane_state(state, plane);
 484                 struct sun4i_layer_state *layer_state =
 485                         state_to_sun4i_layer_state(plane_state);
 486                 struct drm_framebuffer *fb = plane_state->fb;
 487                 struct drm_format_name_buf format_name;
 488
 489                 if (sun4i_backend_plane_uses_frontend(plane_state)) {
 490                         DRM_DEBUG_DRIVER("Using the frontend for plane %d\n",
 491                                          plane->index);
 492
 493                         layer_state->uses_frontend = true;
 494                         num_frontend_planes++;
 495                 } else {
 496                         layer_state->uses_frontend = false;
 497                 }
 498
 499                 DRM_DEBUG_DRIVER("Plane FB format is %s\n",
 500                                  drm_get_format_name(fb->format->format,
 501                                                      &format_name));
 502                 if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
 503                         num_alpha_planes++;
 504
 505                 if (sun4i_backend_format_is_yuv(fb->format->format)) {
 506                         DRM_DEBUG_DRIVER("Plane FB format is YUV\n");
 507                         num_yuv_planes++;
 508                 }
 509
 510                 DRM_DEBUG_DRIVER("Plane zpos is %d\n",
 511                                  plane_state->normalized_zpos);
 512
 513                 /* Sort our planes by Zpos */
 514                 plane_states[plane_state->normalized_zpos] = plane_state;
 515
 516                 num_planes++;
 517         }
 518
 519         /* All our planes were disabled, bail out */
 520         if (!num_planes)
 521                 return 0;
 522
 523         /*
 524          * The hardware is a bit unusual here.
 525          *
 526          * Even though it supports 4 layers, it does the composition
 527          * in two separate steps.
 528          *
 529          * The first one is assigning a layer to one of its two
 530          * pipes. If more that 1 layer is assigned to the same pipe,
 531          * and if pixels overlaps, the pipe will take the pixel from
 532          * the layer with the highest priority.
 533          *
 534          * The second step is the actual alpha blending, that takes
 535          * the two pipes as input, and uses the eventual alpha
 536          * component to do the transparency between the two.
 537          *
 538          * This two steps scenario makes us unable to guarantee a
 539          * robust alpha blending between the 4 layers in all
 540          * situations, since this means that we need to have one layer
 541          * with alpha at the lowest position of our two pipes.
 542          *
 543          * However, we cannot even do that, since the hardware has a
 544          * bug where the lowest plane of the lowest pipe (pipe 0,
 545          * priority 0), if it has any alpha, will discard the pixel
 546          * entirely and just display the pixels in the background
 547          * color (black by default).
 548          *
 549          * This means that we effectively have only three valid
 550          * configurations with alpha, all of them with the alpha being
 551          * on pipe1 with the lowest position, which can be 1, 2 or 3
 552          * depending on the number of planes and their zpos.
 553          */
 554         if (num_alpha_planes > SUN4I_BACKEND_NUM_ALPHA_LAYERS) {
 555                 DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n");
 556                 return -EINVAL;
 557         }
 558
 559         /* We can't have an alpha plane at the lowest position */
 560         if (plane_states[0]->fb->format->has_alpha ||
 561             (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))
 562                 return -EINVAL;
 563
 564         for (i = 1; i < num_planes; i++) {
 565                 struct drm_plane_state *p_state = plane_states[i];
 566                 struct drm_framebuffer *fb = p_state->fb;
 567                 struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state);
 568
 569                 /*
 570                  * The only alpha position is the lowest plane of the
 571                  * second pipe.
 572                  */
 573                 if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
 574                         current_pipe++;
 575
 576                 s_state->pipe = current_pipe;
 577         }
 578
 579         /* We can only have a single YUV plane at a time */
 580         if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) {
 581                 DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n");
 582                 return -EINVAL;
 583         }
 584
 585         if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) {
 586                 DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n");
 587                 return -EINVAL;
 588         }
 589
 590         DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n",
 591                          num_planes, num_alpha_planes, num_frontend_planes,
 592                          num_yuv_planes);
 593
 594         return 0;
 595 }
 596
 597 static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine)
 598 {
 599         struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
 600         struct sun4i_frontend *frontend = backend->frontend;
 601
 602         if (!frontend)
 603                 return;
 604
 605         /*
 606          * In a teardown scenario with the frontend involved, we have
 607          * to keep the frontend enabled until the next vblank, and
 608          * only then disable it.
 609          *
 610          * This is due to the fact that the backend will not take into
 611          * account the new configuration (with the plane that used to
 612          * be fed by the frontend now disabled) until we write to the
 613          * commit bit and the hardware fetches the new configuration
 614          * during the next vblank.
 615          *
 616          * So we keep the frontend around in order to prevent any
 617          * visual artifacts.
 618          */
 619         spin_lock(&backend->frontend_lock);
 620         if (backend->frontend_teardown) {
 621                 sun4i_frontend_exit(frontend);
 622                 backend->frontend_teardown = false;
 623         }
 624         spin_unlock(&backend->frontend_lock);
 625 };
 626
 627 static int sun4i_backend_init_sat(struct device *dev) {
 628         struct sun4i_backend *backend = dev_get_drvdata(dev);
 629         int ret;
 630
 631         backend->sat_reset = devm_reset_control_get(dev, "sat");
 632         if (IS_ERR(backend->sat_reset)) {
 633                 dev_err(dev, "Couldn't get the SAT reset line\n");
 634                 return PTR_ERR(backend->sat_reset);
 635         }
 636
 637         ret = reset_control_deassert(backend->sat_reset);
 638         if (ret) {
 639                 dev_err(dev, "Couldn't deassert the SAT reset line\n");
 640                 return ret;
 641         }
 642
 643         backend->sat_clk = devm_clk_get(dev, "sat");
 644         if (IS_ERR(backend->sat_clk)) {
 645                 dev_err(dev, "Couldn't get our SAT clock\n");
 646                 ret = PTR_ERR(backend->sat_clk);
 647                 goto err_assert_reset;
 648         }
 649
 650         ret = clk_prepare_enable(backend->sat_clk);
 651         if (ret) {
 652                 dev_err(dev, "Couldn't enable the SAT clock\n");
 653                 return ret;
 654         }
 655
 656         return 0;
 657
 658 err_assert_reset:
 659         reset_control_assert(backend->sat_reset);
 660         return ret;
 661 }
 662
 663 static int sun4i_backend_free_sat(struct device *dev) {
 664         struct sun4i_backend *backend = dev_get_drvdata(dev);
 665
 666         clk_disable_unprepare(backend->sat_clk);
 667         reset_control_assert(backend->sat_reset);
 668
 669         return 0;
 670 }
 671
 672 /*
 673  * The display backend can take video output from the display frontend, or
 674  * the display enhancement unit on the A80, as input for one it its layers.
 675  * This relationship within the display pipeline is encoded in the device
 676  * tree with of_graph, and we use it here to figure out which backend, if
 677  * there are 2 or more, we are currently probing. The number would be in
 678  * the "reg" property of the upstream output port endpoint.
 679  */
 680 static int sun4i_backend_of_get_id(struct device_node *node)
 681 {
 682         struct device_node *port, *ep;
 683         int ret = -EINVAL;
 684
 685         /* input is port 0 */
 686         port = of_graph_get_port_by_id(node, 0);
 687         if (!port)
 688                 return -EINVAL;
 689
 690         /* try finding an upstream endpoint */
 691         for_each_available_child_of_node(port, ep) {
 692                 struct device_node *remote;
 693                 u32 reg;
 694
 695                 remote = of_graph_get_remote_endpoint(ep);
 696                 if (!remote)
 697                         continue;
 698
 699                 ret = of_property_read_u32(remote, "reg", &reg);
 700                 if (ret)
 701                         continue;
 702
 703                 ret = reg;
 704         }
 705
 706         of_node_put(port);
 707
 708         return ret;
 709 }
 710
 711 /* TODO: This needs to take multiple pipelines into account */
 712 static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv,
 713                                                           struct device_node *node)
 714 {
 715         struct device_node *port, *ep, *remote;
 716         struct sun4i_frontend *frontend;
 717
 718         port = of_graph_get_port_by_id(node, 0);
 719         if (!port)
 720                 return ERR_PTR(-EINVAL);
 721
 722         for_each_available_child_of_node(port, ep) {
 723                 remote = of_graph_get_remote_port_parent(ep);
 724                 if (!remote)
 725                         continue;
 726
 727                 /* does this node match any registered engines? */
 728                 list_for_each_entry(frontend, &drv->frontend_list, list) {
 729                         if (remote == frontend->node) {
 730                                 of_node_put(remote);
 731                                 of_node_put(port);
 732                                 return frontend;
 733                         }
 734                 }
 735         }
 736
 737         return ERR_PTR(-EINVAL);
 738 }
 739
 740 static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
 741         .atomic_begin                   = sun4i_backend_atomic_begin,
 742         .atomic_check                   = sun4i_backend_atomic_check,
 743         .commit                         = sun4i_backend_commit,
 744         .layers_init                    = sun4i_layers_init,
 745         .apply_color_correction         = sun4i_backend_apply_color_correction,
 746         .disable_color_correction       = sun4i_backend_disable_color_correction,
 747         .vblank_quirk                   = sun4i_backend_vblank_quirk,
 748 };
 749
 750 static struct regmap_config sun4i_backend_regmap_config = {
 751         .reg_bits       = 32,
 752         .val_bits       = 32,
 753         .reg_stride     = 4,
 754         .max_register   = 0x5800,
 755 };
 756
 757 static int sun4i_backend_bind(struct device *dev, struct device *master,
 758                               void *data)
 759 {
 760         struct platform_device *pdev = to_platform_device(dev);
 761         struct drm_device *drm = data;
 762         struct sun4i_drv *drv = drm->dev_private;
 763         struct sun4i_backend *backend;
 764         const struct sun4i_backend_quirks *quirks;
 765         struct resource *res;
 766         void __iomem *regs;
 767         int i, ret;
 768
 769         backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
 770         if (!backend)
 771                 return -ENOMEM;
 772         dev_set_drvdata(dev, backend);
 773         spin_lock_init(&backend->frontend_lock);
 774
 775         backend->engine.node = dev->of_node;
 776         backend->engine.ops = &sun4i_backend_engine_ops;
 777         backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
 778         if (backend->engine.id < 0)
 779                 return backend->engine.id;
 780
 781         backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
 782         if (IS_ERR(backend->frontend))
 783                 dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n");
 784
 785         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 786         regs = devm_ioremap_resource(dev, res);
 787         if (IS_ERR(regs))
 788                 return PTR_ERR(regs);
 789
 790         backend->reset = devm_reset_control_get(dev, NULL);
 791         if (IS_ERR(backend->reset)) {
 792                 dev_err(dev, "Couldn't get our reset line\n");
 793                 return PTR_ERR(backend->reset);
 794         }
 795
 796         ret = reset_control_deassert(backend->reset);
 797         if (ret) {
 798                 dev_err(dev, "Couldn't deassert our reset line\n");
 799                 return ret;
 800         }
 801
 802         backend->bus_clk = devm_clk_get(dev, "ahb");
 803         if (IS_ERR(backend->bus_clk)) {
 804                 dev_err(dev, "Couldn't get the backend bus clock\n");
 805                 ret = PTR_ERR(backend->bus_clk);
 806                 goto err_assert_reset;
 807         }
 808         clk_prepare_enable(backend->bus_clk);
 809
 810         backend->mod_clk = devm_clk_get(dev, "mod");
 811         if (IS_ERR(backend->mod_clk)) {
 812                 dev_err(dev, "Couldn't get the backend module clock\n");
 813                 ret = PTR_ERR(backend->mod_clk);
 814                 goto err_disable_bus_clk;
 815         }
 816         clk_prepare_enable(backend->mod_clk);
 817
 818         backend->ram_clk = devm_clk_get(dev, "ram");
 819         if (IS_ERR(backend->ram_clk)) {
 820                 dev_err(dev, "Couldn't get the backend RAM clock\n");
 821                 ret = PTR_ERR(backend->ram_clk);
 822                 goto err_disable_mod_clk;
 823         }
 824         clk_prepare_enable(backend->ram_clk);
 825
 826         if (of_device_is_compatible(dev->of_node,
 827                                     "allwinner,sun8i-a33-display-backend")) {
 828                 ret = sun4i_backend_init_sat(dev);
 829                 if (ret) {
 830                         dev_err(dev, "Couldn't init SAT resources\n");
 831                         goto err_disable_ram_clk;
 832                 }
 833         }
 834
 835         backend->engine.regs = devm_regmap_init_mmio(dev, regs,
 836                                                      &sun4i_backend_regmap_config);
 837         if (IS_ERR(backend->engine.regs)) {
 838                 dev_err(dev, "Couldn't create the backend regmap\n");
 839                 return PTR_ERR(backend->engine.regs);
 840         }
 841
 842         list_add_tail(&backend->engine.list, &drv->engine_list);
 843
 844         /*
 845          * Many of the backend's layer configuration registers have
 846          * undefined default values. This poses a risk as we use
 847          * regmap_update_bits in some places, and don't overwrite
 848          * the whole register.
 849          *
 850          * Clear the registers here to have something predictable.
 851          */
 852         for (i = 0x800; i < 0x1000; i += 4)
 853                 regmap_write(backend->engine.regs, i, 0);
 854
 855         /* Disable registers autoloading */
 856         regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 857                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
 858
 859         /* Enable the backend */
 860         regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 861                      SUN4I_BACKEND_MODCTL_DEBE_EN |
 862                      SUN4I_BACKEND_MODCTL_START_CTL);
 863
 864         /* Set output selection if needed */
 865         quirks = of_device_get_match_data(dev);
 866         if (quirks->needs_output_muxing) {
 867                 /*
 868                  * We assume there is no dynamic muxing of backends
 869                  * and TCONs, so we select the backend with same ID.
 870                  *
 871                  * While dynamic selection might be interesting, since
 872                  * the CRTC is tied to the TCON, while the layers are
 873                  * tied to the backends, this means, we will need to
 874                  * switch between groups of layers. There might not be
 875                  * a way to represent this constraint in DRM.
 876                  */
 877                 regmap_update_bits(backend->engine.regs,
 878                                    SUN4I_BACKEND_MODCTL_REG,
 879                                    SUN4I_BACKEND_MODCTL_OUT_SEL,
 880                                    (backend->engine.id
 881                                     ? SUN4I_BACKEND_MODCTL_OUT_LCD1
 882                                     : SUN4I_BACKEND_MODCTL_OUT_LCD0));
 883         }
 884
 885         return 0;
 886
 887 err_disable_ram_clk:
 888         clk_disable_unprepare(backend->ram_clk);
 889 err_disable_mod_clk:
 890         clk_disable_unprepare(backend->mod_clk);
 891 err_disable_bus_clk:
 892         clk_disable_unprepare(backend->bus_clk);
 893 err_assert_reset:
 894         reset_control_assert(backend->reset);
 895         return ret;
 896 }
 897
 898 static void sun4i_backend_unbind(struct device *dev, struct device *master,
 899                                  void *data)
 900 {
 901         struct sun4i_backend *backend = dev_get_drvdata(dev);
 902
 903         list_del(&backend->engine.list);
 904
 905         if (of_device_is_compatible(dev->of_node,
 906                                     "allwinner,sun8i-a33-display-backend"))
 907                 sun4i_backend_free_sat(dev);
 908
 909         clk_disable_unprepare(backend->ram_clk);
 910         clk_disable_unprepare(backend->mod_clk);
 911         clk_disable_unprepare(backend->bus_clk);
 912         reset_control_assert(backend->reset);
 913 }
 914
 915 static const struct component_ops sun4i_backend_ops = {
 916         .bind   = sun4i_backend_bind,
 917         .unbind = sun4i_backend_unbind,
 918 };
 919
 920 static int sun4i_backend_probe(struct platform_device *pdev)
 921 {
 922         return component_add(&pdev->dev, &sun4i_backend_ops);
 923 }
 924
 925 static int sun4i_backend_remove(struct platform_device *pdev)
 926 {
 927         component_del(&pdev->dev, &sun4i_backend_ops);
 928
 929         return 0;
 930 }
 931
 932 static const struct sun4i_backend_quirks sun4i_backend_quirks = {
 933         .needs_output_muxing = true,
 934 };
 935
 936 static const struct sun4i_backend_quirks sun5i_backend_quirks = {
 937 };
 938
 939 static const struct sun4i_backend_quirks sun6i_backend_quirks = {
 940 };
 941
 942 static const struct sun4i_backend_quirks sun7i_backend_quirks = {
 943         .needs_output_muxing = true,
 944 };
 945
 946 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = {
 947 };
 948
 949 static const struct sun4i_backend_quirks sun9i_backend_quirks = {
 950 };
 951
 952 static const struct of_device_id sun4i_backend_of_table[] = {
 953         {
 954                 .compatible = "allwinner,sun4i-a10-display-backend",
 955                 .data = &sun4i_backend_quirks,
 956         },
 957         {
 958                 .compatible = "allwinner,sun5i-a13-display-backend",
 959                 .data = &sun5i_backend_quirks,
 960         },
 961         {
 962                 .compatible = "allwinner,sun6i-a31-display-backend",
 963                 .data = &sun6i_backend_quirks,
 964         },
 965         {
 966                 .compatible = "allwinner,sun7i-a20-display-backend",
 967                 .data = &sun7i_backend_quirks,
 968         },
 969         {
 970                 .compatible = "allwinner,sun8i-a33-display-backend",
 971                 .data = &sun8i_a33_backend_quirks,
 972         },
 973         {
 974                 .compatible = "allwinner,sun9i-a80-display-backend",
 975                 .data = &sun9i_backend_quirks,
 976         },
 977         { }
 978 };
 979 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
 980
 981 static struct platform_driver sun4i_backend_platform_driver = {
 982         .probe          = sun4i_backend_probe,
 983         .remove         = sun4i_backend_remove,
 984         .driver         = {
 985                 .name           = "sun4i-backend",
 986                 .of_match_table = sun4i_backend_of_table,
 987         },
 988 };
 989 module_platform_driver(sun4i_backend_platform_driver);
 990
 991 MODULE_AUTHOR("Maxime Ripard <[email protected]>");
 992 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
 993 MODULE_LICENSE("GPL");