drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 /* Here's the desired hotplug mode */
  40 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45                            ADPA_CRT_HOTPLUG_ENABLE)
  46
  47 struct intel_crt {
  48         struct intel_encoder base;
  49         /* DPMS state is stored in the connector, which we need in the
  50          * encoder's enable/disable callbacks */
  51         struct intel_connector *connector;
  52         bool force_hotplug_required;
  53         i915_reg_t adpa_reg;
  54 };
  55
  56 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57 {
  58         return container_of(encoder, struct intel_crt, base);
  59 }
  60
  61 static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62 {
  63         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64 }
  65
  66 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67                                    enum pipe *pipe)
  68 {
  69         struct drm_device *dev = encoder->base.dev;
  70         struct drm_i915_private *dev_priv = to_i915(dev);
  71         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72         u32 tmp;
  73         bool ret;
  74
  75         if (!intel_display_power_get_if_enabled(dev_priv,
  76                                                 encoder->power_domain))
  77                 return false;
  78
  79         ret = false;
  80
  81         tmp = I915_READ(crt->adpa_reg);
  82
  83         if (!(tmp & ADPA_DAC_ENABLE))
  84                 goto out;
  85
  86         if (HAS_PCH_CPT(dev_priv))
  87                 *pipe = PORT_TO_PIPE_CPT(tmp);
  88         else
  89                 *pipe = PORT_TO_PIPE(tmp);
  90
  91         ret = true;
  92 out:
  93         intel_display_power_put(dev_priv, encoder->power_domain);
  94
  95         return ret;
  96 }
  97
  98 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  99 {
 100         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 101         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 102         u32 tmp, flags = 0;
 103
 104         tmp = I915_READ(crt->adpa_reg);
 105
 106         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 107                 flags |= DRM_MODE_FLAG_PHSYNC;
 108         else
 109                 flags |= DRM_MODE_FLAG_NHSYNC;
 110
 111         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 112                 flags |= DRM_MODE_FLAG_PVSYNC;
 113         else
 114                 flags |= DRM_MODE_FLAG_NVSYNC;
 115
 116         return flags;
 117 }
 118
 119 static void intel_crt_get_config(struct intel_encoder *encoder,
 120                                  struct intel_crtc_state *pipe_config)
 121 {
 122         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 123
 124         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 125
 126         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 127 }
 128
 129 static void hsw_crt_get_config(struct intel_encoder *encoder,
 130                                struct intel_crtc_state *pipe_config)
 131 {
 132         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 133
 134         intel_ddi_get_config(encoder, pipe_config);
 135
 136         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 137                                               DRM_MODE_FLAG_NHSYNC |
 138                                               DRM_MODE_FLAG_PVSYNC |
 139                                               DRM_MODE_FLAG_NVSYNC);
 140         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 141
 142         pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
 143 }
 144
 145 /* Note: The caller is required to filter out dpms modes not supported by the
 146  * platform. */
 147 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 148                                const struct intel_crtc_state *crtc_state,
 149                                int mode)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 152         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 153         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 154         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
 155         u32 adpa;
 156
 157         if (INTEL_GEN(dev_priv) >= 5)
 158                 adpa = ADPA_HOTPLUG_BITS;
 159         else
 160                 adpa = 0;
 161
 162         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 163                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 164         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 165                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 166
 167         /* For CPT allow 3 pipe config, for others just use A or B */
 168         if (HAS_PCH_LPT(dev_priv))
 169                 ; /* Those bits don't exist here */
 170         else if (HAS_PCH_CPT(dev_priv))
 171                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 172         else if (crtc->pipe == 0)
 173                 adpa |= ADPA_PIPE_A_SELECT;
 174         else
 175                 adpa |= ADPA_PIPE_B_SELECT;
 176
 177         if (!HAS_PCH_SPLIT(dev_priv))
 178                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
 179
 180         switch (mode) {
 181         case DRM_MODE_DPMS_ON:
 182                 adpa |= ADPA_DAC_ENABLE;
 183                 break;
 184         case DRM_MODE_DPMS_STANDBY:
 185                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 186                 break;
 187         case DRM_MODE_DPMS_SUSPEND:
 188                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 189                 break;
 190         case DRM_MODE_DPMS_OFF:
 191                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 192                 break;
 193         }
 194
 195         I915_WRITE(crt->adpa_reg, adpa);
 196 }
 197
 198 static void intel_disable_crt(struct intel_encoder *encoder,
 199                               const struct intel_crtc_state *old_crtc_state,
 200                               const struct drm_connector_state *old_conn_state)
 201 {
 202         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 203 }
 204
 205 static void pch_disable_crt(struct intel_encoder *encoder,
 206                             const struct intel_crtc_state *old_crtc_state,
 207                             const struct drm_connector_state *old_conn_state)
 208 {
 209 }
 210
 211 static void pch_post_disable_crt(struct intel_encoder *encoder,
 212                                  const struct intel_crtc_state *old_crtc_state,
 213                                  const struct drm_connector_state *old_conn_state)
 214 {
 215         intel_disable_crt(encoder, old_crtc_state, old_conn_state);
 216 }
 217
 218 static void hsw_disable_crt(struct intel_encoder *encoder,
 219                             const struct intel_crtc_state *old_crtc_state,
 220                             const struct drm_connector_state *old_conn_state)
 221 {
 222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 223
 224         WARN_ON(!old_crtc_state->has_pch_encoder);
 225
 226         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 227 }
 228
 229 static void hsw_post_disable_crt(struct intel_encoder *encoder,
 230                                  const struct intel_crtc_state *old_crtc_state,
 231                                  const struct drm_connector_state *old_conn_state)
 232 {
 233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 234
 235         pch_post_disable_crt(encoder, old_crtc_state, old_conn_state);
 236
 237         lpt_disable_pch_transcoder(dev_priv);
 238         lpt_disable_iclkip(dev_priv);
 239
 240         intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state);
 241
 242         WARN_ON(!old_crtc_state->has_pch_encoder);
 243
 244         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 245 }
 246
 247 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder,
 248                                    const struct intel_crtc_state *crtc_state,
 249                                    const struct drm_connector_state *conn_state)
 250 {
 251         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 252
 253         WARN_ON(!crtc_state->has_pch_encoder);
 254
 255         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 256 }
 257
 258 static void hsw_pre_enable_crt(struct intel_encoder *encoder,
 259                                const struct intel_crtc_state *crtc_state,
 260                                const struct drm_connector_state *conn_state)
 261 {
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 264         enum pipe pipe = crtc->pipe;
 265
 266         WARN_ON(!crtc_state->has_pch_encoder);
 267
 268         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 269
 270         dev_priv->display.fdi_link_train(crtc, crtc_state);
 271 }
 272
 273 static void hsw_enable_crt(struct intel_encoder *encoder,
 274                            const struct intel_crtc_state *crtc_state,
 275                            const struct drm_connector_state *conn_state)
 276 {
 277         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 278         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 279         enum pipe pipe = crtc->pipe;
 280
 281         WARN_ON(!crtc_state->has_pch_encoder);
 282
 283         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 284
 285         intel_wait_for_vblank(dev_priv, pipe);
 286         intel_wait_for_vblank(dev_priv, pipe);
 287         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 288         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 289 }
 290
 291 static void intel_enable_crt(struct intel_encoder *encoder,
 292                              const struct intel_crtc_state *crtc_state,
 293                              const struct drm_connector_state *conn_state)
 294 {
 295         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 296 }
 297
 298 static enum drm_mode_status
 299 intel_crt_mode_valid(struct drm_connector *connector,
 300                      struct drm_display_mode *mode)
 301 {
 302         struct drm_device *dev = connector->dev;
 303         struct drm_i915_private *dev_priv = to_i915(dev);
 304         int max_dotclk = dev_priv->max_dotclk_freq;
 305         int max_clock;
 306
 307         if (mode->clock < 25000)
 308                 return MODE_CLOCK_LOW;
 309
 310         if (HAS_PCH_LPT(dev_priv))
 311                 max_clock = 180000;
 312         else if (IS_VALLEYVIEW(dev_priv))
 313                 /*
 314                  * 270 MHz due to current DPLL limits,
 315                  * DAC limit supposedly 355 MHz.
 316                  */
 317                 max_clock = 270000;
 318         else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
 319                 max_clock = 400000;
 320         else
 321                 max_clock = 350000;
 322         if (mode->clock > max_clock)
 323                 return MODE_CLOCK_HIGH;
 324
 325         if (mode->clock > max_dotclk)
 326                 return MODE_CLOCK_HIGH;
 327
 328         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 329         if (HAS_PCH_LPT(dev_priv) &&
 330             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 331                 return MODE_CLOCK_HIGH;
 332
 333         return MODE_OK;
 334 }
 335
 336 static bool intel_crt_compute_config(struct intel_encoder *encoder,
 337                                      struct intel_crtc_state *pipe_config,
 338                                      struct drm_connector_state *conn_state)
 339 {
 340         return true;
 341 }
 342
 343 static bool pch_crt_compute_config(struct intel_encoder *encoder,
 344                                    struct intel_crtc_state *pipe_config,
 345                                    struct drm_connector_state *conn_state)
 346 {
 347         pipe_config->has_pch_encoder = true;
 348
 349         return true;
 350 }
 351
 352 static bool hsw_crt_compute_config(struct intel_encoder *encoder,
 353                                    struct intel_crtc_state *pipe_config,
 354                                    struct drm_connector_state *conn_state)
 355 {
 356         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 357
 358         pipe_config->has_pch_encoder = true;
 359
 360         /* LPT FDI RX only supports 8bpc. */
 361         if (HAS_PCH_LPT(dev_priv)) {
 362                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 363                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
 364                         return false;
 365                 }
 366
 367                 pipe_config->pipe_bpp = 24;
 368         }
 369
 370         /* FDI must always be 2.7 GHz */
 371         pipe_config->port_clock = 135000 * 2;
 372
 373         return true;
 374 }
 375
 376 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 377 {
 378         struct drm_device *dev = connector->dev;
 379         struct intel_crt *crt = intel_attached_crt(connector);
 380         struct drm_i915_private *dev_priv = to_i915(dev);
 381         u32 adpa;
 382         bool ret;
 383
 384         /* The first time through, trigger an explicit detection cycle */
 385         if (crt->force_hotplug_required) {
 386                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 387                 u32 save_adpa;
 388
 389                 crt->force_hotplug_required = 0;
 390
 391                 save_adpa = adpa = I915_READ(crt->adpa_reg);
 392                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 393
 394                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 395                 if (turn_off_dac)
 396                         adpa &= ~ADPA_DAC_ENABLE;
 397
 398                 I915_WRITE(crt->adpa_reg, adpa);
 399
 400                 if (intel_wait_for_register(dev_priv,
 401                                             crt->adpa_reg,
 402                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 403                                             1000))
 404                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 405
 406                 if (turn_off_dac) {
 407                         I915_WRITE(crt->adpa_reg, save_adpa);
 408                         POSTING_READ(crt->adpa_reg);
 409                 }
 410         }
 411
 412         /* Check the status to see if both blue and green are on now */
 413         adpa = I915_READ(crt->adpa_reg);
 414         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 415                 ret = true;
 416         else
 417                 ret = false;
 418         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
 419
 420         return ret;
 421 }
 422
 423 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 424 {
 425         struct drm_device *dev = connector->dev;
 426         struct intel_crt *crt = intel_attached_crt(connector);
 427         struct drm_i915_private *dev_priv = to_i915(dev);
 428         bool reenable_hpd;
 429         u32 adpa;
 430         bool ret;
 431         u32 save_adpa;
 432
 433         /*
 434          * Doing a force trigger causes a hpd interrupt to get sent, which can
 435          * get us stuck in a loop if we're polling:
 436          *  - We enable power wells and reset the ADPA
 437          *  - output_poll_exec does force probe on VGA, triggering a hpd
 438          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 439          *  - output_poll_exec shuts off the ADPA, unlocks
 440          *    dev->mode_config.mutex
 441          *  - HPD handler runs, resets ADPA and brings us back to the start
 442          *
 443          * Just disable HPD interrupts here to prevent this
 444          */
 445         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 446
 447         save_adpa = adpa = I915_READ(crt->adpa_reg);
 448         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 449
 450         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 451
 452         I915_WRITE(crt->adpa_reg, adpa);
 453
 454         if (intel_wait_for_register(dev_priv,
 455                                     crt->adpa_reg,
 456                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
 457                                     1000)) {
 458                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 459                 I915_WRITE(crt->adpa_reg, save_adpa);
 460         }
 461
 462         /* Check the status to see if both blue and green are on now */
 463         adpa = I915_READ(crt->adpa_reg);
 464         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 465                 ret = true;
 466         else
 467                 ret = false;
 468
 469         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 470
 471         if (reenable_hpd)
 472                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 473
 474         return ret;
 475 }
 476
 477 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 478 {
 479         struct drm_device *dev = connector->dev;
 480         struct drm_i915_private *dev_priv = to_i915(dev);
 481         u32 stat;
 482         bool ret = false;
 483         int i, tries = 0;
 484
 485         if (HAS_PCH_SPLIT(dev_priv))
 486                 return intel_ironlake_crt_detect_hotplug(connector);
 487
 488         if (IS_VALLEYVIEW(dev_priv))
 489                 return valleyview_crt_detect_hotplug(connector);
 490
 491         /*
 492          * On 4 series desktop, CRT detect sequence need to be done twice
 493          * to get a reliable result.
 494          */
 495
 496         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv))
 497                 tries = 2;
 498         else
 499                 tries = 1;
 500
 501         for (i = 0; i < tries ; i++) {
 502                 /* turn on the FORCE_DETECT */
 503                 i915_hotplug_interrupt_update(dev_priv,
 504                                               CRT_HOTPLUG_FORCE_DETECT,
 505                                               CRT_HOTPLUG_FORCE_DETECT);
 506                 /* wait for FORCE_DETECT to go off */
 507                 if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
 508                                             CRT_HOTPLUG_FORCE_DETECT, 0,
 509                                             1000))
 510                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
 511         }
 512
 513         stat = I915_READ(PORT_HOTPLUG_STAT);
 514         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 515                 ret = true;
 516
 517         /* clear the interrupt we just generated, if any */
 518         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 519
 520         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 521
 522         return ret;
 523 }
 524
 525 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
 526                                 struct i2c_adapter *i2c)
 527 {
 528         struct edid *edid;
 529
 530         edid = drm_get_edid(connector, i2c);
 531
 532         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
 533                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 534                 intel_gmbus_force_bit(i2c, true);
 535                 edid = drm_get_edid(connector, i2c);
 536                 intel_gmbus_force_bit(i2c, false);
 537         }
 538
 539         return edid;
 540 }
 541
 542 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 543 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 544                                 struct i2c_adapter *adapter)
 545 {
 546         struct edid *edid;
 547         int ret;
 548
 549         edid = intel_crt_get_edid(connector, adapter);
 550         if (!edid)
 551                 return 0;
 552
 553         ret = intel_connector_update_modes(connector, edid);
 554         kfree(edid);
 555
 556         return ret;
 557 }
 558
 559 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 560 {
 561         struct intel_crt *crt = intel_attached_crt(connector);
 562         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 563         struct edid *edid;
 564         struct i2c_adapter *i2c;
 565         bool ret = false;
 566
 567         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 568
 569         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 570         edid = intel_crt_get_edid(connector, i2c);
 571
 572         if (edid) {
 573                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
 574
 575                 /*
 576                  * This may be a DVI-I connector with a shared DDC
 577                  * link between analog and digital outputs, so we
 578                  * have to check the EDID input spec of the attached device.
 579                  */
 580                 if (!is_digital) {
 581                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
 582                         ret = true;
 583                 } else {
 584                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 585                 }
 586         } else {
 587                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
 588         }
 589
 590         kfree(edid);
 591
 592         return ret;
 593 }
 594
 595 static enum drm_connector_status
 596 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
 597 {
 598         struct drm_device *dev = crt->base.base.dev;
 599         struct drm_i915_private *dev_priv = to_i915(dev);
 600         uint32_t save_bclrpat;
 601         uint32_t save_vtotal;
 602         uint32_t vtotal, vactive;
 603         uint32_t vsample;
 604         uint32_t vblank, vblank_start, vblank_end;
 605         uint32_t dsl;
 606         i915_reg_t bclrpat_reg, vtotal_reg,
 607                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
 608         uint8_t st00;
 609         enum drm_connector_status status;
 610
 611         DRM_DEBUG_KMS("starting load-detect on CRT\n");
 612
 613         bclrpat_reg = BCLRPAT(pipe);
 614         vtotal_reg = VTOTAL(pipe);
 615         vblank_reg = VBLANK(pipe);
 616         vsync_reg = VSYNC(pipe);
 617         pipeconf_reg = PIPECONF(pipe);
 618         pipe_dsl_reg = PIPEDSL(pipe);
 619
 620         save_bclrpat = I915_READ(bclrpat_reg);
 621         save_vtotal = I915_READ(vtotal_reg);
 622         vblank = I915_READ(vblank_reg);
 623
 624         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 625         vactive = (save_vtotal & 0x7ff) + 1;
 626
 627         vblank_start = (vblank & 0xfff) + 1;
 628         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 629
 630         /* Set the border color to purple. */
 631         I915_WRITE(bclrpat_reg, 0x500050);
 632
 633         if (!IS_GEN2(dev_priv)) {
 634                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 635                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 636                 POSTING_READ(pipeconf_reg);
 637                 /* Wait for next Vblank to substitue
 638                  * border color for Color info */
 639                 intel_wait_for_vblank(dev_priv, pipe);
 640                 st00 = I915_READ8(_VGA_MSR_WRITE);
 641                 status = ((st00 & (1 << 4)) != 0) ?
 642                         connector_status_connected :
 643                         connector_status_disconnected;
 644
 645                 I915_WRITE(pipeconf_reg, pipeconf);
 646         } else {
 647                 bool restore_vblank = false;
 648                 int count, detect;
 649
 650                 /*
 651                 * If there isn't any border, add some.
 652                 * Yes, this will flicker
 653                 */
 654                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 655                         uint32_t vsync = I915_READ(vsync_reg);
 656                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 657
 658                         vblank_start = vsync_start;
 659                         I915_WRITE(vblank_reg,
 660                                    (vblank_start - 1) |
 661                                    ((vblank_end - 1) << 16));
 662                         restore_vblank = true;
 663                 }
 664                 /* sample in the vertical border, selecting the larger one */
 665                 if (vblank_start - vactive >= vtotal - vblank_end)
 666                         vsample = (vblank_start + vactive) >> 1;
 667                 else
 668                         vsample = (vtotal + vblank_end) >> 1;
 669
 670                 /*
 671                  * Wait for the border to be displayed
 672                  */
 673                 while (I915_READ(pipe_dsl_reg) >= vactive)
 674                         ;
 675                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 676                         ;
 677                 /*
 678                  * Watch ST00 for an entire scanline
 679                  */
 680                 detect = 0;
 681                 count = 0;
 682                 do {
 683                         count++;
 684                         /* Read the ST00 VGA status register */
 685                         st00 = I915_READ8(_VGA_MSR_WRITE);
 686                         if (st00 & (1 << 4))
 687                                 detect++;
 688                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 689
 690                 /* restore vblank if necessary */
 691                 if (restore_vblank)
 692                         I915_WRITE(vblank_reg, vblank);
 693                 /*
 694                  * If more than 3/4 of the scanline detected a monitor,
 695                  * then it is assumed to be present. This works even on i830,
 696                  * where there isn't any way to force the border color across
 697                  * the screen
 698                  */
 699                 status = detect * 4 > count * 3 ?
 700                          connector_status_connected :
 701                          connector_status_disconnected;
 702         }
 703
 704         /* Restore previous settings */
 705         I915_WRITE(bclrpat_reg, save_bclrpat);
 706
 707         return status;
 708 }
 709
 710 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 711 {
 712         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 713         return 1;
 714 }
 715
 716 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 717         {
 718                 .callback = intel_spurious_crt_detect_dmi_callback,
 719                 .ident = "ACER ZGB",
 720                 .matches = {
 721                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 722                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 723                 },
 724         },
 725         {
 726                 .callback = intel_spurious_crt_detect_dmi_callback,
 727                 .ident = "Intel DZ77BH-55K",
 728                 .matches = {
 729                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 730                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 731                 },
 732         },
 733         { }
 734 };
 735
 736 static int
 737 intel_crt_detect(struct drm_connector *connector,
 738                  struct drm_modeset_acquire_ctx *ctx,
 739                  bool force)
 740 {
 741         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 742         struct intel_crt *crt = intel_attached_crt(connector);
 743         struct intel_encoder *intel_encoder = &crt->base;
 744         int status, ret;
 745         struct intel_load_detect_pipe tmp;
 746
 747         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
 748                       connector->base.id, connector->name,
 749                       force);
 750
 751         if (i915_modparams.load_detect_test) {
 752                 intel_display_power_get(dev_priv, intel_encoder->power_domain);
 753                 goto load_detect;
 754         }
 755
 756         /* Skip machines without VGA that falsely report hotplug events */
 757         if (dmi_check_system(intel_spurious_crt_detect))
 758                 return connector_status_disconnected;
 759
 760         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 761
 762         if (I915_HAS_HOTPLUG(dev_priv)) {
 763                 /* We can not rely on the HPD pin always being correctly wired
 764                  * up, for example many KVM do not pass it through, and so
 765                  * only trust an assertion that the monitor is connected.
 766                  */
 767                 if (intel_crt_detect_hotplug(connector)) {
 768                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
 769                         status = connector_status_connected;
 770                         goto out;
 771                 } else
 772                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
 773         }
 774
 775         if (intel_crt_detect_ddc(connector)) {
 776                 status = connector_status_connected;
 777                 goto out;
 778         }
 779
 780         /* Load detection is broken on HPD capable machines. Whoever wants a
 781          * broken monitor (without edid) to work behind a broken kvm (that fails
 782          * to have the right resistors for HP detection) needs to fix this up.
 783          * For now just bail out. */
 784         if (I915_HAS_HOTPLUG(dev_priv)) {
 785                 status = connector_status_disconnected;
 786                 goto out;
 787         }
 788
 789 load_detect:
 790         if (!force) {
 791                 status = connector->status;
 792                 goto out;
 793         }
 794
 795         /* for pre-945g platforms use load detect */
 796         ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
 797         if (ret > 0) {
 798                 if (intel_crt_detect_ddc(connector))
 799                         status = connector_status_connected;
 800                 else if (INTEL_GEN(dev_priv) < 4)
 801                         status = intel_crt_load_detect(crt,
 802                                 to_intel_crtc(connector->state->crtc)->pipe);
 803                 else if (i915_modparams.load_detect_test)
 804                         status = connector_status_disconnected;
 805                 else
 806                         status = connector_status_unknown;
 807                 intel_release_load_detect_pipe(connector, &tmp, ctx);
 808         } else if (ret == 0) {
 809                 status = connector_status_unknown;
 810         } else {
 811                 status = ret;
 812         }
 813
 814 out:
 815         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 816         return status;
 817 }
 818
 819 static void intel_crt_destroy(struct drm_connector *connector)
 820 {
 821         drm_connector_cleanup(connector);
 822         kfree(connector);
 823 }
 824
 825 static int intel_crt_get_modes(struct drm_connector *connector)
 826 {
 827         struct drm_device *dev = connector->dev;
 828         struct drm_i915_private *dev_priv = to_i915(dev);
 829         struct intel_crt *crt = intel_attached_crt(connector);
 830         struct intel_encoder *intel_encoder = &crt->base;
 831         int ret;
 832         struct i2c_adapter *i2c;
 833
 834         intel_display_power_get(dev_priv, intel_encoder->power_domain);
 835
 836         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
 837         ret = intel_crt_ddc_get_modes(connector, i2c);
 838         if (ret || !IS_G4X(dev_priv))
 839                 goto out;
 840
 841         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 842         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 843         ret = intel_crt_ddc_get_modes(connector, i2c);
 844
 845 out:
 846         intel_display_power_put(dev_priv, intel_encoder->power_domain);
 847
 848         return ret;
 849 }
 850
 851 void intel_crt_reset(struct drm_encoder *encoder)
 852 {
 853         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 854         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 855
 856         if (INTEL_GEN(dev_priv) >= 5) {
 857                 u32 adpa;
 858
 859                 adpa = I915_READ(crt->adpa_reg);
 860                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 861                 adpa |= ADPA_HOTPLUG_BITS;
 862                 I915_WRITE(crt->adpa_reg, adpa);
 863                 POSTING_READ(crt->adpa_reg);
 864
 865                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
 866                 crt->force_hotplug_required = 1;
 867         }
 868
 869 }
 870
 871 /*
 872  * Routines for controlling stuff on the analog port
 873  */
 874
 875 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 876         .fill_modes = drm_helper_probe_single_connector_modes,
 877         .late_register = intel_connector_register,
 878         .early_unregister = intel_connector_unregister,
 879         .destroy = intel_crt_destroy,
 880         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 881         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 882 };
 883
 884 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 885         .detect_ctx = intel_crt_detect,
 886         .mode_valid = intel_crt_mode_valid,
 887         .get_modes = intel_crt_get_modes,
 888 };
 889
 890 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 891         .reset = intel_crt_reset,
 892         .destroy = intel_encoder_destroy,
 893 };
 894
 895 void intel_crt_init(struct drm_i915_private *dev_priv)
 896 {
 897         struct drm_connector *connector;
 898         struct intel_crt *crt;
 899         struct intel_connector *intel_connector;
 900         i915_reg_t adpa_reg;
 901         u32 adpa;
 902
 903         if (HAS_PCH_SPLIT(dev_priv))
 904                 adpa_reg = PCH_ADPA;
 905         else if (IS_VALLEYVIEW(dev_priv))
 906                 adpa_reg = VLV_ADPA;
 907         else
 908                 adpa_reg = ADPA;
 909
 910         adpa = I915_READ(adpa_reg);
 911         if ((adpa & ADPA_DAC_ENABLE) == 0) {
 912                 /*
 913                  * On some machines (some IVB at least) CRT can be
 914                  * fused off, but there's no known fuse bit to
 915                  * indicate that. On these machine the ADPA register
 916                  * works normally, except the DAC enable bit won't
 917                  * take. So the only way to tell is attempt to enable
 918                  * it and see what happens.
 919                  */
 920                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
 921                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
 922                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
 923                         return;
 924                 I915_WRITE(adpa_reg, adpa);
 925         }
 926
 927         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
 928         if (!crt)
 929                 return;
 930
 931         intel_connector = intel_connector_alloc();
 932         if (!intel_connector) {
 933                 kfree(crt);
 934                 return;
 935         }
 936
 937         connector = &intel_connector->base;
 938         crt->connector = intel_connector;
 939         drm_connector_init(&dev_priv->drm, &intel_connector->base,
 940                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 941
 942         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
 943                          DRM_MODE_ENCODER_DAC, "CRT");
 944
 945         intel_connector_attach_encoder(intel_connector, &crt->base);
 946
 947         crt->base.type = INTEL_OUTPUT_ANALOG;
 948         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
 949         if (IS_I830(dev_priv))
 950                 crt->base.crtc_mask = (1 << 0);
 951         else
 952                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 953
 954         if (IS_GEN2(dev_priv))
 955                 connector->interlace_allowed = 0;
 956         else
 957                 connector->interlace_allowed = 1;
 958         connector->doublescan_allowed = 0;
 959
 960         crt->adpa_reg = adpa_reg;
 961
 962         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
 963
 964         if (I915_HAS_HOTPLUG(dev_priv) &&
 965             !dmi_check_system(intel_spurious_crt_detect)) {
 966                 crt->base.hpd_pin = HPD_CRT;
 967                 crt->base.hotplug = intel_encoder_hotplug;
 968         }
 969
 970         if (HAS_DDI(dev_priv)) {
 971                 crt->base.port = PORT_E;
 972                 crt->base.get_config = hsw_crt_get_config;
 973                 crt->base.get_hw_state = intel_ddi_get_hw_state;
 974                 crt->base.compute_config = hsw_crt_compute_config;
 975                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
 976                 crt->base.pre_enable = hsw_pre_enable_crt;
 977                 crt->base.enable = hsw_enable_crt;
 978                 crt->base.disable = hsw_disable_crt;
 979                 crt->base.post_disable = hsw_post_disable_crt;
 980         } else {
 981                 if (HAS_PCH_SPLIT(dev_priv)) {
 982                         crt->base.compute_config = pch_crt_compute_config;
 983                         crt->base.disable = pch_disable_crt;
 984                         crt->base.post_disable = pch_post_disable_crt;
 985                 } else {
 986                         crt->base.compute_config = intel_crt_compute_config;
 987                         crt->base.disable = intel_disable_crt;
 988                 }
 989                 crt->base.port = PORT_NONE;
 990                 crt->base.get_config = intel_crt_get_config;
 991                 crt->base.get_hw_state = intel_crt_get_hw_state;
 992                 crt->base.enable = intel_enable_crt;
 993         }
 994         intel_connector->get_hw_state = intel_connector_get_hw_state;
 995
 996         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 997
 998         if (!I915_HAS_HOTPLUG(dev_priv))
 999                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1000
1001         /*
1002          * Configure the automatic hotplug detection stuff
1003          */
1004         crt->force_hotplug_required = 0;
1005
1006         /*
1007          * TODO: find a proper way to discover whether we need to set the the
1008          * polarity and link reversal bits or not, instead of relying on the
1009          * BIOS.
1010          */
1011         if (HAS_PCH_LPT(dev_priv)) {
1012                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1013                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1014
1015                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
1016         }
1017
1018         intel_crt_reset(&crt->base.base);
1019 }