drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 421 {
 422         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 423                 333333 : 320000;
 424
 425         /*
 426          * We seem to get an unstable or solid color picture at 200MHz.
 427          * Not sure what's wrong. For now use 200MHz only when all pipes
 428          * are off.
 429          */
 430         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 431                 return 400000;
 432         else if (min_cdclk > 266667)
 433                 return freq_320;
 434         else if (min_cdclk > 0)
 435                 return 266667;
 436         else
 437                 return 200000;
 438 }
 439
 440 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 441 {
 442         if (IS_VALLEYVIEW(dev_priv)) {
 443                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 444                         return 2;
 445                 else if (cdclk >= 266667)
 446                         return 1;
 447                 else
 448                         return 0;
 449         } else {
 450                 /*
 451                  * Specs are full of misinformation, but testing on actual
 452                  * hardware has shown that we just need to write the desired
 453                  * CCK divider into the Punit register.
 454                  */
 455                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 456         }
 457 }
 458
 459 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 460                           struct intel_cdclk_state *cdclk_state)
 461 {
 462         u32 val;
 463
 464         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 465         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 466                                                CCK_DISPLAY_CLOCK_CONTROL,
 467                                                cdclk_state->vco);
 468
 469         mutex_lock(&dev_priv->pcu_lock);
 470         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 471         mutex_unlock(&dev_priv->pcu_lock);
 472
 473         if (IS_VALLEYVIEW(dev_priv))
 474                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
 475                         DSPFREQGUAR_SHIFT;
 476         else
 477                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 478                         DSPFREQGUAR_SHIFT_CHV;
 479 }
 480
 481 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 482 {
 483         unsigned int credits, default_credits;
 484
 485         if (IS_CHERRYVIEW(dev_priv))
 486                 default_credits = PFI_CREDIT(12);
 487         else
 488                 default_credits = PFI_CREDIT(8);
 489
 490         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 491                 /* CHV suggested value is 31 or 63 */
 492                 if (IS_CHERRYVIEW(dev_priv))
 493                         credits = PFI_CREDIT_63;
 494                 else
 495                         credits = PFI_CREDIT(15);
 496         } else {
 497                 credits = default_credits;
 498         }
 499
 500         /*
 501          * WA - write default credits before re-programming
 502          * FIXME: should we also set the resend bit here?
 503          */
 504         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 505                    default_credits);
 506
 507         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 508                    credits | PFI_CREDIT_RESEND);
 509
 510         /*
 511          * FIXME is this guaranteed to clear
 512          * immediately or should we poll for it?
 513          */
 514         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 515 }
 516
 517 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 518                           const struct intel_cdclk_state *cdclk_state)
 519 {
 520         int cdclk = cdclk_state->cdclk;
 521         u32 val, cmd = cdclk_state->voltage_level;
 522
 523         switch (cdclk) {
 524         case 400000:
 525         case 333333:
 526         case 320000:
 527         case 266667:
 528         case 200000:
 529                 break;
 530         default:
 531                 MISSING_CASE(cdclk);
 532                 return;
 533         }
 534
 535         /* There are cases where we can end up here with power domains
 536          * off and a CDCLK frequency other than the minimum, like when
 537          * issuing a modeset without actually changing any display after
 538          * a system suspend.  So grab the PIPE-A domain, which covers
 539          * the HW blocks needed for the following programming.
 540          */
 541         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 542
 543         mutex_lock(&dev_priv->pcu_lock);
 544         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 545         val &= ~DSPFREQGUAR_MASK;
 546         val |= (cmd << DSPFREQGUAR_SHIFT);
 547         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 548         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 549                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 550                      50)) {
 551                 DRM_ERROR("timed out waiting for CDclk change\n");
 552         }
 553         mutex_unlock(&dev_priv->pcu_lock);
 554
 555         mutex_lock(&dev_priv->sb_lock);
 556
 557         if (cdclk == 400000) {
 558                 u32 divider;
 559
 560                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 561                                             cdclk) - 1;
 562
 563                 /* adjust cdclk divider */
 564                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 565                 val &= ~CCK_FREQUENCY_VALUES;
 566                 val |= divider;
 567                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 568
 569                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 570                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 571                              50))
 572                         DRM_ERROR("timed out waiting for CDclk change\n");
 573         }
 574
 575         /* adjust self-refresh exit latency value */
 576         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 577         val &= ~0x7f;
 578
 579         /*
 580          * For high bandwidth configs, we set a higher latency in the bunit
 581          * so that the core display fetch happens in time to avoid underruns.
 582          */
 583         if (cdclk == 400000)
 584                 val |= 4500 / 250; /* 4.5 usec */
 585         else
 586                 val |= 3000 / 250; /* 3.0 usec */
 587         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 588
 589         mutex_unlock(&dev_priv->sb_lock);
 590
 591         intel_update_cdclk(dev_priv);
 592
 593         vlv_program_pfi_credits(dev_priv);
 594
 595         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 596 }
 597
 598 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 599                           const struct intel_cdclk_state *cdclk_state)
 600 {
 601         int cdclk = cdclk_state->cdclk;
 602         u32 val, cmd = cdclk_state->voltage_level;
 603
 604         switch (cdclk) {
 605         case 333333:
 606         case 320000:
 607         case 266667:
 608         case 200000:
 609                 break;
 610         default:
 611                 MISSING_CASE(cdclk);
 612                 return;
 613         }
 614
 615         /* There are cases where we can end up here with power domains
 616          * off and a CDCLK frequency other than the minimum, like when
 617          * issuing a modeset without actually changing any display after
 618          * a system suspend.  So grab the PIPE-A domain, which covers
 619          * the HW blocks needed for the following programming.
 620          */
 621         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 622
 623         mutex_lock(&dev_priv->pcu_lock);
 624         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 625         val &= ~DSPFREQGUAR_MASK_CHV;
 626         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 627         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 628         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 629                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 630                      50)) {
 631                 DRM_ERROR("timed out waiting for CDclk change\n");
 632         }
 633         mutex_unlock(&dev_priv->pcu_lock);
 634
 635         intel_update_cdclk(dev_priv);
 636
 637         vlv_program_pfi_credits(dev_priv);
 638
 639         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 640 }
 641
 642 static int bdw_calc_cdclk(int min_cdclk)
 643 {
 644         if (min_cdclk > 540000)
 645                 return 675000;
 646         else if (min_cdclk > 450000)
 647                 return 540000;
 648         else if (min_cdclk > 337500)
 649                 return 450000;
 650         else
 651                 return 337500;
 652 }
 653
 654 static u8 bdw_calc_voltage_level(int cdclk)
 655 {
 656         switch (cdclk) {
 657         default:
 658         case 337500:
 659                 return 2;
 660         case 450000:
 661                 return 0;
 662         case 540000:
 663                 return 1;
 664         case 675000:
 665                 return 3;
 666         }
 667 }
 668
 669 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 670                           struct intel_cdclk_state *cdclk_state)
 671 {
 672         uint32_t lcpll = I915_READ(LCPLL_CTL);
 673         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 674
 675         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 676                 cdclk_state->cdclk = 800000;
 677         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 678                 cdclk_state->cdclk = 450000;
 679         else if (freq == LCPLL_CLK_FREQ_450)
 680                 cdclk_state->cdclk = 450000;
 681         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 682                 cdclk_state->cdclk = 540000;
 683         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 684                 cdclk_state->cdclk = 337500;
 685         else
 686                 cdclk_state->cdclk = 675000;
 687
 688         /*
 689          * Can't read this out :( Let's assume it's
 690          * at least what the CDCLK frequency requires.
 691          */
 692         cdclk_state->voltage_level =
 693                 bdw_calc_voltage_level(cdclk_state->cdclk);
 694 }
 695
 696 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 697                           const struct intel_cdclk_state *cdclk_state)
 698 {
 699         int cdclk = cdclk_state->cdclk;
 700         uint32_t val;
 701         int ret;
 702
 703         if (WARN((I915_READ(LCPLL_CTL) &
 704                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 705                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 706                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 707                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 708                  "trying to change cdclk frequency with cdclk not enabled\n"))
 709                 return;
 710
 711         mutex_lock(&dev_priv->pcu_lock);
 712         ret = sandybridge_pcode_write(dev_priv,
 713                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 714         mutex_unlock(&dev_priv->pcu_lock);
 715         if (ret) {
 716                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 717                 return;
 718         }
 719
 720         val = I915_READ(LCPLL_CTL);
 721         val |= LCPLL_CD_SOURCE_FCLK;
 722         I915_WRITE(LCPLL_CTL, val);
 723
 724         /*
 725          * According to the spec, it should be enough to poll for this 1 us.
 726          * However, extensive testing shows that this can take longer.
 727          */
 728         if (wait_for_us(I915_READ(LCPLL_CTL) &
 729                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 730                 DRM_ERROR("Switching to FCLK failed\n");
 731
 732         val = I915_READ(LCPLL_CTL);
 733         val &= ~LCPLL_CLK_FREQ_MASK;
 734
 735         switch (cdclk) {
 736         default:
 737                 MISSING_CASE(cdclk);
 738                 /* fall through */
 739         case 337500:
 740                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 741                 break;
 742         case 450000:
 743                 val |= LCPLL_CLK_FREQ_450;
 744                 break;
 745         case 540000:
 746                 val |= LCPLL_CLK_FREQ_54O_BDW;
 747                 break;
 748         case 675000:
 749                 val |= LCPLL_CLK_FREQ_675_BDW;
 750                 break;
 751         }
 752
 753         I915_WRITE(LCPLL_CTL, val);
 754
 755         val = I915_READ(LCPLL_CTL);
 756         val &= ~LCPLL_CD_SOURCE_FCLK;
 757         I915_WRITE(LCPLL_CTL, val);
 758
 759         if (wait_for_us((I915_READ(LCPLL_CTL) &
 760                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 761                 DRM_ERROR("Switching back to LCPLL failed\n");
 762
 763         mutex_lock(&dev_priv->pcu_lock);
 764         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
 765                                 cdclk_state->voltage_level);
 766         mutex_unlock(&dev_priv->pcu_lock);
 767
 768         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 769
 770         intel_update_cdclk(dev_priv);
 771 }
 772
 773 static int skl_calc_cdclk(int min_cdclk, int vco)
 774 {
 775         if (vco == 8640000) {
 776                 if (min_cdclk > 540000)
 777                         return 617143;
 778                 else if (min_cdclk > 432000)
 779                         return 540000;
 780                 else if (min_cdclk > 308571)
 781                         return 432000;
 782                 else
 783                         return 308571;
 784         } else {
 785                 if (min_cdclk > 540000)
 786                         return 675000;
 787                 else if (min_cdclk > 450000)
 788                         return 540000;
 789                 else if (min_cdclk > 337500)
 790                         return 450000;
 791                 else
 792                         return 337500;
 793         }
 794 }
 795
 796 static u8 skl_calc_voltage_level(int cdclk)
 797 {
 798         switch (cdclk) {
 799         default:
 800         case 308571:
 801         case 337500:
 802                 return 0;
 803         case 450000:
 804         case 432000:
 805                 return 1;
 806         case 540000:
 807                 return 2;
 808         case 617143:
 809         case 675000:
 810                 return 3;
 811         }
 812 }
 813
 814 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 815                              struct intel_cdclk_state *cdclk_state)
 816 {
 817         u32 val;
 818
 819         cdclk_state->ref = 24000;
 820         cdclk_state->vco = 0;
 821
 822         val = I915_READ(LCPLL1_CTL);
 823         if ((val & LCPLL_PLL_ENABLE) == 0)
 824                 return;
 825
 826         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 827                 return;
 828
 829         val = I915_READ(DPLL_CTRL1);
 830
 831         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 832                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 833                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 834                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 835                 return;
 836
 837         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 838         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 839         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 840         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 841         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 842                 cdclk_state->vco = 8100000;
 843                 break;
 844         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 845         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 846                 cdclk_state->vco = 8640000;
 847                 break;
 848         default:
 849                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 850                 break;
 851         }
 852 }
 853
 854 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 855                           struct intel_cdclk_state *cdclk_state)
 856 {
 857         u32 cdctl;
 858
 859         skl_dpll0_update(dev_priv, cdclk_state);
 860
 861         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
 862
 863         if (cdclk_state->vco == 0)
 864                 goto out;
 865
 866         cdctl = I915_READ(CDCLK_CTL);
 867
 868         if (cdclk_state->vco == 8640000) {
 869                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 870                 case CDCLK_FREQ_450_432:
 871                         cdclk_state->cdclk = 432000;
 872                         break;
 873                 case CDCLK_FREQ_337_308:
 874                         cdclk_state->cdclk = 308571;
 875                         break;
 876                 case CDCLK_FREQ_540:
 877                         cdclk_state->cdclk = 540000;
 878                         break;
 879                 case CDCLK_FREQ_675_617:
 880                         cdclk_state->cdclk = 617143;
 881                         break;
 882                 default:
 883                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 884                         break;
 885                 }
 886         } else {
 887                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 888                 case CDCLK_FREQ_450_432:
 889                         cdclk_state->cdclk = 450000;
 890                         break;
 891                 case CDCLK_FREQ_337_308:
 892                         cdclk_state->cdclk = 337500;
 893                         break;
 894                 case CDCLK_FREQ_540:
 895                         cdclk_state->cdclk = 540000;
 896                         break;
 897                 case CDCLK_FREQ_675_617:
 898                         cdclk_state->cdclk = 675000;
 899                         break;
 900                 default:
 901                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 902                         break;
 903                 }
 904         }
 905
 906  out:
 907         /*
 908          * Can't read this out :( Let's assume it's
 909          * at least what the CDCLK frequency requires.
 910          */
 911         cdclk_state->voltage_level =
 912                 skl_calc_voltage_level(cdclk_state->cdclk);
 913 }
 914
 915 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 916 static int skl_cdclk_decimal(int cdclk)
 917 {
 918         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 919 }
 920
 921 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 922                                         int vco)
 923 {
 924         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 925
 926         dev_priv->skl_preferred_vco_freq = vco;
 927
 928         if (changed)
 929                 intel_update_max_cdclk(dev_priv);
 930 }
 931
 932 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 933 {
 934         u32 val;
 935
 936         WARN_ON(vco != 8100000 && vco != 8640000);
 937
 938         /*
 939          * We always enable DPLL0 with the lowest link rate possible, but still
 940          * taking into account the VCO required to operate the eDP panel at the
 941          * desired frequency. The usual DP link rates operate with a VCO of
 942          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 943          * The modeset code is responsible for the selection of the exact link
 944          * rate later on, with the constraint of choosing a frequency that
 945          * works with vco.
 946          */
 947         val = I915_READ(DPLL_CTRL1);
 948
 949         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 950                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 951         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 952         if (vco == 8640000)
 953                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 954                                             SKL_DPLL0);
 955         else
 956                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 957                                             SKL_DPLL0);
 958
 959         I915_WRITE(DPLL_CTRL1, val);
 960         POSTING_READ(DPLL_CTRL1);
 961
 962         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 963
 964         if (intel_wait_for_register(dev_priv,
 965                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 966                                     5))
 967                 DRM_ERROR("DPLL0 not locked\n");
 968
 969         dev_priv->cdclk.hw.vco = vco;
 970
 971         /* We'll want to keep using the current vco from now on. */
 972         skl_set_preferred_cdclk_vco(dev_priv, vco);
 973 }
 974
 975 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 976 {
 977         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 978         if (intel_wait_for_register(dev_priv,
 979                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 980                                    1))
 981                 DRM_ERROR("Couldn't disable DPLL0\n");
 982
 983         dev_priv->cdclk.hw.vco = 0;
 984 }
 985
 986 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 987                           const struct intel_cdclk_state *cdclk_state)
 988 {
 989         int cdclk = cdclk_state->cdclk;
 990         int vco = cdclk_state->vco;
 991         u32 freq_select, cdclk_ctl;
 992         int ret;
 993
 994         mutex_lock(&dev_priv->pcu_lock);
 995         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 996                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 997                                 SKL_CDCLK_READY_FOR_CHANGE,
 998                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 999         mutex_unlock(&dev_priv->pcu_lock);
1000         if (ret) {
1001                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1002                           ret);
1003                 return;
1004         }
1005
1006         /* Choose frequency for this cdclk */
1007         switch (cdclk) {
1008         default:
1009                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1010                 WARN_ON(vco != 0);
1011                 /* fall through */
1012         case 308571:
1013         case 337500:
1014                 freq_select = CDCLK_FREQ_337_308;
1015                 break;
1016         case 450000:
1017         case 432000:
1018                 freq_select = CDCLK_FREQ_450_432;
1019                 break;
1020         case 540000:
1021                 freq_select = CDCLK_FREQ_540;
1022                 break;
1023         case 617143:
1024         case 675000:
1025                 freq_select = CDCLK_FREQ_675_617;
1026                 break;
1027         }
1028
1029         if (dev_priv->cdclk.hw.vco != 0 &&
1030             dev_priv->cdclk.hw.vco != vco)
1031                 skl_dpll0_disable(dev_priv);
1032
1033         cdclk_ctl = I915_READ(CDCLK_CTL);
1034
1035         if (dev_priv->cdclk.hw.vco != vco) {
1036                 /* Wa Display #1183: skl,kbl,cfl */
1037                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1038                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1039                 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1040         }
1041
1042         /* Wa Display #1183: skl,kbl,cfl */
1043         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1044         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1045         POSTING_READ(CDCLK_CTL);
1046
1047         if (dev_priv->cdclk.hw.vco != vco)
1048                 skl_dpll0_enable(dev_priv, vco);
1049
1050         /* Wa Display #1183: skl,kbl,cfl */
1051         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1052         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1053
1054         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1055         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1056
1057         /* Wa Display #1183: skl,kbl,cfl */
1058         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1059         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1060         POSTING_READ(CDCLK_CTL);
1061
1062         /* inform PCU of the change */
1063         mutex_lock(&dev_priv->pcu_lock);
1064         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1065                                 cdclk_state->voltage_level);
1066         mutex_unlock(&dev_priv->pcu_lock);
1067
1068         intel_update_cdclk(dev_priv);
1069 }
1070
1071 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1072 {
1073         uint32_t cdctl, expected;
1074
1075         /*
1076          * check if the pre-os initialized the display
1077          * There is SWF18 scratchpad register defined which is set by the
1078          * pre-os which can be used by the OS drivers to check the status
1079          */
1080         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1081                 goto sanitize;
1082
1083         intel_update_cdclk(dev_priv);
1084         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1085
1086         /* Is PLL enabled and locked ? */
1087         if (dev_priv->cdclk.hw.vco == 0 ||
1088             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1089                 goto sanitize;
1090
1091         /* DPLL okay; verify the cdclock
1092          *
1093          * Noticed in some instances that the freq selection is correct but
1094          * decimal part is programmed wrong from BIOS where pre-os does not
1095          * enable display. Verify the same as well.
1096          */
1097         cdctl = I915_READ(CDCLK_CTL);
1098         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1099                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1100         if (cdctl == expected)
1101                 /* All well; nothing to sanitize */
1102                 return;
1103
1104 sanitize:
1105         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1106
1107         /* force cdclk programming */
1108         dev_priv->cdclk.hw.cdclk = 0;
1109         /* force full PLL disable + enable */
1110         dev_priv->cdclk.hw.vco = -1;
1111 }
1112
1113 /**
1114  * skl_init_cdclk - Initialize CDCLK on SKL
1115  * @dev_priv: i915 device
1116  *
1117  * Initialize CDCLK for SKL and derivatives. This is generally
1118  * done only during the display core initialization sequence,
1119  * after which the DMC will take care of turning CDCLK off/on
1120  * as needed.
1121  */
1122 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1123 {
1124         struct intel_cdclk_state cdclk_state;
1125
1126         skl_sanitize_cdclk(dev_priv);
1127
1128         if (dev_priv->cdclk.hw.cdclk != 0 &&
1129             dev_priv->cdclk.hw.vco != 0) {
1130                 /*
1131                  * Use the current vco as our initial
1132                  * guess as to what the preferred vco is.
1133                  */
1134                 if (dev_priv->skl_preferred_vco_freq == 0)
1135                         skl_set_preferred_cdclk_vco(dev_priv,
1136                                                     dev_priv->cdclk.hw.vco);
1137                 return;
1138         }
1139
1140         cdclk_state = dev_priv->cdclk.hw;
1141
1142         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1143         if (cdclk_state.vco == 0)
1144                 cdclk_state.vco = 8100000;
1145         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1146         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1147
1148         skl_set_cdclk(dev_priv, &cdclk_state);
1149 }
1150
1151 /**
1152  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1153  * @dev_priv: i915 device
1154  *
1155  * Uninitialize CDCLK for SKL and derivatives. This is done only
1156  * during the display core uninitialization sequence.
1157  */
1158 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1159 {
1160         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1161
1162         cdclk_state.cdclk = cdclk_state.bypass;
1163         cdclk_state.vco = 0;
1164         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1165
1166         skl_set_cdclk(dev_priv, &cdclk_state);
1167 }
1168
1169 static int bxt_calc_cdclk(int min_cdclk)
1170 {
1171         if (min_cdclk > 576000)
1172                 return 624000;
1173         else if (min_cdclk > 384000)
1174                 return 576000;
1175         else if (min_cdclk > 288000)
1176                 return 384000;
1177         else if (min_cdclk > 144000)
1178                 return 288000;
1179         else
1180                 return 144000;
1181 }
1182
1183 static int glk_calc_cdclk(int min_cdclk)
1184 {
1185         if (min_cdclk > 158400)
1186                 return 316800;
1187         else if (min_cdclk > 79200)
1188                 return 158400;
1189         else
1190                 return 79200;
1191 }
1192
1193 static u8 bxt_calc_voltage_level(int cdclk)
1194 {
1195         return DIV_ROUND_UP(cdclk, 25000);
1196 }
1197
1198 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1199 {
1200         int ratio;
1201
1202         if (cdclk == dev_priv->cdclk.hw.bypass)
1203                 return 0;
1204
1205         switch (cdclk) {
1206         default:
1207                 MISSING_CASE(cdclk);
1208                 /* fall through */
1209         case 144000:
1210         case 288000:
1211         case 384000:
1212         case 576000:
1213                 ratio = 60;
1214                 break;
1215         case 624000:
1216                 ratio = 65;
1217                 break;
1218         }
1219
1220         return dev_priv->cdclk.hw.ref * ratio;
1221 }
1222
1223 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1224 {
1225         int ratio;
1226
1227         if (cdclk == dev_priv->cdclk.hw.bypass)
1228                 return 0;
1229
1230         switch (cdclk) {
1231         default:
1232                 MISSING_CASE(cdclk);
1233                 /* fall through */
1234         case  79200:
1235         case 158400:
1236         case 316800:
1237                 ratio = 33;
1238                 break;
1239         }
1240
1241         return dev_priv->cdclk.hw.ref * ratio;
1242 }
1243
1244 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1245                               struct intel_cdclk_state *cdclk_state)
1246 {
1247         u32 val;
1248
1249         cdclk_state->ref = 19200;
1250         cdclk_state->vco = 0;
1251
1252         val = I915_READ(BXT_DE_PLL_ENABLE);
1253         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1254                 return;
1255
1256         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1257                 return;
1258
1259         val = I915_READ(BXT_DE_PLL_CTL);
1260         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1261 }
1262
1263 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1264                           struct intel_cdclk_state *cdclk_state)
1265 {
1266         u32 divider;
1267         int div;
1268
1269         bxt_de_pll_update(dev_priv, cdclk_state);
1270
1271         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1272
1273         if (cdclk_state->vco == 0)
1274                 goto out;
1275
1276         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1277
1278         switch (divider) {
1279         case BXT_CDCLK_CD2X_DIV_SEL_1:
1280                 div = 2;
1281                 break;
1282         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1283                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1284                 div = 3;
1285                 break;
1286         case BXT_CDCLK_CD2X_DIV_SEL_2:
1287                 div = 4;
1288                 break;
1289         case BXT_CDCLK_CD2X_DIV_SEL_4:
1290                 div = 8;
1291                 break;
1292         default:
1293                 MISSING_CASE(divider);
1294                 return;
1295         }
1296
1297         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1298
1299  out:
1300         /*
1301          * Can't read this out :( Let's assume it's
1302          * at least what the CDCLK frequency requires.
1303          */
1304         cdclk_state->voltage_level =
1305                 bxt_calc_voltage_level(cdclk_state->cdclk);
1306 }
1307
1308 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1309 {
1310         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1311
1312         /* Timeout 200us */
1313         if (intel_wait_for_register(dev_priv,
1314                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1315                                     1))
1316                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1317
1318         dev_priv->cdclk.hw.vco = 0;
1319 }
1320
1321 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1322 {
1323         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1324         u32 val;
1325
1326         val = I915_READ(BXT_DE_PLL_CTL);
1327         val &= ~BXT_DE_PLL_RATIO_MASK;
1328         val |= BXT_DE_PLL_RATIO(ratio);
1329         I915_WRITE(BXT_DE_PLL_CTL, val);
1330
1331         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1332
1333         /* Timeout 200us */
1334         if (intel_wait_for_register(dev_priv,
1335                                     BXT_DE_PLL_ENABLE,
1336                                     BXT_DE_PLL_LOCK,
1337                                     BXT_DE_PLL_LOCK,
1338                                     1))
1339                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1340
1341         dev_priv->cdclk.hw.vco = vco;
1342 }
1343
1344 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1345                           const struct intel_cdclk_state *cdclk_state)
1346 {
1347         int cdclk = cdclk_state->cdclk;
1348         int vco = cdclk_state->vco;
1349         u32 val, divider;
1350         int ret;
1351
1352         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1353         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1354         default:
1355                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1356                 WARN_ON(vco != 0);
1357                 /* fall through */
1358         case 2:
1359                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1360                 break;
1361         case 3:
1362                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1363                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1364                 break;
1365         case 4:
1366                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1367                 break;
1368         case 8:
1369                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1370                 break;
1371         }
1372
1373         /*
1374          * Inform power controller of upcoming frequency change. BSpec
1375          * requires us to wait up to 150usec, but that leads to timeouts;
1376          * the 2ms used here is based on experiment.
1377          */
1378         mutex_lock(&dev_priv->pcu_lock);
1379         ret = sandybridge_pcode_write_timeout(dev_priv,
1380                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1381                                               0x80000000, 150, 2);
1382         mutex_unlock(&dev_priv->pcu_lock);
1383
1384         if (ret) {
1385                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1386                           ret, cdclk);
1387                 return;
1388         }
1389
1390         if (dev_priv->cdclk.hw.vco != 0 &&
1391             dev_priv->cdclk.hw.vco != vco)
1392                 bxt_de_pll_disable(dev_priv);
1393
1394         if (dev_priv->cdclk.hw.vco != vco)
1395                 bxt_de_pll_enable(dev_priv, vco);
1396
1397         val = divider | skl_cdclk_decimal(cdclk);
1398         /*
1399          * FIXME if only the cd2x divider needs changing, it could be done
1400          * without shutting off the pipe (if only one pipe is active).
1401          */
1402         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1403         /*
1404          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1405          * enable otherwise.
1406          */
1407         if (cdclk >= 500000)
1408                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1409         I915_WRITE(CDCLK_CTL, val);
1410
1411         mutex_lock(&dev_priv->pcu_lock);
1412         /*
1413          * The timeout isn't specified, the 2ms used here is based on
1414          * experiment.
1415          * FIXME: Waiting for the request completion could be delayed until
1416          * the next PCODE request based on BSpec.
1417          */
1418         ret = sandybridge_pcode_write_timeout(dev_priv,
1419                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1420                                               cdclk_state->voltage_level, 150, 2);
1421         mutex_unlock(&dev_priv->pcu_lock);
1422
1423         if (ret) {
1424                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1425                           ret, cdclk);
1426                 return;
1427         }
1428
1429         intel_update_cdclk(dev_priv);
1430 }
1431
1432 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1433 {
1434         u32 cdctl, expected;
1435
1436         intel_update_cdclk(dev_priv);
1437         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1438
1439         if (dev_priv->cdclk.hw.vco == 0 ||
1440             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1441                 goto sanitize;
1442
1443         /* DPLL okay; verify the cdclock
1444          *
1445          * Some BIOS versions leave an incorrect decimal frequency value and
1446          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1447          * so sanitize this register.
1448          */
1449         cdctl = I915_READ(CDCLK_CTL);
1450         /*
1451          * Let's ignore the pipe field, since BIOS could have configured the
1452          * dividers both synching to an active pipe, or asynchronously
1453          * (PIPE_NONE).
1454          */
1455         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1456
1457         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1458                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1459         /*
1460          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1461          * enable otherwise.
1462          */
1463         if (dev_priv->cdclk.hw.cdclk >= 500000)
1464                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1465
1466         if (cdctl == expected)
1467                 /* All well; nothing to sanitize */
1468                 return;
1469
1470 sanitize:
1471         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1472
1473         /* force cdclk programming */
1474         dev_priv->cdclk.hw.cdclk = 0;
1475
1476         /* force full PLL disable + enable */
1477         dev_priv->cdclk.hw.vco = -1;
1478 }
1479
1480 /**
1481  * bxt_init_cdclk - Initialize CDCLK on BXT
1482  * @dev_priv: i915 device
1483  *
1484  * Initialize CDCLK for BXT and derivatives. This is generally
1485  * done only during the display core initialization sequence,
1486  * after which the DMC will take care of turning CDCLK off/on
1487  * as needed.
1488  */
1489 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1490 {
1491         struct intel_cdclk_state cdclk_state;
1492
1493         bxt_sanitize_cdclk(dev_priv);
1494
1495         if (dev_priv->cdclk.hw.cdclk != 0 &&
1496             dev_priv->cdclk.hw.vco != 0)
1497                 return;
1498
1499         cdclk_state = dev_priv->cdclk.hw;
1500
1501         /*
1502          * FIXME:
1503          * - The initial CDCLK needs to be read from VBT.
1504          *   Need to make this change after VBT has changes for BXT.
1505          */
1506         if (IS_GEMINILAKE(dev_priv)) {
1507                 cdclk_state.cdclk = glk_calc_cdclk(0);
1508                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1509         } else {
1510                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1511                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1512         }
1513         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1514
1515         bxt_set_cdclk(dev_priv, &cdclk_state);
1516 }
1517
1518 /**
1519  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1520  * @dev_priv: i915 device
1521  *
1522  * Uninitialize CDCLK for BXT and derivatives. This is done only
1523  * during the display core uninitialization sequence.
1524  */
1525 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1526 {
1527         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1528
1529         cdclk_state.cdclk = cdclk_state.bypass;
1530         cdclk_state.vco = 0;
1531         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1532
1533         bxt_set_cdclk(dev_priv, &cdclk_state);
1534 }
1535
1536 static int cnl_calc_cdclk(int min_cdclk)
1537 {
1538         if (min_cdclk > 336000)
1539                 return 528000;
1540         else if (min_cdclk > 168000)
1541                 return 336000;
1542         else
1543                 return 168000;
1544 }
1545
1546 static u8 cnl_calc_voltage_level(int cdclk)
1547 {
1548         switch (cdclk) {
1549         default:
1550         case 168000:
1551                 return 0;
1552         case 336000:
1553                 return 1;
1554         case 528000:
1555                 return 2;
1556         }
1557 }
1558
1559 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1560                                  struct intel_cdclk_state *cdclk_state)
1561 {
1562         u32 val;
1563
1564         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1565                 cdclk_state->ref = 24000;
1566         else
1567                 cdclk_state->ref = 19200;
1568
1569         cdclk_state->vco = 0;
1570
1571         val = I915_READ(BXT_DE_PLL_ENABLE);
1572         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1573                 return;
1574
1575         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1576                 return;
1577
1578         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1579 }
1580
1581 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1582                          struct intel_cdclk_state *cdclk_state)
1583 {
1584         u32 divider;
1585         int div;
1586
1587         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1588
1589         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1590
1591         if (cdclk_state->vco == 0)
1592                 goto out;
1593
1594         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1595
1596         switch (divider) {
1597         case BXT_CDCLK_CD2X_DIV_SEL_1:
1598                 div = 2;
1599                 break;
1600         case BXT_CDCLK_CD2X_DIV_SEL_2:
1601                 div = 4;
1602                 break;
1603         default:
1604                 MISSING_CASE(divider);
1605                 return;
1606         }
1607
1608         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1609
1610  out:
1611         /*
1612          * Can't read this out :( Let's assume it's
1613          * at least what the CDCLK frequency requires.
1614          */
1615         cdclk_state->voltage_level =
1616                 cnl_calc_voltage_level(cdclk_state->cdclk);
1617 }
1618
1619 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1620 {
1621         u32 val;
1622
1623         val = I915_READ(BXT_DE_PLL_ENABLE);
1624         val &= ~BXT_DE_PLL_PLL_ENABLE;
1625         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1626
1627         /* Timeout 200us */
1628         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1629                 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
1630
1631         dev_priv->cdclk.hw.vco = 0;
1632 }
1633
1634 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1635 {
1636         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1637         u32 val;
1638
1639         val = CNL_CDCLK_PLL_RATIO(ratio);
1640         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1641
1642         val |= BXT_DE_PLL_PLL_ENABLE;
1643         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1644
1645         /* Timeout 200us */
1646         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1647                 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
1648
1649         dev_priv->cdclk.hw.vco = vco;
1650 }
1651
1652 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1653                           const struct intel_cdclk_state *cdclk_state)
1654 {
1655         int cdclk = cdclk_state->cdclk;
1656         int vco = cdclk_state->vco;
1657         u32 val, divider;
1658         int ret;
1659
1660         mutex_lock(&dev_priv->pcu_lock);
1661         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1662                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1663                                 SKL_CDCLK_READY_FOR_CHANGE,
1664                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1665         mutex_unlock(&dev_priv->pcu_lock);
1666         if (ret) {
1667                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1668                           ret);
1669                 return;
1670         }
1671
1672         /* cdclk = vco / 2 / div{1,2} */
1673         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1674         default:
1675                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1676                 WARN_ON(vco != 0);
1677                 /* fall through */
1678         case 2:
1679                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1680                 break;
1681         case 4:
1682                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1683                 break;
1684         }
1685
1686         if (dev_priv->cdclk.hw.vco != 0 &&
1687             dev_priv->cdclk.hw.vco != vco)
1688                 cnl_cdclk_pll_disable(dev_priv);
1689
1690         if (dev_priv->cdclk.hw.vco != vco)
1691                 cnl_cdclk_pll_enable(dev_priv, vco);
1692
1693         val = divider | skl_cdclk_decimal(cdclk);
1694         /*
1695          * FIXME if only the cd2x divider needs changing, it could be done
1696          * without shutting off the pipe (if only one pipe is active).
1697          */
1698         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1699         I915_WRITE(CDCLK_CTL, val);
1700
1701         /* inform PCU of the change */
1702         mutex_lock(&dev_priv->pcu_lock);
1703         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1704                                 cdclk_state->voltage_level);
1705         mutex_unlock(&dev_priv->pcu_lock);
1706
1707         intel_update_cdclk(dev_priv);
1708
1709         /*
1710          * Can't read out the voltage level :(
1711          * Let's just assume everything is as expected.
1712          */
1713         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1714 }
1715
1716 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1717 {
1718         int ratio;
1719
1720         if (cdclk == dev_priv->cdclk.hw.bypass)
1721                 return 0;
1722
1723         switch (cdclk) {
1724         default:
1725                 MISSING_CASE(cdclk);
1726                 /* fall through */
1727         case 168000:
1728         case 336000:
1729                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1730                 break;
1731         case 528000:
1732                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1733                 break;
1734         }
1735
1736         return dev_priv->cdclk.hw.ref * ratio;
1737 }
1738
1739 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1740 {
1741         u32 cdctl, expected;
1742
1743         intel_update_cdclk(dev_priv);
1744         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1745
1746         if (dev_priv->cdclk.hw.vco == 0 ||
1747             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1748                 goto sanitize;
1749
1750         /* DPLL okay; verify the cdclock
1751          *
1752          * Some BIOS versions leave an incorrect decimal frequency value and
1753          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1754          * so sanitize this register.
1755          */
1756         cdctl = I915_READ(CDCLK_CTL);
1757         /*
1758          * Let's ignore the pipe field, since BIOS could have configured the
1759          * dividers both synching to an active pipe, or asynchronously
1760          * (PIPE_NONE).
1761          */
1762         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1763
1764         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1765                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1766
1767         if (cdctl == expected)
1768                 /* All well; nothing to sanitize */
1769                 return;
1770
1771 sanitize:
1772         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1773
1774         /* force cdclk programming */
1775         dev_priv->cdclk.hw.cdclk = 0;
1776
1777         /* force full PLL disable + enable */
1778         dev_priv->cdclk.hw.vco = -1;
1779 }
1780
1781 static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1782 {
1783         int ranges_24[] = { 312000, 552000, 648000 };
1784         int ranges_19_38[] = { 307200, 556800, 652800 };
1785         int *ranges;
1786
1787         switch (ref) {
1788         default:
1789                 MISSING_CASE(ref);
1790         case 24000:
1791                 ranges = ranges_24;
1792                 break;
1793         case 19200:
1794         case 38400:
1795                 ranges = ranges_19_38;
1796                 break;
1797         }
1798
1799         if (min_cdclk > ranges[1])
1800                 return ranges[2];
1801         else if (min_cdclk > ranges[0])
1802                 return ranges[1];
1803         else
1804                 return ranges[0];
1805 }
1806
1807 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1808 {
1809         int ratio;
1810
1811         if (cdclk == dev_priv->cdclk.hw.bypass)
1812                 return 0;
1813
1814         switch (cdclk) {
1815         default:
1816                 MISSING_CASE(cdclk);
1817         case 307200:
1818         case 556800:
1819         case 652800:
1820                 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1821                         dev_priv->cdclk.hw.ref != 38400);
1822                 break;
1823         case 312000:
1824         case 552000:
1825         case 648000:
1826                 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1827         }
1828
1829         ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1830
1831         return dev_priv->cdclk.hw.ref * ratio;
1832 }
1833
1834 static void icl_set_cdclk(struct drm_i915_private *dev_priv,
1835                           const struct intel_cdclk_state *cdclk_state)
1836 {
1837         unsigned int cdclk = cdclk_state->cdclk;
1838         unsigned int vco = cdclk_state->vco;
1839         int ret;
1840
1841         mutex_lock(&dev_priv->pcu_lock);
1842         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1843                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1844                                 SKL_CDCLK_READY_FOR_CHANGE,
1845                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1846         mutex_unlock(&dev_priv->pcu_lock);
1847         if (ret) {
1848                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1849                           ret);
1850                 return;
1851         }
1852
1853         if (dev_priv->cdclk.hw.vco != 0 &&
1854             dev_priv->cdclk.hw.vco != vco)
1855                 cnl_cdclk_pll_disable(dev_priv);
1856
1857         if (dev_priv->cdclk.hw.vco != vco)
1858                 cnl_cdclk_pll_enable(dev_priv, vco);
1859
1860         I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
1861                               skl_cdclk_decimal(cdclk));
1862
1863         mutex_lock(&dev_priv->pcu_lock);
1864         /* TODO: add proper DVFS support. */
1865         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, 2);
1866         mutex_unlock(&dev_priv->pcu_lock);
1867
1868         intel_update_cdclk(dev_priv);
1869 }
1870
1871 static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1872                           struct intel_cdclk_state *cdclk_state)
1873 {
1874         u32 val;
1875
1876         cdclk_state->bypass = 50000;
1877
1878         val = I915_READ(SKL_DSSM);
1879         switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1880         default:
1881                 MISSING_CASE(val);
1882         case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1883                 cdclk_state->ref = 24000;
1884                 break;
1885         case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1886                 cdclk_state->ref = 19200;
1887                 break;
1888         case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1889                 cdclk_state->ref = 38400;
1890                 break;
1891         }
1892
1893         val = I915_READ(BXT_DE_PLL_ENABLE);
1894         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1895             (val & BXT_DE_PLL_LOCK) == 0) {
1896                 /*
1897                  * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1898                  * setting it to zero is a way to signal that.
1899                  */
1900                 cdclk_state->vco = 0;
1901                 cdclk_state->cdclk = cdclk_state->bypass;
1902                 return;
1903         }
1904
1905         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1906
1907         val = I915_READ(CDCLK_CTL);
1908         WARN_ON((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0);
1909
1910         cdclk_state->cdclk = cdclk_state->vco / 2;
1911 }
1912
1913 /**
1914  * icl_init_cdclk - Initialize CDCLK on ICL
1915  * @dev_priv: i915 device
1916  *
1917  * Initialize CDCLK for ICL. This consists mainly of initializing
1918  * dev_priv->cdclk.hw and sanitizing the state of the hardware if needed. This
1919  * is generally done only during the display core initialization sequence, after
1920  * which the DMC will take care of turning CDCLK off/on as needed.
1921  */
1922 void icl_init_cdclk(struct drm_i915_private *dev_priv)
1923 {
1924         struct intel_cdclk_state sanitized_state;
1925         u32 val;
1926
1927         /* This sets dev_priv->cdclk.hw. */
1928         intel_update_cdclk(dev_priv);
1929         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1930
1931         /* This means CDCLK disabled. */
1932         if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1933                 goto sanitize;
1934
1935         val = I915_READ(CDCLK_CTL);
1936
1937         if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1938                 goto sanitize;
1939
1940         if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1941             skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1942                 goto sanitize;
1943
1944         return;
1945
1946 sanitize:
1947         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1948
1949         sanitized_state.ref = dev_priv->cdclk.hw.ref;
1950         sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
1951         sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
1952                                                      sanitized_state.cdclk);
1953
1954         icl_set_cdclk(dev_priv, &sanitized_state);
1955 }
1956
1957 /**
1958  * icl_uninit_cdclk - Uninitialize CDCLK on ICL
1959  * @dev_priv: i915 device
1960  *
1961  * Uninitialize CDCLK for ICL. This is done only during the display core
1962  * uninitialization sequence.
1963  */
1964 void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
1965 {
1966         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1967
1968         cdclk_state.cdclk = cdclk_state.bypass;
1969         cdclk_state.vco = 0;
1970
1971         icl_set_cdclk(dev_priv, &cdclk_state);
1972 }
1973
1974 /**
1975  * cnl_init_cdclk - Initialize CDCLK on CNL
1976  * @dev_priv: i915 device
1977  *
1978  * Initialize CDCLK for CNL. This is generally
1979  * done only during the display core initialization sequence,
1980  * after which the DMC will take care of turning CDCLK off/on
1981  * as needed.
1982  */
1983 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1984 {
1985         struct intel_cdclk_state cdclk_state;
1986
1987         cnl_sanitize_cdclk(dev_priv);
1988
1989         if (dev_priv->cdclk.hw.cdclk != 0 &&
1990             dev_priv->cdclk.hw.vco != 0)
1991                 return;
1992
1993         cdclk_state = dev_priv->cdclk.hw;
1994
1995         cdclk_state.cdclk = cnl_calc_cdclk(0);
1996         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1997         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
1998
1999         cnl_set_cdclk(dev_priv, &cdclk_state);
2000 }
2001
2002 /**
2003  * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
2004  * @dev_priv: i915 device
2005  *
2006  * Uninitialize CDCLK for CNL. This is done only
2007  * during the display core uninitialization sequence.
2008  */
2009 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
2010 {
2011         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
2012
2013         cdclk_state.cdclk = cdclk_state.bypass;
2014         cdclk_state.vco = 0;
2015         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
2016
2017         cnl_set_cdclk(dev_priv, &cdclk_state);
2018 }
2019
2020 /**
2021  * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
2022  * @a: first CDCLK state
2023  * @b: second CDCLK state
2024  *
2025  * Returns:
2026  * True if the CDCLK states require pipes to be off during reprogramming, false if not.
2027  */
2028 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
2029                                const struct intel_cdclk_state *b)
2030 {
2031         return a->cdclk != b->cdclk ||
2032                 a->vco != b->vco ||
2033                 a->ref != b->ref;
2034 }
2035
2036 /**
2037  * intel_cdclk_changed - Determine if two CDCLK states are different
2038  * @a: first CDCLK state
2039  * @b: second CDCLK state
2040  *
2041  * Returns:
2042  * True if the CDCLK states don't match, false if they do.
2043  */
2044 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2045                          const struct intel_cdclk_state *b)
2046 {
2047         return intel_cdclk_needs_modeset(a, b) ||
2048                 a->voltage_level != b->voltage_level;
2049 }
2050
2051 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2052                             const char *context)
2053 {
2054         DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2055                          context, cdclk_state->cdclk, cdclk_state->vco,
2056                          cdclk_state->ref, cdclk_state->bypass,
2057                          cdclk_state->voltage_level);
2058 }
2059
2060 /**
2061  * intel_set_cdclk - Push the CDCLK state to the hardware
2062  * @dev_priv: i915 device
2063  * @cdclk_state: new CDCLK state
2064  *
2065  * Program the hardware based on the passed in CDCLK state,
2066  * if necessary.
2067  */
2068 void intel_set_cdclk(struct drm_i915_private *dev_priv,
2069                      const struct intel_cdclk_state *cdclk_state)
2070 {
2071         if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
2072                 return;
2073
2074         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2075                 return;
2076
2077         intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
2078
2079         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
2080
2081         if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2082                  "cdclk state doesn't match!\n")) {
2083                 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2084                 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2085         }
2086 }
2087
2088 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2089                                      int pixel_rate)
2090 {
2091         if (INTEL_GEN(dev_priv) >= 10)
2092                 return DIV_ROUND_UP(pixel_rate, 2);
2093         else if (IS_GEMINILAKE(dev_priv))
2094                 /*
2095                  * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
2096                  * as a temporary workaround. Use a higher cdclk instead. (Note that
2097                  * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
2098                  * cdclk.)
2099                  */
2100                 return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
2101         else if (IS_GEN9(dev_priv) ||
2102                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2103                 return pixel_rate;
2104         else if (IS_CHERRYVIEW(dev_priv))
2105                 return DIV_ROUND_UP(pixel_rate * 100, 95);
2106         else
2107                 return DIV_ROUND_UP(pixel_rate * 100, 90);
2108 }
2109
2110 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2111 {
2112         struct drm_i915_private *dev_priv =
2113                 to_i915(crtc_state->base.crtc->dev);
2114         int min_cdclk;
2115
2116         if (!crtc_state->base.enable)
2117                 return 0;
2118
2119         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
2120
2121         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2122         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2123                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2124
2125         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2126          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2127          * there may be audio corruption or screen corruption." This cdclk
2128          * restriction for GLK is 316.8 MHz.
2129          */
2130         if (intel_crtc_has_dp_encoder(crtc_state) &&
2131             crtc_state->has_audio &&
2132             crtc_state->port_clock >= 540000 &&
2133             crtc_state->lane_count == 4) {
2134                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2135                         /* Display WA #1145: glk,cnl */
2136                         min_cdclk = max(316800, min_cdclk);
2137                 } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
2138                         /* Display WA #1144: skl,bxt */
2139                         min_cdclk = max(432000, min_cdclk);
2140                 }
2141         }
2142
2143         /*
2144          * According to BSpec, "The CD clock frequency must be at least twice
2145          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2146          *
2147          * FIXME: Check the actual, not default, BCLK being used.
2148          *
2149          * FIXME: This does not depend on ->has_audio because the higher CDCLK
2150          * is required for audio probe, also when there are no audio capable
2151          * displays connected at probe time. This leads to unnecessarily high
2152          * CDCLK when audio is not required.
2153          *
2154          * FIXME: This limit is only applied when there are displays connected
2155          * at probe time. If we probe without displays, we'll still end up using
2156          * the platform minimum CDCLK, failing audio probe.
2157          */
2158         if (INTEL_GEN(dev_priv) >= 9)
2159                 min_cdclk = max(2 * 96000, min_cdclk);
2160
2161         /*
2162          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2163          * than 320000KHz.
2164          */
2165         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2166             IS_VALLEYVIEW(dev_priv))
2167                 min_cdclk = max(320000, min_cdclk);
2168
2169         if (min_cdclk > dev_priv->max_cdclk_freq) {
2170                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2171                               min_cdclk, dev_priv->max_cdclk_freq);
2172                 return -EINVAL;
2173         }
2174
2175         return min_cdclk;
2176 }
2177
2178 static int intel_compute_min_cdclk(struct drm_atomic_state *state)
2179 {
2180         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2181         struct drm_i915_private *dev_priv = to_i915(state->dev);
2182         struct intel_crtc *crtc;
2183         struct intel_crtc_state *crtc_state;
2184         int min_cdclk, i;
2185         enum pipe pipe;
2186
2187         memcpy(intel_state->min_cdclk, dev_priv->min_cdclk,
2188                sizeof(intel_state->min_cdclk));
2189
2190         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2191                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2192                 if (min_cdclk < 0)
2193                         return min_cdclk;
2194
2195                 intel_state->min_cdclk[i] = min_cdclk;
2196         }
2197
2198         min_cdclk = 0;
2199         for_each_pipe(dev_priv, pipe)
2200                 min_cdclk = max(intel_state->min_cdclk[pipe], min_cdclk);
2201
2202         return min_cdclk;
2203 }
2204
2205 /*
2206  * Note that this functions assumes that 0 is
2207  * the lowest voltage value, and higher values
2208  * correspond to increasingly higher voltages.
2209  *
2210  * Should that relationship no longer hold on
2211  * future platforms this code will need to be
2212  * adjusted.
2213  */
2214 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2215 {
2216         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2217         struct intel_crtc *crtc;
2218         struct intel_crtc_state *crtc_state;
2219         u8 min_voltage_level;
2220         int i;
2221         enum pipe pipe;
2222
2223         memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2224                sizeof(state->min_voltage_level));
2225
2226         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2227                 if (crtc_state->base.enable)
2228                         state->min_voltage_level[i] =
2229                                 crtc_state->min_voltage_level;
2230                 else
2231                         state->min_voltage_level[i] = 0;
2232         }
2233
2234         min_voltage_level = 0;
2235         for_each_pipe(dev_priv, pipe)
2236                 min_voltage_level = max(state->min_voltage_level[pipe],
2237                                         min_voltage_level);
2238
2239         return min_voltage_level;
2240 }
2241
2242 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
2243 {
2244         struct drm_i915_private *dev_priv = to_i915(state->dev);
2245         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2246         int min_cdclk, cdclk;
2247
2248         min_cdclk = intel_compute_min_cdclk(state);
2249         if (min_cdclk < 0)
2250                 return min_cdclk;
2251
2252         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2253
2254         intel_state->cdclk.logical.cdclk = cdclk;
2255         intel_state->cdclk.logical.voltage_level =
2256                 vlv_calc_voltage_level(dev_priv, cdclk);
2257
2258         if (!intel_state->active_crtcs) {
2259                 cdclk = vlv_calc_cdclk(dev_priv, 0);
2260
2261                 intel_state->cdclk.actual.cdclk = cdclk;
2262                 intel_state->cdclk.actual.voltage_level =
2263                         vlv_calc_voltage_level(dev_priv, cdclk);
2264         } else {
2265                 intel_state->cdclk.actual =
2266                         intel_state->cdclk.logical;
2267         }
2268
2269         return 0;
2270 }
2271
2272 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
2273 {
2274         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2275         int min_cdclk, cdclk;
2276
2277         min_cdclk = intel_compute_min_cdclk(state);
2278         if (min_cdclk < 0)
2279                 return min_cdclk;
2280
2281         /*
2282          * FIXME should also account for plane ratio
2283          * once 64bpp pixel formats are supported.
2284          */
2285         cdclk = bdw_calc_cdclk(min_cdclk);
2286
2287         intel_state->cdclk.logical.cdclk = cdclk;
2288         intel_state->cdclk.logical.voltage_level =
2289                 bdw_calc_voltage_level(cdclk);
2290
2291         if (!intel_state->active_crtcs) {
2292                 cdclk = bdw_calc_cdclk(0);
2293
2294                 intel_state->cdclk.actual.cdclk = cdclk;
2295                 intel_state->cdclk.actual.voltage_level =
2296                         bdw_calc_voltage_level(cdclk);
2297         } else {
2298                 intel_state->cdclk.actual =
2299                         intel_state->cdclk.logical;
2300         }
2301
2302         return 0;
2303 }
2304
2305 static int skl_dpll0_vco(struct intel_atomic_state *intel_state)
2306 {
2307         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
2308         struct intel_crtc *crtc;
2309         struct intel_crtc_state *crtc_state;
2310         int vco, i;
2311
2312         vco = intel_state->cdclk.logical.vco;
2313         if (!vco)
2314                 vco = dev_priv->skl_preferred_vco_freq;
2315
2316         for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
2317                 if (!crtc_state->base.enable)
2318                         continue;
2319
2320                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2321                         continue;
2322
2323                 /*
2324                  * DPLL0 VCO may need to be adjusted to get the correct
2325                  * clock for eDP. This will affect cdclk as well.
2326                  */
2327                 switch (crtc_state->port_clock / 2) {
2328                 case 108000:
2329                 case 216000:
2330                         vco = 8640000;
2331                         break;
2332                 default:
2333                         vco = 8100000;
2334                         break;
2335                 }
2336         }
2337
2338         return vco;
2339 }
2340
2341 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
2342 {
2343         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2344         int min_cdclk, cdclk, vco;
2345
2346         min_cdclk = intel_compute_min_cdclk(state);
2347         if (min_cdclk < 0)
2348                 return min_cdclk;
2349
2350         vco = skl_dpll0_vco(intel_state);
2351
2352         /*
2353          * FIXME should also account for plane ratio
2354          * once 64bpp pixel formats are supported.
2355          */
2356         cdclk = skl_calc_cdclk(min_cdclk, vco);
2357
2358         intel_state->cdclk.logical.vco = vco;
2359         intel_state->cdclk.logical.cdclk = cdclk;
2360         intel_state->cdclk.logical.voltage_level =
2361                 skl_calc_voltage_level(cdclk);
2362
2363         if (!intel_state->active_crtcs) {
2364                 cdclk = skl_calc_cdclk(0, vco);
2365
2366                 intel_state->cdclk.actual.vco = vco;
2367                 intel_state->cdclk.actual.cdclk = cdclk;
2368                 intel_state->cdclk.actual.voltage_level =
2369                         skl_calc_voltage_level(cdclk);
2370         } else {
2371                 intel_state->cdclk.actual =
2372                         intel_state->cdclk.logical;
2373         }
2374
2375         return 0;
2376 }
2377
2378 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
2379 {
2380         struct drm_i915_private *dev_priv = to_i915(state->dev);
2381         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2382         int min_cdclk, cdclk, vco;
2383
2384         min_cdclk = intel_compute_min_cdclk(state);
2385         if (min_cdclk < 0)
2386                 return min_cdclk;
2387
2388         if (IS_GEMINILAKE(dev_priv)) {
2389                 cdclk = glk_calc_cdclk(min_cdclk);
2390                 vco = glk_de_pll_vco(dev_priv, cdclk);
2391         } else {
2392                 cdclk = bxt_calc_cdclk(min_cdclk);
2393                 vco = bxt_de_pll_vco(dev_priv, cdclk);
2394         }
2395
2396         intel_state->cdclk.logical.vco = vco;
2397         intel_state->cdclk.logical.cdclk = cdclk;
2398         intel_state->cdclk.logical.voltage_level =
2399                 bxt_calc_voltage_level(cdclk);
2400
2401         if (!intel_state->active_crtcs) {
2402                 if (IS_GEMINILAKE(dev_priv)) {
2403                         cdclk = glk_calc_cdclk(0);
2404                         vco = glk_de_pll_vco(dev_priv, cdclk);
2405                 } else {
2406                         cdclk = bxt_calc_cdclk(0);
2407                         vco = bxt_de_pll_vco(dev_priv, cdclk);
2408                 }
2409
2410                 intel_state->cdclk.actual.vco = vco;
2411                 intel_state->cdclk.actual.cdclk = cdclk;
2412                 intel_state->cdclk.actual.voltage_level =
2413                         bxt_calc_voltage_level(cdclk);
2414         } else {
2415                 intel_state->cdclk.actual =
2416                         intel_state->cdclk.logical;
2417         }
2418
2419         return 0;
2420 }
2421
2422 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
2423 {
2424         struct drm_i915_private *dev_priv = to_i915(state->dev);
2425         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2426         int min_cdclk, cdclk, vco;
2427
2428         min_cdclk = intel_compute_min_cdclk(state);
2429         if (min_cdclk < 0)
2430                 return min_cdclk;
2431
2432         cdclk = cnl_calc_cdclk(min_cdclk);
2433         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2434
2435         intel_state->cdclk.logical.vco = vco;
2436         intel_state->cdclk.logical.cdclk = cdclk;
2437         intel_state->cdclk.logical.voltage_level =
2438                 max(cnl_calc_voltage_level(cdclk),
2439                     cnl_compute_min_voltage_level(intel_state));
2440
2441         if (!intel_state->active_crtcs) {
2442                 cdclk = cnl_calc_cdclk(0);
2443                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2444
2445                 intel_state->cdclk.actual.vco = vco;
2446                 intel_state->cdclk.actual.cdclk = cdclk;
2447                 intel_state->cdclk.actual.voltage_level =
2448                         cnl_calc_voltage_level(cdclk);
2449         } else {
2450                 intel_state->cdclk.actual =
2451                         intel_state->cdclk.logical;
2452         }
2453
2454         return 0;
2455 }
2456
2457 static int icl_modeset_calc_cdclk(struct drm_atomic_state *state)
2458 {
2459         struct drm_i915_private *dev_priv = to_i915(state->dev);
2460         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2461         unsigned int ref = intel_state->cdclk.logical.ref;
2462         int min_cdclk, cdclk, vco;
2463
2464         min_cdclk = intel_compute_min_cdclk(state);
2465         if (min_cdclk < 0)
2466                 return min_cdclk;
2467
2468         cdclk = icl_calc_cdclk(min_cdclk, ref);
2469         vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2470
2471         intel_state->cdclk.logical.vco = vco;
2472         intel_state->cdclk.logical.cdclk = cdclk;
2473
2474         if (!intel_state->active_crtcs) {
2475                 cdclk = icl_calc_cdclk(0, ref);
2476                 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2477
2478                 intel_state->cdclk.actual.vco = vco;
2479                 intel_state->cdclk.actual.cdclk = cdclk;
2480         } else {
2481                 intel_state->cdclk.actual = intel_state->cdclk.logical;
2482         }
2483
2484         return 0;
2485 }
2486
2487 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2488 {
2489         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2490
2491         if (INTEL_GEN(dev_priv) >= 10)
2492                 return 2 * max_cdclk_freq;
2493         else if (IS_GEMINILAKE(dev_priv))
2494                 /*
2495                  * FIXME: Limiting to 99% as a temporary workaround. See
2496                  * intel_min_cdclk() for details.
2497                  */
2498                 return 2 * max_cdclk_freq * 99 / 100;
2499         else if (IS_GEN9(dev_priv) ||
2500                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2501                 return max_cdclk_freq;
2502         else if (IS_CHERRYVIEW(dev_priv))
2503                 return max_cdclk_freq*95/100;
2504         else if (INTEL_GEN(dev_priv) < 4)
2505                 return 2*max_cdclk_freq*90/100;
2506         else
2507                 return max_cdclk_freq*90/100;
2508 }
2509
2510 /**
2511  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2512  * @dev_priv: i915 device
2513  *
2514  * Determine the maximum CDCLK frequency the platform supports, and also
2515  * derive the maximum dot clock frequency the maximum CDCLK frequency
2516  * allows.
2517  */
2518 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2519 {
2520         if (IS_ICELAKE(dev_priv)) {
2521                 if (dev_priv->cdclk.hw.ref == 24000)
2522                         dev_priv->max_cdclk_freq = 648000;
2523                 else
2524                         dev_priv->max_cdclk_freq = 652800;
2525         } else if (IS_CANNONLAKE(dev_priv)) {
2526                 dev_priv->max_cdclk_freq = 528000;
2527         } else if (IS_GEN9_BC(dev_priv)) {
2528                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2529                 int max_cdclk, vco;
2530
2531                 vco = dev_priv->skl_preferred_vco_freq;
2532                 WARN_ON(vco != 8100000 && vco != 8640000);
2533
2534                 /*
2535                  * Use the lower (vco 8640) cdclk values as a
2536                  * first guess. skl_calc_cdclk() will correct it
2537                  * if the preferred vco is 8100 instead.
2538                  */
2539                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2540                         max_cdclk = 617143;
2541                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2542                         max_cdclk = 540000;
2543                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2544                         max_cdclk = 432000;
2545                 else
2546                         max_cdclk = 308571;
2547
2548                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2549         } else if (IS_GEMINILAKE(dev_priv)) {
2550                 dev_priv->max_cdclk_freq = 316800;
2551         } else if (IS_BROXTON(dev_priv)) {
2552                 dev_priv->max_cdclk_freq = 624000;
2553         } else if (IS_BROADWELL(dev_priv))  {
2554                 /*
2555                  * FIXME with extra cooling we can allow
2556                  * 540 MHz for ULX and 675 Mhz for ULT.
2557                  * How can we know if extra cooling is
2558                  * available? PCI ID, VTB, something else?
2559                  */
2560                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2561                         dev_priv->max_cdclk_freq = 450000;
2562                 else if (IS_BDW_ULX(dev_priv))
2563                         dev_priv->max_cdclk_freq = 450000;
2564                 else if (IS_BDW_ULT(dev_priv))
2565                         dev_priv->max_cdclk_freq = 540000;
2566                 else
2567                         dev_priv->max_cdclk_freq = 675000;
2568         } else if (IS_CHERRYVIEW(dev_priv)) {
2569                 dev_priv->max_cdclk_freq = 320000;
2570         } else if (IS_VALLEYVIEW(dev_priv)) {
2571                 dev_priv->max_cdclk_freq = 400000;
2572         } else {
2573                 /* otherwise assume cdclk is fixed */
2574                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2575         }
2576
2577         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2578
2579         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2580                          dev_priv->max_cdclk_freq);
2581
2582         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2583                          dev_priv->max_dotclk_freq);
2584 }
2585
2586 /**
2587  * intel_update_cdclk - Determine the current CDCLK frequency
2588  * @dev_priv: i915 device
2589  *
2590  * Determine the current CDCLK frequency.
2591  */
2592 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2593 {
2594         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2595
2596         /*
2597          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2598          * Programmng [sic] note: bit[9:2] should be programmed to the number
2599          * of cdclk that generates 4MHz reference clock freq which is used to
2600          * generate GMBus clock. This will vary with the cdclk freq.
2601          */
2602         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2603                 I915_WRITE(GMBUSFREQ_VLV,
2604                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2605 }
2606
2607 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2608 {
2609         u32 rawclk;
2610         int divider, fraction;
2611
2612         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2613                 /* 24 MHz */
2614                 divider = 24000;
2615                 fraction = 0;
2616         } else {
2617                 /* 19.2 MHz */
2618                 divider = 19000;
2619                 fraction = 200;
2620         }
2621
2622         rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2623         if (fraction)
2624                 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2625                                                             fraction) - 1);
2626
2627         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2628         return divider + fraction;
2629 }
2630
2631 static int icp_rawclk(struct drm_i915_private *dev_priv)
2632 {
2633         u32 rawclk;
2634         int divider, numerator, denominator, frequency;
2635
2636         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2637                 frequency = 24000;
2638                 divider = 23;
2639                 numerator = 0;
2640                 denominator = 0;
2641         } else {
2642                 frequency = 19200;
2643                 divider = 18;
2644                 numerator = 1;
2645                 denominator = 4;
2646         }
2647
2648         rawclk = CNP_RAWCLK_DIV(divider) | ICP_RAWCLK_NUM(numerator) |
2649                  ICP_RAWCLK_DEN(denominator);
2650
2651         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2652         return frequency;
2653 }
2654
2655 static int pch_rawclk(struct drm_i915_private *dev_priv)
2656 {
2657         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2658 }
2659
2660 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2661 {
2662         /* RAWCLK_FREQ_VLV register updated from power well code */
2663         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2664                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2665 }
2666
2667 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2668 {
2669         uint32_t clkcfg;
2670
2671         /* hrawclock is 1/4 the FSB frequency */
2672         clkcfg = I915_READ(CLKCFG);
2673         switch (clkcfg & CLKCFG_FSB_MASK) {
2674         case CLKCFG_FSB_400:
2675                 return 100000;
2676         case CLKCFG_FSB_533:
2677                 return 133333;
2678         case CLKCFG_FSB_667:
2679                 return 166667;
2680         case CLKCFG_FSB_800:
2681                 return 200000;
2682         case CLKCFG_FSB_1067:
2683         case CLKCFG_FSB_1067_ALT:
2684                 return 266667;
2685         case CLKCFG_FSB_1333:
2686         case CLKCFG_FSB_1333_ALT:
2687                 return 333333;
2688         default:
2689                 return 133333;
2690         }
2691 }
2692
2693 /**
2694  * intel_update_rawclk - Determine the current RAWCLK frequency
2695  * @dev_priv: i915 device
2696  *
2697  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2698  * frequency clock so this needs to done only once.
2699  */
2700 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2701 {
2702         if (HAS_PCH_ICP(dev_priv))
2703                 dev_priv->rawclk_freq = icp_rawclk(dev_priv);
2704         else if (HAS_PCH_CNP(dev_priv))
2705                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2706         else if (HAS_PCH_SPLIT(dev_priv))
2707                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2708         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2709                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2710         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2711                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2712         else
2713                 /* no rawclk on other platforms, or no need to know it */
2714                 return;
2715
2716         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2717 }
2718
2719 /**
2720  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2721  * @dev_priv: i915 device
2722  */
2723 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2724 {
2725         if (IS_CHERRYVIEW(dev_priv)) {
2726                 dev_priv->display.set_cdclk = chv_set_cdclk;
2727                 dev_priv->display.modeset_calc_cdclk =
2728                         vlv_modeset_calc_cdclk;
2729         } else if (IS_VALLEYVIEW(dev_priv)) {
2730                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2731                 dev_priv->display.modeset_calc_cdclk =
2732                         vlv_modeset_calc_cdclk;
2733         } else if (IS_BROADWELL(dev_priv)) {
2734                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2735                 dev_priv->display.modeset_calc_cdclk =
2736                         bdw_modeset_calc_cdclk;
2737         } else if (IS_GEN9_LP(dev_priv)) {
2738                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2739                 dev_priv->display.modeset_calc_cdclk =
2740                         bxt_modeset_calc_cdclk;
2741         } else if (IS_GEN9_BC(dev_priv)) {
2742                 dev_priv->display.set_cdclk = skl_set_cdclk;
2743                 dev_priv->display.modeset_calc_cdclk =
2744                         skl_modeset_calc_cdclk;
2745         } else if (IS_CANNONLAKE(dev_priv)) {
2746                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2747                 dev_priv->display.modeset_calc_cdclk =
2748                         cnl_modeset_calc_cdclk;
2749         } else if (IS_ICELAKE(dev_priv)) {
2750                 dev_priv->display.set_cdclk = icl_set_cdclk;
2751                 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
2752         }
2753
2754         if (IS_ICELAKE(dev_priv))
2755                 dev_priv->display.get_cdclk = icl_get_cdclk;
2756         else if (IS_CANNONLAKE(dev_priv))
2757                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2758         else if (IS_GEN9_BC(dev_priv))
2759                 dev_priv->display.get_cdclk = skl_get_cdclk;
2760         else if (IS_GEN9_LP(dev_priv))
2761                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2762         else if (IS_BROADWELL(dev_priv))
2763                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2764         else if (IS_HASWELL(dev_priv))
2765                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2766         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2767                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2768         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2769                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2770         else if (IS_GEN5(dev_priv))
2771                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2772         else if (IS_GM45(dev_priv))
2773                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2774         else if (IS_G45(dev_priv))
2775                 dev_priv->display.get_cdclk = g33_get_cdclk;
2776         else if (IS_I965GM(dev_priv))
2777                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2778         else if (IS_I965G(dev_priv))
2779                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2780         else if (IS_PINEVIEW(dev_priv))
2781                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2782         else if (IS_G33(dev_priv))
2783                 dev_priv->display.get_cdclk = g33_get_cdclk;
2784         else if (IS_I945GM(dev_priv))
2785                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2786         else if (IS_I945G(dev_priv))
2787                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2788         else if (IS_I915GM(dev_priv))
2789                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2790         else if (IS_I915G(dev_priv))
2791                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2792         else if (IS_I865G(dev_priv))
2793                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2794         else if (IS_I85X(dev_priv))
2795                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2796         else if (IS_I845G(dev_priv))
2797                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2798         else { /* 830 */
2799                 WARN(!IS_I830(dev_priv),
2800                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2801                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2802         }
2803 }