drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Keith Packard <[email protected]>
  26  *    Mika Kuoppala <[email protected]>
  27  *
  28  */
  29
  30 #include <generated/utsrelease.h>
  31 #include <linux/stop_machine.h>
  32 #include <linux/zlib.h>
  33 #include <drm/drm_print.h>
  34
  35 #include "i915_gpu_error.h"
  36 #include "i915_drv.h"
  37
  38 static inline const struct intel_engine_cs *
  39 engine_lookup(const struct drm_i915_private *i915, unsigned int id)
  40 {
  41         if (id >= I915_NUM_ENGINES)
  42                 return NULL;
  43
  44         return i915->engine[id];
  45 }
  46
  47 static inline const char *
  48 __engine_name(const struct intel_engine_cs *engine)
  49 {
  50         return engine ? engine->name : "";
  51 }
  52
  53 static const char *
  54 engine_name(const struct drm_i915_private *i915, unsigned int id)
  55 {
  56         return __engine_name(engine_lookup(i915, id));
  57 }
  58
  59 static const char *tiling_flag(int tiling)
  60 {
  61         switch (tiling) {
  62         default:
  63         case I915_TILING_NONE: return "";
  64         case I915_TILING_X: return " X";
  65         case I915_TILING_Y: return " Y";
  66         }
  67 }
  68
  69 static const char *dirty_flag(int dirty)
  70 {
  71         return dirty ? " dirty" : "";
  72 }
  73
  74 static const char *purgeable_flag(int purgeable)
  75 {
  76         return purgeable ? " purgeable" : "";
  77 }
  78
  79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  80 {
  81
  82         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  83                 e->err = -ENOSPC;
  84                 return false;
  85         }
  86
  87         if (e->bytes == e->size - 1 || e->err)
  88                 return false;
  89
  90         return true;
  91 }
  92
  93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  94                               unsigned len)
  95 {
  96         if (e->pos + len <= e->start) {
  97                 e->pos += len;
  98                 return false;
  99         }
 100
 101         /* First vsnprintf needs to fit in its entirety for memmove */
 102         if (len >= e->size) {
 103                 e->err = -EIO;
 104                 return false;
 105         }
 106
 107         return true;
 108 }
 109
 110 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
 111                                  unsigned len)
 112 {
 113         /* If this is first printf in this window, adjust it so that
 114          * start position matches start of the buffer
 115          */
 116
 117         if (e->pos < e->start) {
 118                 const size_t off = e->start - e->pos;
 119
 120                 /* Should not happen but be paranoid */
 121                 if (off > len || e->bytes) {
 122                         e->err = -EIO;
 123                         return;
 124                 }
 125
 126                 memmove(e->buf, e->buf + off, len - off);
 127                 e->bytes = len - off;
 128                 e->pos = e->start;
 129                 return;
 130         }
 131
 132         e->bytes += len;
 133         e->pos += len;
 134 }
 135
 136 __printf(2, 0)
 137 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 138                                const char *f, va_list args)
 139 {
 140         unsigned len;
 141
 142         if (!__i915_error_ok(e))
 143                 return;
 144
 145         /* Seek the first printf which is hits start position */
 146         if (e->pos < e->start) {
 147                 va_list tmp;
 148
 149                 va_copy(tmp, args);
 150                 len = vsnprintf(NULL, 0, f, tmp);
 151                 va_end(tmp);
 152
 153                 if (!__i915_error_seek(e, len))
 154                         return;
 155         }
 156
 157         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 158         if (len >= e->size - e->bytes)
 159                 len = e->size - e->bytes - 1;
 160
 161         __i915_error_advance(e, len);
 162 }
 163
 164 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 165                             const char *str)
 166 {
 167         unsigned len;
 168
 169         if (!__i915_error_ok(e))
 170                 return;
 171
 172         len = strlen(str);
 173
 174         /* Seek the first printf which is hits start position */
 175         if (e->pos < e->start) {
 176                 if (!__i915_error_seek(e, len))
 177                         return;
 178         }
 179
 180         if (len >= e->size - e->bytes)
 181                 len = e->size - e->bytes - 1;
 182         memcpy(e->buf + e->bytes, str, len);
 183
 184         __i915_error_advance(e, len);
 185 }
 186
 187 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 188 #define err_puts(e, s) i915_error_puts(e, s)
 189
 190 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 191 {
 192         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 193 }
 194
 195 static inline struct drm_printer
 196 i915_error_printer(struct drm_i915_error_state_buf *e)
 197 {
 198         struct drm_printer p = {
 199                 .printfn = __i915_printfn_error,
 200                 .arg = e,
 201         };
 202         return p;
 203 }
 204
 205 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 206
 207 struct compress {
 208         struct z_stream_s zstream;
 209         void *tmp;
 210 };
 211
 212 static bool compress_init(struct compress *c)
 213 {
 214         struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
 215
 216         zstream->workspace =
 217                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 218                         GFP_ATOMIC | __GFP_NOWARN);
 219         if (!zstream->workspace)
 220                 return false;
 221
 222         if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
 223                 kfree(zstream->workspace);
 224                 return false;
 225         }
 226
 227         c->tmp = NULL;
 228         if (i915_has_memcpy_from_wc())
 229                 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 230
 231         return true;
 232 }
 233
 234 static int compress_page(struct compress *c,
 235                          void *src,
 236                          struct drm_i915_error_object *dst)
 237 {
 238         struct z_stream_s *zstream = &c->zstream;
 239
 240         zstream->next_in = src;
 241         if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 242                 zstream->next_in = c->tmp;
 243         zstream->avail_in = PAGE_SIZE;
 244
 245         do {
 246                 if (zstream->avail_out == 0) {
 247                         unsigned long page;
 248
 249                         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 250                         if (!page)
 251                                 return -ENOMEM;
 252
 253                         dst->pages[dst->page_count++] = (void *)page;
 254
 255                         zstream->next_out = (void *)page;
 256                         zstream->avail_out = PAGE_SIZE;
 257                 }
 258
 259                 if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
 260                         return -EIO;
 261         } while (zstream->avail_in);
 262
 263         /* Fallback to uncompressed if we increase size? */
 264         if (0 && zstream->total_out > zstream->total_in)
 265                 return -E2BIG;
 266
 267         return 0;
 268 }
 269
 270 static void compress_fini(struct compress *c,
 271                           struct drm_i915_error_object *dst)
 272 {
 273         struct z_stream_s *zstream = &c->zstream;
 274
 275         if (dst) {
 276                 zlib_deflate(zstream, Z_FINISH);
 277                 dst->unused = zstream->avail_out;
 278         }
 279
 280         zlib_deflateEnd(zstream);
 281         kfree(zstream->workspace);
 282
 283         if (c->tmp)
 284                 free_page((unsigned long)c->tmp);
 285 }
 286
 287 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 288 {
 289         err_puts(m, ":");
 290 }
 291
 292 #else
 293
 294 struct compress {
 295 };
 296
 297 static bool compress_init(struct compress *c)
 298 {
 299         return true;
 300 }
 301
 302 static int compress_page(struct compress *c,
 303                          void *src,
 304                          struct drm_i915_error_object *dst)
 305 {
 306         unsigned long page;
 307         void *ptr;
 308
 309         page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
 310         if (!page)
 311                 return -ENOMEM;
 312
 313         ptr = (void *)page;
 314         if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
 315                 memcpy(ptr, src, PAGE_SIZE);
 316         dst->pages[dst->page_count++] = ptr;
 317
 318         return 0;
 319 }
 320
 321 static void compress_fini(struct compress *c,
 322                           struct drm_i915_error_object *dst)
 323 {
 324 }
 325
 326 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 327 {
 328         err_puts(m, "~");
 329 }
 330
 331 #endif
 332
 333 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 334                                 const char *name,
 335                                 struct drm_i915_error_buffer *err,
 336                                 int count)
 337 {
 338         int i;
 339
 340         err_printf(m, "%s [%d]:\n", name, count);
 341
 342         while (count--) {
 343                 err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
 344                            upper_32_bits(err->gtt_offset),
 345                            lower_32_bits(err->gtt_offset),
 346                            err->size,
 347                            err->read_domains,
 348                            err->write_domain);
 349                 for (i = 0; i < I915_NUM_ENGINES; i++)
 350                         err_printf(m, "%02x ", err->rseqno[i]);
 351
 352                 err_printf(m, "] %02x", err->wseqno);
 353                 err_puts(m, tiling_flag(err->tiling));
 354                 err_puts(m, dirty_flag(err->dirty));
 355                 err_puts(m, purgeable_flag(err->purgeable));
 356                 err_puts(m, err->userptr ? " userptr" : "");
 357                 err_puts(m, err->engine != -1 ? " " : "");
 358                 err_puts(m, engine_name(m->i915, err->engine));
 359                 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
 360
 361                 if (err->name)
 362                         err_printf(m, " (name: %d)", err->name);
 363                 if (err->fence_reg != I915_FENCE_REG_NONE)
 364                         err_printf(m, " (fence: %d)", err->fence_reg);
 365
 366                 err_puts(m, "\n");
 367                 err++;
 368         }
 369 }
 370
 371 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 372                                  const struct drm_i915_error_engine *ee)
 373 {
 374         int slice;
 375         int subslice;
 376
 377         err_printf(m, "  INSTDONE: 0x%08x\n",
 378                    ee->instdone.instdone);
 379
 380         if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
 381                 return;
 382
 383         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 384                    ee->instdone.slice_common);
 385
 386         if (INTEL_GEN(m->i915) <= 6)
 387                 return;
 388
 389         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 390                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 391                            slice, subslice,
 392                            ee->instdone.sampler[slice][subslice]);
 393
 394         for_each_instdone_slice_subslice(m->i915, slice, subslice)
 395                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 396                            slice, subslice,
 397                            ee->instdone.row[slice][subslice]);
 398 }
 399
 400 static const char *bannable(const struct drm_i915_error_context *ctx)
 401 {
 402         return ctx->bannable ? "" : " (unbannable)";
 403 }
 404
 405 static void error_print_request(struct drm_i915_error_state_buf *m,
 406                                 const char *prefix,
 407                                 const struct drm_i915_error_request *erq,
 408                                 const unsigned long epoch)
 409 {
 410         if (!erq->seqno)
 411                 return;
 412
 413         err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n",
 414                    prefix, erq->pid, erq->ban_score,
 415                    erq->context, erq->seqno, erq->sched_attr.priority,
 416                    jiffies_to_msecs(erq->jiffies - epoch),
 417                    erq->start, erq->head, erq->tail);
 418 }
 419
 420 static void error_print_context(struct drm_i915_error_state_buf *m,
 421                                 const char *header,
 422                                 const struct drm_i915_error_context *ctx)
 423 {
 424         err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d%s guilty %d active %d\n",
 425                    header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
 426                    ctx->sched_attr.priority, ctx->ban_score, bannable(ctx),
 427                    ctx->guilty, ctx->active);
 428 }
 429
 430 static void error_print_engine(struct drm_i915_error_state_buf *m,
 431                                const struct drm_i915_error_engine *ee,
 432                                const unsigned long epoch)
 433 {
 434         int n;
 435
 436         err_printf(m, "%s command stream:\n",
 437                    engine_name(m->i915, ee->engine_id));
 438         err_printf(m, "  IDLE?: %s\n", yesno(ee->idle));
 439         err_printf(m, "  START: 0x%08x\n", ee->start);
 440         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 441         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 442                    ee->tail, ee->rq_post, ee->rq_tail);
 443         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 444         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 445         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 446         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 447                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 448         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 449         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 450
 451         error_print_instdone(m, ee);
 452
 453         if (ee->batchbuffer) {
 454                 u64 start = ee->batchbuffer->gtt_offset;
 455                 u64 end = start + ee->batchbuffer->gtt_size;
 456
 457                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 458                            upper_32_bits(start), lower_32_bits(start),
 459                            upper_32_bits(end), lower_32_bits(end));
 460         }
 461         if (INTEL_GEN(m->i915) >= 4) {
 462                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 463                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 464                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 465                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 466         }
 467         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 468         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 469                    lower_32_bits(ee->faddr));
 470         if (INTEL_GEN(m->i915) >= 6) {
 471                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 472                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 473                 err_printf(m, "  SYNC_0: 0x%08x\n",
 474                            ee->semaphore_mboxes[0]);
 475                 err_printf(m, "  SYNC_1: 0x%08x\n",
 476                            ee->semaphore_mboxes[1]);
 477                 if (HAS_VEBOX(m->i915))
 478                         err_printf(m, "  SYNC_2: 0x%08x\n",
 479                                    ee->semaphore_mboxes[2]);
 480         }
 481         if (USES_PPGTT(m->i915)) {
 482                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 483
 484                 if (INTEL_GEN(m->i915) >= 8) {
 485                         int i;
 486                         for (i = 0; i < 4; i++)
 487                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 488                                            i, ee->vm_info.pdp[i]);
 489                 } else {
 490                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 491                                    ee->vm_info.pp_dir_base);
 492                 }
 493         }
 494         err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
 495         err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
 496         err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
 497         err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
 498         err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
 499         err_printf(m, "  hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
 500         err_printf(m, "  hangcheck action: %s\n",
 501                    hangcheck_action_to_str(ee->hangcheck_action));
 502         err_printf(m, "  hangcheck action timestamp: %dms (%lu%s)\n",
 503                    jiffies_to_msecs(ee->hangcheck_timestamp - epoch),
 504                    ee->hangcheck_timestamp,
 505                    ee->hangcheck_timestamp == epoch ? "; epoch" : "");
 506         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 507
 508         for (n = 0; n < ee->num_ports; n++) {
 509                 err_printf(m, "  ELSP[%d]:", n);
 510                 error_print_request(m, " ", &ee->execlist[n], epoch);
 511         }
 512
 513         error_print_context(m, "  Active context: ", &ee->context);
 514 }
 515
 516 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 517 {
 518         va_list args;
 519
 520         va_start(args, f);
 521         i915_error_vprintf(e, f, args);
 522         va_end(args);
 523 }
 524
 525 static int
 526 ascii85_encode_len(int len)
 527 {
 528         return DIV_ROUND_UP(len, 4);
 529 }
 530
 531 static bool
 532 ascii85_encode(u32 in, char *out)
 533 {
 534         int i;
 535
 536         if (in == 0)
 537                 return false;
 538
 539         out[5] = '\0';
 540         for (i = 5; i--; ) {
 541                 out[i] = '!' + in % 85;
 542                 in /= 85;
 543         }
 544
 545         return true;
 546 }
 547
 548 static void print_error_obj(struct drm_i915_error_state_buf *m,
 549                             struct intel_engine_cs *engine,
 550                             const char *name,
 551                             struct drm_i915_error_object *obj)
 552 {
 553         char out[6];
 554         int page;
 555
 556         if (!obj)
 557                 return;
 558
 559         if (name) {
 560                 err_printf(m, "%s --- %s = 0x%08x %08x\n",
 561                            engine ? engine->name : "global", name,
 562                            upper_32_bits(obj->gtt_offset),
 563                            lower_32_bits(obj->gtt_offset));
 564         }
 565
 566         err_compression_marker(m);
 567         for (page = 0; page < obj->page_count; page++) {
 568                 int i, len;
 569
 570                 len = PAGE_SIZE;
 571                 if (page == obj->page_count - 1)
 572                         len -= obj->unused;
 573                 len = ascii85_encode_len(len);
 574
 575                 for (i = 0; i < len; i++) {
 576                         if (ascii85_encode(obj->pages[page][i], out))
 577                                 err_puts(m, out);
 578                         else
 579                                 err_puts(m, "z");
 580                 }
 581         }
 582         err_puts(m, "\n");
 583 }
 584
 585 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 586                                    const struct intel_device_info *info,
 587                                    const struct intel_driver_caps *caps)
 588 {
 589         struct drm_printer p = i915_error_printer(m);
 590
 591         intel_device_info_dump_flags(info, &p);
 592         intel_driver_caps_print(caps, &p);
 593         intel_device_info_dump_topology(&info->sseu, &p);
 594 }
 595
 596 static void err_print_params(struct drm_i915_error_state_buf *m,
 597                              const struct i915_params *params)
 598 {
 599         struct drm_printer p = i915_error_printer(m);
 600
 601         i915_params_dump(params, &p);
 602 }
 603
 604 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 605                             struct drm_i915_private *i915)
 606 {
 607         struct pci_dev *pdev = i915->drm.pdev;
 608
 609         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 610         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 611         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 612                    pdev->subsystem_vendor,
 613                    pdev->subsystem_device);
 614 }
 615
 616 static void err_print_uc(struct drm_i915_error_state_buf *m,
 617                          const struct i915_error_uc *error_uc)
 618 {
 619         struct drm_printer p = i915_error_printer(m);
 620         const struct i915_gpu_state *error =
 621                 container_of(error_uc, typeof(*error), uc);
 622
 623         if (!error->device_info.has_guc)
 624                 return;
 625
 626         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 627         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 628         print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
 629 }
 630
 631 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 632                             const struct i915_gpu_state *error)
 633 {
 634         struct drm_i915_private *dev_priv = m->i915;
 635         struct drm_i915_error_object *obj;
 636         struct timespec64 ts;
 637         int i, j;
 638
 639         if (!error) {
 640                 err_printf(m, "No error state collected\n");
 641                 return 0;
 642         }
 643
 644         if (*error->error_msg)
 645                 err_printf(m, "%s\n", error->error_msg);
 646         err_printf(m, "Kernel: " UTS_RELEASE "\n");
 647         ts = ktime_to_timespec64(error->time);
 648         err_printf(m, "Time: %lld s %ld us\n",
 649                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 650         ts = ktime_to_timespec64(error->boottime);
 651         err_printf(m, "Boottime: %lld s %ld us\n",
 652                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 653         ts = ktime_to_timespec64(error->uptime);
 654         err_printf(m, "Uptime: %lld s %ld us\n",
 655                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 656         err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
 657         err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n",
 658                    error->capture,
 659                    jiffies_to_msecs(jiffies - error->capture),
 660                    jiffies_to_msecs(error->capture - error->epoch));
 661
 662         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 663                 if (error->engine[i].hangcheck_stalled &&
 664                     error->engine[i].context.pid) {
 665                         err_printf(m, "Active process (on ring %s): %s [%d], score %d%s\n",
 666                                    engine_name(m->i915, i),
 667                                    error->engine[i].context.comm,
 668                                    error->engine[i].context.pid,
 669                                    error->engine[i].context.ban_score,
 670                                    bannable(&error->engine[i].context));
 671                 }
 672         }
 673         err_printf(m, "Reset count: %u\n", error->reset_count);
 674         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 675         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 676         err_print_pciid(m, error->i915);
 677
 678         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 679
 680         if (HAS_CSR(dev_priv)) {
 681                 struct intel_csr *csr = &dev_priv->csr;
 682
 683                 err_printf(m, "DMC loaded: %s\n",
 684                            yesno(csr->dmc_payload != NULL));
 685                 err_printf(m, "DMC fw version: %d.%d\n",
 686                            CSR_VERSION_MAJOR(csr->version),
 687                            CSR_VERSION_MINOR(csr->version));
 688         }
 689
 690         err_printf(m, "GT awake: %s\n", yesno(error->awake));
 691         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 692         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 693         err_printf(m, "EIR: 0x%08x\n", error->eir);
 694         err_printf(m, "IER: 0x%08x\n", error->ier);
 695         for (i = 0; i < error->ngtier; i++)
 696                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
 697         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 698         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 699         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 700         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 701         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 702
 703         for (i = 0; i < error->nfence; i++)
 704                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 705
 706         if (INTEL_GEN(dev_priv) >= 6) {
 707                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 708
 709                 if (INTEL_GEN(dev_priv) >= 8)
 710                         err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 711                                    error->fault_data1, error->fault_data0);
 712
 713                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 714         }
 715
 716         if (IS_GEN7(dev_priv))
 717                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 718
 719         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 720                 if (error->engine[i].engine_id != -1)
 721                         error_print_engine(m, &error->engine[i], error->epoch);
 722         }
 723
 724         for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
 725                 char buf[128];
 726                 int len, first = 1;
 727
 728                 if (!error->active_vm[i])
 729                         break;
 730
 731                 len = scnprintf(buf, sizeof(buf), "Active (");
 732                 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
 733                         if (error->engine[j].vm != error->active_vm[i])
 734                                 continue;
 735
 736                         len += scnprintf(buf + len, sizeof(buf), "%s%s",
 737                                          first ? "" : ", ",
 738                                          dev_priv->engine[j]->name);
 739                         first = 0;
 740                 }
 741                 scnprintf(buf + len, sizeof(buf), ")");
 742                 print_error_buffers(m, buf,
 743                                     error->active_bo[i],
 744                                     error->active_bo_count[i]);
 745         }
 746
 747         print_error_buffers(m, "Pinned (global)",
 748                             error->pinned_bo,
 749                             error->pinned_bo_count);
 750
 751         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 752                 const struct drm_i915_error_engine *ee = &error->engine[i];
 753
 754                 obj = ee->batchbuffer;
 755                 if (obj) {
 756                         err_puts(m, dev_priv->engine[i]->name);
 757                         if (ee->context.pid)
 758                                 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d%s)",
 759                                            ee->context.comm,
 760                                            ee->context.pid,
 761                                            ee->context.handle,
 762                                            ee->context.hw_id,
 763                                            ee->context.ban_score,
 764                                            bannable(&ee->context));
 765                         err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 766                                    upper_32_bits(obj->gtt_offset),
 767                                    lower_32_bits(obj->gtt_offset));
 768                         print_error_obj(m, dev_priv->engine[i], NULL, obj);
 769                 }
 770
 771                 for (j = 0; j < ee->user_bo_count; j++)
 772                         print_error_obj(m, dev_priv->engine[i],
 773                                         "user", ee->user_bo[j]);
 774
 775                 if (ee->num_requests) {
 776                         err_printf(m, "%s --- %d requests\n",
 777                                    dev_priv->engine[i]->name,
 778                                    ee->num_requests);
 779                         for (j = 0; j < ee->num_requests; j++)
 780                                 error_print_request(m, " ",
 781                                                     &ee->requests[j],
 782                                                     error->epoch);
 783                 }
 784
 785                 if (IS_ERR(ee->waiters)) {
 786                         err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
 787                                    dev_priv->engine[i]->name);
 788                 } else if (ee->num_waiters) {
 789                         err_printf(m, "%s --- %d waiters\n",
 790                                    dev_priv->engine[i]->name,
 791                                    ee->num_waiters);
 792                         for (j = 0; j < ee->num_waiters; j++) {
 793                                 err_printf(m, " seqno 0x%08x for %s [%d]\n",
 794                                            ee->waiters[j].seqno,
 795                                            ee->waiters[j].comm,
 796                                            ee->waiters[j].pid);
 797                         }
 798                 }
 799
 800                 print_error_obj(m, dev_priv->engine[i],
 801                                 "ringbuffer", ee->ringbuffer);
 802
 803                 print_error_obj(m, dev_priv->engine[i],
 804                                 "HW Status", ee->hws_page);
 805
 806                 print_error_obj(m, dev_priv->engine[i],
 807                                 "HW context", ee->ctx);
 808
 809                 print_error_obj(m, dev_priv->engine[i],
 810                                 "WA context", ee->wa_ctx);
 811
 812                 print_error_obj(m, dev_priv->engine[i],
 813                                 "WA batchbuffer", ee->wa_batchbuffer);
 814
 815                 print_error_obj(m, dev_priv->engine[i],
 816                                 "NULL context", ee->default_state);
 817         }
 818
 819         if (error->overlay)
 820                 intel_overlay_print_error_state(m, error->overlay);
 821
 822         if (error->display)
 823                 intel_display_print_error_state(m, error->display);
 824
 825         err_print_capabilities(m, &error->device_info, &error->driver_caps);
 826         err_print_params(m, &error->params);
 827         err_print_uc(m, &error->uc);
 828
 829         if (m->bytes == 0 && m->err)
 830                 return m->err;
 831
 832         return 0;
 833 }
 834
 835 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 836                               struct drm_i915_private *i915,
 837                               size_t count, loff_t pos)
 838 {
 839         memset(ebuf, 0, sizeof(*ebuf));
 840         ebuf->i915 = i915;
 841
 842         /* We need to have enough room to store any i915_error_state printf
 843          * so that we can move it to start position.
 844          */
 845         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 846         ebuf->buf = kmalloc(ebuf->size,
 847                                 GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
 848
 849         if (ebuf->buf == NULL) {
 850                 ebuf->size = PAGE_SIZE;
 851                 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
 852         }
 853
 854         if (ebuf->buf == NULL) {
 855                 ebuf->size = 128;
 856                 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
 857         }
 858
 859         if (ebuf->buf == NULL)
 860                 return -ENOMEM;
 861
 862         ebuf->start = pos;
 863
 864         return 0;
 865 }
 866
 867 static void i915_error_object_free(struct drm_i915_error_object *obj)
 868 {
 869         int page;
 870
 871         if (obj == NULL)
 872                 return;
 873
 874         for (page = 0; page < obj->page_count; page++)
 875                 free_page((unsigned long)obj->pages[page]);
 876
 877         kfree(obj);
 878 }
 879
 880 static __always_inline void free_param(const char *type, void *x)
 881 {
 882         if (!__builtin_strcmp(type, "char *"))
 883                 kfree(*(void **)x);
 884 }
 885
 886 static void cleanup_params(struct i915_gpu_state *error)
 887 {
 888 #define FREE(T, x, ...) free_param(#T, &error->params.x);
 889         I915_PARAMS_FOR_EACH(FREE);
 890 #undef FREE
 891 }
 892
 893 static void cleanup_uc_state(struct i915_gpu_state *error)
 894 {
 895         struct i915_error_uc *error_uc = &error->uc;
 896
 897         kfree(error_uc->guc_fw.path);
 898         kfree(error_uc->huc_fw.path);
 899         i915_error_object_free(error_uc->guc_log);
 900 }
 901
 902 void __i915_gpu_state_free(struct kref *error_ref)
 903 {
 904         struct i915_gpu_state *error =
 905                 container_of(error_ref, typeof(*error), ref);
 906         long i, j;
 907
 908         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
 909                 struct drm_i915_error_engine *ee = &error->engine[i];
 910
 911                 for (j = 0; j < ee->user_bo_count; j++)
 912                         i915_error_object_free(ee->user_bo[j]);
 913                 kfree(ee->user_bo);
 914
 915                 i915_error_object_free(ee->batchbuffer);
 916                 i915_error_object_free(ee->wa_batchbuffer);
 917                 i915_error_object_free(ee->ringbuffer);
 918                 i915_error_object_free(ee->hws_page);
 919                 i915_error_object_free(ee->ctx);
 920                 i915_error_object_free(ee->wa_ctx);
 921
 922                 kfree(ee->requests);
 923                 if (!IS_ERR_OR_NULL(ee->waiters))
 924                         kfree(ee->waiters);
 925         }
 926
 927         for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
 928                 kfree(error->active_bo[i]);
 929         kfree(error->pinned_bo);
 930
 931         kfree(error->overlay);
 932         kfree(error->display);
 933
 934         cleanup_params(error);
 935         cleanup_uc_state(error);
 936
 937         kfree(error);
 938 }
 939
 940 static struct drm_i915_error_object *
 941 i915_error_object_create(struct drm_i915_private *i915,
 942                          struct i915_vma *vma)
 943 {
 944         struct i915_ggtt *ggtt = &i915->ggtt;
 945         const u64 slot = ggtt->error_capture.start;
 946         struct drm_i915_error_object *dst;
 947         struct compress compress;
 948         unsigned long num_pages;
 949         struct sgt_iter iter;
 950         dma_addr_t dma;
 951
 952         if (!vma)
 953                 return NULL;
 954
 955         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
 956         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
 957         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
 958                       GFP_ATOMIC | __GFP_NOWARN);
 959         if (!dst)
 960                 return NULL;
 961
 962         dst->gtt_offset = vma->node.start;
 963         dst->gtt_size = vma->node.size;
 964         dst->page_count = 0;
 965         dst->unused = 0;
 966
 967         if (!compress_init(&compress)) {
 968                 kfree(dst);
 969                 return NULL;
 970         }
 971
 972         for_each_sgt_dma(dma, iter, vma->pages) {
 973                 void __iomem *s;
 974                 int ret;
 975
 976                 ggtt->base.insert_page(&ggtt->base, dma, slot,
 977                                        I915_CACHE_NONE, 0);
 978
 979                 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
 980                 ret = compress_page(&compress, (void  __force *)s, dst);
 981                 io_mapping_unmap_atomic(s);
 982
 983                 if (ret)
 984                         goto unwind;
 985         }
 986         goto out;
 987
 988 unwind:
 989         while (dst->page_count--)
 990                 free_page((unsigned long)dst->pages[dst->page_count]);
 991         kfree(dst);
 992         dst = NULL;
 993
 994 out:
 995         compress_fini(&compress, dst);
 996         ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE);
 997         return dst;
 998 }
 999
1000 /* The error capture is special as tries to run underneath the normal
1001  * locking rules - so we use the raw version of the i915_gem_active lookup.
1002  */
1003 static inline uint32_t
1004 __active_get_seqno(struct i915_gem_active *active)
1005 {
1006         struct i915_request *request;
1007
1008         request = __i915_gem_active_peek(active);
1009         return request ? request->global_seqno : 0;
1010 }
1011
1012 static inline int
1013 __active_get_engine_id(struct i915_gem_active *active)
1014 {
1015         struct i915_request *request;
1016
1017         request = __i915_gem_active_peek(active);
1018         return request ? request->engine->id : -1;
1019 }
1020
1021 static void capture_bo(struct drm_i915_error_buffer *err,
1022                        struct i915_vma *vma)
1023 {
1024         struct drm_i915_gem_object *obj = vma->obj;
1025         int i;
1026
1027         err->size = obj->base.size;
1028         err->name = obj->base.name;
1029
1030         for (i = 0; i < I915_NUM_ENGINES; i++)
1031                 err->rseqno[i] = __active_get_seqno(&vma->last_read[i]);
1032         err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
1033         err->engine = __active_get_engine_id(&obj->frontbuffer_write);
1034
1035         err->gtt_offset = vma->node.start;
1036         err->read_domains = obj->read_domains;
1037         err->write_domain = obj->write_domain;
1038         err->fence_reg = vma->fence ? vma->fence->id : -1;
1039         err->tiling = i915_gem_object_get_tiling(obj);
1040         err->dirty = obj->mm.dirty;
1041         err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
1042         err->userptr = obj->userptr.mm != NULL;
1043         err->cache_level = obj->cache_level;
1044 }
1045
1046 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
1047                             int count, struct list_head *head,
1048                             bool pinned_only)
1049 {
1050         struct i915_vma *vma;
1051         int i = 0;
1052
1053         list_for_each_entry(vma, head, vm_link) {
1054                 if (pinned_only && !i915_vma_is_pinned(vma))
1055                         continue;
1056
1057                 capture_bo(err++, vma);
1058                 if (++i == count)
1059                         break;
1060         }
1061
1062         return i;
1063 }
1064
1065 /* Generate a semi-unique error code. The code is not meant to have meaning, The
1066  * code's only purpose is to try to prevent false duplicated bug reports by
1067  * grossly estimating a GPU error state.
1068  *
1069  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1070  * the hang if we could strip the GTT offset information from it.
1071  *
1072  * It's only a small step better than a random number in its current form.
1073  */
1074 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
1075                                          struct i915_gpu_state *error,
1076                                          int *engine_id)
1077 {
1078         uint32_t error_code = 0;
1079         int i;
1080
1081         /* IPEHR would be an ideal way to detect errors, as it's the gross
1082          * measure of "the command that hung." However, has some very common
1083          * synchronization commands which almost always appear in the case
1084          * strictly a client bug. Use instdone to differentiate those some.
1085          */
1086         for (i = 0; i < I915_NUM_ENGINES; i++) {
1087                 if (error->engine[i].hangcheck_stalled) {
1088                         if (engine_id)
1089                                 *engine_id = i;
1090
1091                         return error->engine[i].ipehr ^
1092                                error->engine[i].instdone.instdone;
1093                 }
1094         }
1095
1096         return error_code;
1097 }
1098
1099 static void gem_record_fences(struct i915_gpu_state *error)
1100 {
1101         struct drm_i915_private *dev_priv = error->i915;
1102         int i;
1103
1104         if (INTEL_GEN(dev_priv) >= 6) {
1105                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1106                         error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1107         } else if (INTEL_GEN(dev_priv) >= 4) {
1108                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1109                         error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1110         } else {
1111                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1112                         error->fence[i] = I915_READ(FENCE_REG(i));
1113         }
1114         error->nfence = i;
1115 }
1116
1117 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1118                                         struct drm_i915_error_engine *ee)
1119 {
1120         struct drm_i915_private *dev_priv = engine->i915;
1121
1122         ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1123         ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1124         if (HAS_VEBOX(dev_priv))
1125                 ee->semaphore_mboxes[2] =
1126                         I915_READ(RING_SYNC_2(engine->mmio_base));
1127 }
1128
1129 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1130                                         struct drm_i915_error_engine *ee)
1131 {
1132         struct intel_breadcrumbs *b = &engine->breadcrumbs;
1133         struct drm_i915_error_waiter *waiter;
1134         struct rb_node *rb;
1135         int count;
1136
1137         ee->num_waiters = 0;
1138         ee->waiters = NULL;
1139
1140         if (RB_EMPTY_ROOT(&b->waiters))
1141                 return;
1142
1143         if (!spin_trylock_irq(&b->rb_lock)) {
1144                 ee->waiters = ERR_PTR(-EDEADLK);
1145                 return;
1146         }
1147
1148         count = 0;
1149         for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1150                 count++;
1151         spin_unlock_irq(&b->rb_lock);
1152
1153         waiter = NULL;
1154         if (count)
1155                 waiter = kmalloc_array(count,
1156                                        sizeof(struct drm_i915_error_waiter),
1157                                        GFP_ATOMIC);
1158         if (!waiter)
1159                 return;
1160
1161         if (!spin_trylock_irq(&b->rb_lock)) {
1162                 kfree(waiter);
1163                 ee->waiters = ERR_PTR(-EDEADLK);
1164                 return;
1165         }
1166
1167         ee->waiters = waiter;
1168         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1169                 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1170
1171                 strcpy(waiter->comm, w->tsk->comm);
1172                 waiter->pid = w->tsk->pid;
1173                 waiter->seqno = w->seqno;
1174                 waiter++;
1175
1176                 if (++ee->num_waiters == count)
1177                         break;
1178         }
1179         spin_unlock_irq(&b->rb_lock);
1180 }
1181
1182 static void error_record_engine_registers(struct i915_gpu_state *error,
1183                                           struct intel_engine_cs *engine,
1184                                           struct drm_i915_error_engine *ee)
1185 {
1186         struct drm_i915_private *dev_priv = engine->i915;
1187
1188         if (INTEL_GEN(dev_priv) >= 6) {
1189                 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1190                 if (INTEL_GEN(dev_priv) >= 8) {
1191                         ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
1192                 } else {
1193                         gen6_record_semaphore_state(engine, ee);
1194                         ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1195                 }
1196         }
1197
1198         if (INTEL_GEN(dev_priv) >= 4) {
1199                 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1200                 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1201                 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1202                 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1203                 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1204                 if (INTEL_GEN(dev_priv) >= 8) {
1205                         ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1206                         ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1207                 }
1208                 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1209         } else {
1210                 ee->faddr = I915_READ(DMA_FADD_I8XX);
1211                 ee->ipeir = I915_READ(IPEIR);
1212                 ee->ipehr = I915_READ(IPEHR);
1213         }
1214
1215         intel_engine_get_instdone(engine, &ee->instdone);
1216
1217         ee->waiting = intel_engine_has_waiter(engine);
1218         ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1219         ee->acthd = intel_engine_get_active_head(engine);
1220         ee->seqno = intel_engine_get_seqno(engine);
1221         ee->last_seqno = intel_engine_last_submit(engine);
1222         ee->start = I915_READ_START(engine);
1223         ee->head = I915_READ_HEAD(engine);
1224         ee->tail = I915_READ_TAIL(engine);
1225         ee->ctl = I915_READ_CTL(engine);
1226         if (INTEL_GEN(dev_priv) > 2)
1227                 ee->mode = I915_READ_MODE(engine);
1228
1229         if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1230                 i915_reg_t mmio;
1231
1232                 if (IS_GEN7(dev_priv)) {
1233                         switch (engine->id) {
1234                         default:
1235                         case RCS:
1236                                 mmio = RENDER_HWS_PGA_GEN7;
1237                                 break;
1238                         case BCS:
1239                                 mmio = BLT_HWS_PGA_GEN7;
1240                                 break;
1241                         case VCS:
1242                                 mmio = BSD_HWS_PGA_GEN7;
1243                                 break;
1244                         case VECS:
1245                                 mmio = VEBOX_HWS_PGA_GEN7;
1246                                 break;
1247                         }
1248                 } else if (IS_GEN6(engine->i915)) {
1249                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1250                 } else {
1251                         /* XXX: gen8 returns to sanity */
1252                         mmio = RING_HWS_PGA(engine->mmio_base);
1253                 }
1254
1255                 ee->hws = I915_READ(mmio);
1256         }
1257
1258         ee->idle = intel_engine_is_idle(engine);
1259         ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1260         ee->hangcheck_action = engine->hangcheck.action;
1261         ee->hangcheck_stalled = engine->hangcheck.stalled;
1262         ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1263                                                   engine);
1264
1265         if (USES_PPGTT(dev_priv)) {
1266                 int i;
1267
1268                 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1269
1270                 if (IS_GEN6(dev_priv))
1271                         ee->vm_info.pp_dir_base =
1272                                 I915_READ(RING_PP_DIR_BASE_READ(engine));
1273                 else if (IS_GEN7(dev_priv))
1274                         ee->vm_info.pp_dir_base =
1275                                 I915_READ(RING_PP_DIR_BASE(engine));
1276                 else if (INTEL_GEN(dev_priv) >= 8)
1277                         for (i = 0; i < 4; i++) {
1278                                 ee->vm_info.pdp[i] =
1279                                         I915_READ(GEN8_RING_PDP_UDW(engine, i));
1280                                 ee->vm_info.pdp[i] <<= 32;
1281                                 ee->vm_info.pdp[i] |=
1282                                         I915_READ(GEN8_RING_PDP_LDW(engine, i));
1283                         }
1284         }
1285 }
1286
1287 static void record_request(struct i915_request *request,
1288                            struct drm_i915_error_request *erq)
1289 {
1290         erq->context = request->ctx->hw_id;
1291         erq->sched_attr = request->sched.attr;
1292         erq->ban_score = atomic_read(&request->ctx->ban_score);
1293         erq->seqno = request->global_seqno;
1294         erq->jiffies = request->emitted_jiffies;
1295         erq->start = i915_ggtt_offset(request->ring->vma);
1296         erq->head = request->head;
1297         erq->tail = request->tail;
1298
1299         rcu_read_lock();
1300         erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
1301         rcu_read_unlock();
1302 }
1303
1304 static void engine_record_requests(struct intel_engine_cs *engine,
1305                                    struct i915_request *first,
1306                                    struct drm_i915_error_engine *ee)
1307 {
1308         struct i915_request *request;
1309         int count;
1310
1311         count = 0;
1312         request = first;
1313         list_for_each_entry_from(request, &engine->timeline.requests, link)
1314                 count++;
1315         if (!count)
1316                 return;
1317
1318         ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1319         if (!ee->requests)
1320                 return;
1321
1322         ee->num_requests = count;
1323
1324         count = 0;
1325         request = first;
1326         list_for_each_entry_from(request, &engine->timeline.requests, link) {
1327                 if (count >= ee->num_requests) {
1328                         /*
1329                          * If the ring request list was changed in
1330                          * between the point where the error request
1331                          * list was created and dimensioned and this
1332                          * point then just exit early to avoid crashes.
1333                          *
1334                          * We don't need to communicate that the
1335                          * request list changed state during error
1336                          * state capture and that the error state is
1337                          * slightly incorrect as a consequence since we
1338                          * are typically only interested in the request
1339                          * list state at the point of error state
1340                          * capture, not in any changes happening during
1341                          * the capture.
1342                          */
1343                         break;
1344                 }
1345
1346                 record_request(request, &ee->requests[count++]);
1347         }
1348         ee->num_requests = count;
1349 }
1350
1351 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1352                                           struct drm_i915_error_engine *ee)
1353 {
1354         const struct intel_engine_execlists * const execlists = &engine->execlists;
1355         unsigned int n;
1356
1357         for (n = 0; n < execlists_num_ports(execlists); n++) {
1358                 struct i915_request *rq = port_request(&execlists->port[n]);
1359
1360                 if (!rq)
1361                         break;
1362
1363                 record_request(rq, &ee->execlist[n]);
1364         }
1365
1366         ee->num_ports = n;
1367 }
1368
1369 static void record_context(struct drm_i915_error_context *e,
1370                            struct i915_gem_context *ctx)
1371 {
1372         if (ctx->pid) {
1373                 struct task_struct *task;
1374
1375                 rcu_read_lock();
1376                 task = pid_task(ctx->pid, PIDTYPE_PID);
1377                 if (task) {
1378                         strcpy(e->comm, task->comm);
1379                         e->pid = task->pid;
1380                 }
1381                 rcu_read_unlock();
1382         }
1383
1384         e->handle = ctx->user_handle;
1385         e->hw_id = ctx->hw_id;
1386         e->sched_attr = ctx->sched;
1387         e->ban_score = atomic_read(&ctx->ban_score);
1388         e->bannable = i915_gem_context_is_bannable(ctx);
1389         e->guilty = atomic_read(&ctx->guilty_count);
1390         e->active = atomic_read(&ctx->active_count);
1391 }
1392
1393 static void request_record_user_bo(struct i915_request *request,
1394                                    struct drm_i915_error_engine *ee)
1395 {
1396         struct i915_capture_list *c;
1397         struct drm_i915_error_object **bo;
1398         long count;
1399
1400         count = 0;
1401         for (c = request->capture_list; c; c = c->next)
1402                 count++;
1403
1404         bo = NULL;
1405         if (count)
1406                 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
1407         if (!bo)
1408                 return;
1409
1410         count = 0;
1411         for (c = request->capture_list; c; c = c->next) {
1412                 bo[count] = i915_error_object_create(request->i915, c->vma);
1413                 if (!bo[count])
1414                         break;
1415                 count++;
1416         }
1417
1418         ee->user_bo = bo;
1419         ee->user_bo_count = count;
1420 }
1421
1422 static struct drm_i915_error_object *
1423 capture_object(struct drm_i915_private *dev_priv,
1424                struct drm_i915_gem_object *obj)
1425 {
1426         if (obj && i915_gem_object_has_pages(obj)) {
1427                 struct i915_vma fake = {
1428                         .node = { .start = U64_MAX, .size = obj->base.size },
1429                         .size = obj->base.size,
1430                         .pages = obj->mm.pages,
1431                         .obj = obj,
1432                 };
1433
1434                 return i915_error_object_create(dev_priv, &fake);
1435         } else {
1436                 return NULL;
1437         }
1438 }
1439
1440 static void gem_record_rings(struct i915_gpu_state *error)
1441 {
1442         struct drm_i915_private *i915 = error->i915;
1443         struct i915_ggtt *ggtt = &i915->ggtt;
1444         int i;
1445
1446         for (i = 0; i < I915_NUM_ENGINES; i++) {
1447                 struct intel_engine_cs *engine = i915->engine[i];
1448                 struct drm_i915_error_engine *ee = &error->engine[i];
1449                 struct i915_request *request;
1450
1451                 ee->engine_id = -1;
1452
1453                 if (!engine)
1454                         continue;
1455
1456                 ee->engine_id = i;
1457
1458                 error_record_engine_registers(error, engine, ee);
1459                 error_record_engine_waiters(engine, ee);
1460                 error_record_engine_execlists(engine, ee);
1461
1462                 request = i915_gem_find_active_request(engine);
1463                 if (request) {
1464                         struct intel_ring *ring;
1465
1466                         ee->vm = request->ctx->ppgtt ?
1467                                 &request->ctx->ppgtt->base : &ggtt->base;
1468
1469                         record_context(&ee->context, request->ctx);
1470
1471                         /* We need to copy these to an anonymous buffer
1472                          * as the simplest method to avoid being overwritten
1473                          * by userspace.
1474                          */
1475                         ee->batchbuffer =
1476                                 i915_error_object_create(i915, request->batch);
1477
1478                         if (HAS_BROKEN_CS_TLB(i915))
1479                                 ee->wa_batchbuffer =
1480                                         i915_error_object_create(i915,
1481                                                                  engine->scratch);
1482                         request_record_user_bo(request, ee);
1483
1484                         ee->ctx =
1485                                 i915_error_object_create(i915,
1486                                                          to_intel_context(request->ctx,
1487                                                                           engine)->state);
1488
1489                         error->simulated |=
1490                                 i915_gem_context_no_error_capture(request->ctx);
1491
1492                         ee->rq_head = request->head;
1493                         ee->rq_post = request->postfix;
1494                         ee->rq_tail = request->tail;
1495
1496                         ring = request->ring;
1497                         ee->cpu_ring_head = ring->head;
1498                         ee->cpu_ring_tail = ring->tail;
1499                         ee->ringbuffer =
1500                                 i915_error_object_create(i915, ring->vma);
1501
1502                         engine_record_requests(engine, request, ee);
1503                 }
1504
1505                 ee->hws_page =
1506                         i915_error_object_create(i915,
1507                                                  engine->status_page.vma);
1508
1509                 ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
1510
1511                 ee->default_state = capture_object(i915, engine->default_state);
1512         }
1513 }
1514
1515 static void gem_capture_vm(struct i915_gpu_state *error,
1516                            struct i915_address_space *vm,
1517                            int idx)
1518 {
1519         struct drm_i915_error_buffer *active_bo;
1520         struct i915_vma *vma;
1521         int count;
1522
1523         count = 0;
1524         list_for_each_entry(vma, &vm->active_list, vm_link)
1525                 count++;
1526
1527         active_bo = NULL;
1528         if (count)
1529                 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1530         if (active_bo)
1531                 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1532         else
1533                 count = 0;
1534
1535         error->active_vm[idx] = vm;
1536         error->active_bo[idx] = active_bo;
1537         error->active_bo_count[idx] = count;
1538 }
1539
1540 static void capture_active_buffers(struct i915_gpu_state *error)
1541 {
1542         int cnt = 0, i, j;
1543
1544         BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1545         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1546         BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1547
1548         /* Scan each engine looking for unique active contexts/vm */
1549         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1550                 struct drm_i915_error_engine *ee = &error->engine[i];
1551                 bool found;
1552
1553                 if (!ee->vm)
1554                         continue;
1555
1556                 found = false;
1557                 for (j = 0; j < i && !found; j++)
1558                         found = error->engine[j].vm == ee->vm;
1559                 if (!found)
1560                         gem_capture_vm(error, ee->vm, cnt++);
1561         }
1562 }
1563
1564 static void capture_pinned_buffers(struct i915_gpu_state *error)
1565 {
1566         struct i915_address_space *vm = &error->i915->ggtt.base;
1567         struct drm_i915_error_buffer *bo;
1568         struct i915_vma *vma;
1569         int count_inactive, count_active;
1570
1571         count_inactive = 0;
1572         list_for_each_entry(vma, &vm->active_list, vm_link)
1573                 count_inactive++;
1574
1575         count_active = 0;
1576         list_for_each_entry(vma, &vm->inactive_list, vm_link)
1577                 count_active++;
1578
1579         bo = NULL;
1580         if (count_inactive + count_active)
1581                 bo = kcalloc(count_inactive + count_active,
1582                              sizeof(*bo), GFP_ATOMIC);
1583         if (!bo)
1584                 return;
1585
1586         count_inactive = capture_error_bo(bo, count_inactive,
1587                                           &vm->active_list, true);
1588         count_active = capture_error_bo(bo + count_inactive, count_active,
1589                                         &vm->inactive_list, true);
1590         error->pinned_bo_count = count_inactive + count_active;
1591         error->pinned_bo = bo;
1592 }
1593
1594 static void capture_uc_state(struct i915_gpu_state *error)
1595 {
1596         struct drm_i915_private *i915 = error->i915;
1597         struct i915_error_uc *error_uc = &error->uc;
1598
1599         /* Capturing uC state won't be useful if there is no GuC */
1600         if (!error->device_info.has_guc)
1601                 return;
1602
1603         error_uc->guc_fw = i915->guc.fw;
1604         error_uc->huc_fw = i915->huc.fw;
1605
1606         /* Non-default firmware paths will be specified by the modparam.
1607          * As modparams are generally accesible from the userspace make
1608          * explicit copies of the firmware paths.
1609          */
1610         error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
1611         error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
1612         error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
1613 }
1614
1615 /* Capture all registers which don't fit into another category. */
1616 static void capture_reg_state(struct i915_gpu_state *error)
1617 {
1618         struct drm_i915_private *dev_priv = error->i915;
1619         int i;
1620
1621         /* General organization
1622          * 1. Registers specific to a single generation
1623          * 2. Registers which belong to multiple generations
1624          * 3. Feature specific registers.
1625          * 4. Everything else
1626          * Please try to follow the order.
1627          */
1628
1629         /* 1: Registers specific to a single generation */
1630         if (IS_VALLEYVIEW(dev_priv)) {
1631                 error->gtier[0] = I915_READ(GTIER);
1632                 error->ier = I915_READ(VLV_IER);
1633                 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1634         }
1635
1636         if (IS_GEN7(dev_priv))
1637                 error->err_int = I915_READ(GEN7_ERR_INT);
1638
1639         if (INTEL_GEN(dev_priv) >= 8) {
1640                 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1641                 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1642         }
1643
1644         if (IS_GEN6(dev_priv)) {
1645                 error->forcewake = I915_READ_FW(FORCEWAKE);
1646                 error->gab_ctl = I915_READ(GAB_CTL);
1647                 error->gfx_mode = I915_READ(GFX_MODE);
1648         }
1649
1650         /* 2: Registers which belong to multiple generations */
1651         if (INTEL_GEN(dev_priv) >= 7)
1652                 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1653
1654         if (INTEL_GEN(dev_priv) >= 6) {
1655                 error->derrmr = I915_READ(DERRMR);
1656                 error->error = I915_READ(ERROR_GEN6);
1657                 error->done_reg = I915_READ(DONE_REG);
1658         }
1659
1660         if (INTEL_GEN(dev_priv) >= 5)
1661                 error->ccid = I915_READ(CCID);
1662
1663         /* 3: Feature specific registers */
1664         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1665                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1666                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1667         }
1668
1669         /* 4: Everything else */
1670         if (INTEL_GEN(dev_priv) >= 8) {
1671                 error->ier = I915_READ(GEN8_DE_MISC_IER);
1672                 for (i = 0; i < 4; i++)
1673                         error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1674                 error->ngtier = 4;
1675         } else if (HAS_PCH_SPLIT(dev_priv)) {
1676                 error->ier = I915_READ(DEIER);
1677                 error->gtier[0] = I915_READ(GTIER);
1678                 error->ngtier = 1;
1679         } else if (IS_GEN2(dev_priv)) {
1680                 error->ier = I915_READ16(IER);
1681         } else if (!IS_VALLEYVIEW(dev_priv)) {
1682                 error->ier = I915_READ(IER);
1683         }
1684         error->eir = I915_READ(EIR);
1685         error->pgtbl_er = I915_READ(PGTBL_ER);
1686 }
1687
1688 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1689                                    struct i915_gpu_state *error,
1690                                    u32 engine_mask,
1691                                    const char *error_msg)
1692 {
1693         u32 ecode;
1694         int engine_id = -1, len;
1695
1696         ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1697
1698         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1699                         "GPU HANG: ecode %d:%d:0x%08x",
1700                         INTEL_GEN(dev_priv), engine_id, ecode);
1701
1702         if (engine_id != -1 && error->engine[engine_id].context.pid)
1703                 len += scnprintf(error->error_msg + len,
1704                                  sizeof(error->error_msg) - len,
1705                                  ", in %s [%d]",
1706                                  error->engine[engine_id].context.comm,
1707                                  error->engine[engine_id].context.pid);
1708
1709         scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1710                   ", reason: %s, action: %s",
1711                   error_msg,
1712                   engine_mask ? "reset" : "continue");
1713 }
1714
1715 static void capture_gen_state(struct i915_gpu_state *error)
1716 {
1717         struct drm_i915_private *i915 = error->i915;
1718
1719         error->awake = i915->gt.awake;
1720         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1721         error->suspended = i915->runtime_pm.suspended;
1722
1723         error->iommu = -1;
1724 #ifdef CONFIG_INTEL_IOMMU
1725         error->iommu = intel_iommu_gfx_mapped;
1726 #endif
1727         error->reset_count = i915_reset_count(&i915->gpu_error);
1728         error->suspend_count = i915->suspend_count;
1729
1730         memcpy(&error->device_info,
1731                INTEL_INFO(i915),
1732                sizeof(error->device_info));
1733         error->driver_caps = i915->caps;
1734 }
1735
1736 static __always_inline void dup_param(const char *type, void *x)
1737 {
1738         if (!__builtin_strcmp(type, "char *"))
1739                 *(void **)x = kstrdup(*(void **)x, GFP_ATOMIC);
1740 }
1741
1742 static void capture_params(struct i915_gpu_state *error)
1743 {
1744         error->params = i915_modparams;
1745 #define DUP(T, x, ...) dup_param(#T, &error->params.x);
1746         I915_PARAMS_FOR_EACH(DUP);
1747 #undef DUP
1748 }
1749
1750 static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
1751 {
1752         unsigned long epoch = error->capture;
1753         int i;
1754
1755         for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1756                 const struct drm_i915_error_engine *ee = &error->engine[i];
1757
1758                 if (ee->hangcheck_stalled &&
1759                     time_before(ee->hangcheck_timestamp, epoch))
1760                         epoch = ee->hangcheck_timestamp;
1761         }
1762
1763         return epoch;
1764 }
1765
1766 static int capture(void *data)
1767 {
1768         struct i915_gpu_state *error = data;
1769
1770         error->time = ktime_get_real();
1771         error->boottime = ktime_get_boottime();
1772         error->uptime = ktime_sub(ktime_get(),
1773                                   error->i915->gt.last_init_time);
1774         error->capture = jiffies;
1775
1776         capture_params(error);
1777         capture_gen_state(error);
1778         capture_uc_state(error);
1779         capture_reg_state(error);
1780         gem_record_fences(error);
1781         gem_record_rings(error);
1782         capture_active_buffers(error);
1783         capture_pinned_buffers(error);
1784
1785         error->overlay = intel_overlay_capture_error_state(error->i915);
1786         error->display = intel_display_capture_error_state(error->i915);
1787
1788         error->epoch = capture_find_epoch(error);
1789
1790         return 0;
1791 }
1792
1793 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1794
1795 struct i915_gpu_state *
1796 i915_capture_gpu_state(struct drm_i915_private *i915)
1797 {
1798         struct i915_gpu_state *error;
1799
1800         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1801         if (!error)
1802                 return NULL;
1803
1804         kref_init(&error->ref);
1805         error->i915 = i915;
1806
1807         stop_machine(capture, error, NULL);
1808
1809         return error;
1810 }
1811
1812 /**
1813  * i915_capture_error_state - capture an error record for later analysis
1814  * @i915: i915 device
1815  * @engine_mask: the mask of engines triggering the hang
1816  * @error_msg: a message to insert into the error capture header
1817  *
1818  * Should be called when an error is detected (either a hang or an error
1819  * interrupt) to capture error state from the time of the error.  Fills
1820  * out a structure which becomes available in debugfs for user level tools
1821  * to pick up.
1822  */
1823 void i915_capture_error_state(struct drm_i915_private *i915,
1824                               u32 engine_mask,
1825                               const char *error_msg)
1826 {
1827         static bool warned;
1828         struct i915_gpu_state *error;
1829         unsigned long flags;
1830
1831         if (!i915_modparams.error_capture)
1832                 return;
1833
1834         if (READ_ONCE(i915->gpu_error.first_error))
1835                 return;
1836
1837         error = i915_capture_gpu_state(i915);
1838         if (!error) {
1839                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1840                 return;
1841         }
1842
1843         i915_error_capture_msg(i915, error, engine_mask, error_msg);
1844         DRM_INFO("%s\n", error->error_msg);
1845
1846         if (!error->simulated) {
1847                 spin_lock_irqsave(&i915->gpu_error.lock, flags);
1848                 if (!i915->gpu_error.first_error) {
1849                         i915->gpu_error.first_error = error;
1850                         error = NULL;
1851                 }
1852                 spin_unlock_irqrestore(&i915->gpu_error.lock, flags);
1853         }
1854
1855         if (error) {
1856                 __i915_gpu_state_free(&error->ref);
1857                 return;
1858         }
1859
1860         if (!warned &&
1861             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1862                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1863                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1864                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1865                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1866                 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1867                          i915->drm.primary->index);
1868                 warned = true;
1869         }
1870 }
1871
1872 struct i915_gpu_state *
1873 i915_first_error_state(struct drm_i915_private *i915)
1874 {
1875         struct i915_gpu_state *error;
1876
1877         spin_lock_irq(&i915->gpu_error.lock);
1878         error = i915->gpu_error.first_error;
1879         if (error)
1880                 i915_gpu_state_get(error);
1881         spin_unlock_irq(&i915->gpu_error.lock);
1882
1883         return error;
1884 }
1885
1886 void i915_reset_error_state(struct drm_i915_private *i915)
1887 {
1888         struct i915_gpu_state *error;
1889
1890         spin_lock_irq(&i915->gpu_error.lock);
1891         error = i915->gpu_error.first_error;
1892         i915->gpu_error.first_error = NULL;
1893         spin_unlock_irq(&i915->gpu_error.lock);
1894
1895         i915_gpu_state_put(error);
1896 }