drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "amdgpu_amdkfd.h"
  24 #include "amd_shared.h"
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include <linux/module.h>
  29
  30 const struct kgd2kfd_calls *kgd2kfd;
  31 bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
  32
  33 static const unsigned int compute_vmid_bitmap = 0xFF00;
  34
  35 int amdgpu_amdkfd_init(void)
  36 {
  37         int ret;
  38
  39 #if defined(CONFIG_HSA_AMD_MODULE)
  40         int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
  41
  42         kgd2kfd_init_p = symbol_request(kgd2kfd_init);
  43
  44         if (kgd2kfd_init_p == NULL)
  45                 return -ENOENT;
  46
  47         ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
  48         if (ret) {
  49                 symbol_put(kgd2kfd_init);
  50                 kgd2kfd = NULL;
  51         }
  52
  53 #elif defined(CONFIG_HSA_AMD)
  54         ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
  55         if (ret)
  56                 kgd2kfd = NULL;
  57
  58 #else
  59         ret = -ENOENT;
  60 #endif
  61         amdgpu_amdkfd_gpuvm_init_mem_limits();
  62
  63         return ret;
  64 }
  65
  66 void amdgpu_amdkfd_fini(void)
  67 {
  68         if (kgd2kfd) {
  69                 kgd2kfd->exit();
  70                 symbol_put(kgd2kfd_init);
  71         }
  72 }
  73
  74 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
  75 {
  76         const struct kfd2kgd_calls *kfd2kgd;
  77
  78         if (!kgd2kfd)
  79                 return;
  80
  81         switch (adev->asic_type) {
  82 #ifdef CONFIG_DRM_AMDGPU_CIK
  83         case CHIP_KAVERI:
  84         case CHIP_HAWAII:
  85                 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
  86                 break;
  87 #endif
  88         case CHIP_CARRIZO:
  89         case CHIP_TONGA:
  90         case CHIP_FIJI:
  91         case CHIP_POLARIS10:
  92         case CHIP_POLARIS11:
  93                 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
  94                 break;
  95         default:
  96                 dev_dbg(adev->dev, "kfd not supported on this ASIC\n");
  97                 return;
  98         }
  99
 100         adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
 101                                    adev->pdev, kfd2kgd);
 102 }
 103
 104 /**
 105  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 106  *                                setup amdkfd
 107  *
 108  * @adev: amdgpu_device pointer
 109  * @aperture_base: output returning doorbell aperture base physical address
 110  * @aperture_size: output returning doorbell aperture size in bytes
 111  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 112  *
 113  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 114  * takes doorbells required for its own rings and reports the setup to amdkfd.
 115  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 116  */
 117 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 118                                          phys_addr_t *aperture_base,
 119                                          size_t *aperture_size,
 120                                          size_t *start_offset)
 121 {
 122         /*
 123          * The first num_doorbells are used by amdgpu.
 124          * amdkfd takes whatever's left in the aperture.
 125          */
 126         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 127                 *aperture_base = adev->doorbell.base;
 128                 *aperture_size = adev->doorbell.size;
 129                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 130         } else {
 131                 *aperture_base = 0;
 132                 *aperture_size = 0;
 133                 *start_offset = 0;
 134         }
 135 }
 136
 137 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 138 {
 139         int i;
 140         int last_valid_bit;
 141         if (adev->kfd) {
 142                 struct kgd2kfd_shared_resources gpu_resources = {
 143                         .compute_vmid_bitmap = compute_vmid_bitmap,
 144                         .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
 145                         .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
 146                         .gpuvm_size = min(adev->vm_manager.max_pfn
 147                                           << AMDGPU_GPU_PAGE_SHIFT,
 148                                           AMDGPU_VA_HOLE_START),
 149                         .drm_render_minor = adev->ddev->render->index
 150                 };
 151
 152                 /* this is going to have a few of the MSBs set that we need to
 153                  * clear */
 154                 bitmap_complement(gpu_resources.queue_bitmap,
 155                                   adev->gfx.mec.queue_bitmap,
 156                                   KGD_MAX_QUEUES);
 157
 158                 /* remove the KIQ bit as well */
 159                 if (adev->gfx.kiq.ring.ready)
 160                         clear_bit(amdgpu_gfx_queue_to_bit(adev,
 161                                                           adev->gfx.kiq.ring.me - 1,
 162                                                           adev->gfx.kiq.ring.pipe,
 163                                                           adev->gfx.kiq.ring.queue),
 164                                   gpu_resources.queue_bitmap);
 165
 166                 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
 167                  * nbits is not compile time constant */
 168                 last_valid_bit = 1 /* only first MEC can have compute queues */
 169                                 * adev->gfx.mec.num_pipe_per_mec
 170                                 * adev->gfx.mec.num_queue_per_pipe;
 171                 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
 172                         clear_bit(i, gpu_resources.queue_bitmap);
 173
 174                 amdgpu_doorbell_get_kfd_info(adev,
 175                                 &gpu_resources.doorbell_physical_address,
 176                                 &gpu_resources.doorbell_aperture_size,
 177                                 &gpu_resources.doorbell_start_offset);
 178
 179                 kgd2kfd->device_init(adev->kfd, &gpu_resources);
 180         }
 181 }
 182
 183 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
 184 {
 185         if (adev->kfd) {
 186                 kgd2kfd->device_exit(adev->kfd);
 187                 adev->kfd = NULL;
 188         }
 189 }
 190
 191 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 192                 const void *ih_ring_entry)
 193 {
 194         if (adev->kfd)
 195                 kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
 196 }
 197
 198 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
 199 {
 200         if (adev->kfd)
 201                 kgd2kfd->suspend(adev->kfd);
 202 }
 203
 204 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
 205 {
 206         int r = 0;
 207
 208         if (adev->kfd)
 209                 r = kgd2kfd->resume(adev->kfd);
 210
 211         return r;
 212 }
 213
 214 int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
 215                         void **mem_obj, uint64_t *gpu_addr,
 216                         void **cpu_ptr)
 217 {
 218         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 219         struct amdgpu_bo *bo = NULL;
 220         int r;
 221         uint64_t gpu_addr_tmp = 0;
 222         void *cpu_ptr_tmp = NULL;
 223
 224         r = amdgpu_bo_create(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 225                              AMDGPU_GEM_CREATE_CPU_GTT_USWC, ttm_bo_type_kernel,
 226                              NULL, &bo);
 227         if (r) {
 228                 dev_err(adev->dev,
 229                         "failed to allocate BO for amdkfd (%d)\n", r);
 230                 return r;
 231         }
 232
 233         /* map the buffer */
 234         r = amdgpu_bo_reserve(bo, true);
 235         if (r) {
 236                 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
 237                 goto allocate_mem_reserve_bo_failed;
 238         }
 239
 240         r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT,
 241                                 &gpu_addr_tmp);
 242         if (r) {
 243                 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
 244                 goto allocate_mem_pin_bo_failed;
 245         }
 246
 247         r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
 248         if (r) {
 249                 dev_err(adev->dev,
 250                         "(%d) failed to map bo to kernel for amdkfd\n", r);
 251                 goto allocate_mem_kmap_bo_failed;
 252         }
 253
 254         *mem_obj = bo;
 255         *gpu_addr = gpu_addr_tmp;
 256         *cpu_ptr = cpu_ptr_tmp;
 257
 258         amdgpu_bo_unreserve(bo);
 259
 260         return 0;
 261
 262 allocate_mem_kmap_bo_failed:
 263         amdgpu_bo_unpin(bo);
 264 allocate_mem_pin_bo_failed:
 265         amdgpu_bo_unreserve(bo);
 266 allocate_mem_reserve_bo_failed:
 267         amdgpu_bo_unref(&bo);
 268
 269         return r;
 270 }
 271
 272 void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
 273 {
 274         struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
 275
 276         amdgpu_bo_reserve(bo, true);
 277         amdgpu_bo_kunmap(bo);
 278         amdgpu_bo_unpin(bo);
 279         amdgpu_bo_unreserve(bo);
 280         amdgpu_bo_unref(&(bo));
 281 }
 282
 283 void get_local_mem_info(struct kgd_dev *kgd,
 284                         struct kfd_local_mem_info *mem_info)
 285 {
 286         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 287         uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
 288                                              ~((1ULL << 32) - 1);
 289         resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
 290
 291         memset(mem_info, 0, sizeof(*mem_info));
 292         if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
 293                 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
 294                 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
 295                                 adev->gmc.visible_vram_size;
 296         } else {
 297                 mem_info->local_mem_size_public = 0;
 298                 mem_info->local_mem_size_private = adev->gmc.real_vram_size;
 299         }
 300         mem_info->vram_width = adev->gmc.vram_width;
 301
 302         pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
 303                         &adev->gmc.aper_base, &aper_limit,
 304                         mem_info->local_mem_size_public,
 305                         mem_info->local_mem_size_private);
 306
 307         if (amdgpu_emu_mode == 1) {
 308                 mem_info->mem_clk_max = 100;
 309                 return;
 310         }
 311
 312         if (amdgpu_sriov_vf(adev))
 313                 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
 314         else
 315                 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
 316 }
 317
 318 uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
 319 {
 320         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 321
 322         if (adev->gfx.funcs->get_gpu_clock_counter)
 323                 return adev->gfx.funcs->get_gpu_clock_counter(adev);
 324         return 0;
 325 }
 326
 327 uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 328 {
 329         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 330
 331         /* the sclk is in quantas of 10kHz */
 332         if (amdgpu_emu_mode == 1)
 333                 return 100;
 334
 335         if (amdgpu_sriov_vf(adev))
 336                 return adev->clock.default_sclk / 100;
 337
 338         return amdgpu_dpm_get_sclk(adev, false) / 100;
 339 }
 340
 341 void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
 342 {
 343         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 344         struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
 345
 346         memset(cu_info, 0, sizeof(*cu_info));
 347         if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
 348                 return;
 349
 350         cu_info->cu_active_number = acu_info.number;
 351         cu_info->cu_ao_mask = acu_info.ao_cu_mask;
 352         memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
 353                sizeof(acu_info.bitmap));
 354         cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 355         cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 356         cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 357         cu_info->simd_per_cu = acu_info.simd_per_cu;
 358         cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
 359         cu_info->wave_front_size = acu_info.wave_front_size;
 360         cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
 361         cu_info->lds_size = acu_info.lds_size;
 362 }
 363
 364 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
 365 {
 366         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 367
 368         return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 369 }
 370
 371 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 372                                 uint32_t vmid, uint64_t gpu_addr,
 373                                 uint32_t *ib_cmd, uint32_t ib_len)
 374 {
 375         struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
 376         struct amdgpu_job *job;
 377         struct amdgpu_ib *ib;
 378         struct amdgpu_ring *ring;
 379         struct dma_fence *f = NULL;
 380         int ret;
 381
 382         switch (engine) {
 383         case KGD_ENGINE_MEC1:
 384                 ring = &adev->gfx.compute_ring[0];
 385                 break;
 386         case KGD_ENGINE_SDMA1:
 387                 ring = &adev->sdma.instance[0].ring;
 388                 break;
 389         case KGD_ENGINE_SDMA2:
 390                 ring = &adev->sdma.instance[1].ring;
 391                 break;
 392         default:
 393                 pr_err("Invalid engine in IB submission: %d\n", engine);
 394                 ret = -EINVAL;
 395                 goto err;
 396         }
 397
 398         ret = amdgpu_job_alloc(adev, 1, &job, NULL);
 399         if (ret)
 400                 goto err;
 401
 402         ib = &job->ibs[0];
 403         memset(ib, 0, sizeof(struct amdgpu_ib));
 404
 405         ib->gpu_addr = gpu_addr;
 406         ib->ptr = ib_cmd;
 407         ib->length_dw = ib_len;
 408         /* This works for NO_HWS. TODO: need to handle without knowing VMID */
 409         job->vmid = vmid;
 410
 411         ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
 412         if (ret) {
 413                 DRM_ERROR("amdgpu: failed to schedule IB.\n");
 414                 goto err_ib_sched;
 415         }
 416
 417         ret = dma_fence_wait(f, false);
 418
 419 err_ib_sched:
 420         dma_fence_put(f);
 421         amdgpu_job_free(job);
 422 err:
 423         return ret;
 424 }
 425
 426 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
 427 {
 428         if (adev->kfd) {
 429                 if ((1 << vmid) & compute_vmid_bitmap)
 430                         return true;
 431         }
 432
 433         return false;
 434 }