drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.dpm.ac_power = true;
  72                 else
  73                         adev->pm.dpm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 /**
  81  * DOC: power_dpm_state
  82  *
  83  * This is a legacy interface and is only provided for backwards compatibility.
  84  * The amdgpu driver provides a sysfs API for adjusting certain power
  85  * related parameters.  The file power_dpm_state is used for this.
  86  * It accepts the following arguments:
  87  * - battery
  88  * - balanced
  89  * - performance
  90  *
  91  * battery
  92  *
  93  * On older GPUs, the vbios provided a special power state for battery
  94  * operation.  Selecting battery switched to this state.  This is no
  95  * longer provided on newer GPUs so the option does nothing in that case.
  96  *
  97  * balanced
  98  *
  99  * On older GPUs, the vbios provided a special power state for balanced
 100  * operation.  Selecting balanced switched to this state.  This is no
 101  * longer provided on newer GPUs so the option does nothing in that case.
 102  *
 103  * performance
 104  *
 105  * On older GPUs, the vbios provided a special power state for performance
 106  * operation.  Selecting performance switched to this state.  This is no
 107  * longer provided on newer GPUs so the option does nothing in that case.
 108  *
 109  */
 110
 111 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 112                                     struct device_attribute *attr,
 113                                     char *buf)
 114 {
 115         struct drm_device *ddev = dev_get_drvdata(dev);
 116         struct amdgpu_device *adev = ddev->dev_private;
 117         enum amd_pm_state_type pm;
 118
 119         if (adev->powerplay.pp_funcs->get_current_power_state)
 120                 pm = amdgpu_dpm_get_current_power_state(adev);
 121         else
 122                 pm = adev->pm.dpm.user_state;
 123
 124         return snprintf(buf, PAGE_SIZE, "%s\n",
 125                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 126                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 127 }
 128
 129 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 130                                     struct device_attribute *attr,
 131                                     const char *buf,
 132                                     size_t count)
 133 {
 134         struct drm_device *ddev = dev_get_drvdata(dev);
 135         struct amdgpu_device *adev = ddev->dev_private;
 136         enum amd_pm_state_type  state;
 137
 138         if (strncmp("battery", buf, strlen("battery")) == 0)
 139                 state = POWER_STATE_TYPE_BATTERY;
 140         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 141                 state = POWER_STATE_TYPE_BALANCED;
 142         else if (strncmp("performance", buf, strlen("performance")) == 0)
 143                 state = POWER_STATE_TYPE_PERFORMANCE;
 144         else {
 145                 count = -EINVAL;
 146                 goto fail;
 147         }
 148
 149         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 150                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 151         } else {
 152                 mutex_lock(&adev->pm.mutex);
 153                 adev->pm.dpm.user_state = state;
 154                 mutex_unlock(&adev->pm.mutex);
 155
 156                 /* Can't set dpm state when the card is off */
 157                 if (!(adev->flags & AMD_IS_PX) ||
 158                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 159                         amdgpu_pm_compute_clocks(adev);
 160         }
 161 fail:
 162         return count;
 163 }
 164
 165
 166 /**
 167  * DOC: power_dpm_force_performance_level
 168  *
 169  * The amdgpu driver provides a sysfs API for adjusting certain power
 170  * related parameters.  The file power_dpm_force_performance_level is
 171  * used for this.  It accepts the following arguments:
 172  * - auto
 173  * - low
 174  * - high
 175  * - manual
 176  * - GPU fan
 177  * - profile_standard
 178  * - profile_min_sclk
 179  * - profile_min_mclk
 180  * - profile_peak
 181  *
 182  * auto
 183  *
 184  * When auto is selected, the driver will attempt to dynamically select
 185  * the optimal power profile for current conditions in the driver.
 186  *
 187  * low
 188  *
 189  * When low is selected, the clocks are forced to the lowest power state.
 190  *
 191  * high
 192  *
 193  * When high is selected, the clocks are forced to the highest power state.
 194  *
 195  * manual
 196  *
 197  * When manual is selected, the user can manually adjust which power states
 198  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 199  * and pp_dpm_pcie files and adjust the power state transition heuristics
 200  * via the pp_power_profile_mode sysfs file.
 201  *
 202  * profile_standard
 203  * profile_min_sclk
 204  * profile_min_mclk
 205  * profile_peak
 206  *
 207  * When the profiling modes are selected, clock and power gating are
 208  * disabled and the clocks are set for different profiling cases. This
 209  * mode is recommended for profiling specific work loads where you do
 210  * not want clock or power gating for clock fluctuation to interfere
 211  * with your results. profile_standard sets the clocks to a fixed clock
 212  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 213  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 214  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 215  *
 216  */
 217
 218 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 219                                                 struct device_attribute *attr,
 220                                                                 char *buf)
 221 {
 222         struct drm_device *ddev = dev_get_drvdata(dev);
 223         struct amdgpu_device *adev = ddev->dev_private;
 224         enum amd_dpm_forced_level level = 0xff;
 225
 226         if  ((adev->flags & AMD_IS_PX) &&
 227              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 228                 return snprintf(buf, PAGE_SIZE, "off\n");
 229
 230         if (adev->powerplay.pp_funcs->get_performance_level)
 231                 level = amdgpu_dpm_get_performance_level(adev);
 232         else
 233                 level = adev->pm.dpm.forced_level;
 234
 235         return snprintf(buf, PAGE_SIZE, "%s\n",
 236                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 237                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 238                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 239                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 240                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 241                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 242                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 243                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 244                         "unknown");
 245 }
 246
 247 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 248                                                        struct device_attribute *attr,
 249                                                        const char *buf,
 250                                                        size_t count)
 251 {
 252         struct drm_device *ddev = dev_get_drvdata(dev);
 253         struct amdgpu_device *adev = ddev->dev_private;
 254         enum amd_dpm_forced_level level;
 255         enum amd_dpm_forced_level current_level = 0xff;
 256         int ret = 0;
 257
 258         /* Can't force performance level when the card is off */
 259         if  ((adev->flags & AMD_IS_PX) &&
 260              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 261                 return -EINVAL;
 262
 263         if (adev->powerplay.pp_funcs->get_performance_level)
 264                 current_level = amdgpu_dpm_get_performance_level(adev);
 265
 266         if (strncmp("low", buf, strlen("low")) == 0) {
 267                 level = AMD_DPM_FORCED_LEVEL_LOW;
 268         } else if (strncmp("high", buf, strlen("high")) == 0) {
 269                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 270         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 271                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 272         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 273                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 274         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 275                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 276         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 277                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 278         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 279                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 280         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 281                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 282         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 283                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 284         }  else {
 285                 count = -EINVAL;
 286                 goto fail;
 287         }
 288
 289         if (current_level == level)
 290                 return count;
 291
 292         if (adev->powerplay.pp_funcs->force_performance_level) {
 293                 mutex_lock(&adev->pm.mutex);
 294                 if (adev->pm.dpm.thermal_active) {
 295                         count = -EINVAL;
 296                         mutex_unlock(&adev->pm.mutex);
 297                         goto fail;
 298                 }
 299                 ret = amdgpu_dpm_force_performance_level(adev, level);
 300                 if (ret)
 301                         count = -EINVAL;
 302                 else
 303                         adev->pm.dpm.forced_level = level;
 304                 mutex_unlock(&adev->pm.mutex);
 305         }
 306
 307 fail:
 308         return count;
 309 }
 310
 311 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 312                 struct device_attribute *attr,
 313                 char *buf)
 314 {
 315         struct drm_device *ddev = dev_get_drvdata(dev);
 316         struct amdgpu_device *adev = ddev->dev_private;
 317         struct pp_states_info data;
 318         int i, buf_len;
 319
 320         if (adev->powerplay.pp_funcs->get_pp_num_states)
 321                 amdgpu_dpm_get_pp_num_states(adev, &data);
 322
 323         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 324         for (i = 0; i < data.nums; i++)
 325                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 326                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 327                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 328                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 329                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 330
 331         return buf_len;
 332 }
 333
 334 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 335                 struct device_attribute *attr,
 336                 char *buf)
 337 {
 338         struct drm_device *ddev = dev_get_drvdata(dev);
 339         struct amdgpu_device *adev = ddev->dev_private;
 340         struct pp_states_info data;
 341         enum amd_pm_state_type pm = 0;
 342         int i = 0;
 343
 344         if (adev->powerplay.pp_funcs->get_current_power_state
 345                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 346                 pm = amdgpu_dpm_get_current_power_state(adev);
 347                 amdgpu_dpm_get_pp_num_states(adev, &data);
 348
 349                 for (i = 0; i < data.nums; i++) {
 350                         if (pm == data.states[i])
 351                                 break;
 352                 }
 353
 354                 if (i == data.nums)
 355                         i = -EINVAL;
 356         }
 357
 358         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 359 }
 360
 361 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 362                 struct device_attribute *attr,
 363                 char *buf)
 364 {
 365         struct drm_device *ddev = dev_get_drvdata(dev);
 366         struct amdgpu_device *adev = ddev->dev_private;
 367
 368         if (adev->pp_force_state_enabled)
 369                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 370         else
 371                 return snprintf(buf, PAGE_SIZE, "\n");
 372 }
 373
 374 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 375                 struct device_attribute *attr,
 376                 const char *buf,
 377                 size_t count)
 378 {
 379         struct drm_device *ddev = dev_get_drvdata(dev);
 380         struct amdgpu_device *adev = ddev->dev_private;
 381         enum amd_pm_state_type state = 0;
 382         unsigned long idx;
 383         int ret;
 384
 385         if (strlen(buf) == 1)
 386                 adev->pp_force_state_enabled = false;
 387         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 388                         adev->powerplay.pp_funcs->get_pp_num_states) {
 389                 struct pp_states_info data;
 390
 391                 ret = kstrtoul(buf, 0, &idx);
 392                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 393                         count = -EINVAL;
 394                         goto fail;
 395                 }
 396
 397                 amdgpu_dpm_get_pp_num_states(adev, &data);
 398                 state = data.states[idx];
 399                 /* only set user selected power states */
 400                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 401                     state != POWER_STATE_TYPE_DEFAULT) {
 402                         amdgpu_dpm_dispatch_task(adev,
 403                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 404                         adev->pp_force_state_enabled = true;
 405                 }
 406         }
 407 fail:
 408         return count;
 409 }
 410
 411 /**
 412  * DOC: pp_table
 413  *
 414  * The amdgpu driver provides a sysfs API for uploading new powerplay
 415  * tables.  The file pp_table is used for this.  Reading the file
 416  * will dump the current power play table.  Writing to the file
 417  * will attempt to upload a new powerplay table and re-initialize
 418  * powerplay using that new table.
 419  *
 420  */
 421
 422 static ssize_t amdgpu_get_pp_table(struct device *dev,
 423                 struct device_attribute *attr,
 424                 char *buf)
 425 {
 426         struct drm_device *ddev = dev_get_drvdata(dev);
 427         struct amdgpu_device *adev = ddev->dev_private;
 428         char *table = NULL;
 429         int size;
 430
 431         if (adev->powerplay.pp_funcs->get_pp_table)
 432                 size = amdgpu_dpm_get_pp_table(adev, &table);
 433         else
 434                 return 0;
 435
 436         if (size >= PAGE_SIZE)
 437                 size = PAGE_SIZE - 1;
 438
 439         memcpy(buf, table, size);
 440
 441         return size;
 442 }
 443
 444 static ssize_t amdgpu_set_pp_table(struct device *dev,
 445                 struct device_attribute *attr,
 446                 const char *buf,
 447                 size_t count)
 448 {
 449         struct drm_device *ddev = dev_get_drvdata(dev);
 450         struct amdgpu_device *adev = ddev->dev_private;
 451
 452         if (adev->powerplay.pp_funcs->set_pp_table)
 453                 amdgpu_dpm_set_pp_table(adev, buf, count);
 454
 455         return count;
 456 }
 457
 458 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 459                 struct device_attribute *attr,
 460                 const char *buf,
 461                 size_t count)
 462 {
 463         struct drm_device *ddev = dev_get_drvdata(dev);
 464         struct amdgpu_device *adev = ddev->dev_private;
 465         int ret;
 466         uint32_t parameter_size = 0;
 467         long parameter[64];
 468         char buf_cpy[128];
 469         char *tmp_str;
 470         char *sub_str;
 471         const char delimiter[3] = {' ', '\n', '\0'};
 472         uint32_t type;
 473
 474         if (count > 127)
 475                 return -EINVAL;
 476
 477         if (*buf == 's')
 478                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 479         else if (*buf == 'm')
 480                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 481         else if(*buf == 'r')
 482                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 483         else if (*buf == 'c')
 484                 type = PP_OD_COMMIT_DPM_TABLE;
 485         else
 486                 return -EINVAL;
 487
 488         memcpy(buf_cpy, buf, count+1);
 489
 490         tmp_str = buf_cpy;
 491
 492         while (isspace(*++tmp_str));
 493
 494         while (tmp_str[0]) {
 495                 sub_str = strsep(&tmp_str, delimiter);
 496                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 497                 if (ret)
 498                         return -EINVAL;
 499                 parameter_size++;
 500
 501                 while (isspace(*tmp_str))
 502                         tmp_str++;
 503         }
 504
 505         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 506                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 507                                                 parameter, parameter_size);
 508
 509         if (ret)
 510                 return -EINVAL;
 511
 512         if (type == PP_OD_COMMIT_DPM_TABLE) {
 513                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 514                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 515                         return count;
 516                 } else {
 517                         return -EINVAL;
 518                 }
 519         }
 520
 521         return count;
 522 }
 523
 524 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 525                 struct device_attribute *attr,
 526                 char *buf)
 527 {
 528         struct drm_device *ddev = dev_get_drvdata(dev);
 529         struct amdgpu_device *adev = ddev->dev_private;
 530         uint32_t size = 0;
 531
 532         if (adev->powerplay.pp_funcs->print_clock_levels) {
 533                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 534                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 535                 return size;
 536         } else {
 537                 return snprintf(buf, PAGE_SIZE, "\n");
 538         }
 539
 540 }
 541
 542 /**
 543  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
 544  *
 545  * The amdgpu driver provides a sysfs API for adjusting what power levels
 546  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 547  * and pp_dpm_pcie are used for this.
 548  *
 549  * Reading back the files will show you the available power levels within
 550  * the power state and the clock information for those levels.
 551  *
 552  * To manually adjust these states, first select manual using
 553  * power_dpm_force_performance_level.  Writing a string of the level
 554  * numbers to the file will select which levels you want to enable.
 555  * E.g., writing 456 to the file will enable levels 4, 5, and 6.
 556  *
 557  */
 558
 559 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 560                 struct device_attribute *attr,
 561                 char *buf)
 562 {
 563         struct drm_device *ddev = dev_get_drvdata(dev);
 564         struct amdgpu_device *adev = ddev->dev_private;
 565
 566         if (adev->powerplay.pp_funcs->print_clock_levels)
 567                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 568         else
 569                 return snprintf(buf, PAGE_SIZE, "\n");
 570 }
 571
 572 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 573                 struct device_attribute *attr,
 574                 const char *buf,
 575                 size_t count)
 576 {
 577         struct drm_device *ddev = dev_get_drvdata(dev);
 578         struct amdgpu_device *adev = ddev->dev_private;
 579         int ret;
 580         long level;
 581         uint32_t i, mask = 0;
 582         char sub_str[2];
 583
 584         for (i = 0; i < strlen(buf); i++) {
 585                 if (*(buf + i) == '\n')
 586                         continue;
 587                 sub_str[0] = *(buf + i);
 588                 sub_str[1] = '\0';
 589                 ret = kstrtol(sub_str, 0, &level);
 590
 591                 if (ret) {
 592                         count = -EINVAL;
 593                         goto fail;
 594                 }
 595                 mask |= 1 << level;
 596         }
 597
 598         if (adev->powerplay.pp_funcs->force_clock_level)
 599                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 600
 601 fail:
 602         return count;
 603 }
 604
 605 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 606                 struct device_attribute *attr,
 607                 char *buf)
 608 {
 609         struct drm_device *ddev = dev_get_drvdata(dev);
 610         struct amdgpu_device *adev = ddev->dev_private;
 611
 612         if (adev->powerplay.pp_funcs->print_clock_levels)
 613                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 614         else
 615                 return snprintf(buf, PAGE_SIZE, "\n");
 616 }
 617
 618 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 619                 struct device_attribute *attr,
 620                 const char *buf,
 621                 size_t count)
 622 {
 623         struct drm_device *ddev = dev_get_drvdata(dev);
 624         struct amdgpu_device *adev = ddev->dev_private;
 625         int ret;
 626         long level;
 627         uint32_t i, mask = 0;
 628         char sub_str[2];
 629
 630         for (i = 0; i < strlen(buf); i++) {
 631                 if (*(buf + i) == '\n')
 632                         continue;
 633                 sub_str[0] = *(buf + i);
 634                 sub_str[1] = '\0';
 635                 ret = kstrtol(sub_str, 0, &level);
 636
 637                 if (ret) {
 638                         count = -EINVAL;
 639                         goto fail;
 640                 }
 641                 mask |= 1 << level;
 642         }
 643         if (adev->powerplay.pp_funcs->force_clock_level)
 644                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 645
 646 fail:
 647         return count;
 648 }
 649
 650 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 651                 struct device_attribute *attr,
 652                 char *buf)
 653 {
 654         struct drm_device *ddev = dev_get_drvdata(dev);
 655         struct amdgpu_device *adev = ddev->dev_private;
 656
 657         if (adev->powerplay.pp_funcs->print_clock_levels)
 658                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 659         else
 660                 return snprintf(buf, PAGE_SIZE, "\n");
 661 }
 662
 663 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 664                 struct device_attribute *attr,
 665                 const char *buf,
 666                 size_t count)
 667 {
 668         struct drm_device *ddev = dev_get_drvdata(dev);
 669         struct amdgpu_device *adev = ddev->dev_private;
 670         int ret;
 671         long level;
 672         uint32_t i, mask = 0;
 673         char sub_str[2];
 674
 675         for (i = 0; i < strlen(buf); i++) {
 676                 if (*(buf + i) == '\n')
 677                         continue;
 678                 sub_str[0] = *(buf + i);
 679                 sub_str[1] = '\0';
 680                 ret = kstrtol(sub_str, 0, &level);
 681
 682                 if (ret) {
 683                         count = -EINVAL;
 684                         goto fail;
 685                 }
 686                 mask |= 1 << level;
 687         }
 688         if (adev->powerplay.pp_funcs->force_clock_level)
 689                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 690
 691 fail:
 692         return count;
 693 }
 694
 695 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 696                 struct device_attribute *attr,
 697                 char *buf)
 698 {
 699         struct drm_device *ddev = dev_get_drvdata(dev);
 700         struct amdgpu_device *adev = ddev->dev_private;
 701         uint32_t value = 0;
 702
 703         if (adev->powerplay.pp_funcs->get_sclk_od)
 704                 value = amdgpu_dpm_get_sclk_od(adev);
 705
 706         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 707 }
 708
 709 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 710                 struct device_attribute *attr,
 711                 const char *buf,
 712                 size_t count)
 713 {
 714         struct drm_device *ddev = dev_get_drvdata(dev);
 715         struct amdgpu_device *adev = ddev->dev_private;
 716         int ret;
 717         long int value;
 718
 719         ret = kstrtol(buf, 0, &value);
 720
 721         if (ret) {
 722                 count = -EINVAL;
 723                 goto fail;
 724         }
 725         if (adev->powerplay.pp_funcs->set_sclk_od)
 726                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 727
 728         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 729                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 730         } else {
 731                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 732                 amdgpu_pm_compute_clocks(adev);
 733         }
 734
 735 fail:
 736         return count;
 737 }
 738
 739 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 740                 struct device_attribute *attr,
 741                 char *buf)
 742 {
 743         struct drm_device *ddev = dev_get_drvdata(dev);
 744         struct amdgpu_device *adev = ddev->dev_private;
 745         uint32_t value = 0;
 746
 747         if (adev->powerplay.pp_funcs->get_mclk_od)
 748                 value = amdgpu_dpm_get_mclk_od(adev);
 749
 750         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 751 }
 752
 753 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 754                 struct device_attribute *attr,
 755                 const char *buf,
 756                 size_t count)
 757 {
 758         struct drm_device *ddev = dev_get_drvdata(dev);
 759         struct amdgpu_device *adev = ddev->dev_private;
 760         int ret;
 761         long int value;
 762
 763         ret = kstrtol(buf, 0, &value);
 764
 765         if (ret) {
 766                 count = -EINVAL;
 767                 goto fail;
 768         }
 769         if (adev->powerplay.pp_funcs->set_mclk_od)
 770                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 771
 772         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 773                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 774         } else {
 775                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 776                 amdgpu_pm_compute_clocks(adev);
 777         }
 778
 779 fail:
 780         return count;
 781 }
 782
 783 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 784                 struct device_attribute *attr,
 785                 char *buf)
 786 {
 787         struct drm_device *ddev = dev_get_drvdata(dev);
 788         struct amdgpu_device *adev = ddev->dev_private;
 789
 790         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 791                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 792
 793         return snprintf(buf, PAGE_SIZE, "\n");
 794 }
 795
 796
 797 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 798                 struct device_attribute *attr,
 799                 const char *buf,
 800                 size_t count)
 801 {
 802         int ret = 0xff;
 803         struct drm_device *ddev = dev_get_drvdata(dev);
 804         struct amdgpu_device *adev = ddev->dev_private;
 805         uint32_t parameter_size = 0;
 806         long parameter[64];
 807         char *sub_str, buf_cpy[128];
 808         char *tmp_str;
 809         uint32_t i = 0;
 810         char tmp[2];
 811         long int profile_mode = 0;
 812         const char delimiter[3] = {' ', '\n', '\0'};
 813
 814         tmp[0] = *(buf);
 815         tmp[1] = '\0';
 816         ret = kstrtol(tmp, 0, &profile_mode);
 817         if (ret)
 818                 goto fail;
 819
 820         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 821                 if (count < 2 || count > 127)
 822                         return -EINVAL;
 823                 while (isspace(*++buf))
 824                         i++;
 825                 memcpy(buf_cpy, buf, count-i);
 826                 tmp_str = buf_cpy;
 827                 while (tmp_str[0]) {
 828                         sub_str = strsep(&tmp_str, delimiter);
 829                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 830                         if (ret) {
 831                                 count = -EINVAL;
 832                                 goto fail;
 833                         }
 834                         parameter_size++;
 835                         while (isspace(*tmp_str))
 836                                 tmp_str++;
 837                 }
 838         }
 839         parameter[parameter_size] = profile_mode;
 840         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 841                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 842
 843         if (!ret)
 844                 return count;
 845 fail:
 846         return -EINVAL;
 847 }
 848
 849 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 850 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 851                    amdgpu_get_dpm_forced_performance_level,
 852                    amdgpu_set_dpm_forced_performance_level);
 853 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 854 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 855 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 856                 amdgpu_get_pp_force_state,
 857                 amdgpu_set_pp_force_state);
 858 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 859                 amdgpu_get_pp_table,
 860                 amdgpu_set_pp_table);
 861 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 862                 amdgpu_get_pp_dpm_sclk,
 863                 amdgpu_set_pp_dpm_sclk);
 864 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 865                 amdgpu_get_pp_dpm_mclk,
 866                 amdgpu_set_pp_dpm_mclk);
 867 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 868                 amdgpu_get_pp_dpm_pcie,
 869                 amdgpu_set_pp_dpm_pcie);
 870 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 871                 amdgpu_get_pp_sclk_od,
 872                 amdgpu_set_pp_sclk_od);
 873 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 874                 amdgpu_get_pp_mclk_od,
 875                 amdgpu_set_pp_mclk_od);
 876 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 877                 amdgpu_get_pp_power_profile_mode,
 878                 amdgpu_set_pp_power_profile_mode);
 879 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 880                 amdgpu_get_pp_od_clk_voltage,
 881                 amdgpu_set_pp_od_clk_voltage);
 882
 883 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 884                                       struct device_attribute *attr,
 885                                       char *buf)
 886 {
 887         struct amdgpu_device *adev = dev_get_drvdata(dev);
 888         struct drm_device *ddev = adev->ddev;
 889         int r, temp, size = sizeof(temp);
 890
 891         /* Can't get temperature when the card is off */
 892         if  ((adev->flags & AMD_IS_PX) &&
 893              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 894                 return -EINVAL;
 895
 896         /* sanity check PP is enabled */
 897         if (!(adev->powerplay.pp_funcs &&
 898               adev->powerplay.pp_funcs->read_sensor))
 899                 return -EINVAL;
 900
 901         /* get the temperature */
 902         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 903                                    (void *)&temp, &size);
 904         if (r)
 905                 return r;
 906
 907         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 908 }
 909
 910 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 911                                              struct device_attribute *attr,
 912                                              char *buf)
 913 {
 914         struct amdgpu_device *adev = dev_get_drvdata(dev);
 915         int hyst = to_sensor_dev_attr(attr)->index;
 916         int temp;
 917
 918         if (hyst)
 919                 temp = adev->pm.dpm.thermal.min_temp;
 920         else
 921                 temp = adev->pm.dpm.thermal.max_temp;
 922
 923         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 924 }
 925
 926 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 927                                             struct device_attribute *attr,
 928                                             char *buf)
 929 {
 930         struct amdgpu_device *adev = dev_get_drvdata(dev);
 931         u32 pwm_mode = 0;
 932
 933         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 934                 return -EINVAL;
 935
 936         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 937
 938         return sprintf(buf, "%i\n", pwm_mode);
 939 }
 940
 941 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 942                                             struct device_attribute *attr,
 943                                             const char *buf,
 944                                             size_t count)
 945 {
 946         struct amdgpu_device *adev = dev_get_drvdata(dev);
 947         int err;
 948         int value;
 949
 950         /* Can't adjust fan when the card is off */
 951         if  ((adev->flags & AMD_IS_PX) &&
 952              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 953                 return -EINVAL;
 954
 955         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
 956                 return -EINVAL;
 957
 958         err = kstrtoint(buf, 10, &value);
 959         if (err)
 960                 return err;
 961
 962         amdgpu_dpm_set_fan_control_mode(adev, value);
 963
 964         return count;
 965 }
 966
 967 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 968                                          struct device_attribute *attr,
 969                                          char *buf)
 970 {
 971         return sprintf(buf, "%i\n", 0);
 972 }
 973
 974 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 975                                          struct device_attribute *attr,
 976                                          char *buf)
 977 {
 978         return sprintf(buf, "%i\n", 255);
 979 }
 980
 981 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 982                                      struct device_attribute *attr,
 983                                      const char *buf, size_t count)
 984 {
 985         struct amdgpu_device *adev = dev_get_drvdata(dev);
 986         int err;
 987         u32 value;
 988
 989         /* Can't adjust fan when the card is off */
 990         if  ((adev->flags & AMD_IS_PX) &&
 991              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 992                 return -EINVAL;
 993
 994         err = kstrtou32(buf, 10, &value);
 995         if (err)
 996                 return err;
 997
 998         value = (value * 100) / 255;
 999
1000         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1001                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1002                 if (err)
1003                         return err;
1004         }
1005
1006         return count;
1007 }
1008
1009 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1010                                      struct device_attribute *attr,
1011                                      char *buf)
1012 {
1013         struct amdgpu_device *adev = dev_get_drvdata(dev);
1014         int err;
1015         u32 speed = 0;
1016
1017         /* Can't adjust fan when the card is off */
1018         if  ((adev->flags & AMD_IS_PX) &&
1019              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1020                 return -EINVAL;
1021
1022         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1023                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1024                 if (err)
1025                         return err;
1026         }
1027
1028         speed = (speed * 255) / 100;
1029
1030         return sprintf(buf, "%i\n", speed);
1031 }
1032
1033 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1034                                            struct device_attribute *attr,
1035                                            char *buf)
1036 {
1037         struct amdgpu_device *adev = dev_get_drvdata(dev);
1038         int err;
1039         u32 speed = 0;
1040
1041         /* Can't adjust fan when the card is off */
1042         if  ((adev->flags & AMD_IS_PX) &&
1043              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1044                 return -EINVAL;
1045
1046         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1047                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1048                 if (err)
1049                         return err;
1050         }
1051
1052         return sprintf(buf, "%i\n", speed);
1053 }
1054
1055 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1056                                         struct device_attribute *attr,
1057                                         char *buf)
1058 {
1059         struct amdgpu_device *adev = dev_get_drvdata(dev);
1060         struct drm_device *ddev = adev->ddev;
1061         u32 vddgfx;
1062         int r, size = sizeof(vddgfx);
1063
1064         /* Can't get voltage when the card is off */
1065         if  ((adev->flags & AMD_IS_PX) &&
1066              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1067                 return -EINVAL;
1068
1069         /* sanity check PP is enabled */
1070         if (!(adev->powerplay.pp_funcs &&
1071               adev->powerplay.pp_funcs->read_sensor))
1072               return -EINVAL;
1073
1074         /* get the voltage */
1075         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1076                                    (void *)&vddgfx, &size);
1077         if (r)
1078                 return r;
1079
1080         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1081 }
1082
1083 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1084                                               struct device_attribute *attr,
1085                                               char *buf)
1086 {
1087         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1088 }
1089
1090 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1091                                        struct device_attribute *attr,
1092                                        char *buf)
1093 {
1094         struct amdgpu_device *adev = dev_get_drvdata(dev);
1095         struct drm_device *ddev = adev->ddev;
1096         u32 vddnb;
1097         int r, size = sizeof(vddnb);
1098
1099         /* only APUs have vddnb */
1100         if  (adev->flags & AMD_IS_APU)
1101                 return -EINVAL;
1102
1103         /* Can't get voltage when the card is off */
1104         if  ((adev->flags & AMD_IS_PX) &&
1105              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1106                 return -EINVAL;
1107
1108         /* sanity check PP is enabled */
1109         if (!(adev->powerplay.pp_funcs &&
1110               adev->powerplay.pp_funcs->read_sensor))
1111               return -EINVAL;
1112
1113         /* get the voltage */
1114         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1115                                    (void *)&vddnb, &size);
1116         if (r)
1117                 return r;
1118
1119         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1120 }
1121
1122 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1123                                               struct device_attribute *attr,
1124                                               char *buf)
1125 {
1126         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1127 }
1128
1129 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1130                                            struct device_attribute *attr,
1131                                            char *buf)
1132 {
1133         struct amdgpu_device *adev = dev_get_drvdata(dev);
1134         struct drm_device *ddev = adev->ddev;
1135         u32 query = 0;
1136         int r, size = sizeof(u32);
1137         unsigned uw;
1138
1139         /* Can't get power when the card is off */
1140         if  ((adev->flags & AMD_IS_PX) &&
1141              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1142                 return -EINVAL;
1143
1144         /* sanity check PP is enabled */
1145         if (!(adev->powerplay.pp_funcs &&
1146               adev->powerplay.pp_funcs->read_sensor))
1147               return -EINVAL;
1148
1149         /* get the voltage */
1150         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1151                                    (void *)&query, &size);
1152         if (r)
1153                 return r;
1154
1155         /* convert to microwatts */
1156         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1157
1158         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1159 }
1160
1161 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1162                                          struct device_attribute *attr,
1163                                          char *buf)
1164 {
1165         return sprintf(buf, "%i\n", 0);
1166 }
1167
1168 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1169                                          struct device_attribute *attr,
1170                                          char *buf)
1171 {
1172         struct amdgpu_device *adev = dev_get_drvdata(dev);
1173         uint32_t limit = 0;
1174
1175         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1176                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1177                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1178         } else {
1179                 return snprintf(buf, PAGE_SIZE, "\n");
1180         }
1181 }
1182
1183 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1184                                          struct device_attribute *attr,
1185                                          char *buf)
1186 {
1187         struct amdgpu_device *adev = dev_get_drvdata(dev);
1188         uint32_t limit = 0;
1189
1190         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1191                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1192                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1193         } else {
1194                 return snprintf(buf, PAGE_SIZE, "\n");
1195         }
1196 }
1197
1198
1199 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1200                 struct device_attribute *attr,
1201                 const char *buf,
1202                 size_t count)
1203 {
1204         struct amdgpu_device *adev = dev_get_drvdata(dev);
1205         int err;
1206         u32 value;
1207
1208         err = kstrtou32(buf, 10, &value);
1209         if (err)
1210                 return err;
1211
1212         value = value / 1000000; /* convert to Watt */
1213         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1214                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1215                 if (err)
1216                         return err;
1217         } else {
1218                 return -EINVAL;
1219         }
1220
1221         return count;
1222 }
1223
1224
1225 /**
1226  * DOC: hwmon
1227  *
1228  * The amdgpu driver exposes the following sensor interfaces:
1229  * - GPU temperature (via the on-die sensor)
1230  * - GPU voltage
1231  * - Northbridge voltage (APUs only)
1232  * - GPU power
1233  * - GPU fan
1234  *
1235  * hwmon interfaces for GPU temperature:
1236  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1237  * - temp1_crit: temperature critical max value in millidegrees Celsius
1238  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1239  *
1240  * hwmon interfaces for GPU voltage:
1241  * - in0_input: the voltage on the GPU in millivolts
1242  * - in1_input: the voltage on the Northbridge in millivolts
1243  *
1244  * hwmon interfaces for GPU power:
1245  * - power1_average: average power used by the GPU in microWatts
1246  * - power1_cap_min: minimum cap supported in microWatts
1247  * - power1_cap_max: maximum cap supported in microWatts
1248  * - power1_cap: selected power cap in microWatts
1249  *
1250  * hwmon interfaces for GPU fan:
1251  * - pwm1: pulse width modulation fan level (0-255)
1252  * - pwm1_enable: pulse width modulation fan control method
1253  *                0: no fan speed control
1254  *                1: manual fan speed control using pwm interface
1255  *                2: automatic fan speed control
1256  * - pwm1_min: pulse width modulation fan control minimum level (0)
1257  * - pwm1_max: pulse width modulation fan control maximum level (255)
1258  * - fan1_input: fan speed in RPM
1259  *
1260  * You can use hwmon tools like sensors to view this information on your system.
1261  *
1262  */
1263
1264 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1265 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1266 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1267 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1268 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1269 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1270 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1271 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1272 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1273 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1274 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1275 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1276 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1277 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1278 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1279 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1280
1281 static struct attribute *hwmon_attributes[] = {
1282         &sensor_dev_attr_temp1_input.dev_attr.attr,
1283         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1284         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1285         &sensor_dev_attr_pwm1.dev_attr.attr,
1286         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1287         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1288         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1289         &sensor_dev_attr_fan1_input.dev_attr.attr,
1290         &sensor_dev_attr_in0_input.dev_attr.attr,
1291         &sensor_dev_attr_in0_label.dev_attr.attr,
1292         &sensor_dev_attr_in1_input.dev_attr.attr,
1293         &sensor_dev_attr_in1_label.dev_attr.attr,
1294         &sensor_dev_attr_power1_average.dev_attr.attr,
1295         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1296         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1297         &sensor_dev_attr_power1_cap.dev_attr.attr,
1298         NULL
1299 };
1300
1301 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1302                                         struct attribute *attr, int index)
1303 {
1304         struct device *dev = kobj_to_dev(kobj);
1305         struct amdgpu_device *adev = dev_get_drvdata(dev);
1306         umode_t effective_mode = attr->mode;
1307
1308         /* handle non-powerplay limitations */
1309         if (!adev->powerplay.pp_handle) {
1310                 /* Skip fan attributes if fan is not present */
1311                 if (adev->pm.no_fan &&
1312                     (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1313                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1314                      attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1315                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1316                         return 0;
1317                 /* requires powerplay */
1318                 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1319                         return 0;
1320         }
1321
1322         /* Skip limit attributes if DPM is not enabled */
1323         if (!adev->pm.dpm_enabled &&
1324             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1325              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1326              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1327              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1328              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1329              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1330                 return 0;
1331
1332         /* mask fan attributes if we have no bindings for this asic to expose */
1333         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1334              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1335             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1336              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1337                 effective_mode &= ~S_IRUGO;
1338
1339         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1340              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1341             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1342              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1343                 effective_mode &= ~S_IWUSR;
1344
1345         if ((adev->flags & AMD_IS_APU) &&
1346             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1347              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1348              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1349                 return 0;
1350
1351         /* hide max/min values if we can't both query and manage the fan */
1352         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1353              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1354             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1355              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1356                 return 0;
1357
1358         /* only APUs have vddnb */
1359         if (!(adev->flags & AMD_IS_APU) &&
1360             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1361              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1362                 return 0;
1363
1364         return effective_mode;
1365 }
1366
1367 static const struct attribute_group hwmon_attrgroup = {
1368         .attrs = hwmon_attributes,
1369         .is_visible = hwmon_attributes_visible,
1370 };
1371
1372 static const struct attribute_group *hwmon_groups[] = {
1373         &hwmon_attrgroup,
1374         NULL
1375 };
1376
1377 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1378 {
1379         struct amdgpu_device *adev =
1380                 container_of(work, struct amdgpu_device,
1381                              pm.dpm.thermal.work);
1382         /* switch to the thermal state */
1383         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1384         int temp, size = sizeof(temp);
1385
1386         if (!adev->pm.dpm_enabled)
1387                 return;
1388
1389         if (adev->powerplay.pp_funcs &&
1390             adev->powerplay.pp_funcs->read_sensor &&
1391             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1392                                     (void *)&temp, &size)) {
1393                 if (temp < adev->pm.dpm.thermal.min_temp)
1394                         /* switch back the user state */
1395                         dpm_state = adev->pm.dpm.user_state;
1396         } else {
1397                 if (adev->pm.dpm.thermal.high_to_low)
1398                         /* switch back the user state */
1399                         dpm_state = adev->pm.dpm.user_state;
1400         }
1401         mutex_lock(&adev->pm.mutex);
1402         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1403                 adev->pm.dpm.thermal_active = true;
1404         else
1405                 adev->pm.dpm.thermal_active = false;
1406         adev->pm.dpm.state = dpm_state;
1407         mutex_unlock(&adev->pm.mutex);
1408
1409         amdgpu_pm_compute_clocks(adev);
1410 }
1411
1412 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1413                                                      enum amd_pm_state_type dpm_state)
1414 {
1415         int i;
1416         struct amdgpu_ps *ps;
1417         u32 ui_class;
1418         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1419                 true : false;
1420
1421         /* check if the vblank period is too short to adjust the mclk */
1422         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1423                 if (amdgpu_dpm_vblank_too_short(adev))
1424                         single_display = false;
1425         }
1426
1427         /* certain older asics have a separare 3D performance state,
1428          * so try that first if the user selected performance
1429          */
1430         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1431                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1432         /* balanced states don't exist at the moment */
1433         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1434                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1435
1436 restart_search:
1437         /* Pick the best power state based on current conditions */
1438         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1439                 ps = &adev->pm.dpm.ps[i];
1440                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1441                 switch (dpm_state) {
1442                 /* user states */
1443                 case POWER_STATE_TYPE_BATTERY:
1444                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1445                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1446                                         if (single_display)
1447                                                 return ps;
1448                                 } else
1449                                         return ps;
1450                         }
1451                         break;
1452                 case POWER_STATE_TYPE_BALANCED:
1453                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1454                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1455                                         if (single_display)
1456                                                 return ps;
1457                                 } else
1458                                         return ps;
1459                         }
1460                         break;
1461                 case POWER_STATE_TYPE_PERFORMANCE:
1462                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1463                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1464                                         if (single_display)
1465                                                 return ps;
1466                                 } else
1467                                         return ps;
1468                         }
1469                         break;
1470                 /* internal states */
1471                 case POWER_STATE_TYPE_INTERNAL_UVD:
1472                         if (adev->pm.dpm.uvd_ps)
1473                                 return adev->pm.dpm.uvd_ps;
1474                         else
1475                                 break;
1476                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1477                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1478                                 return ps;
1479                         break;
1480                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1481                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1482                                 return ps;
1483                         break;
1484                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1485                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1486                                 return ps;
1487                         break;
1488                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1489                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1490                                 return ps;
1491                         break;
1492                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1493                         return adev->pm.dpm.boot_ps;
1494                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1495                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1496                                 return ps;
1497                         break;
1498                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1499                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1500                                 return ps;
1501                         break;
1502                 case POWER_STATE_TYPE_INTERNAL_ULV:
1503                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1504                                 return ps;
1505                         break;
1506                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1507                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1508                                 return ps;
1509                         break;
1510                 default:
1511                         break;
1512                 }
1513         }
1514         /* use a fallback state if we didn't match */
1515         switch (dpm_state) {
1516         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1517                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1518                 goto restart_search;
1519         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1520         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1521         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1522                 if (adev->pm.dpm.uvd_ps) {
1523                         return adev->pm.dpm.uvd_ps;
1524                 } else {
1525                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1526                         goto restart_search;
1527                 }
1528         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1529                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1530                 goto restart_search;
1531         case POWER_STATE_TYPE_INTERNAL_ACPI:
1532                 dpm_state = POWER_STATE_TYPE_BATTERY;
1533                 goto restart_search;
1534         case POWER_STATE_TYPE_BATTERY:
1535         case POWER_STATE_TYPE_BALANCED:
1536         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1537                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1538                 goto restart_search;
1539         default:
1540                 break;
1541         }
1542
1543         return NULL;
1544 }
1545
1546 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1547 {
1548         struct amdgpu_ps *ps;
1549         enum amd_pm_state_type dpm_state;
1550         int ret;
1551         bool equal = false;
1552
1553         /* if dpm init failed */
1554         if (!adev->pm.dpm_enabled)
1555                 return;
1556
1557         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1558                 /* add other state override checks here */
1559                 if ((!adev->pm.dpm.thermal_active) &&
1560                     (!adev->pm.dpm.uvd_active))
1561                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1562         }
1563         dpm_state = adev->pm.dpm.state;
1564
1565         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1566         if (ps)
1567                 adev->pm.dpm.requested_ps = ps;
1568         else
1569                 return;
1570
1571         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1572                 printk("switching from power state:\n");
1573                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1574                 printk("switching to power state:\n");
1575                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1576         }
1577
1578         /* update whether vce is active */
1579         ps->vce_active = adev->pm.dpm.vce_active;
1580         if (adev->powerplay.pp_funcs->display_configuration_changed)
1581                 amdgpu_dpm_display_configuration_changed(adev);
1582
1583         ret = amdgpu_dpm_pre_set_power_state(adev);
1584         if (ret)
1585                 return;
1586
1587         if (adev->powerplay.pp_funcs->check_state_equal) {
1588                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1589                         equal = false;
1590         }
1591
1592         if (equal)
1593                 return;
1594
1595         amdgpu_dpm_set_power_state(adev);
1596         amdgpu_dpm_post_set_power_state(adev);
1597
1598         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1599         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1600
1601         if (adev->powerplay.pp_funcs->force_performance_level) {
1602                 if (adev->pm.dpm.thermal_active) {
1603                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1604                         /* force low perf level for thermal */
1605                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1606                         /* save the user's level */
1607                         adev->pm.dpm.forced_level = level;
1608                 } else {
1609                         /* otherwise, user selected level */
1610                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1611                 }
1612         }
1613 }
1614
1615 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1616 {
1617         if (adev->powerplay.pp_funcs->powergate_uvd) {
1618                 /* enable/disable UVD */
1619                 mutex_lock(&adev->pm.mutex);
1620                 amdgpu_dpm_powergate_uvd(adev, !enable);
1621                 mutex_unlock(&adev->pm.mutex);
1622         } else {
1623                 if (enable) {
1624                         mutex_lock(&adev->pm.mutex);
1625                         adev->pm.dpm.uvd_active = true;
1626                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1627                         mutex_unlock(&adev->pm.mutex);
1628                 } else {
1629                         mutex_lock(&adev->pm.mutex);
1630                         adev->pm.dpm.uvd_active = false;
1631                         mutex_unlock(&adev->pm.mutex);
1632                 }
1633                 amdgpu_pm_compute_clocks(adev);
1634         }
1635 }
1636
1637 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1638 {
1639         if (adev->powerplay.pp_funcs->powergate_vce) {
1640                 /* enable/disable VCE */
1641                 mutex_lock(&adev->pm.mutex);
1642                 amdgpu_dpm_powergate_vce(adev, !enable);
1643                 mutex_unlock(&adev->pm.mutex);
1644         } else {
1645                 if (enable) {
1646                         mutex_lock(&adev->pm.mutex);
1647                         adev->pm.dpm.vce_active = true;
1648                         /* XXX select vce level based on ring/task */
1649                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1650                         mutex_unlock(&adev->pm.mutex);
1651                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1652                                                                AMD_CG_STATE_UNGATE);
1653                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1654                                                                AMD_PG_STATE_UNGATE);
1655                         amdgpu_pm_compute_clocks(adev);
1656                 } else {
1657                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1658                                                                AMD_PG_STATE_GATE);
1659                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1660                                                                AMD_CG_STATE_GATE);
1661                         mutex_lock(&adev->pm.mutex);
1662                         adev->pm.dpm.vce_active = false;
1663                         mutex_unlock(&adev->pm.mutex);
1664                         amdgpu_pm_compute_clocks(adev);
1665                 }
1666
1667         }
1668 }
1669
1670 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1671 {
1672         int i;
1673
1674         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1675                 return;
1676
1677         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1678                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1679
1680 }
1681
1682 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1683 {
1684         int ret;
1685
1686         if (adev->pm.sysfs_initialized)
1687                 return 0;
1688
1689         if (adev->pm.dpm_enabled == 0)
1690                 return 0;
1691
1692         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1693                                                                    DRIVER_NAME, adev,
1694                                                                    hwmon_groups);
1695         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1696                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1697                 dev_err(adev->dev,
1698                         "Unable to register hwmon device: %d\n", ret);
1699                 return ret;
1700         }
1701
1702         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1703         if (ret) {
1704                 DRM_ERROR("failed to create device file for dpm state\n");
1705                 return ret;
1706         }
1707         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1708         if (ret) {
1709                 DRM_ERROR("failed to create device file for dpm state\n");
1710                 return ret;
1711         }
1712
1713
1714         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1715         if (ret) {
1716                 DRM_ERROR("failed to create device file pp_num_states\n");
1717                 return ret;
1718         }
1719         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1720         if (ret) {
1721                 DRM_ERROR("failed to create device file pp_cur_state\n");
1722                 return ret;
1723         }
1724         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1725         if (ret) {
1726                 DRM_ERROR("failed to create device file pp_force_state\n");
1727                 return ret;
1728         }
1729         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1730         if (ret) {
1731                 DRM_ERROR("failed to create device file pp_table\n");
1732                 return ret;
1733         }
1734
1735         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1736         if (ret) {
1737                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1738                 return ret;
1739         }
1740         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1741         if (ret) {
1742                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1743                 return ret;
1744         }
1745         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1746         if (ret) {
1747                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1748                 return ret;
1749         }
1750         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1751         if (ret) {
1752                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1753                 return ret;
1754         }
1755         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1756         if (ret) {
1757                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1758                 return ret;
1759         }
1760         ret = device_create_file(adev->dev,
1761                         &dev_attr_pp_power_profile_mode);
1762         if (ret) {
1763                 DRM_ERROR("failed to create device file "
1764                                 "pp_power_profile_mode\n");
1765                 return ret;
1766         }
1767         ret = device_create_file(adev->dev,
1768                         &dev_attr_pp_od_clk_voltage);
1769         if (ret) {
1770                 DRM_ERROR("failed to create device file "
1771                                 "pp_od_clk_voltage\n");
1772                 return ret;
1773         }
1774         ret = amdgpu_debugfs_pm_init(adev);
1775         if (ret) {
1776                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1777                 return ret;
1778         }
1779
1780         adev->pm.sysfs_initialized = true;
1781
1782         return 0;
1783 }
1784
1785 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1786 {
1787         if (adev->pm.dpm_enabled == 0)
1788                 return;
1789
1790         if (adev->pm.int_hwmon_dev)
1791                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1792         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1793         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1794
1795         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1796         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1797         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1798         device_remove_file(adev->dev, &dev_attr_pp_table);
1799
1800         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1801         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1802         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1803         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1804         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1805         device_remove_file(adev->dev,
1806                         &dev_attr_pp_power_profile_mode);
1807         device_remove_file(adev->dev,
1808                         &dev_attr_pp_od_clk_voltage);
1809 }
1810
1811 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1812 {
1813         int i = 0;
1814
1815         if (!adev->pm.dpm_enabled)
1816                 return;
1817
1818         if (adev->mode_info.num_crtc)
1819                 amdgpu_display_bandwidth_update(adev);
1820
1821         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1822                 struct amdgpu_ring *ring = adev->rings[i];
1823                 if (ring && ring->ready)
1824                         amdgpu_fence_wait_empty(ring);
1825         }
1826
1827         if (!amdgpu_device_has_dc_support(adev)) {
1828                 mutex_lock(&adev->pm.mutex);
1829                 amdgpu_dpm_get_active_displays(adev);
1830                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
1831                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1832                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1833                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1834                 if (adev->pm.pm_display_cfg.vrefresh > 120)
1835                         adev->pm.pm_display_cfg.min_vblank_time = 0;
1836                 if (adev->powerplay.pp_funcs->display_configuration_change)
1837                         adev->powerplay.pp_funcs->display_configuration_change(
1838                                                         adev->powerplay.pp_handle,
1839                                                         &adev->pm.pm_display_cfg);
1840                 mutex_unlock(&adev->pm.mutex);
1841         }
1842
1843         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1844                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1845         } else {
1846                 mutex_lock(&adev->pm.mutex);
1847                 /* update battery/ac status */
1848                 if (power_supply_is_system_supplied() > 0)
1849                         adev->pm.dpm.ac_power = true;
1850                 else
1851                         adev->pm.dpm.ac_power = false;
1852
1853                 amdgpu_dpm_change_power_state_locked(adev);
1854
1855                 mutex_unlock(&adev->pm.mutex);
1856         }
1857 }
1858
1859 /*
1860  * Debugfs info
1861  */
1862 #if defined(CONFIG_DEBUG_FS)
1863
1864 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1865 {
1866         uint32_t value;
1867         uint32_t query = 0;
1868         int size;
1869
1870         /* sanity check PP is enabled */
1871         if (!(adev->powerplay.pp_funcs &&
1872               adev->powerplay.pp_funcs->read_sensor))
1873               return -EINVAL;
1874
1875         /* GPU Clocks */
1876         size = sizeof(value);
1877         seq_printf(m, "GFX Clocks and Power:\n");
1878         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1879                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1880         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1881                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1882         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1883                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1884         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1885                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1886         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1887                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1888         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1889                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1890         size = sizeof(uint32_t);
1891         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1892                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
1893         size = sizeof(value);
1894         seq_printf(m, "\n");
1895
1896         /* GPU Temp */
1897         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1898                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1899
1900         /* GPU Load */
1901         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1902                 seq_printf(m, "GPU Load: %u %%\n", value);
1903         seq_printf(m, "\n");
1904
1905         /* UVD clocks */
1906         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1907                 if (!value) {
1908                         seq_printf(m, "UVD: Disabled\n");
1909                 } else {
1910                         seq_printf(m, "UVD: Enabled\n");
1911                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1912                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1913                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1914                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1915                 }
1916         }
1917         seq_printf(m, "\n");
1918
1919         /* VCE clocks */
1920         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1921                 if (!value) {
1922                         seq_printf(m, "VCE: Disabled\n");
1923                 } else {
1924                         seq_printf(m, "VCE: Enabled\n");
1925                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1926                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1927                 }
1928         }
1929
1930         return 0;
1931 }
1932
1933 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1934 {
1935         int i;
1936
1937         for (i = 0; clocks[i].flag; i++)
1938                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1939                            (flags & clocks[i].flag) ? "On" : "Off");
1940 }
1941
1942 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1943 {
1944         struct drm_info_node *node = (struct drm_info_node *) m->private;
1945         struct drm_device *dev = node->minor->dev;
1946         struct amdgpu_device *adev = dev->dev_private;
1947         struct drm_device *ddev = adev->ddev;
1948         u32 flags = 0;
1949
1950         amdgpu_device_ip_get_clockgating_state(adev, &flags);
1951         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1952         amdgpu_parse_cg_state(m, flags);
1953         seq_printf(m, "\n");
1954
1955         if (!adev->pm.dpm_enabled) {
1956                 seq_printf(m, "dpm not enabled\n");
1957                 return 0;
1958         }
1959         if  ((adev->flags & AMD_IS_PX) &&
1960              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1961                 seq_printf(m, "PX asic powered off\n");
1962         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
1963                 mutex_lock(&adev->pm.mutex);
1964                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
1965                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
1966                 else
1967                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1968                 mutex_unlock(&adev->pm.mutex);
1969         } else {
1970                 return amdgpu_debugfs_pm_info_pp(m, adev);
1971         }
1972
1973         return 0;
1974 }
1975
1976 static const struct drm_info_list amdgpu_pm_info_list[] = {
1977         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1978 };
1979 #endif
1980
1981 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1982 {
1983 #if defined(CONFIG_DEBUG_FS)
1984         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1985 #else
1986         return 0;
1987 #endif
1988 }