drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drm_drv.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_vcn.h"
  29 #include "amdgpu_pm.h"
  30 #include "soc15.h"
  31 #include "soc15d.h"
  32 #include "vcn_v2_0.h"
  33 #include "mmsch_v1_0.h"
  34 #include "vcn_v2_5.h"
  35
  36 #include "vcn/vcn_2_5_offset.h"
  37 #include "vcn/vcn_2_5_sh_mask.h"
  38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  39
  40 #define VCN_VID_SOC_ADDRESS_2_0                                 0x1fa00
  41 #define VCN1_VID_SOC_ADDRESS_3_0                                0x48200
  42
  43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                        0x27
  44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                    0x0f
  45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                  0x10
  46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET                  0x11
  47 #define mmUVD_NO_OP_INTERNAL_OFFSET                             0x29
  48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET                       0x66
  49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET                          0xc01d
  50
  51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET                   0x431
  52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET          0x3b4
  53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x3b5
  54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET                       0x25c
  55
  56 #define VCN25_MAX_HW_INSTANCES_ARCTURUS                 2
  57
  58 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
  59 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
  60 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
  61 static int vcn_v2_5_set_powergating_state(void *handle,
  62                                 enum amd_powergating_state state);
  63 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
  64                                 int inst_idx, struct dpg_pause_state *new_state);
  65 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
  66 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);
  67
  68 static int amdgpu_ih_clientid_vcns[] = {
  69         SOC15_IH_CLIENTID_VCN,
  70         SOC15_IH_CLIENTID_VCN1
  71 };
  72
  73 /**
  74  * vcn_v2_5_early_init - set function pointers and load microcode
  75  *
  76  * @handle: amdgpu_device pointer
  77  *
  78  * Set ring and irq function pointers
  79  * Load microcode from filesystem
  80  */
  81 static int vcn_v2_5_early_init(void *handle)
  82 {
  83         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  84
  85         if (amdgpu_sriov_vf(adev)) {
  86                 adev->vcn.num_vcn_inst = 2;
  87                 adev->vcn.harvest_config = 0;
  88                 adev->vcn.num_enc_rings = 1;
  89         } else {
  90                 u32 harvest;
  91                 int i;
  92
  93                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
  94                         harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
  95                         if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
  96                                 adev->vcn.harvest_config |= 1 << i;
  97                 }
  98                 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
  99                                         AMDGPU_VCN_HARVEST_VCN1))
 100                         /* both instances are harvested, disable the block */
 101                         return -ENOENT;
 102
 103                 adev->vcn.num_enc_rings = 2;
 104         }
 105
 106         vcn_v2_5_set_dec_ring_funcs(adev);
 107         vcn_v2_5_set_enc_ring_funcs(adev);
 108         vcn_v2_5_set_irq_funcs(adev);
 109         vcn_v2_5_set_ras_funcs(adev);
 110
 111         return amdgpu_vcn_early_init(adev);
 112 }
 113
 114 /**
 115  * vcn_v2_5_sw_init - sw init for VCN block
 116  *
 117  * @handle: amdgpu_device pointer
 118  *
 119  * Load firmware and sw initialization
 120  */
 121 static int vcn_v2_5_sw_init(void *handle)
 122 {
 123         struct amdgpu_ring *ring;
 124         int i, j, r;
 125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 126
 127         for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
 128                 if (adev->vcn.harvest_config & (1 << j))
 129                         continue;
 130                 /* VCN DEC TRAP */
 131                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
 132                                 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
 133                 if (r)
 134                         return r;
 135
 136                 /* VCN ENC TRAP */
 137                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 138                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
 139                                 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
 140                         if (r)
 141                                 return r;
 142                 }
 143
 144                 /* VCN POISON TRAP */
 145                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
 146                         VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].irq);
 147                 if (r)
 148                         return r;
 149         }
 150
 151         r = amdgpu_vcn_sw_init(adev);
 152         if (r)
 153                 return r;
 154
 155         amdgpu_vcn_setup_ucode(adev);
 156
 157         r = amdgpu_vcn_resume(adev);
 158         if (r)
 159                 return r;
 160
 161         for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
 162                 volatile struct amdgpu_fw_shared *fw_shared;
 163
 164                 if (adev->vcn.harvest_config & (1 << j))
 165                         continue;
 166                 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
 167                 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
 168                 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
 169                 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
 170                 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
 171                 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
 172
 173                 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
 174                 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);
 175                 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
 176                 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);
 177                 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
 178                 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);
 179                 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
 180                 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);
 181                 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
 182                 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);
 183
 184                 ring = &adev->vcn.inst[j].ring_dec;
 185                 ring->use_doorbell = true;
 186
 187                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 188                                 (amdgpu_sriov_vf(adev) ? 2*j : 8*j);
 189                 sprintf(ring->name, "vcn_dec_%d", j);
 190                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
 191                                      0, AMDGPU_RING_PRIO_DEFAULT, NULL);
 192                 if (r)
 193                         return r;
 194
 195                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 196                         enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
 197
 198                         ring = &adev->vcn.inst[j].ring_enc[i];
 199                         ring->use_doorbell = true;
 200
 201                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 202                                         (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j));
 203
 204                         sprintf(ring->name, "vcn_enc_%d.%d", j, i);
 205                         r = amdgpu_ring_init(adev, ring, 512,
 206                                              &adev->vcn.inst[j].irq, 0,
 207                                              hw_prio, NULL);
 208                         if (r)
 209                                 return r;
 210                 }
 211
 212                 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;
 213                 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
 214
 215                 if (amdgpu_vcnfw_log)
 216                         amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 217         }
 218
 219         if (amdgpu_sriov_vf(adev)) {
 220                 r = amdgpu_virt_alloc_mm_table(adev);
 221                 if (r)
 222                         return r;
 223         }
 224
 225         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 226                 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
 227
 228         return 0;
 229 }
 230
 231 /**
 232  * vcn_v2_5_sw_fini - sw fini for VCN block
 233  *
 234  * @handle: amdgpu_device pointer
 235  *
 236  * VCN suspend and free up sw allocation
 237  */
 238 static int vcn_v2_5_sw_fini(void *handle)
 239 {
 240         int i, r, idx;
 241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 242         volatile struct amdgpu_fw_shared *fw_shared;
 243
 244         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 245                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 246                         if (adev->vcn.harvest_config & (1 << i))
 247                                 continue;
 248                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 249                         fw_shared->present_flag_0 = 0;
 250                 }
 251                 drm_dev_exit(idx);
 252         }
 253
 254
 255         if (amdgpu_sriov_vf(adev))
 256                 amdgpu_virt_free_mm_table(adev);
 257
 258         r = amdgpu_vcn_suspend(adev);
 259         if (r)
 260                 return r;
 261
 262         r = amdgpu_vcn_sw_fini(adev);
 263
 264         return r;
 265 }
 266
 267 /**
 268  * vcn_v2_5_hw_init - start and test VCN block
 269  *
 270  * @handle: amdgpu_device pointer
 271  *
 272  * Initialize the hardware, boot up the VCPU and do some testing
 273  */
 274 static int vcn_v2_5_hw_init(void *handle)
 275 {
 276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 277         struct amdgpu_ring *ring;
 278         int i, j, r = 0;
 279
 280         if (amdgpu_sriov_vf(adev))
 281                 r = vcn_v2_5_sriov_start(adev);
 282
 283         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
 284                 if (adev->vcn.harvest_config & (1 << j))
 285                         continue;
 286
 287                 if (amdgpu_sriov_vf(adev)) {
 288                         adev->vcn.inst[j].ring_enc[0].sched.ready = true;
 289                         adev->vcn.inst[j].ring_enc[1].sched.ready = false;
 290                         adev->vcn.inst[j].ring_enc[2].sched.ready = false;
 291                         adev->vcn.inst[j].ring_dec.sched.ready = true;
 292                 } else {
 293
 294                         ring = &adev->vcn.inst[j].ring_dec;
 295
 296                         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 297                                                      ring->doorbell_index, j);
 298
 299                         r = amdgpu_ring_test_helper(ring);
 300                         if (r)
 301                                 goto done;
 302
 303                         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 304                                 ring = &adev->vcn.inst[j].ring_enc[i];
 305                                 r = amdgpu_ring_test_helper(ring);
 306                                 if (r)
 307                                         goto done;
 308                         }
 309                 }
 310         }
 311
 312 done:
 313         if (!r)
 314                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 315                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 316
 317         return r;
 318 }
 319
 320 /**
 321  * vcn_v2_5_hw_fini - stop the hardware block
 322  *
 323  * @handle: amdgpu_device pointer
 324  *
 325  * Stop the VCN block, mark ring as not ready any more
 326  */
 327 static int vcn_v2_5_hw_fini(void *handle)
 328 {
 329         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 330         int i;
 331
 332         cancel_delayed_work_sync(&adev->vcn.idle_work);
 333
 334         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 335                 if (adev->vcn.harvest_config & (1 << i))
 336                         continue;
 337
 338                 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 339                     (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 340                      RREG32_SOC15(VCN, i, mmUVD_STATUS)))
 341                         vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
 342         }
 343
 344         return 0;
 345 }
 346
 347 /**
 348  * vcn_v2_5_suspend - suspend VCN block
 349  *
 350  * @handle: amdgpu_device pointer
 351  *
 352  * HW fini and suspend VCN block
 353  */
 354 static int vcn_v2_5_suspend(void *handle)
 355 {
 356         int r;
 357         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 358
 359         r = vcn_v2_5_hw_fini(adev);
 360         if (r)
 361                 return r;
 362
 363         r = amdgpu_vcn_suspend(adev);
 364
 365         return r;
 366 }
 367
 368 /**
 369  * vcn_v2_5_resume - resume VCN block
 370  *
 371  * @handle: amdgpu_device pointer
 372  *
 373  * Resume firmware and hw init VCN block
 374  */
 375 static int vcn_v2_5_resume(void *handle)
 376 {
 377         int r;
 378         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 379
 380         r = amdgpu_vcn_resume(adev);
 381         if (r)
 382                 return r;
 383
 384         r = vcn_v2_5_hw_init(adev);
 385
 386         return r;
 387 }
 388
 389 /**
 390  * vcn_v2_5_mc_resume - memory controller programming
 391  *
 392  * @adev: amdgpu_device pointer
 393  *
 394  * Let the VCN memory controller know it's offsets
 395  */
 396 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
 397 {
 398         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 399         uint32_t offset;
 400         int i;
 401
 402         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 403                 if (adev->vcn.harvest_config & (1 << i))
 404                         continue;
 405                 /* cache window 0: fw */
 406                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 407                         WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 408                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo));
 409                         WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 410                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi));
 411                         WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
 412                         offset = 0;
 413                 } else {
 414                         WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 415                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
 416                         WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 417                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
 418                         offset = size;
 419                         WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,
 420                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 421                 }
 422                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size);
 423
 424                 /* cache window 1: stack */
 425                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 426                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
 427                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 428                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
 429                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
 430                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 431
 432                 /* cache window 2: context */
 433                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 434                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 435                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 436                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 437                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
 438                 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 439
 440                 /* non-cache window */
 441                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 442                         lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
 443                 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 444                         upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
 445                 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
 446                 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,
 447                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
 448         }
 449 }
 450
 451 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 452 {
 453         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 454         uint32_t offset;
 455
 456         /* cache window 0: fw */
 457         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 458                 if (!indirect) {
 459                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 460                                 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 461                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 462                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 463                                 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 464                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 465                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 466                                 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 467                 } else {
 468                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 469                                 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 470                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 471                                 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 472                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 473                                 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 474                 }
 475                 offset = 0;
 476         } else {
 477                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 478                         VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 479                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 480                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 481                         VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 482                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 483                 offset = size;
 484                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 485                         VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),
 486                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 487         }
 488
 489         if (!indirect)
 490                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 491                         VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 492         else
 493                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 494                         VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 495
 496         /* cache window 1: stack */
 497         if (!indirect) {
 498                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 499                         VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 500                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 501                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 502                         VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 503                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 504                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 505                         VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 506         } else {
 507                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 508                         VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 509                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 510                         VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 511                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 512                         VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 513         }
 514         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 515                 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 516
 517         /* cache window 2: context */
 518         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 519                 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 520                 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 521         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 522                 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 523                 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 524         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 525                 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 526         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 527                 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 528
 529         /* non-cache window */
 530         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 531                 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 532                 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 533         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 534                 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 535                 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 536         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 537                 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 538         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 539                 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0),
 540                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
 541
 542         /* VCN global tiling registers */
 543         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 544                 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 545 }
 546
 547 /**
 548  * vcn_v2_5_disable_clock_gating - disable VCN clock gating
 549  *
 550  * @adev: amdgpu_device pointer
 551  *
 552  * Disable clock gating for VCN block
 553  */
 554 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
 555 {
 556         uint32_t data;
 557         int i;
 558
 559         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 560                 if (adev->vcn.harvest_config & (1 << i))
 561                         continue;
 562                 /* UVD disable CGC */
 563                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 564                 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 565                         data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 566                 else
 567                         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 568                 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 569                 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 570                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 571
 572                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
 573                 data &= ~(UVD_CGC_GATE__SYS_MASK
 574                         | UVD_CGC_GATE__UDEC_MASK
 575                         | UVD_CGC_GATE__MPEG2_MASK
 576                         | UVD_CGC_GATE__REGS_MASK
 577                         | UVD_CGC_GATE__RBC_MASK
 578                         | UVD_CGC_GATE__LMI_MC_MASK
 579                         | UVD_CGC_GATE__LMI_UMC_MASK
 580                         | UVD_CGC_GATE__IDCT_MASK
 581                         | UVD_CGC_GATE__MPRD_MASK
 582                         | UVD_CGC_GATE__MPC_MASK
 583                         | UVD_CGC_GATE__LBSI_MASK
 584                         | UVD_CGC_GATE__LRBBM_MASK
 585                         | UVD_CGC_GATE__UDEC_RE_MASK
 586                         | UVD_CGC_GATE__UDEC_CM_MASK
 587                         | UVD_CGC_GATE__UDEC_IT_MASK
 588                         | UVD_CGC_GATE__UDEC_DB_MASK
 589                         | UVD_CGC_GATE__UDEC_MP_MASK
 590                         | UVD_CGC_GATE__WCB_MASK
 591                         | UVD_CGC_GATE__VCPU_MASK
 592                         | UVD_CGC_GATE__MMSCH_MASK);
 593
 594                 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
 595
 596                 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);
 597
 598                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 599                 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 600                         | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 601                         | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 602                         | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 603                         | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 604                         | UVD_CGC_CTRL__SYS_MODE_MASK
 605                         | UVD_CGC_CTRL__UDEC_MODE_MASK
 606                         | UVD_CGC_CTRL__MPEG2_MODE_MASK
 607                         | UVD_CGC_CTRL__REGS_MODE_MASK
 608                         | UVD_CGC_CTRL__RBC_MODE_MASK
 609                         | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 610                         | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 611                         | UVD_CGC_CTRL__IDCT_MODE_MASK
 612                         | UVD_CGC_CTRL__MPRD_MODE_MASK
 613                         | UVD_CGC_CTRL__MPC_MODE_MASK
 614                         | UVD_CGC_CTRL__LBSI_MODE_MASK
 615                         | UVD_CGC_CTRL__LRBBM_MODE_MASK
 616                         | UVD_CGC_CTRL__WCB_MODE_MASK
 617                         | UVD_CGC_CTRL__VCPU_MODE_MASK
 618                         | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 619                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 620
 621                 /* turn on */
 622                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
 623                 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 624                         | UVD_SUVD_CGC_GATE__SIT_MASK
 625                         | UVD_SUVD_CGC_GATE__SMP_MASK
 626                         | UVD_SUVD_CGC_GATE__SCM_MASK
 627                         | UVD_SUVD_CGC_GATE__SDB_MASK
 628                         | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 629                         | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 630                         | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 631                         | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 632                         | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 633                         | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 634                         | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 635                         | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 636                         | UVD_SUVD_CGC_GATE__SCLR_MASK
 637                         | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 638                         | UVD_SUVD_CGC_GATE__ENT_MASK
 639                         | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 640                         | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 641                         | UVD_SUVD_CGC_GATE__SITE_MASK
 642                         | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 643                         | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 644                         | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 645                         | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 646                         | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 647                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
 648
 649                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
 650                 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 651                         | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 652                         | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 653                         | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 654                         | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 655                         | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 656                         | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 657                         | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 658                         | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 659                         | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 660                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
 661         }
 662 }
 663
 664 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
 665                 uint8_t sram_sel, int inst_idx, uint8_t indirect)
 666 {
 667         uint32_t reg_data = 0;
 668
 669         /* enable sw clock gating control */
 670         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 671                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 672         else
 673                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 674         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 675         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 676         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 677                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 678                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 679                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 680                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 681                  UVD_CGC_CTRL__SYS_MODE_MASK |
 682                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 683                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 684                  UVD_CGC_CTRL__REGS_MODE_MASK |
 685                  UVD_CGC_CTRL__RBC_MODE_MASK |
 686                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 687                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 688                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 689                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 690                  UVD_CGC_CTRL__MPC_MODE_MASK |
 691                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 692                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 693                  UVD_CGC_CTRL__WCB_MODE_MASK |
 694                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 695                  UVD_CGC_CTRL__MMSCH_MODE_MASK);
 696         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 697                 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 698
 699         /* turn off clock gating */
 700         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 701                 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
 702
 703         /* turn on SUVD clock gating */
 704         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 705                 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 706
 707         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 708         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 709                 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 710 }
 711
 712 /**
 713  * vcn_v2_5_enable_clock_gating - enable VCN clock gating
 714  *
 715  * @adev: amdgpu_device pointer
 716  *
 717  * Enable clock gating for VCN block
 718  */
 719 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
 720 {
 721         uint32_t data = 0;
 722         int i;
 723
 724         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 725                 if (adev->vcn.harvest_config & (1 << i))
 726                         continue;
 727                 /* enable UVD CGC */
 728                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 729                 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 730                         data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 731                 else
 732                         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 733                 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 734                 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 735                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 736
 737                 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
 738                 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 739                         | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 740                         | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 741                         | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 742                         | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 743                         | UVD_CGC_CTRL__SYS_MODE_MASK
 744                         | UVD_CGC_CTRL__UDEC_MODE_MASK
 745                         | UVD_CGC_CTRL__MPEG2_MODE_MASK
 746                         | UVD_CGC_CTRL__REGS_MODE_MASK
 747                         | UVD_CGC_CTRL__RBC_MODE_MASK
 748                         | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 749                         | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 750                         | UVD_CGC_CTRL__IDCT_MODE_MASK
 751                         | UVD_CGC_CTRL__MPRD_MODE_MASK
 752                         | UVD_CGC_CTRL__MPC_MODE_MASK
 753                         | UVD_CGC_CTRL__LBSI_MODE_MASK
 754                         | UVD_CGC_CTRL__LRBBM_MODE_MASK
 755                         | UVD_CGC_CTRL__WCB_MODE_MASK
 756                         | UVD_CGC_CTRL__VCPU_MODE_MASK);
 757                 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
 758
 759                 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
 760                 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 761                         | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 762                         | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 763                         | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 764                         | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 765                         | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 766                         | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 767                         | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 768                         | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 769                         | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 770                 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
 771         }
 772 }
 773
 774 static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx,
 775                                 bool indirect)
 776 {
 777         uint32_t tmp;
 778
 779         if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(2, 6, 0))
 780                 return;
 781
 782         tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
 783               VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
 784               VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
 785               VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
 786         WREG32_SOC15_DPG_MODE(inst_idx,
 787                               SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL),
 788                               tmp, 0, indirect);
 789
 790         tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
 791         WREG32_SOC15_DPG_MODE(inst_idx,
 792                               SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN),
 793                               tmp, 0, indirect);
 794
 795         tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
 796         WREG32_SOC15_DPG_MODE(inst_idx,
 797                               SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN),
 798                               tmp, 0, indirect);
 799 }
 800
 801 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 802 {
 803         volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 804         struct amdgpu_ring *ring;
 805         uint32_t rb_bufsz, tmp;
 806
 807         /* disable register anti-hang mechanism */
 808         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
 809                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 810         /* enable dynamic power gating mode */
 811         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
 812         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 813         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 814         WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
 815
 816         if (indirect)
 817                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 818
 819         /* enable clock gating */
 820         vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 821
 822         /* enable VCPU clock */
 823         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 824         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 825         tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
 826         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 827                 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 828
 829         /* disable master interupt */
 830         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 831                 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
 832
 833         /* setup mmUVD_LMI_CTRL */
 834         tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 835                 UVD_LMI_CTRL__REQ_MODE_MASK |
 836                 UVD_LMI_CTRL__CRC_RESET_MASK |
 837                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 838                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 839                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 840                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 841                 0x00100000L);
 842         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 843                 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
 844
 845         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 846                 VCN, 0, mmUVD_MPC_CNTL),
 847                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 848
 849         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 850                 VCN, 0, mmUVD_MPC_SET_MUXA0),
 851                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 852                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 853                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 854                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 855
 856         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 857                 VCN, 0, mmUVD_MPC_SET_MUXB0),
 858                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 859                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 860                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 861                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 862
 863         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 864                 VCN, 0, mmUVD_MPC_SET_MUX),
 865                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 866                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 867                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 868
 869         vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
 870
 871         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 872                 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
 873         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 874                 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
 875
 876         /* enable LMI MC and UMC channels */
 877         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 878                 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);
 879
 880         vcn_v2_6_enable_ras(adev, inst_idx, indirect);
 881
 882         /* unblock VCPU register access */
 883         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 884                 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
 885
 886         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 887         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 888         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 889                 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 890
 891         /* enable master interrupt */
 892         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 893                 VCN, 0, mmUVD_MASTINT_EN),
 894                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 895
 896         if (indirect)
 897                 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
 898                                     (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
 899                                                (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
 900
 901         ring = &adev->vcn.inst[inst_idx].ring_dec;
 902         /* force RBC into idle state */
 903         rb_bufsz = order_base_2(ring->ring_size);
 904         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 905         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 906         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 907         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 908         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 909         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
 910
 911         /* Stall DPG before WPTR/RPTR reset */
 912         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
 913                 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
 914                 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
 915         fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
 916
 917         /* set the write pointer delay */
 918         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
 919
 920         /* set the wb address */
 921         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
 922                 (upper_32_bits(ring->gpu_addr) >> 2));
 923
 924         /* program the RB_BASE for ring buffer */
 925         WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 926                 lower_32_bits(ring->gpu_addr));
 927         WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 928                 upper_32_bits(ring->gpu_addr));
 929
 930         /* Initialize the ring buffer's read and write pointers */
 931         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
 932
 933         WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
 934
 935         ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
 936         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
 937                 lower_32_bits(ring->wptr));
 938
 939         fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
 940         /* Unstall DPG */
 941         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
 942                 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
 943
 944         return 0;
 945 }
 946
 947 static int vcn_v2_5_start(struct amdgpu_device *adev)
 948 {
 949         struct amdgpu_ring *ring;
 950         uint32_t rb_bufsz, tmp;
 951         int i, j, k, r;
 952
 953         if (adev->pm.dpm_enabled)
 954                 amdgpu_dpm_enable_uvd(adev, true);
 955
 956         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 957                 if (adev->vcn.harvest_config & (1 << i))
 958                         continue;
 959                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
 960                         r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
 961                         continue;
 962                 }
 963
 964                 /* disable register anti-hang mechanism */
 965                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,
 966                         ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 967
 968                 /* set uvd status busy */
 969                 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 970                 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
 971         }
 972
 973         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 974                 return 0;
 975
 976         /*SW clock gating */
 977         vcn_v2_5_disable_clock_gating(adev);
 978
 979         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 980                 if (adev->vcn.harvest_config & (1 << i))
 981                         continue;
 982                 /* enable VCPU clock */
 983                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
 984                         UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
 985
 986                 /* disable master interrupt */
 987                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
 988                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 989
 990                 /* setup mmUVD_LMI_CTRL */
 991                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
 992                 tmp &= ~0xff;
 993                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|
 994                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 995                         UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 996                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 997                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 998
 999                 /* setup mmUVD_MPC_CNTL */
1000                 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1001                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1002                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1003                 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1004
1005                 /* setup UVD_MPC_SET_MUXA0 */
1006                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1007                         ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1008                         (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1009                         (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1010                         (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1011
1012                 /* setup UVD_MPC_SET_MUXB0 */
1013                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1014                         ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1015                         (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1016                         (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1017                         (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1018
1019                 /* setup mmUVD_MPC_SET_MUX */
1020                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1021                         ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1022                         (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1023                         (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1024         }
1025
1026         vcn_v2_5_mc_resume(adev);
1027
1028         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1029                 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1030                 if (adev->vcn.harvest_config & (1 << i))
1031                         continue;
1032                 /* VCN global tiling registers */
1033                 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
1034                         adev->gfx.config.gb_addr_config);
1035                 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
1036                         adev->gfx.config.gb_addr_config);
1037
1038                 /* enable LMI MC and UMC channels */
1039                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1040                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1041
1042                 /* unblock VCPU register access */
1043                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1044                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1045
1046                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1047                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1048
1049                 for (k = 0; k < 10; ++k) {
1050                         uint32_t status;
1051
1052                         for (j = 0; j < 100; ++j) {
1053                                 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1054                                 if (status & 2)
1055                                         break;
1056                                 if (amdgpu_emu_mode == 1)
1057                                         msleep(500);
1058                                 else
1059                                         mdelay(10);
1060                         }
1061                         r = 0;
1062                         if (status & 2)
1063                                 break;
1064
1065                         DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1066                         WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1067                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1068                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1069                         mdelay(10);
1070                         WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1071                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1072
1073                         mdelay(10);
1074                         r = -1;
1075                 }
1076
1077                 if (r) {
1078                         DRM_ERROR("VCN decode not responding, giving up!!!\n");
1079                         return r;
1080                 }
1081
1082                 /* enable master interrupt */
1083                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1084                         UVD_MASTINT_EN__VCPU_EN_MASK,
1085                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
1086
1087                 /* clear the busy bit of VCN_STATUS */
1088                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1089                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1090
1091                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1092
1093                 ring = &adev->vcn.inst[i].ring_dec;
1094                 /* force RBC into idle state */
1095                 rb_bufsz = order_base_2(ring->ring_size);
1096                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1097                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1098                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1099                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1100                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1101                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1102
1103                 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1104                 /* program the RB_BASE for ring buffer */
1105                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1106                         lower_32_bits(ring->gpu_addr));
1107                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1108                         upper_32_bits(ring->gpu_addr));
1109
1110                 /* Initialize the ring buffer's read and write pointers */
1111                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1112
1113                 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1114                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1115                                 lower_32_bits(ring->wptr));
1116                 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1117
1118                 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1119                 ring = &adev->vcn.inst[i].ring_enc[0];
1120                 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1121                 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1122                 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1123                 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1124                 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1125                 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1126
1127                 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1128                 ring = &adev->vcn.inst[i].ring_enc[1];
1129                 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1130                 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1131                 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1132                 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1133                 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1134                 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1135         }
1136
1137         return 0;
1138 }
1139
1140 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev,
1141                                 struct amdgpu_mm_table *table)
1142 {
1143         uint32_t data = 0, loop = 0, size = 0;
1144         uint64_t addr = table->gpu_addr;
1145         struct mmsch_v1_1_init_header *header = NULL;
1146
1147         header = (struct mmsch_v1_1_init_header *)table->cpu_addr;
1148         size = header->total_size;
1149
1150         /*
1151          * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of
1152          *  memory descriptor location
1153          */
1154         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1155         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1156
1157         /* 2, update vmid of descriptor */
1158         data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1159         data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1160         /* use domain0 for MM scheduler */
1161         data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1162         WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data);
1163
1164         /* 3, notify mmsch about the size of this descriptor */
1165         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1166
1167         /* 4, set resp to zero */
1168         WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1169
1170         /*
1171          * 5, kick off the initialization and wait until
1172          * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1173          */
1174         WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1175
1176         data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1177         loop = 10;
1178         while ((data & 0x10000002) != 0x10000002) {
1179                 udelay(100);
1180                 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1181                 loop--;
1182                 if (!loop)
1183                         break;
1184         }
1185
1186         if (!loop) {
1187                 dev_err(adev->dev,
1188                         "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n",
1189                         data);
1190                 return -EBUSY;
1191         }
1192
1193         return 0;
1194 }
1195
1196 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
1197 {
1198         struct amdgpu_ring *ring;
1199         uint32_t offset, size, tmp, i, rb_bufsz;
1200         uint32_t table_size = 0;
1201         struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } };
1202         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } };
1203         struct mmsch_v1_0_cmd_end end = { { 0 } };
1204         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1205         struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table;
1206
1207         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1208         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1209         end.cmd_header.command_type = MMSCH_COMMAND__END;
1210
1211         header->version = MMSCH_VERSION;
1212         header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2;
1213         init_table += header->total_size;
1214
1215         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1216                 header->eng[i].table_offset = header->total_size;
1217                 header->eng[i].init_status = 0;
1218                 header->eng[i].table_size = 0;
1219
1220                 table_size = 0;
1221
1222                 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(
1223                         SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),
1224                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1225
1226                 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1227                 /* mc resume*/
1228                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1229                         MMSCH_V1_0_INSERT_DIRECT_WT(
1230                                 SOC15_REG_OFFSET(VCN, i,
1231                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1232                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1233                         MMSCH_V1_0_INSERT_DIRECT_WT(
1234                                 SOC15_REG_OFFSET(VCN, i,
1235                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1236                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1237                         offset = 0;
1238                         MMSCH_V1_0_INSERT_DIRECT_WT(
1239                                 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0);
1240                 } else {
1241                         MMSCH_V1_0_INSERT_DIRECT_WT(
1242                                 SOC15_REG_OFFSET(VCN, i,
1243                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1244                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1245                         MMSCH_V1_0_INSERT_DIRECT_WT(
1246                                 SOC15_REG_OFFSET(VCN, i,
1247                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1248                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1249                         offset = size;
1250                         MMSCH_V1_0_INSERT_DIRECT_WT(
1251                                 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),
1252                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1253                 }
1254
1255                 MMSCH_V1_0_INSERT_DIRECT_WT(
1256                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),
1257                         size);
1258                 MMSCH_V1_0_INSERT_DIRECT_WT(
1259                         SOC15_REG_OFFSET(VCN, i,
1260                                 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1261                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1262                 MMSCH_V1_0_INSERT_DIRECT_WT(
1263                         SOC15_REG_OFFSET(VCN, i,
1264                                 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1265                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1266                 MMSCH_V1_0_INSERT_DIRECT_WT(
1267                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),
1268                         0);
1269                 MMSCH_V1_0_INSERT_DIRECT_WT(
1270                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1),
1271                         AMDGPU_VCN_STACK_SIZE);
1272                 MMSCH_V1_0_INSERT_DIRECT_WT(
1273                         SOC15_REG_OFFSET(VCN, i,
1274                                 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1275                         lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1276                                 AMDGPU_VCN_STACK_SIZE));
1277                 MMSCH_V1_0_INSERT_DIRECT_WT(
1278                         SOC15_REG_OFFSET(VCN, i,
1279                                 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1280                         upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1281                                 AMDGPU_VCN_STACK_SIZE));
1282                 MMSCH_V1_0_INSERT_DIRECT_WT(
1283                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),
1284                         0);
1285                 MMSCH_V1_0_INSERT_DIRECT_WT(
1286                         SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),
1287                         AMDGPU_VCN_CONTEXT_SIZE);
1288
1289                 ring = &adev->vcn.inst[i].ring_enc[0];
1290                 ring->wptr = 0;
1291
1292                 MMSCH_V1_0_INSERT_DIRECT_WT(
1293                         SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO),
1294                         lower_32_bits(ring->gpu_addr));
1295                 MMSCH_V1_0_INSERT_DIRECT_WT(
1296                         SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),
1297                         upper_32_bits(ring->gpu_addr));
1298                 MMSCH_V1_0_INSERT_DIRECT_WT(
1299                         SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),
1300                         ring->ring_size / 4);
1301
1302                 ring = &adev->vcn.inst[i].ring_dec;
1303                 ring->wptr = 0;
1304                 MMSCH_V1_0_INSERT_DIRECT_WT(
1305                         SOC15_REG_OFFSET(VCN, i,
1306                                 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1307                         lower_32_bits(ring->gpu_addr));
1308                 MMSCH_V1_0_INSERT_DIRECT_WT(
1309                         SOC15_REG_OFFSET(VCN, i,
1310                                 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1311                         upper_32_bits(ring->gpu_addr));
1312
1313                 /* force RBC into idle state */
1314                 rb_bufsz = order_base_2(ring->ring_size);
1315                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1316                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1317                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1318                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1319                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1320                 MMSCH_V1_0_INSERT_DIRECT_WT(
1321                         SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp);
1322
1323                 /* add end packet */
1324                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
1325                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1326                 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1327
1328                 /* refine header */
1329                 header->eng[i].table_size = table_size;
1330                 header->total_size += table_size;
1331         }
1332
1333         return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);
1334 }
1335
1336 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1337 {
1338         uint32_t tmp;
1339
1340         /* Wait for power status to be 1 */
1341         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1342                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1343
1344         /* wait for read ptr to be equal to write ptr */
1345         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1346         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1347
1348         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1349         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1350
1351         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1352         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1353
1354         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1355                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1356
1357         /* disable dynamic power gating mode */
1358         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1359                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1360
1361         return 0;
1362 }
1363
1364 static int vcn_v2_5_stop(struct amdgpu_device *adev)
1365 {
1366         uint32_t tmp;
1367         int i, r = 0;
1368
1369         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1370                 if (adev->vcn.harvest_config & (1 << i))
1371                         continue;
1372                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1373                         r = vcn_v2_5_stop_dpg_mode(adev, i);
1374                         continue;
1375                 }
1376
1377                 /* wait for vcn idle */
1378                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1379                 if (r)
1380                         return r;
1381
1382                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1383                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1384                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1385                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1386                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1387                 if (r)
1388                         return r;
1389
1390                 /* block LMI UMC channel */
1391                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1392                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1393                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1394
1395                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1396                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1397                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1398                 if (r)
1399                         return r;
1400
1401                 /* block VCPU register access */
1402                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1403                         UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1404                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1405
1406                 /* reset VCPU */
1407                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1408                         UVD_VCPU_CNTL__BLK_RST_MASK,
1409                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1410
1411                 /* disable VCPU clock */
1412                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1413                         ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1414
1415                 /* clear status */
1416                 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1417
1418                 vcn_v2_5_enable_clock_gating(adev);
1419
1420                 /* enable register anti-hang mechanism */
1421                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),
1422                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
1423                         ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1424         }
1425
1426         if (adev->pm.dpm_enabled)
1427                 amdgpu_dpm_enable_uvd(adev, false);
1428
1429         return 0;
1430 }
1431
1432 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
1433                                 int inst_idx, struct dpg_pause_state *new_state)
1434 {
1435         struct amdgpu_ring *ring;
1436         uint32_t reg_data = 0;
1437         int ret_code = 0;
1438
1439         /* pause/unpause if state is changed */
1440         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1441                 DRM_DEBUG("dpg pause state changed %d -> %d",
1442                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1443                 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1444                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1445
1446                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1447                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1448                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1449
1450                         if (!ret_code) {
1451                                 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1452
1453                                 /* pause DPG */
1454                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1455                                 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1456
1457                                 /* wait for ACK */
1458                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1459                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1460                                            UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1461
1462                                 /* Stall DPG before WPTR/RPTR reset */
1463                                 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1464                                            UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1465                                            ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1466
1467                                 /* Restore */
1468                                 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1469                                 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1470                                 ring->wptr = 0;
1471                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1472                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1473                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1474                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1475                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1476                                 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1477
1478                                 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1479                                 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1480                                 ring->wptr = 0;
1481                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1482                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1483                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1484                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1485                                 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1486                                 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1487
1488                                 /* Unstall DPG */
1489                                 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1490                                            0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1491
1492                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1493                                            UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1494                         }
1495                 } else {
1496                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1497                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1498                         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1499                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1500                 }
1501                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1502         }
1503
1504         return 0;
1505 }
1506
1507 /**
1508  * vcn_v2_5_dec_ring_get_rptr - get read pointer
1509  *
1510  * @ring: amdgpu_ring pointer
1511  *
1512  * Returns the current hardware read pointer
1513  */
1514 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
1515 {
1516         struct amdgpu_device *adev = ring->adev;
1517
1518         return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1519 }
1520
1521 /**
1522  * vcn_v2_5_dec_ring_get_wptr - get write pointer
1523  *
1524  * @ring: amdgpu_ring pointer
1525  *
1526  * Returns the current hardware write pointer
1527  */
1528 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
1529 {
1530         struct amdgpu_device *adev = ring->adev;
1531
1532         if (ring->use_doorbell)
1533                 return *ring->wptr_cpu_addr;
1534         else
1535                 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1536 }
1537
1538 /**
1539  * vcn_v2_5_dec_ring_set_wptr - set write pointer
1540  *
1541  * @ring: amdgpu_ring pointer
1542  *
1543  * Commits the write pointer to the hardware
1544  */
1545 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
1546 {
1547         struct amdgpu_device *adev = ring->adev;
1548
1549         if (ring->use_doorbell) {
1550                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1551                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1552         } else {
1553                 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1554         }
1555 }
1556
1557 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
1558         .type = AMDGPU_RING_TYPE_VCN_DEC,
1559         .align_mask = 0xf,
1560         .secure_submission_supported = true,
1561         .vmhub = AMDGPU_MMHUB_1,
1562         .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1563         .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1564         .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1565         .emit_frame_size =
1566                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1567                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1568                 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1569                 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1570                 6,
1571         .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1572         .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1573         .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1574         .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1575         .test_ring = vcn_v2_0_dec_ring_test_ring,
1576         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1577         .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1578         .insert_start = vcn_v2_0_dec_ring_insert_start,
1579         .insert_end = vcn_v2_0_dec_ring_insert_end,
1580         .pad_ib = amdgpu_ring_generic_pad_ib,
1581         .begin_use = amdgpu_vcn_ring_begin_use,
1582         .end_use = amdgpu_vcn_ring_end_use,
1583         .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1584         .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1585         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1586 };
1587
1588 static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = {
1589         .type = AMDGPU_RING_TYPE_VCN_DEC,
1590         .align_mask = 0xf,
1591         .secure_submission_supported = true,
1592         .vmhub = AMDGPU_MMHUB_0,
1593         .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1594         .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1595         .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1596         .emit_frame_size =
1597                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1598                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1599                 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1600                 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1601                 6,
1602         .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1603         .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1604         .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1605         .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1606         .test_ring = vcn_v2_0_dec_ring_test_ring,
1607         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1608         .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1609         .insert_start = vcn_v2_0_dec_ring_insert_start,
1610         .insert_end = vcn_v2_0_dec_ring_insert_end,
1611         .pad_ib = amdgpu_ring_generic_pad_ib,
1612         .begin_use = amdgpu_vcn_ring_begin_use,
1613         .end_use = amdgpu_vcn_ring_end_use,
1614         .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1615         .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1616         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1617 };
1618
1619 /**
1620  * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
1621  *
1622  * @ring: amdgpu_ring pointer
1623  *
1624  * Returns the current hardware enc read pointer
1625  */
1626 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
1627 {
1628         struct amdgpu_device *adev = ring->adev;
1629
1630         if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1631                 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1632         else
1633                 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1634 }
1635
1636 /**
1637  * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
1638  *
1639  * @ring: amdgpu_ring pointer
1640  *
1641  * Returns the current hardware enc write pointer
1642  */
1643 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
1644 {
1645         struct amdgpu_device *adev = ring->adev;
1646
1647         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1648                 if (ring->use_doorbell)
1649                         return *ring->wptr_cpu_addr;
1650                 else
1651                         return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
1652         } else {
1653                 if (ring->use_doorbell)
1654                         return *ring->wptr_cpu_addr;
1655                 else
1656                         return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
1657         }
1658 }
1659
1660 /**
1661  * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
1662  *
1663  * @ring: amdgpu_ring pointer
1664  *
1665  * Commits the enc write pointer to the hardware
1666  */
1667 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
1668 {
1669         struct amdgpu_device *adev = ring->adev;
1670
1671         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1672                 if (ring->use_doorbell) {
1673                         *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1674                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1675                 } else {
1676                         WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1677                 }
1678         } else {
1679                 if (ring->use_doorbell) {
1680                         *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1681                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1682                 } else {
1683                         WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1684                 }
1685         }
1686 }
1687
1688 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
1689         .type = AMDGPU_RING_TYPE_VCN_ENC,
1690         .align_mask = 0x3f,
1691         .nop = VCN_ENC_CMD_NO_OP,
1692         .vmhub = AMDGPU_MMHUB_1,
1693         .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1694         .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1695         .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1696         .emit_frame_size =
1697                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1698                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1699                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1700                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1701                 1, /* vcn_v2_0_enc_ring_insert_end */
1702         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1703         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1704         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1705         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1706         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1707         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1708         .insert_nop = amdgpu_ring_insert_nop,
1709         .insert_end = vcn_v2_0_enc_ring_insert_end,
1710         .pad_ib = amdgpu_ring_generic_pad_ib,
1711         .begin_use = amdgpu_vcn_ring_begin_use,
1712         .end_use = amdgpu_vcn_ring_end_use,
1713         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1714         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1715         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1716 };
1717
1718 static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = {
1719         .type = AMDGPU_RING_TYPE_VCN_ENC,
1720         .align_mask = 0x3f,
1721         .nop = VCN_ENC_CMD_NO_OP,
1722         .vmhub = AMDGPU_MMHUB_0,
1723         .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1724         .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1725         .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1726         .emit_frame_size =
1727                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1728                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1729                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1730                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1731                 1, /* vcn_v2_0_enc_ring_insert_end */
1732         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1733         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1734         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1735         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1736         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1737         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1738         .insert_nop = amdgpu_ring_insert_nop,
1739         .insert_end = vcn_v2_0_enc_ring_insert_end,
1740         .pad_ib = amdgpu_ring_generic_pad_ib,
1741         .begin_use = amdgpu_vcn_ring_begin_use,
1742         .end_use = amdgpu_vcn_ring_end_use,
1743         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1744         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1745         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1746 };
1747
1748 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
1749 {
1750         int i;
1751
1752         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1753                 if (adev->vcn.harvest_config & (1 << i))
1754                         continue;
1755                 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
1756                         adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
1757                 else /* CHIP_ALDEBARAN */
1758                         adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
1759                 adev->vcn.inst[i].ring_dec.me = i;
1760                 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
1761         }
1762 }
1763
1764 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
1765 {
1766         int i, j;
1767
1768         for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
1769                 if (adev->vcn.harvest_config & (1 << j))
1770                         continue;
1771                 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1772                         if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
1773                                 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
1774                         else /* CHIP_ALDEBARAN */
1775                                 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
1776                         adev->vcn.inst[j].ring_enc[i].me = j;
1777                 }
1778                 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);
1779         }
1780 }
1781
1782 static bool vcn_v2_5_is_idle(void *handle)
1783 {
1784         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1785         int i, ret = 1;
1786
1787         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1788                 if (adev->vcn.harvest_config & (1 << i))
1789                         continue;
1790                 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
1791         }
1792
1793         return ret;
1794 }
1795
1796 static int vcn_v2_5_wait_for_idle(void *handle)
1797 {
1798         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1799         int i, ret = 0;
1800
1801         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1802                 if (adev->vcn.harvest_config & (1 << i))
1803                         continue;
1804                 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
1805                         UVD_STATUS__IDLE);
1806                 if (ret)
1807                         return ret;
1808         }
1809
1810         return ret;
1811 }
1812
1813 static int vcn_v2_5_set_clockgating_state(void *handle,
1814                                           enum amd_clockgating_state state)
1815 {
1816         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1817         bool enable = (state == AMD_CG_STATE_GATE);
1818
1819         if (amdgpu_sriov_vf(adev))
1820                 return 0;
1821
1822         if (enable) {
1823                 if (!vcn_v2_5_is_idle(handle))
1824                         return -EBUSY;
1825                 vcn_v2_5_enable_clock_gating(adev);
1826         } else {
1827                 vcn_v2_5_disable_clock_gating(adev);
1828         }
1829
1830         return 0;
1831 }
1832
1833 static int vcn_v2_5_set_powergating_state(void *handle,
1834                                           enum amd_powergating_state state)
1835 {
1836         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1837         int ret;
1838
1839         if (amdgpu_sriov_vf(adev))
1840                 return 0;
1841
1842         if(state == adev->vcn.cur_state)
1843                 return 0;
1844
1845         if (state == AMD_PG_STATE_GATE)
1846                 ret = vcn_v2_5_stop(adev);
1847         else
1848                 ret = vcn_v2_5_start(adev);
1849
1850         if(!ret)
1851                 adev->vcn.cur_state = state;
1852
1853         return ret;
1854 }
1855
1856 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
1857                                         struct amdgpu_irq_src *source,
1858                                         unsigned type,
1859                                         enum amdgpu_interrupt_state state)
1860 {
1861         return 0;
1862 }
1863
1864 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
1865                                       struct amdgpu_irq_src *source,
1866                                       struct amdgpu_iv_entry *entry)
1867 {
1868         uint32_t ip_instance;
1869
1870         switch (entry->client_id) {
1871         case SOC15_IH_CLIENTID_VCN:
1872                 ip_instance = 0;
1873                 break;
1874         case SOC15_IH_CLIENTID_VCN1:
1875                 ip_instance = 1;
1876                 break;
1877         default:
1878                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1879                 return 0;
1880         }
1881
1882         DRM_DEBUG("IH: VCN TRAP\n");
1883
1884         switch (entry->src_id) {
1885         case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1886                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
1887                 break;
1888         case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1889                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1890                 break;
1891         case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1892                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
1893                 break;
1894         case VCN_2_6__SRCID_UVD_POISON:
1895                 amdgpu_vcn_process_poison_irq(adev, source, entry);
1896                 break;
1897         default:
1898                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1899                           entry->src_id, entry->src_data[0]);
1900                 break;
1901         }
1902
1903         return 0;
1904 }
1905
1906 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
1907         .set = vcn_v2_5_set_interrupt_state,
1908         .process = vcn_v2_5_process_interrupt,
1909 };
1910
1911 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
1912 {
1913         int i;
1914
1915         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1916                 if (adev->vcn.harvest_config & (1 << i))
1917                         continue;
1918                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1919                 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
1920         }
1921 }
1922
1923 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
1924         .name = "vcn_v2_5",
1925         .early_init = vcn_v2_5_early_init,
1926         .late_init = NULL,
1927         .sw_init = vcn_v2_5_sw_init,
1928         .sw_fini = vcn_v2_5_sw_fini,
1929         .hw_init = vcn_v2_5_hw_init,
1930         .hw_fini = vcn_v2_5_hw_fini,
1931         .suspend = vcn_v2_5_suspend,
1932         .resume = vcn_v2_5_resume,
1933         .is_idle = vcn_v2_5_is_idle,
1934         .wait_for_idle = vcn_v2_5_wait_for_idle,
1935         .check_soft_reset = NULL,
1936         .pre_soft_reset = NULL,
1937         .soft_reset = NULL,
1938         .post_soft_reset = NULL,
1939         .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1940         .set_powergating_state = vcn_v2_5_set_powergating_state,
1941 };
1942
1943 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
1944         .name = "vcn_v2_6",
1945         .early_init = vcn_v2_5_early_init,
1946         .late_init = NULL,
1947         .sw_init = vcn_v2_5_sw_init,
1948         .sw_fini = vcn_v2_5_sw_fini,
1949         .hw_init = vcn_v2_5_hw_init,
1950         .hw_fini = vcn_v2_5_hw_fini,
1951         .suspend = vcn_v2_5_suspend,
1952         .resume = vcn_v2_5_resume,
1953         .is_idle = vcn_v2_5_is_idle,
1954         .wait_for_idle = vcn_v2_5_wait_for_idle,
1955         .check_soft_reset = NULL,
1956         .pre_soft_reset = NULL,
1957         .soft_reset = NULL,
1958         .post_soft_reset = NULL,
1959         .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1960         .set_powergating_state = vcn_v2_5_set_powergating_state,
1961 };
1962
1963 const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
1964 {
1965                 .type = AMD_IP_BLOCK_TYPE_VCN,
1966                 .major = 2,
1967                 .minor = 5,
1968                 .rev = 0,
1969                 .funcs = &vcn_v2_5_ip_funcs,
1970 };
1971
1972 const struct amdgpu_ip_block_version vcn_v2_6_ip_block =
1973 {
1974                 .type = AMD_IP_BLOCK_TYPE_VCN,
1975                 .major = 2,
1976                 .minor = 6,
1977                 .rev = 0,
1978                 .funcs = &vcn_v2_6_ip_funcs,
1979 };
1980
1981 static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
1982                         uint32_t instance, uint32_t sub_block)
1983 {
1984         uint32_t poison_stat = 0, reg_value = 0;
1985
1986         switch (sub_block) {
1987         case AMDGPU_VCN_V2_6_VCPU_VCODEC:
1988                 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS);
1989                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
1990                 break;
1991         default:
1992                 break;
1993         }
1994
1995         if (poison_stat)
1996                 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
1997                         instance, sub_block);
1998
1999         return poison_stat;
2000 }
2001
2002 static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev)
2003 {
2004         uint32_t inst, sub;
2005         uint32_t poison_stat = 0;
2006
2007         for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
2008                 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++)
2009                         poison_stat +=
2010                         vcn_v2_6_query_poison_by_instance(adev, inst, sub);
2011
2012         return !!poison_stat;
2013 }
2014
2015 const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = {
2016         .query_poison_status = vcn_v2_6_query_poison_status,
2017 };
2018
2019 static struct amdgpu_vcn_ras vcn_v2_6_ras = {
2020         .ras_block = {
2021                 .hw_ops = &vcn_v2_6_ras_hw_ops,
2022         },
2023 };
2024
2025 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev)
2026 {
2027         switch (adev->ip_versions[VCN_HWIP][0]) {
2028         case IP_VERSION(2, 6, 0):
2029                 adev->vcn.ras = &vcn_v2_6_ras;
2030                 break;
2031         default:
2032                 break;
2033         }
2034
2035         amdgpu_vcn_set_ras_funcs(adev);
2036 }