drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include "amdgpu.h"
  37 #include "amdgpu_trace.h"
  38
  39
  40 int amdgpu_ttm_init(struct amdgpu_device *adev);
  41 void amdgpu_ttm_fini(struct amdgpu_device *adev);
  42
  43 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
  44                                                 struct ttm_mem_reg * mem)
  45 {
  46         u64 ret = 0;
  47         if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) {
  48                 ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) >
  49                            adev->mc.visible_vram_size ?
  50                            adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT):
  51                            mem->size;
  52         }
  53         return ret;
  54 }
  55
  56 static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
  57                        struct ttm_mem_reg *old_mem,
  58                        struct ttm_mem_reg *new_mem)
  59 {
  60         u64 vis_size;
  61         if (!adev)
  62                 return;
  63
  64         if (new_mem) {
  65                 switch (new_mem->mem_type) {
  66                 case TTM_PL_TT:
  67                         atomic64_add(new_mem->size, &adev->gtt_usage);
  68                         break;
  69                 case TTM_PL_VRAM:
  70                         atomic64_add(new_mem->size, &adev->vram_usage);
  71                         vis_size = amdgpu_get_vis_part_size(adev, new_mem);
  72                         atomic64_add(vis_size, &adev->vram_vis_usage);
  73                         break;
  74                 }
  75         }
  76
  77         if (old_mem) {
  78                 switch (old_mem->mem_type) {
  79                 case TTM_PL_TT:
  80                         atomic64_sub(old_mem->size, &adev->gtt_usage);
  81                         break;
  82                 case TTM_PL_VRAM:
  83                         atomic64_sub(old_mem->size, &adev->vram_usage);
  84                         vis_size = amdgpu_get_vis_part_size(adev, old_mem);
  85                         atomic64_sub(vis_size, &adev->vram_vis_usage);
  86                         break;
  87                 }
  88         }
  89 }
  90
  91 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  92 {
  93         struct amdgpu_bo *bo;
  94
  95         bo = container_of(tbo, struct amdgpu_bo, tbo);
  96
  97         amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
  98         amdgpu_mn_unregister(bo);
  99
 100         mutex_lock(&bo->adev->gem.mutex);
 101         list_del_init(&bo->list);
 102         mutex_unlock(&bo->adev->gem.mutex);
 103         drm_gem_object_release(&bo->gem_base);
 104         kfree(bo->metadata);
 105         kfree(bo);
 106 }
 107
 108 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 109 {
 110         if (bo->destroy == &amdgpu_ttm_bo_destroy)
 111                 return true;
 112         return false;
 113 }
 114
 115 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
 116 {
 117         u32 c = 0, i;
 118         rbo->placement.placement = rbo->placements;
 119         rbo->placement.busy_placement = rbo->placements;
 120
 121         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 122                 if (rbo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
 123                         rbo->adev->mc.visible_vram_size < rbo->adev->mc.real_vram_size) {
 124                         rbo->placements[c].fpfn =
 125                                 rbo->adev->mc.visible_vram_size >> PAGE_SHIFT;
 126                         rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 127                                                                                  TTM_PL_FLAG_VRAM;
 128                 }
 129                 rbo->placements[c].fpfn = 0;
 130                 rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 131                                                                          TTM_PL_FLAG_VRAM;
 132         }
 133
 134         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 135                 if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
 136                         rbo->placements[c].fpfn = 0;
 137                         rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
 138                                                                                  TTM_PL_FLAG_UNCACHED;
 139                 } else {
 140                         rbo->placements[c].fpfn = 0;
 141                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
 142                 }
 143         }
 144
 145         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 146                 if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
 147                         rbo->placements[c].fpfn = 0;
 148                         rbo->placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM |
 149                                                                                  TTM_PL_FLAG_UNCACHED;
 150                 } else {
 151                         rbo->placements[c].fpfn = 0;
 152                         rbo->placements[c++].flags =  TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
 153                 }
 154         }
 155
 156         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 157                 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 158                                         AMDGPU_PL_FLAG_GDS;
 159         }
 160         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 161                 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 162                                         AMDGPU_PL_FLAG_GWS;
 163         }
 164         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 165                 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 166                                         AMDGPU_PL_FLAG_OA;
 167         }
 168
 169         if (!c) {
 170                 rbo->placements[c].fpfn = 0;
 171                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
 172                                         TTM_PL_FLAG_SYSTEM;
 173         }
 174         rbo->placement.num_placement = c;
 175         rbo->placement.num_busy_placement = c;
 176
 177         for (i = 0; i < c; i++) {
 178                 if ((rbo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 179                         (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 180                         !rbo->placements[i].fpfn)
 181                         rbo->placements[i].lpfn =
 182                                 rbo->adev->mc.visible_vram_size >> PAGE_SHIFT;
 183                 else
 184                         rbo->placements[i].lpfn = 0;
 185         }
 186 }
 187
 188 int amdgpu_bo_create(struct amdgpu_device *adev,
 189                      unsigned long size, int byte_align, bool kernel, u32 domain, u64 flags,
 190                      struct sg_table *sg, struct amdgpu_bo **bo_ptr)
 191 {
 192         struct amdgpu_bo *bo;
 193         enum ttm_bo_type type;
 194         unsigned long page_align;
 195         size_t acc_size;
 196         int r;
 197
 198         /* VI has a hw bug where VM PTEs have to be allocated in groups of 8.
 199          * do this as a temporary workaround
 200          */
 201         if (!(domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
 202                 if (adev->asic_type >= CHIP_TOPAZ) {
 203                         if (byte_align & 0x7fff)
 204                                 byte_align = ALIGN(byte_align, 0x8000);
 205                         if (size & 0x7fff)
 206                                 size = ALIGN(size, 0x8000);
 207                 }
 208         }
 209
 210         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 211         size = ALIGN(size, PAGE_SIZE);
 212
 213         if (kernel) {
 214                 type = ttm_bo_type_kernel;
 215         } else if (sg) {
 216                 type = ttm_bo_type_sg;
 217         } else {
 218                 type = ttm_bo_type_device;
 219         }
 220         *bo_ptr = NULL;
 221
 222         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 223                                        sizeof(struct amdgpu_bo));
 224
 225         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 226         if (bo == NULL)
 227                 return -ENOMEM;
 228         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 229         if (unlikely(r)) {
 230                 kfree(bo);
 231                 return r;
 232         }
 233         bo->adev = adev;
 234         INIT_LIST_HEAD(&bo->list);
 235         INIT_LIST_HEAD(&bo->va);
 236         bo->initial_domain = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 237                                        AMDGPU_GEM_DOMAIN_GTT |
 238                                        AMDGPU_GEM_DOMAIN_CPU |
 239                                        AMDGPU_GEM_DOMAIN_GDS |
 240                                        AMDGPU_GEM_DOMAIN_GWS |
 241                                        AMDGPU_GEM_DOMAIN_OA);
 242
 243         bo->flags = flags;
 244         amdgpu_ttm_placement_from_domain(bo, domain);
 245         /* Kernel allocation are uninterruptible */
 246         down_read(&adev->pm.mclk_lock);
 247         r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
 248                         &bo->placement, page_align, !kernel, NULL,
 249                         acc_size, sg, NULL, &amdgpu_ttm_bo_destroy);
 250         up_read(&adev->pm.mclk_lock);
 251         if (unlikely(r != 0)) {
 252                 return r;
 253         }
 254         *bo_ptr = bo;
 255
 256         trace_amdgpu_bo_create(bo);
 257
 258         return 0;
 259 }
 260
 261 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 262 {
 263         bool is_iomem;
 264         int r;
 265
 266         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 267                 return -EPERM;
 268
 269         if (bo->kptr) {
 270                 if (ptr) {
 271                         *ptr = bo->kptr;
 272                 }
 273                 return 0;
 274         }
 275         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 276         if (r) {
 277                 return r;
 278         }
 279         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 280         if (ptr) {
 281                 *ptr = bo->kptr;
 282         }
 283         return 0;
 284 }
 285
 286 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 287 {
 288         if (bo->kptr == NULL)
 289                 return;
 290         bo->kptr = NULL;
 291         ttm_bo_kunmap(&bo->kmap);
 292 }
 293
 294 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 295 {
 296         if (bo == NULL)
 297                 return NULL;
 298
 299         ttm_bo_reference(&bo->tbo);
 300         return bo;
 301 }
 302
 303 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 304 {
 305         struct ttm_buffer_object *tbo;
 306
 307         if ((*bo) == NULL)
 308                 return;
 309
 310         tbo = &((*bo)->tbo);
 311         ttm_bo_unref(&tbo);
 312         if (tbo == NULL)
 313                 *bo = NULL;
 314 }
 315
 316 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 max_offset,
 317                              u64 *gpu_addr)
 318 {
 319         int r, i;
 320
 321         if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm))
 322                 return -EPERM;
 323
 324         if (bo->pin_count) {
 325                 bo->pin_count++;
 326                 if (gpu_addr)
 327                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 328
 329                 if (max_offset != 0) {
 330                         u64 domain_start;
 331
 332                         if (domain == AMDGPU_GEM_DOMAIN_VRAM)
 333                                 domain_start = bo->adev->mc.vram_start;
 334                         else
 335                                 domain_start = bo->adev->mc.gtt_start;
 336                         WARN_ON_ONCE(max_offset <
 337                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 338                 }
 339
 340                 return 0;
 341         }
 342         amdgpu_ttm_placement_from_domain(bo, domain);
 343         for (i = 0; i < bo->placement.num_placement; i++) {
 344                 /* force to pin into visible video ram */
 345                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 346                         !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
 347                         (!max_offset || max_offset > bo->adev->mc.visible_vram_size))
 348                         bo->placements[i].lpfn =
 349                                 bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
 350                 else
 351                         bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
 352
 353                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 354         }
 355
 356         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 357         if (likely(r == 0)) {
 358                 bo->pin_count = 1;
 359                 if (gpu_addr != NULL)
 360                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 361                 if (domain == AMDGPU_GEM_DOMAIN_VRAM)
 362                         bo->adev->vram_pin_size += amdgpu_bo_size(bo);
 363                 else
 364                         bo->adev->gart_pin_size += amdgpu_bo_size(bo);
 365         } else {
 366                 dev_err(bo->adev->dev, "%p pin failed\n", bo);
 367         }
 368         return r;
 369 }
 370
 371 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 372 {
 373         return amdgpu_bo_pin_restricted(bo, domain, 0, gpu_addr);
 374 }
 375
 376 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 377 {
 378         int r, i;
 379
 380         if (!bo->pin_count) {
 381                 dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
 382                 return 0;
 383         }
 384         bo->pin_count--;
 385         if (bo->pin_count)
 386                 return 0;
 387         for (i = 0; i < bo->placement.num_placement; i++) {
 388                 bo->placements[i].lpfn = 0;
 389                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 390         }
 391         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 392         if (likely(r == 0)) {
 393                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 394                         bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
 395                 else
 396                         bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
 397         } else {
 398                 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
 399         }
 400         return r;
 401 }
 402
 403 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 404 {
 405         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 406         if (0 && (adev->flags & AMDGPU_IS_APU)) {
 407                 /* Useless to evict on IGP chips */
 408                 return 0;
 409         }
 410         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 411 }
 412
 413 void amdgpu_bo_force_delete(struct amdgpu_device *adev)
 414 {
 415         struct amdgpu_bo *bo, *n;
 416
 417         if (list_empty(&adev->gem.objects)) {
 418                 return;
 419         }
 420         dev_err(adev->dev, "Userspace still has active objects !\n");
 421         list_for_each_entry_safe(bo, n, &adev->gem.objects, list) {
 422                 mutex_lock(&adev->ddev->struct_mutex);
 423                 dev_err(adev->dev, "%p %p %lu %lu force free\n",
 424                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 425                         *((unsigned long *)&bo->gem_base.refcount));
 426                 mutex_lock(&bo->adev->gem.mutex);
 427                 list_del_init(&bo->list);
 428                 mutex_unlock(&bo->adev->gem.mutex);
 429                 /* this should unref the ttm bo */
 430                 drm_gem_object_unreference(&bo->gem_base);
 431                 mutex_unlock(&adev->ddev->struct_mutex);
 432         }
 433 }
 434
 435 int amdgpu_bo_init(struct amdgpu_device *adev)
 436 {
 437         /* Add an MTRR for the VRAM */
 438         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 439                                               adev->mc.aper_size);
 440         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 441                 adev->mc.mc_vram_size >> 20,
 442                 (unsigned long long)adev->mc.aper_size >> 20);
 443         DRM_INFO("RAM width %dbits DDR\n",
 444                         adev->mc.vram_width);
 445         return amdgpu_ttm_init(adev);
 446 }
 447
 448 void amdgpu_bo_fini(struct amdgpu_device *adev)
 449 {
 450         amdgpu_ttm_fini(adev);
 451         arch_phys_wc_del(adev->mc.vram_mtrr);
 452 }
 453
 454 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 455                              struct vm_area_struct *vma)
 456 {
 457         return ttm_fbdev_mmap(vma, &bo->tbo);
 458 }
 459
 460 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 461 {
 462         unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 463
 464         bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) & AMDGPU_TILING_EG_BANKW_MASK;
 465         bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) & AMDGPU_TILING_EG_BANKH_MASK;
 466         mtaspect = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK;
 467         tilesplit = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_TILE_SPLIT_MASK;
 468         stilesplit = (tiling_flags >> AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 469         switch (bankw) {
 470         case 0:
 471         case 1:
 472         case 2:
 473         case 4:
 474         case 8:
 475                 break;
 476         default:
 477                 return -EINVAL;
 478         }
 479         switch (bankh) {
 480         case 0:
 481         case 1:
 482         case 2:
 483         case 4:
 484         case 8:
 485                 break;
 486         default:
 487                 return -EINVAL;
 488         }
 489         switch (mtaspect) {
 490         case 0:
 491         case 1:
 492         case 2:
 493         case 4:
 494         case 8:
 495                 break;
 496         default:
 497                 return -EINVAL;
 498         }
 499         if (tilesplit > 6) {
 500                 return -EINVAL;
 501         }
 502         if (stilesplit > 6) {
 503                 return -EINVAL;
 504         }
 505
 506         bo->tiling_flags = tiling_flags;
 507         return 0;
 508 }
 509
 510 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 511 {
 512         lockdep_assert_held(&bo->tbo.resv->lock.base);
 513
 514         if (tiling_flags)
 515                 *tiling_flags = bo->tiling_flags;
 516 }
 517
 518 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 519                             uint32_t metadata_size, uint64_t flags)
 520 {
 521         void *buffer;
 522
 523         if (!metadata_size) {
 524                 if (bo->metadata_size) {
 525                         kfree(bo->metadata);
 526                         bo->metadata_size = 0;
 527                 }
 528                 return 0;
 529         }
 530
 531         if (metadata == NULL)
 532                 return -EINVAL;
 533
 534         buffer = kzalloc(metadata_size, GFP_KERNEL);
 535         if (buffer == NULL)
 536                 return -ENOMEM;
 537
 538         memcpy(buffer, metadata, metadata_size);
 539
 540         kfree(bo->metadata);
 541         bo->metadata_flags = flags;
 542         bo->metadata = buffer;
 543         bo->metadata_size = metadata_size;
 544
 545         return 0;
 546 }
 547
 548 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 549                            size_t buffer_size, uint32_t *metadata_size,
 550                            uint64_t *flags)
 551 {
 552         if (!buffer && !metadata_size)
 553                 return -EINVAL;
 554
 555         if (buffer) {
 556                 if (buffer_size < bo->metadata_size)
 557                         return -EINVAL;
 558
 559                 if (bo->metadata_size)
 560                         memcpy(buffer, bo->metadata, bo->metadata_size);
 561         }
 562
 563         if (metadata_size)
 564                 *metadata_size = bo->metadata_size;
 565         if (flags)
 566                 *flags = bo->metadata_flags;
 567
 568         return 0;
 569 }
 570
 571 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 572                            struct ttm_mem_reg *new_mem)
 573 {
 574         struct amdgpu_bo *rbo;
 575
 576         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 577                 return;
 578
 579         rbo = container_of(bo, struct amdgpu_bo, tbo);
 580         amdgpu_vm_bo_invalidate(rbo->adev, rbo);
 581
 582         /* update statistics */
 583         if (!new_mem)
 584                 return;
 585
 586         /* move_notify is called before move happens */
 587         amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
 588 }
 589
 590 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 591 {
 592         struct amdgpu_device *adev;
 593         struct amdgpu_bo *rbo;
 594         unsigned long offset, size;
 595         int r;
 596
 597         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 598                 return 0;
 599         rbo = container_of(bo, struct amdgpu_bo, tbo);
 600         adev = rbo->adev;
 601         if (bo->mem.mem_type == TTM_PL_VRAM) {
 602                 size = bo->mem.num_pages << PAGE_SHIFT;
 603                 offset = bo->mem.start << PAGE_SHIFT;
 604                 if ((offset + size) > adev->mc.visible_vram_size) {
 605                         /* hurrah the memory is not visible ! */
 606                         amdgpu_ttm_placement_from_domain(rbo, AMDGPU_GEM_DOMAIN_VRAM);
 607                         rbo->placements[0].lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
 608                         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 609                         if (unlikely(r != 0))
 610                                 return r;
 611                         offset = bo->mem.start << PAGE_SHIFT;
 612                         /* this should not happen */
 613                         if ((offset + size) > adev->mc.visible_vram_size)
 614                                 return -EINVAL;
 615                 }
 616         }
 617         return 0;
 618 }
 619
 620 /**
 621  * amdgpu_bo_fence - add fence to buffer object
 622  *
 623  * @bo: buffer object in question
 624  * @fence: fence to add
 625  * @shared: true if fence should be added shared
 626  *
 627  */
 628 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct amdgpu_fence *fence,
 629                      bool shared)
 630 {
 631         struct reservation_object *resv = bo->tbo.resv;
 632
 633         if (shared)
 634                 reservation_object_add_shared_fence(resv, &fence->base);
 635         else
 636                 reservation_object_add_excl_fence(resv, &fence->base);
 637 }