drivers/gpu/drm/amd/amdgpu/soc15_common.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __SOC15_COMMON_H__
  25 #define __SOC15_COMMON_H__
  26
  27 /* Register Access Macros */
  28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
  29
  30 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
  31         ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
  32          amdgpu_sriov_wreg(adev, reg, value, flag, hwip) : \
  33          WREG32(reg, value))
  34
  35 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
  36         ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
  37          amdgpu_sriov_rreg(adev, reg, flag, hwip) : \
  38          RREG32(reg))
  39
  40 #define WREG32_FIELD15(ip, idx, reg, field, val)        \
  41          __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,   \
  42                                 (__RREG32_SOC15_RLC__( \
  43                                         adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
  44                                         0, ip##_HWIP) & \
  45                                 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
  46                               0, ip##_HWIP)
  47
  48 #define WREG32_FIELD15_PREREG(ip, idx, reg_name, field, val)        \
  49         __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name,   \
  50                         (__RREG32_SOC15_RLC__( \
  51                                         adev->reg_offset[ip##_HWIP][idx][reg##reg_name##_BASE_IDX] + reg##reg_name, \
  52                                         0, ip##_HWIP) & \
  53                                         ~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \
  54                         0, ip##_HWIP)
  55
  56 #define RREG32_SOC15(ip, inst, reg) \
  57         __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
  58                          0, ip##_HWIP)
  59
  60 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)
  61
  62 #define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
  63
  64 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
  65         __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
  66                          AMDGPU_REGS_NO_KIQ, ip##_HWIP)
  67
  68 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
  69          __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_HWIP)
  70
  71 #define WREG32_SOC15(ip, inst, reg, value) \
  72          __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
  73                           value, 0, ip##_HWIP)
  74
  75 #define WREG32_SOC15_IP(ip, reg, value) \
  76          __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
  77
  78 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
  79          __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
  80
  81 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
  82         __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
  83                              value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
  84
  85 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
  86          __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
  87                           value, 0, ip##_HWIP)
  88
  89 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
  90 ({      int ret = 0;                                            \
  91         do {                                                    \
  92                 uint32_t old_ = 0;                              \
  93                 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
  94                 uint32_t loop = adev->usec_timeout;             \
  95                 ret = 0;                                        \
  96                 while ((tmp_ & (mask)) != (expected_value)) {   \
  97                         if (old_ != tmp_) {                     \
  98                                 loop = adev->usec_timeout;      \
  99                                 old_ = tmp_;                    \
 100                         } else                                  \
 101                                 udelay(1);                      \
 102                         tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
 103                         loop--;                                 \
 104                         if (!loop) {                            \
 105                                 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
 106                                           inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
 107                                 ret = -ETIMEDOUT;               \
 108                                 break;                          \
 109                         }                                       \
 110                 }                                               \
 111         } while (0);                                            \
 112         ret;                                                    \
 113 })
 114
 115 #define WREG32_RLC(reg, value) \
 116         __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
 117
 118 #define WREG32_RLC_EX(prefix, reg, value) \
 119         do {                                                    \
 120                 if (amdgpu_sriov_fullaccess(adev)) {    \
 121                         uint32_t i = 0; \
 122                         uint32_t retries = 50000;       \
 123                         uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0;       \
 124                         uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1;       \
 125                         uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT;      \
 126                         WREG32(r0, value);      \
 127                         WREG32(r1, (reg | 0x80000000)); \
 128                         WREG32(spare_int, 0x1); \
 129                         for (i = 0; i < retries; i++) { \
 130                                 u32 tmp = RREG32(r1);   \
 131                                 if (!(tmp & 0x80000000))        \
 132                                         break;  \
 133                                 udelay(10);     \
 134                         }       \
 135                         if (i >= retries)       \
 136                                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg);     \
 137                 } else {        \
 138                         WREG32(reg, value); \
 139                 }       \
 140         } while (0)
 141
 142 /* shadow the registers in the callback function */
 143 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
 144         __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP)
 145
 146 /* for GC only */
 147 #define RREG32_RLC(reg) \
 148         __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
 149
 150 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \
 151         __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
 152
 153 #define RREG32_RLC_NO_KIQ(reg, hwip) \
 154         __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
 155
 156 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
 157         do {                                                    \
 158                 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
 159                 if (amdgpu_sriov_fullaccess(adev)) {    \
 160                         uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2;       \
 161                         uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3;       \
 162                         uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL;   \
 163                         uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX;   \
 164                         if (target_reg == grbm_cntl) \
 165                                 WREG32(r2, value);      \
 166                         else if (target_reg == grbm_idx) \
 167                                 WREG32(r3, value);      \
 168                         WREG32(target_reg, value);      \
 169                 } else {        \
 170                         WREG32(target_reg, value); \
 171                 }       \
 172         } while (0)
 173
 174 #define RREG32_SOC15_RLC(ip, inst, reg) \
 175         __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP)
 176
 177 #define WREG32_SOC15_RLC(ip, inst, reg, value) \
 178         do {                                                    \
 179                 uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
 180                 __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \
 181         } while (0)
 182
 183 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \
 184         do {                                                    \
 185                         uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\
 186                         WREG32_RLC_EX(prefix, target_reg, value); \
 187         } while (0)
 188
 189 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val)   \
 190         __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
 191                              (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
 192                                                    AMDGPU_REGS_RLC, ip##_HWIP) & \
 193                               ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
 194                              AMDGPU_REGS_RLC, ip##_HWIP)
 195
 196 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
 197         __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP)
 198
 199 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
 200         __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP)
 201
 202 #endif