drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "gc/gc_10_1_0_offset.h"
  41 #include "gc/gc_10_1_0_sh_mask.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "amdgpu_vkms.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64 #include "smuio_v11_0.h"
  65 #include "smuio_v11_0_6.h"
  66
  67 static const struct amd_ip_funcs nv_common_ip_funcs;
  68
  69 /* Navi */
  70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  71 {
  72         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  73         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  74 };
  75
  76 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  77 {
  78         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  79         .codec_array = nv_video_codecs_encode_array,
  80 };
  81
  82 /* Navi1x */
  83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  84 {
  85         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
  86         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
  88         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
  89         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  90         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  91         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  92 };
  93
  94 static const struct amdgpu_video_codecs nv_video_codecs_decode =
  95 {
  96         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
  97         .codec_array = nv_video_codecs_decode_array,
  98 };
  99
 100 /* Sienna Cichlid */
 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =
 102 {
 103         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 104         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 105         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 111 };
 112
 113 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] =
 114 {
 115         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 116         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 117         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 118         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 119         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 120         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 121         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 122 };
 123
 124 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 =
 125 {
 126         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),
 127         .codec_array = sc_video_codecs_decode_array_vcn0,
 128 };
 129
 130 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =
 131 {
 132         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),
 133         .codec_array = sc_video_codecs_decode_array_vcn1,
 134 };
 135
 136 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 137 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 138 {
 139         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
 140         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
 141 };
 142
 143 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
 144 {
 145         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 146         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 147         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 148         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 149         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 150         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 151         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 152         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 153 };
 154
 155 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] =
 156 {
 157         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 158         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 159         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 160         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 161         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 162         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 163         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 164 };
 165
 166 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
 167 {
 168         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 169         .codec_array = sriov_sc_video_codecs_encode_array,
 170 };
 171
 172 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 =
 173 {
 174         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0),
 175         .codec_array = sriov_sc_video_codecs_decode_array_vcn0,
 176 };
 177
 178 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 =
 179 {
 180         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1),
 181         .codec_array = sriov_sc_video_codecs_decode_array_vcn1,
 182 };
 183
 184 /* Beige Goby*/
 185 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
 186         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 187         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 188         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 189 };
 190
 191 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
 192         .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
 193         .codec_array = bg_video_codecs_decode_array,
 194 };
 195
 196 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
 197         .codec_count = 0,
 198         .codec_array = NULL,
 199 };
 200
 201 /* Yellow Carp*/
 202 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
 203         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 204         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 205         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 206         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 207         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 208 };
 209
 210 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
 211         .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
 212         .codec_array = yc_video_codecs_decode_array,
 213 };
 214
 215 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 216                                  const struct amdgpu_video_codecs **codecs)
 217 {
 218         if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
 219                 return -EINVAL;
 220
 221         switch (adev->ip_versions[UVD_HWIP][0]) {
 222         case IP_VERSION(3, 0, 0):
 223         case IP_VERSION(3, 0, 64):
 224         case IP_VERSION(3, 0, 192):
 225                 if (amdgpu_sriov_vf(adev)) {
 226                         if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 227                                 if (encode)
 228                                         *codecs = &sriov_sc_video_codecs_encode;
 229                                 else
 230                                         *codecs = &sriov_sc_video_codecs_decode_vcn1;
 231                         } else {
 232                                 if (encode)
 233                                         *codecs = &sriov_sc_video_codecs_encode;
 234                                 else
 235                                         *codecs = &sriov_sc_video_codecs_decode_vcn0;
 236                         }
 237                 } else {
 238                         if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 239                                 if (encode)
 240                                         *codecs = &nv_video_codecs_encode;
 241                                 else
 242                                         *codecs = &sc_video_codecs_decode_vcn1;
 243                         } else {
 244                                 if (encode)
 245                                         *codecs = &nv_video_codecs_encode;
 246                                 else
 247                                         *codecs = &sc_video_codecs_decode_vcn0;
 248                         }
 249                 }
 250                 return 0;
 251         case IP_VERSION(3, 0, 16):
 252         case IP_VERSION(3, 0, 2):
 253                 if (encode)
 254                         *codecs = &nv_video_codecs_encode;
 255                 else
 256                         *codecs = &sc_video_codecs_decode_vcn0;
 257                 return 0;
 258         case IP_VERSION(3, 1, 1):
 259         case IP_VERSION(3, 1, 2):
 260                 if (encode)
 261                         *codecs = &nv_video_codecs_encode;
 262                 else
 263                         *codecs = &yc_video_codecs_decode;
 264                 return 0;
 265         case IP_VERSION(3, 0, 33):
 266                 if (encode)
 267                         *codecs = &bg_video_codecs_encode;
 268                 else
 269                         *codecs = &bg_video_codecs_decode;
 270                 return 0;
 271         case IP_VERSION(2, 0, 0):
 272         case IP_VERSION(2, 0, 2):
 273                 if (encode)
 274                         *codecs = &nv_video_codecs_encode;
 275                 else
 276                         *codecs = &nv_video_codecs_decode;
 277                 return 0;
 278         default:
 279                 return -EINVAL;
 280         }
 281 }
 282
 283 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 284 {
 285         unsigned long flags, address, data;
 286         u32 r;
 287
 288         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 289         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 290
 291         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 292         WREG32(address, (reg));
 293         r = RREG32(data);
 294         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 295         return r;
 296 }
 297
 298 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 299 {
 300         unsigned long flags, address, data;
 301
 302         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 303         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 304
 305         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 306         WREG32(address, (reg));
 307         WREG32(data, (v));
 308         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 309 }
 310
 311 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 312 {
 313         return adev->nbio.funcs->get_memsize(adev);
 314 }
 315
 316 static u32 nv_get_xclk(struct amdgpu_device *adev)
 317 {
 318         return adev->clock.spll.reference_freq;
 319 }
 320
 321
 322 void nv_grbm_select(struct amdgpu_device *adev,
 323                      u32 me, u32 pipe, u32 queue, u32 vmid)
 324 {
 325         u32 grbm_gfx_cntl = 0;
 326         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 327         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 328         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 329         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 330
 331         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 332 }
 333
 334 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 335 {
 336         /* todo */
 337 }
 338
 339 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 340 {
 341         /* todo */
 342         return false;
 343 }
 344
 345 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 346         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 347         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 348         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 349         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 350         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 351         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 352         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 353         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 354         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 355         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 356         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 357         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 358         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 359         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 360         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 361         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 362         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 363         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 364         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 365 };
 366
 367 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 368                                          u32 sh_num, u32 reg_offset)
 369 {
 370         uint32_t val;
 371
 372         mutex_lock(&adev->grbm_idx_mutex);
 373         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 374                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 375
 376         val = RREG32(reg_offset);
 377
 378         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 379                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 380         mutex_unlock(&adev->grbm_idx_mutex);
 381         return val;
 382 }
 383
 384 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 385                                       bool indexed, u32 se_num,
 386                                       u32 sh_num, u32 reg_offset)
 387 {
 388         if (indexed) {
 389                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 390         } else {
 391                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 392                         return adev->gfx.config.gb_addr_config;
 393                 return RREG32(reg_offset);
 394         }
 395 }
 396
 397 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 398                             u32 sh_num, u32 reg_offset, u32 *value)
 399 {
 400         uint32_t i;
 401         struct soc15_allowed_register_entry  *en;
 402
 403         *value = 0;
 404         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 405                 en = &nv_allowed_read_registers[i];
 406                 if (!adev->reg_offset[en->hwip][en->inst])
 407                         continue;
 408                 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 409                                         + en->reg_offset))
 410                         continue;
 411
 412                 *value = nv_get_register_value(adev,
 413                                                nv_allowed_read_registers[i].grbm_indexed,
 414                                                se_num, sh_num, reg_offset);
 415                 return 0;
 416         }
 417         return -EINVAL;
 418 }
 419
 420 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 421 {
 422         u32 i;
 423         int ret = 0;
 424
 425         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 426
 427         /* disable BM */
 428         pci_clear_master(adev->pdev);
 429
 430         amdgpu_device_cache_pci_state(adev->pdev);
 431
 432         ret = amdgpu_dpm_mode2_reset(adev);
 433         if (ret)
 434                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 435
 436         amdgpu_device_load_pci_state(adev->pdev);
 437
 438         /* wait for asic to come out of reset */
 439         for (i = 0; i < adev->usec_timeout; i++) {
 440                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 441
 442                 if (memsize != 0xffffffff)
 443                         break;
 444                 udelay(1);
 445         }
 446
 447         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 448
 449         return ret;
 450 }
 451
 452 static enum amd_reset_method
 453 nv_asic_reset_method(struct amdgpu_device *adev)
 454 {
 455         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 456             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 457             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 458             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 459                 return amdgpu_reset_method;
 460
 461         if (amdgpu_reset_method != -1)
 462                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 463                                   amdgpu_reset_method);
 464
 465         switch (adev->ip_versions[MP1_HWIP][0]) {
 466         case IP_VERSION(11, 5, 0):
 467         case IP_VERSION(13, 0, 1):
 468         case IP_VERSION(13, 0, 3):
 469         case IP_VERSION(13, 0, 5):
 470         case IP_VERSION(13, 0, 8):
 471                 return AMD_RESET_METHOD_MODE2;
 472         case IP_VERSION(11, 0, 7):
 473         case IP_VERSION(11, 0, 11):
 474         case IP_VERSION(11, 0, 12):
 475         case IP_VERSION(11, 0, 13):
 476                 return AMD_RESET_METHOD_MODE1;
 477         default:
 478                 if (amdgpu_dpm_is_baco_supported(adev))
 479                         return AMD_RESET_METHOD_BACO;
 480                 else
 481                         return AMD_RESET_METHOD_MODE1;
 482         }
 483 }
 484
 485 static int nv_asic_reset(struct amdgpu_device *adev)
 486 {
 487         int ret = 0;
 488
 489         switch (nv_asic_reset_method(adev)) {
 490         case AMD_RESET_METHOD_PCI:
 491                 dev_info(adev->dev, "PCI reset\n");
 492                 ret = amdgpu_device_pci_reset(adev);
 493                 break;
 494         case AMD_RESET_METHOD_BACO:
 495                 dev_info(adev->dev, "BACO reset\n");
 496                 ret = amdgpu_dpm_baco_reset(adev);
 497                 break;
 498         case AMD_RESET_METHOD_MODE2:
 499                 dev_info(adev->dev, "MODE2 reset\n");
 500                 ret = nv_asic_mode2_reset(adev);
 501                 break;
 502         default:
 503                 dev_info(adev->dev, "MODE1 reset\n");
 504                 ret = amdgpu_device_mode1_reset(adev);
 505                 break;
 506         }
 507
 508         return ret;
 509 }
 510
 511 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 512 {
 513         /* todo */
 514         return 0;
 515 }
 516
 517 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 518 {
 519         /* todo */
 520         return 0;
 521 }
 522
 523 static void nv_program_aspm(struct amdgpu_device *adev)
 524 {
 525         if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk())
 526                 return;
 527
 528         if (!(adev->flags & AMD_IS_APU) &&
 529             (adev->nbio.funcs->program_aspm))
 530                 adev->nbio.funcs->program_aspm(adev);
 531
 532 }
 533
 534 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 535                                         bool enable)
 536 {
 537         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 538         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 539 }
 540
 541 const struct amdgpu_ip_block_version nv_common_ip_block =
 542 {
 543         .type = AMD_IP_BLOCK_TYPE_COMMON,
 544         .major = 1,
 545         .minor = 0,
 546         .rev = 0,
 547         .funcs = &nv_common_ip_funcs,
 548 };
 549
 550 void nv_set_virt_ops(struct amdgpu_device *adev)
 551 {
 552         adev->virt.ops = &xgpu_nv_virt_ops;
 553 }
 554
 555 static bool nv_need_full_reset(struct amdgpu_device *adev)
 556 {
 557         return true;
 558 }
 559
 560 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 561 {
 562         u32 sol_reg;
 563
 564         if (adev->flags & AMD_IS_APU)
 565                 return false;
 566
 567         /* Check sOS sign of life register to confirm sys driver and sOS
 568          * are already been loaded.
 569          */
 570         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 571         if (sol_reg)
 572                 return true;
 573
 574         return false;
 575 }
 576
 577 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 578 {
 579
 580         /* TODO
 581          * dummy implement for pcie_replay_count sysfs interface
 582          * */
 583
 584         return 0;
 585 }
 586
 587 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 588 {
 589         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 590         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 591         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 592         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 593         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 594         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 595         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 596         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 597         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 598         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 599         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 600         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 601         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 602         adev->doorbell_index.gfx_userqueue_start =
 603                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
 604         adev->doorbell_index.gfx_userqueue_end =
 605                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
 606         adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
 607         adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
 608         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 609         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 610         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 611         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 612         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 613         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 614         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 615         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 616         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 617         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 618         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 619
 620         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 621         adev->doorbell_index.sdma_doorbell_range = 20;
 622 }
 623
 624 static void nv_pre_asic_init(struct amdgpu_device *adev)
 625 {
 626 }
 627
 628 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 629                                        bool enter)
 630 {
 631         if (enter)
 632                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 633         else
 634                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 635
 636         if (adev->gfx.funcs->update_perfmon_mgcg)
 637                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 638
 639         if (!(adev->flags & AMD_IS_APU) &&
 640             (adev->nbio.funcs->enable_aspm) &&
 641              amdgpu_device_should_use_aspm(adev))
 642                 adev->nbio.funcs->enable_aspm(adev, !enter);
 643
 644         return 0;
 645 }
 646
 647 static const struct amdgpu_asic_funcs nv_asic_funcs =
 648 {
 649         .read_disabled_bios = &nv_read_disabled_bios,
 650         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 651         .read_register = &nv_read_register,
 652         .reset = &nv_asic_reset,
 653         .reset_method = &nv_asic_reset_method,
 654         .set_vga_state = &nv_vga_set_state,
 655         .get_xclk = &nv_get_xclk,
 656         .set_uvd_clocks = &nv_set_uvd_clocks,
 657         .set_vce_clocks = &nv_set_vce_clocks,
 658         .get_config_memsize = &nv_get_config_memsize,
 659         .init_doorbell_index = &nv_init_doorbell_index,
 660         .need_full_reset = &nv_need_full_reset,
 661         .need_reset_on_init = &nv_need_reset_on_init,
 662         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 663         .supports_baco = &amdgpu_dpm_is_baco_supported,
 664         .pre_asic_init = &nv_pre_asic_init,
 665         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 666         .query_video_codecs = &nv_query_video_codecs,
 667 };
 668
 669 static int nv_common_early_init(void *handle)
 670 {
 671 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 672         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 673
 674         if (!amdgpu_sriov_vf(adev)) {
 675                 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 676                 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 677         }
 678         adev->smc_rreg = NULL;
 679         adev->smc_wreg = NULL;
 680         adev->pcie_rreg = &amdgpu_device_indirect_rreg;
 681         adev->pcie_wreg = &amdgpu_device_indirect_wreg;
 682         adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
 683         adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
 684         adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
 685         adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
 686
 687         /* TODO: will add them during VCN v2 implementation */
 688         adev->uvd_ctx_rreg = NULL;
 689         adev->uvd_ctx_wreg = NULL;
 690
 691         adev->didt_rreg = &nv_didt_rreg;
 692         adev->didt_wreg = &nv_didt_wreg;
 693
 694         adev->asic_funcs = &nv_asic_funcs;
 695
 696         adev->rev_id = amdgpu_device_get_rev_id(adev);
 697         adev->external_rev_id = 0xff;
 698         /* TODO: split the GC and PG flags based on the relevant IP version for which
 699          * they are relevant.
 700          */
 701         switch (adev->ip_versions[GC_HWIP][0]) {
 702         case IP_VERSION(10, 1, 10):
 703                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 704                         AMD_CG_SUPPORT_GFX_CGCG |
 705                         AMD_CG_SUPPORT_IH_CG |
 706                         AMD_CG_SUPPORT_HDP_MGCG |
 707                         AMD_CG_SUPPORT_HDP_LS |
 708                         AMD_CG_SUPPORT_SDMA_MGCG |
 709                         AMD_CG_SUPPORT_SDMA_LS |
 710                         AMD_CG_SUPPORT_MC_MGCG |
 711                         AMD_CG_SUPPORT_MC_LS |
 712                         AMD_CG_SUPPORT_ATHUB_MGCG |
 713                         AMD_CG_SUPPORT_ATHUB_LS |
 714                         AMD_CG_SUPPORT_VCN_MGCG |
 715                         AMD_CG_SUPPORT_JPEG_MGCG |
 716                         AMD_CG_SUPPORT_BIF_MGCG |
 717                         AMD_CG_SUPPORT_BIF_LS;
 718                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 719                         AMD_PG_SUPPORT_VCN_DPG |
 720                         AMD_PG_SUPPORT_JPEG |
 721                         AMD_PG_SUPPORT_ATHUB;
 722                 adev->external_rev_id = adev->rev_id + 0x1;
 723                 break;
 724         case IP_VERSION(10, 1, 1):
 725                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 726                         AMD_CG_SUPPORT_GFX_CGCG |
 727                         AMD_CG_SUPPORT_IH_CG |
 728                         AMD_CG_SUPPORT_HDP_MGCG |
 729                         AMD_CG_SUPPORT_HDP_LS |
 730                         AMD_CG_SUPPORT_SDMA_MGCG |
 731                         AMD_CG_SUPPORT_SDMA_LS |
 732                         AMD_CG_SUPPORT_MC_MGCG |
 733                         AMD_CG_SUPPORT_MC_LS |
 734                         AMD_CG_SUPPORT_ATHUB_MGCG |
 735                         AMD_CG_SUPPORT_ATHUB_LS |
 736                         AMD_CG_SUPPORT_VCN_MGCG |
 737                         AMD_CG_SUPPORT_JPEG_MGCG |
 738                         AMD_CG_SUPPORT_BIF_MGCG |
 739                         AMD_CG_SUPPORT_BIF_LS;
 740                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 741                         AMD_PG_SUPPORT_JPEG |
 742                         AMD_PG_SUPPORT_VCN_DPG;
 743                 adev->external_rev_id = adev->rev_id + 20;
 744                 break;
 745         case IP_VERSION(10, 1, 2):
 746                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 747                         AMD_CG_SUPPORT_GFX_MGLS |
 748                         AMD_CG_SUPPORT_GFX_CGCG |
 749                         AMD_CG_SUPPORT_GFX_CP_LS |
 750                         AMD_CG_SUPPORT_GFX_RLC_LS |
 751                         AMD_CG_SUPPORT_IH_CG |
 752                         AMD_CG_SUPPORT_HDP_MGCG |
 753                         AMD_CG_SUPPORT_HDP_LS |
 754                         AMD_CG_SUPPORT_SDMA_MGCG |
 755                         AMD_CG_SUPPORT_SDMA_LS |
 756                         AMD_CG_SUPPORT_MC_MGCG |
 757                         AMD_CG_SUPPORT_MC_LS |
 758                         AMD_CG_SUPPORT_ATHUB_MGCG |
 759                         AMD_CG_SUPPORT_ATHUB_LS |
 760                         AMD_CG_SUPPORT_VCN_MGCG |
 761                         AMD_CG_SUPPORT_JPEG_MGCG;
 762                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 763                         AMD_PG_SUPPORT_VCN_DPG |
 764                         AMD_PG_SUPPORT_JPEG |
 765                         AMD_PG_SUPPORT_ATHUB;
 766                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 767                  * as a consequence, the rev_id and external_rev_id are wrong.
 768                  * workaround it by hardcoding rev_id to 0 (default value).
 769                  */
 770                 if (amdgpu_sriov_vf(adev))
 771                         adev->rev_id = 0;
 772                 adev->external_rev_id = adev->rev_id + 0xa;
 773                 break;
 774         case IP_VERSION(10, 3, 0):
 775                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 776                         AMD_CG_SUPPORT_GFX_CGCG |
 777                         AMD_CG_SUPPORT_GFX_CGLS |
 778                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 779                         AMD_CG_SUPPORT_MC_MGCG |
 780                         AMD_CG_SUPPORT_VCN_MGCG |
 781                         AMD_CG_SUPPORT_JPEG_MGCG |
 782                         AMD_CG_SUPPORT_HDP_MGCG |
 783                         AMD_CG_SUPPORT_HDP_LS |
 784                         AMD_CG_SUPPORT_IH_CG |
 785                         AMD_CG_SUPPORT_MC_LS;
 786                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 787                         AMD_PG_SUPPORT_VCN_DPG |
 788                         AMD_PG_SUPPORT_JPEG |
 789                         AMD_PG_SUPPORT_ATHUB |
 790                         AMD_PG_SUPPORT_MMHUB;
 791                 if (amdgpu_sriov_vf(adev)) {
 792                         /* hypervisor control CG and PG enablement */
 793                         adev->cg_flags = 0;
 794                         adev->pg_flags = 0;
 795                 }
 796                 adev->external_rev_id = adev->rev_id + 0x28;
 797                 break;
 798         case IP_VERSION(10, 3, 2):
 799                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 800                         AMD_CG_SUPPORT_GFX_CGCG |
 801                         AMD_CG_SUPPORT_GFX_CGLS |
 802                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 803                         AMD_CG_SUPPORT_VCN_MGCG |
 804                         AMD_CG_SUPPORT_JPEG_MGCG |
 805                         AMD_CG_SUPPORT_MC_MGCG |
 806                         AMD_CG_SUPPORT_MC_LS |
 807                         AMD_CG_SUPPORT_HDP_MGCG |
 808                         AMD_CG_SUPPORT_HDP_LS |
 809                         AMD_CG_SUPPORT_IH_CG;
 810                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 811                         AMD_PG_SUPPORT_VCN_DPG |
 812                         AMD_PG_SUPPORT_JPEG |
 813                         AMD_PG_SUPPORT_ATHUB |
 814                         AMD_PG_SUPPORT_MMHUB;
 815                 adev->external_rev_id = adev->rev_id + 0x32;
 816                 break;
 817         case IP_VERSION(10, 3, 1):
 818                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 819                         AMD_CG_SUPPORT_GFX_MGLS |
 820                         AMD_CG_SUPPORT_GFX_CP_LS |
 821                         AMD_CG_SUPPORT_GFX_RLC_LS |
 822                         AMD_CG_SUPPORT_GFX_CGCG |
 823                         AMD_CG_SUPPORT_GFX_CGLS |
 824                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 825                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 826                         AMD_CG_SUPPORT_MC_MGCG |
 827                         AMD_CG_SUPPORT_MC_LS |
 828                         AMD_CG_SUPPORT_GFX_FGCG |
 829                         AMD_CG_SUPPORT_VCN_MGCG |
 830                         AMD_CG_SUPPORT_SDMA_MGCG |
 831                         AMD_CG_SUPPORT_SDMA_LS |
 832                         AMD_CG_SUPPORT_JPEG_MGCG;
 833                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 834                         AMD_PG_SUPPORT_VCN |
 835                         AMD_PG_SUPPORT_VCN_DPG |
 836                         AMD_PG_SUPPORT_JPEG;
 837                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
 838                         adev->external_rev_id = adev->rev_id + 0x01;
 839                 break;
 840         case IP_VERSION(10, 3, 4):
 841                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 842                         AMD_CG_SUPPORT_GFX_CGCG |
 843                         AMD_CG_SUPPORT_GFX_CGLS |
 844                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 845                         AMD_CG_SUPPORT_VCN_MGCG |
 846                         AMD_CG_SUPPORT_JPEG_MGCG |
 847                         AMD_CG_SUPPORT_MC_MGCG |
 848                         AMD_CG_SUPPORT_MC_LS |
 849                         AMD_CG_SUPPORT_HDP_MGCG |
 850                         AMD_CG_SUPPORT_HDP_LS |
 851                         AMD_CG_SUPPORT_IH_CG;
 852                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 853                         AMD_PG_SUPPORT_VCN_DPG |
 854                         AMD_PG_SUPPORT_JPEG |
 855                         AMD_PG_SUPPORT_ATHUB |
 856                         AMD_PG_SUPPORT_MMHUB;
 857                 adev->external_rev_id = adev->rev_id + 0x3c;
 858                 break;
 859         case IP_VERSION(10, 3, 5):
 860                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 861                         AMD_CG_SUPPORT_GFX_CGCG |
 862                         AMD_CG_SUPPORT_GFX_CGLS |
 863                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 864                         AMD_CG_SUPPORT_MC_MGCG |
 865                         AMD_CG_SUPPORT_MC_LS |
 866                         AMD_CG_SUPPORT_HDP_MGCG |
 867                         AMD_CG_SUPPORT_HDP_LS |
 868                         AMD_CG_SUPPORT_IH_CG |
 869                         AMD_CG_SUPPORT_VCN_MGCG;
 870                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 871                         AMD_PG_SUPPORT_VCN_DPG |
 872                         AMD_PG_SUPPORT_ATHUB |
 873                         AMD_PG_SUPPORT_MMHUB;
 874                 adev->external_rev_id = adev->rev_id + 0x46;
 875                 break;
 876         case IP_VERSION(10, 3, 3):
 877                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 878                         AMD_CG_SUPPORT_GFX_MGLS |
 879                         AMD_CG_SUPPORT_GFX_CGCG |
 880                         AMD_CG_SUPPORT_GFX_CGLS |
 881                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 882                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 883                         AMD_CG_SUPPORT_GFX_RLC_LS |
 884                         AMD_CG_SUPPORT_GFX_CP_LS |
 885                         AMD_CG_SUPPORT_GFX_FGCG |
 886                         AMD_CG_SUPPORT_MC_MGCG |
 887                         AMD_CG_SUPPORT_MC_LS |
 888                         AMD_CG_SUPPORT_SDMA_LS |
 889                         AMD_CG_SUPPORT_HDP_MGCG |
 890                         AMD_CG_SUPPORT_HDP_LS |
 891                         AMD_CG_SUPPORT_ATHUB_MGCG |
 892                         AMD_CG_SUPPORT_ATHUB_LS |
 893                         AMD_CG_SUPPORT_IH_CG |
 894                         AMD_CG_SUPPORT_VCN_MGCG |
 895                         AMD_CG_SUPPORT_JPEG_MGCG;
 896                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 897                         AMD_PG_SUPPORT_VCN |
 898                         AMD_PG_SUPPORT_VCN_DPG |
 899                         AMD_PG_SUPPORT_JPEG;
 900                 if (adev->pdev->device == 0x1681)
 901                         adev->external_rev_id = 0x20;
 902                 else
 903                         adev->external_rev_id = adev->rev_id + 0x01;
 904                 break;
 905         case IP_VERSION(10, 1, 3):
 906         case IP_VERSION(10, 1, 4):
 907                 adev->cg_flags = 0;
 908                 adev->pg_flags = 0;
 909                 adev->external_rev_id = adev->rev_id + 0x82;
 910                 break;
 911         case IP_VERSION(10, 3, 6):
 912                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 913                         AMD_CG_SUPPORT_GFX_MGLS |
 914                         AMD_CG_SUPPORT_GFX_CGCG |
 915                         AMD_CG_SUPPORT_GFX_CGLS |
 916                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 917                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 918                         AMD_CG_SUPPORT_GFX_RLC_LS |
 919                         AMD_CG_SUPPORT_GFX_CP_LS |
 920                         AMD_CG_SUPPORT_GFX_FGCG |
 921                         AMD_CG_SUPPORT_MC_MGCG |
 922                         AMD_CG_SUPPORT_MC_LS |
 923                         AMD_CG_SUPPORT_SDMA_LS |
 924                         AMD_CG_SUPPORT_HDP_MGCG |
 925                         AMD_CG_SUPPORT_HDP_LS |
 926                         AMD_CG_SUPPORT_ATHUB_MGCG |
 927                         AMD_CG_SUPPORT_ATHUB_LS |
 928                         AMD_CG_SUPPORT_IH_CG |
 929                         AMD_CG_SUPPORT_VCN_MGCG |
 930                         AMD_CG_SUPPORT_JPEG_MGCG;
 931                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 932                         AMD_PG_SUPPORT_VCN |
 933                         AMD_PG_SUPPORT_VCN_DPG |
 934                         AMD_PG_SUPPORT_JPEG;
 935                 adev->external_rev_id = adev->rev_id + 0x01;
 936                 break;
 937         case IP_VERSION(10, 3, 7):
 938                 adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
 939                         AMD_CG_SUPPORT_GFX_MGLS |
 940                         AMD_CG_SUPPORT_GFX_CGCG |
 941                         AMD_CG_SUPPORT_GFX_CGLS |
 942                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 943                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 944                         AMD_CG_SUPPORT_GFX_RLC_LS |
 945                         AMD_CG_SUPPORT_GFX_CP_LS |
 946                         AMD_CG_SUPPORT_GFX_FGCG |
 947                         AMD_CG_SUPPORT_MC_MGCG |
 948                         AMD_CG_SUPPORT_MC_LS |
 949                         AMD_CG_SUPPORT_SDMA_LS |
 950                         AMD_CG_SUPPORT_HDP_MGCG |
 951                         AMD_CG_SUPPORT_HDP_LS |
 952                         AMD_CG_SUPPORT_ATHUB_MGCG |
 953                         AMD_CG_SUPPORT_ATHUB_LS |
 954                         AMD_CG_SUPPORT_IH_CG |
 955                         AMD_CG_SUPPORT_VCN_MGCG |
 956                         AMD_CG_SUPPORT_JPEG_MGCG;
 957                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 958                         AMD_PG_SUPPORT_VCN_DPG |
 959                         AMD_PG_SUPPORT_JPEG |
 960                         AMD_PG_SUPPORT_GFX_PG;
 961                 adev->external_rev_id = adev->rev_id + 0x01;
 962                 break;
 963         default:
 964                 /* FIXME: not supported yet */
 965                 return -EINVAL;
 966         }
 967
 968         if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
 969                 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
 970                                     AMD_PG_SUPPORT_VCN_DPG |
 971                                     AMD_PG_SUPPORT_JPEG);
 972
 973         if (amdgpu_sriov_vf(adev)) {
 974                 amdgpu_virt_init_setting(adev);
 975                 xgpu_nv_mailbox_set_irq_funcs(adev);
 976         }
 977
 978         return 0;
 979 }
 980
 981 static int nv_common_late_init(void *handle)
 982 {
 983         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 984
 985         if (amdgpu_sriov_vf(adev)) {
 986                 xgpu_nv_mailbox_get_irq(adev);
 987                 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 988                         amdgpu_virt_update_sriov_video_codec(adev,
 989                                                              sriov_sc_video_codecs_encode_array,
 990                                                              ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 991                                                              sriov_sc_video_codecs_decode_array_vcn1,
 992                                                              ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
 993                 } else {
 994                         amdgpu_virt_update_sriov_video_codec(adev,
 995                                                              sriov_sc_video_codecs_encode_array,
 996                                                              ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 997                                                              sriov_sc_video_codecs_decode_array_vcn0,
 998                                                              ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0));
 999                 }
1000         }
1001
1002         return 0;
1003 }
1004
1005 static int nv_common_sw_init(void *handle)
1006 {
1007         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1008
1009         if (amdgpu_sriov_vf(adev))
1010                 xgpu_nv_mailbox_add_irq_id(adev);
1011
1012         return 0;
1013 }
1014
1015 static int nv_common_sw_fini(void *handle)
1016 {
1017         return 0;
1018 }
1019
1020 static int nv_common_hw_init(void *handle)
1021 {
1022         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1023
1024         if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1025                 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1026
1027         if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1028                 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1029
1030         /* enable aspm */
1031         nv_program_aspm(adev);
1032         /* setup nbio registers */
1033         adev->nbio.funcs->init_registers(adev);
1034         /* remap HDP registers to a hole in mmio space,
1035          * for the purpose of expose those registers
1036          * to process space
1037          */
1038         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1039                 adev->nbio.funcs->remap_hdp_registers(adev);
1040         /* enable the doorbell aperture */
1041         nv_enable_doorbell_aperture(adev, true);
1042
1043         return 0;
1044 }
1045
1046 static int nv_common_hw_fini(void *handle)
1047 {
1048         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1049
1050         /* disable the doorbell aperture */
1051         nv_enable_doorbell_aperture(adev, false);
1052
1053         return 0;
1054 }
1055
1056 static int nv_common_suspend(void *handle)
1057 {
1058         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1059
1060         return nv_common_hw_fini(adev);
1061 }
1062
1063 static int nv_common_resume(void *handle)
1064 {
1065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1066
1067         return nv_common_hw_init(adev);
1068 }
1069
1070 static bool nv_common_is_idle(void *handle)
1071 {
1072         return true;
1073 }
1074
1075 static int nv_common_wait_for_idle(void *handle)
1076 {
1077         return 0;
1078 }
1079
1080 static int nv_common_soft_reset(void *handle)
1081 {
1082         return 0;
1083 }
1084
1085 static int nv_common_set_clockgating_state(void *handle,
1086                                            enum amd_clockgating_state state)
1087 {
1088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1089
1090         if (amdgpu_sriov_vf(adev))
1091                 return 0;
1092
1093         switch (adev->ip_versions[NBIO_HWIP][0]) {
1094         case IP_VERSION(2, 3, 0):
1095         case IP_VERSION(2, 3, 1):
1096         case IP_VERSION(2, 3, 2):
1097         case IP_VERSION(3, 3, 0):
1098         case IP_VERSION(3, 3, 1):
1099         case IP_VERSION(3, 3, 2):
1100         case IP_VERSION(3, 3, 3):
1101                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1102                                 state == AMD_CG_STATE_GATE);
1103                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1104                                 state == AMD_CG_STATE_GATE);
1105                 adev->hdp.funcs->update_clock_gating(adev,
1106                                 state == AMD_CG_STATE_GATE);
1107                 adev->smuio.funcs->update_rom_clock_gating(adev,
1108                                 state == AMD_CG_STATE_GATE);
1109                 break;
1110         default:
1111                 break;
1112         }
1113         return 0;
1114 }
1115
1116 static int nv_common_set_powergating_state(void *handle,
1117                                            enum amd_powergating_state state)
1118 {
1119         /* TODO */
1120         return 0;
1121 }
1122
1123 static void nv_common_get_clockgating_state(void *handle, u64 *flags)
1124 {
1125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1126
1127         if (amdgpu_sriov_vf(adev))
1128                 *flags = 0;
1129
1130         adev->nbio.funcs->get_clockgating_state(adev, flags);
1131
1132         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1133
1134         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1135
1136         return;
1137 }
1138
1139 static const struct amd_ip_funcs nv_common_ip_funcs = {
1140         .name = "nv_common",
1141         .early_init = nv_common_early_init,
1142         .late_init = nv_common_late_init,
1143         .sw_init = nv_common_sw_init,
1144         .sw_fini = nv_common_sw_fini,
1145         .hw_init = nv_common_hw_init,
1146         .hw_fini = nv_common_hw_fini,
1147         .suspend = nv_common_suspend,
1148         .resume = nv_common_resume,
1149         .is_idle = nv_common_is_idle,
1150         .wait_for_idle = nv_common_wait_for_idle,
1151         .soft_reset = nv_common_soft_reset,
1152         .set_clockgating_state = nv_common_set_clockgating_state,
1153         .set_powergating_state = nv_common_set_powergating_state,
1154         .get_clockgating_state = nv_common_get_clockgating_state,
1155 };