drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "amdgpu_jpeg.h"
  26 #include "amdgpu_pm.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29 #include "jpeg_v2_0.h"
  30
  31 #include "vcn/vcn_3_0_0_offset.h"
  32 #include "vcn/vcn_3_0_0_sh_mask.h"
  33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  34
  35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET        0x401f
  36
  37 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  38 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  39 static int jpeg_v3_0_set_powergating_state(void *handle,
  40                                 enum amd_powergating_state state);
  41
  42 /**
  43  * jpeg_v3_0_early_init - set function pointers
  44  *
  45  * @handle: amdgpu_device pointer
  46  *
  47  * Set ring and irq function pointers
  48  */
  49 static int jpeg_v3_0_early_init(void *handle)
  50 {
  51         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  52
  53         u32 harvest;
  54
  55         switch (adev->ip_versions[UVD_HWIP][0]) {
  56         case IP_VERSION(3, 1, 1):
  57                 break;
  58         default:
  59                 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
  60                 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
  61                         return -ENOENT;
  62                 break;
  63         }
  64
  65         adev->jpeg.num_jpeg_inst = 1;
  66
  67         jpeg_v3_0_set_dec_ring_funcs(adev);
  68         jpeg_v3_0_set_irq_funcs(adev);
  69
  70         return 0;
  71 }
  72
  73 /**
  74  * jpeg_v3_0_sw_init - sw init for JPEG block
  75  *
  76  * @handle: amdgpu_device pointer
  77  *
  78  * Load firmware and sw initialization
  79  */
  80 static int jpeg_v3_0_sw_init(void *handle)
  81 {
  82         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  83         struct amdgpu_ring *ring;
  84         int r;
  85
  86         /* JPEG TRAP */
  87         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  88                 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
  89         if (r)
  90                 return r;
  91
  92         r = amdgpu_jpeg_sw_init(adev);
  93         if (r)
  94                 return r;
  95
  96         r = amdgpu_jpeg_resume(adev);
  97         if (r)
  98                 return r;
  99
 100         ring = &adev->jpeg.inst->ring_dec;
 101         ring->use_doorbell = true;
 102         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
 103         ring->vm_hub = AMDGPU_MMHUB_0;
 104         sprintf(ring->name, "jpeg_dec");
 105         r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
 106                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 107         if (r)
 108                 return r;
 109
 110         adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
 111         adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
 112
 113         return 0;
 114 }
 115
 116 /**
 117  * jpeg_v3_0_sw_fini - sw fini for JPEG block
 118  *
 119  * @handle: amdgpu_device pointer
 120  *
 121  * JPEG suspend and free up sw allocation
 122  */
 123 static int jpeg_v3_0_sw_fini(void *handle)
 124 {
 125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 126         int r;
 127
 128         r = amdgpu_jpeg_suspend(adev);
 129         if (r)
 130                 return r;
 131
 132         r = amdgpu_jpeg_sw_fini(adev);
 133
 134         return r;
 135 }
 136
 137 /**
 138  * jpeg_v3_0_hw_init - start and test JPEG block
 139  *
 140  * @handle: amdgpu_device pointer
 141  *
 142  */
 143 static int jpeg_v3_0_hw_init(void *handle)
 144 {
 145         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 146         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
 147         int r;
 148
 149         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 150                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
 151
 152         r = amdgpu_ring_test_helper(ring);
 153         if (r)
 154                 return r;
 155
 156         DRM_INFO("JPEG decode initialized successfully.\n");
 157
 158         return 0;
 159 }
 160
 161 /**
 162  * jpeg_v3_0_hw_fini - stop the hardware block
 163  *
 164  * @handle: amdgpu_device pointer
 165  *
 166  * Stop the JPEG block, mark ring as not ready any more
 167  */
 168 static int jpeg_v3_0_hw_fini(void *handle)
 169 {
 170         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 171
 172         cancel_delayed_work_sync(&adev->vcn.idle_work);
 173
 174         if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
 175               RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
 176                 jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 177
 178         return 0;
 179 }
 180
 181 /**
 182  * jpeg_v3_0_suspend - suspend JPEG block
 183  *
 184  * @handle: amdgpu_device pointer
 185  *
 186  * HW fini and suspend JPEG block
 187  */
 188 static int jpeg_v3_0_suspend(void *handle)
 189 {
 190         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 191         int r;
 192
 193         r = jpeg_v3_0_hw_fini(adev);
 194         if (r)
 195                 return r;
 196
 197         r = amdgpu_jpeg_suspend(adev);
 198
 199         return r;
 200 }
 201
 202 /**
 203  * jpeg_v3_0_resume - resume JPEG block
 204  *
 205  * @handle: amdgpu_device pointer
 206  *
 207  * Resume firmware and hw init JPEG block
 208  */
 209 static int jpeg_v3_0_resume(void *handle)
 210 {
 211         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 212         int r;
 213
 214         r = amdgpu_jpeg_resume(adev);
 215         if (r)
 216                 return r;
 217
 218         r = jpeg_v3_0_hw_init(adev);
 219
 220         return r;
 221 }
 222
 223 static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev)
 224 {
 225         uint32_t data = 0;
 226
 227         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
 228         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
 229                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 230         else
 231                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 232
 233         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 234         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 235         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 236
 237         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
 238         data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
 239                 | JPEG_CGC_GATE__JPEG2_DEC_MASK
 240                 | JPEG_CGC_GATE__JPEG_ENC_MASK
 241                 | JPEG_CGC_GATE__JMCIF_MASK
 242                 | JPEG_CGC_GATE__JRBBM_MASK);
 243         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 244
 245         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
 246         data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
 247                 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
 248                 | JPEG_CGC_CTRL__JMCIF_MODE_MASK
 249                 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
 250         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 251 }
 252
 253 static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev)
 254 {
 255         uint32_t data = 0;
 256
 257         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
 258         data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
 259                 |JPEG_CGC_GATE__JPEG2_DEC_MASK
 260                 |JPEG_CGC_GATE__JPEG_ENC_MASK
 261                 |JPEG_CGC_GATE__JMCIF_MASK
 262                 |JPEG_CGC_GATE__JRBBM_MASK);
 263         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 264 }
 265
 266 static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev)
 267 {
 268         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 269                 uint32_t data = 0;
 270                 int r = 0;
 271
 272                 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 273                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
 274
 275                 r = SOC15_WAIT_ON_RREG(JPEG, 0,
 276                         mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
 277                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
 278
 279                 if (r) {
 280                         DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
 281                         return r;
 282                 }
 283         }
 284
 285         /* disable anti hang mechanism */
 286         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
 287                 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 288
 289         /* keep the JPEG in static PG mode */
 290         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0,
 291                 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
 292
 293         return 0;
 294 }
 295
 296 static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev)
 297 {
 298         /* enable anti hang mechanism */
 299         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
 300                 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
 301                 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 302
 303         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 304                 uint32_t data = 0;
 305                 int r = 0;
 306
 307                 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 308                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
 309
 310                 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
 311                         (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
 312                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
 313
 314                 if (r) {
 315                         DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
 316                         return r;
 317                 }
 318         }
 319
 320         return 0;
 321 }
 322
 323 /**
 324  * jpeg_v3_0_start - start JPEG block
 325  *
 326  * @adev: amdgpu_device pointer
 327  *
 328  * Setup and start the JPEG block
 329  */
 330 static int jpeg_v3_0_start(struct amdgpu_device *adev)
 331 {
 332         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
 333         int r;
 334
 335         if (adev->pm.dpm_enabled)
 336                 amdgpu_dpm_enable_jpeg(adev, true);
 337
 338         /* disable power gating */
 339         r = jpeg_v3_0_disable_static_power_gating(adev);
 340         if (r)
 341                 return r;
 342
 343         /* JPEG disable CGC */
 344         jpeg_v3_0_disable_clock_gating(adev);
 345
 346         /* MJPEG global tiling registers */
 347         WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
 348                 adev->gfx.config.gb_addr_config);
 349         WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG,
 350                 adev->gfx.config.gb_addr_config);
 351
 352         /* enable JMI channel */
 353         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
 354                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 355
 356         /* enable System Interrupt for JRBC */
 357         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
 358                 JPEG_SYS_INT_EN__DJRBC_MASK,
 359                 ~JPEG_SYS_INT_EN__DJRBC_MASK);
 360
 361         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 362         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
 363         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
 364                 lower_32_bits(ring->gpu_addr));
 365         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
 366                 upper_32_bits(ring->gpu_addr));
 367         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
 368         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
 369         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
 370         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
 371         ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 372
 373         return 0;
 374 }
 375
 376 /**
 377  * jpeg_v3_0_stop - stop JPEG block
 378  *
 379  * @adev: amdgpu_device pointer
 380  *
 381  * stop the JPEG block
 382  */
 383 static int jpeg_v3_0_stop(struct amdgpu_device *adev)
 384 {
 385         int r;
 386
 387         /* reset JMI */
 388         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
 389                 UVD_JMI_CNTL__SOFT_RESET_MASK,
 390                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 391
 392         jpeg_v3_0_enable_clock_gating(adev);
 393
 394         /* enable power gating */
 395         r = jpeg_v3_0_enable_static_power_gating(adev);
 396         if (r)
 397                 return r;
 398
 399         if (adev->pm.dpm_enabled)
 400                 amdgpu_dpm_enable_jpeg(adev, false);
 401
 402         return 0;
 403 }
 404
 405 /**
 406  * jpeg_v3_0_dec_ring_get_rptr - get read pointer
 407  *
 408  * @ring: amdgpu_ring pointer
 409  *
 410  * Returns the current hardware read pointer
 411  */
 412 static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
 413 {
 414         struct amdgpu_device *adev = ring->adev;
 415
 416         return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
 417 }
 418
 419 /**
 420  * jpeg_v3_0_dec_ring_get_wptr - get write pointer
 421  *
 422  * @ring: amdgpu_ring pointer
 423  *
 424  * Returns the current hardware write pointer
 425  */
 426 static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
 427 {
 428         struct amdgpu_device *adev = ring->adev;
 429
 430         if (ring->use_doorbell)
 431                 return *ring->wptr_cpu_addr;
 432         else
 433                 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 434 }
 435
 436 /**
 437  * jpeg_v3_0_dec_ring_set_wptr - set write pointer
 438  *
 439  * @ring: amdgpu_ring pointer
 440  *
 441  * Commits the write pointer to the hardware
 442  */
 443 static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 444 {
 445         struct amdgpu_device *adev = ring->adev;
 446
 447         if (ring->use_doorbell) {
 448                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
 449                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 450         } else {
 451                 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
 452         }
 453 }
 454
 455 static bool jpeg_v3_0_is_idle(void *handle)
 456 {
 457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 458         int ret = 1;
 459
 460         ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
 461                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
 462                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
 463
 464         return ret;
 465 }
 466
 467 static int jpeg_v3_0_wait_for_idle(void *handle)
 468 {
 469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 470
 471         return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS,
 472                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
 473                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
 474 }
 475
 476 static int jpeg_v3_0_set_clockgating_state(void *handle,
 477                                           enum amd_clockgating_state state)
 478 {
 479         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 480         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 481
 482         if (enable) {
 483                 if (!jpeg_v3_0_is_idle(handle))
 484                         return -EBUSY;
 485                 jpeg_v3_0_enable_clock_gating(adev);
 486         } else {
 487                 jpeg_v3_0_disable_clock_gating(adev);
 488         }
 489
 490         return 0;
 491 }
 492
 493 static int jpeg_v3_0_set_powergating_state(void *handle,
 494                                           enum amd_powergating_state state)
 495 {
 496         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 497         int ret;
 498
 499         if(state == adev->jpeg.cur_state)
 500                 return 0;
 501
 502         if (state == AMD_PG_STATE_GATE)
 503                 ret = jpeg_v3_0_stop(adev);
 504         else
 505                 ret = jpeg_v3_0_start(adev);
 506
 507         if(!ret)
 508                 adev->jpeg.cur_state = state;
 509
 510         return ret;
 511 }
 512
 513 static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev,
 514                                         struct amdgpu_irq_src *source,
 515                                         unsigned type,
 516                                         enum amdgpu_interrupt_state state)
 517 {
 518         return 0;
 519 }
 520
 521 static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev,
 522                                       struct amdgpu_irq_src *source,
 523                                       struct amdgpu_iv_entry *entry)
 524 {
 525         DRM_DEBUG("IH: JPEG TRAP\n");
 526
 527         switch (entry->src_id) {
 528         case VCN_2_0__SRCID__JPEG_DECODE:
 529                 amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
 530                 break;
 531         default:
 532                 DRM_ERROR("Unhandled interrupt: %d %d\n",
 533                           entry->src_id, entry->src_data[0]);
 534                 break;
 535         }
 536
 537         return 0;
 538 }
 539
 540 static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = {
 541         .name = "jpeg_v3_0",
 542         .early_init = jpeg_v3_0_early_init,
 543         .late_init = NULL,
 544         .sw_init = jpeg_v3_0_sw_init,
 545         .sw_fini = jpeg_v3_0_sw_fini,
 546         .hw_init = jpeg_v3_0_hw_init,
 547         .hw_fini = jpeg_v3_0_hw_fini,
 548         .suspend = jpeg_v3_0_suspend,
 549         .resume = jpeg_v3_0_resume,
 550         .is_idle = jpeg_v3_0_is_idle,
 551         .wait_for_idle = jpeg_v3_0_wait_for_idle,
 552         .check_soft_reset = NULL,
 553         .pre_soft_reset = NULL,
 554         .soft_reset = NULL,
 555         .post_soft_reset = NULL,
 556         .set_clockgating_state = jpeg_v3_0_set_clockgating_state,
 557         .set_powergating_state = jpeg_v3_0_set_powergating_state,
 558 };
 559
 560 static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
 561         .type = AMDGPU_RING_TYPE_VCN_JPEG,
 562         .align_mask = 0xf,
 563         .get_rptr = jpeg_v3_0_dec_ring_get_rptr,
 564         .get_wptr = jpeg_v3_0_dec_ring_get_wptr,
 565         .set_wptr = jpeg_v3_0_dec_ring_set_wptr,
 566         .emit_frame_size =
 567                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 568                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 569                 8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */
 570                 18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */
 571                 8 + 16,
 572         .emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */
 573         .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 574         .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 575         .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
 576         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
 577         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 578         .insert_nop = jpeg_v2_0_dec_ring_nop,
 579         .insert_start = jpeg_v2_0_dec_ring_insert_start,
 580         .insert_end = jpeg_v2_0_dec_ring_insert_end,
 581         .pad_ib = amdgpu_ring_generic_pad_ib,
 582         .begin_use = amdgpu_jpeg_ring_begin_use,
 583         .end_use = amdgpu_jpeg_ring_end_use,
 584         .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
 585         .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
 586         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 587 };
 588
 589 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 590 {
 591         adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs;
 592         DRM_INFO("JPEG decode is enabled in VM mode\n");
 593 }
 594
 595 static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = {
 596         .set = jpeg_v3_0_set_interrupt_state,
 597         .process = jpeg_v3_0_process_interrupt,
 598 };
 599
 600 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev)
 601 {
 602         adev->jpeg.inst->irq.num_types = 1;
 603         adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs;
 604 }
 605
 606 const struct amdgpu_ip_block_version jpeg_v3_0_ip_block =
 607 {
 608         .type = AMD_IP_BLOCK_TYPE_JPEG,
 609         .major = 3,
 610         .minor = 0,
 611         .rev = 0,
 612         .funcs = &jpeg_v3_0_ip_funcs,
 613 };