drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <[email protected]>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "amdgpu.h"
  37 #include "amdgpu_pm.h"
  38 #include "amdgpu_uvd.h"
  39 #include "cikd.h"
  40 #include "uvd/uvd_4_2_d.h"
  41
  42 /* 1 second timeout */
  43 #define UVD_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  44
  45 /* Firmware versions for VI */
  46 #define FW_1_65_10      ((1 << 24) | (65 << 16) | (10 << 8))
  47 #define FW_1_87_11      ((1 << 24) | (87 << 16) | (11 << 8))
  48 #define FW_1_87_12      ((1 << 24) | (87 << 16) | (12 << 8))
  49 #define FW_1_37_15      ((1 << 24) | (37 << 16) | (15 << 8))
  50
  51 /* Polaris10/11 firmware version */
  52 #define FW_1_66_16      ((1 << 24) | (66 << 16) | (16 << 8))
  53
  54 /* Firmware Names */
  55 #ifdef CONFIG_DRM_AMDGPU_CIK
  56 #define FIRMWARE_BONAIRE        "amdgpu/bonaire_uvd.bin"
  57 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin"
  58 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin"
  59 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin"
  60 #define FIRMWARE_MULLINS        "amdgpu/mullins_uvd.bin"
  61 #endif
  62 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
  63 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
  64 #define FIRMWARE_FIJI           "amdgpu/fiji_uvd.bin"
  65 #define FIRMWARE_STONEY         "amdgpu/stoney_uvd.bin"
  66 #define FIRMWARE_POLARIS10      "amdgpu/polaris10_uvd.bin"
  67 #define FIRMWARE_POLARIS11      "amdgpu/polaris11_uvd.bin"
  68 #define FIRMWARE_POLARIS12      "amdgpu/polaris12_uvd.bin"
  69 #define FIRMWARE_VEGAM          "amdgpu/vegam_uvd.bin"
  70
  71 #define FIRMWARE_VEGA10         "amdgpu/vega10_uvd.bin"
  72 #define FIRMWARE_VEGA12         "amdgpu/vega12_uvd.bin"
  73 #define FIRMWARE_VEGA20         "amdgpu/vega20_uvd.bin"
  74
  75 /* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */
  76 #define UVD_GPCOM_VCPU_CMD              0x03c3
  77 #define UVD_GPCOM_VCPU_DATA0    0x03c4
  78 #define UVD_GPCOM_VCPU_DATA1    0x03c5
  79 #define UVD_NO_OP                               0x03ff
  80 #define UVD_BASE_SI                             0x3800
  81
  82 /**
  83  * amdgpu_uvd_cs_ctx - Command submission parser context
  84  *
  85  * Used for emulating virtual memory support on UVD 4.2.
  86  */
  87 struct amdgpu_uvd_cs_ctx {
  88         struct amdgpu_cs_parser *parser;
  89         unsigned reg, count;
  90         unsigned data0, data1;
  91         unsigned idx;
  92         unsigned ib_idx;
  93
  94         /* does the IB has a msg command */
  95         bool has_msg_cmd;
  96
  97         /* minimum buffer sizes */
  98         unsigned *buf_sizes;
  99 };
 100
 101 #ifdef CONFIG_DRM_AMDGPU_CIK
 102 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
 103 MODULE_FIRMWARE(FIRMWARE_KABINI);
 104 MODULE_FIRMWARE(FIRMWARE_KAVERI);
 105 MODULE_FIRMWARE(FIRMWARE_HAWAII);
 106 MODULE_FIRMWARE(FIRMWARE_MULLINS);
 107 #endif
 108 MODULE_FIRMWARE(FIRMWARE_TONGA);
 109 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
 110 MODULE_FIRMWARE(FIRMWARE_FIJI);
 111 MODULE_FIRMWARE(FIRMWARE_STONEY);
 112 MODULE_FIRMWARE(FIRMWARE_POLARIS10);
 113 MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 114 MODULE_FIRMWARE(FIRMWARE_POLARIS12);
 115 MODULE_FIRMWARE(FIRMWARE_VEGAM);
 116
 117 MODULE_FIRMWARE(FIRMWARE_VEGA10);
 118 MODULE_FIRMWARE(FIRMWARE_VEGA12);
 119 MODULE_FIRMWARE(FIRMWARE_VEGA20);
 120
 121 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
 122
 123 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 124 {
 125         struct amdgpu_ring *ring;
 126         struct drm_sched_rq *rq;
 127         unsigned long bo_size;
 128         const char *fw_name;
 129         const struct common_firmware_header *hdr;
 130         unsigned family_id;
 131         int i, j, r;
 132
 133         INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
 134
 135         switch (adev->asic_type) {
 136 #ifdef CONFIG_DRM_AMDGPU_CIK
 137         case CHIP_BONAIRE:
 138                 fw_name = FIRMWARE_BONAIRE;
 139                 break;
 140         case CHIP_KABINI:
 141                 fw_name = FIRMWARE_KABINI;
 142                 break;
 143         case CHIP_KAVERI:
 144                 fw_name = FIRMWARE_KAVERI;
 145                 break;
 146         case CHIP_HAWAII:
 147                 fw_name = FIRMWARE_HAWAII;
 148                 break;
 149         case CHIP_MULLINS:
 150                 fw_name = FIRMWARE_MULLINS;
 151                 break;
 152 #endif
 153         case CHIP_TONGA:
 154                 fw_name = FIRMWARE_TONGA;
 155                 break;
 156         case CHIP_FIJI:
 157                 fw_name = FIRMWARE_FIJI;
 158                 break;
 159         case CHIP_CARRIZO:
 160                 fw_name = FIRMWARE_CARRIZO;
 161                 break;
 162         case CHIP_STONEY:
 163                 fw_name = FIRMWARE_STONEY;
 164                 break;
 165         case CHIP_POLARIS10:
 166                 fw_name = FIRMWARE_POLARIS10;
 167                 break;
 168         case CHIP_POLARIS11:
 169                 fw_name = FIRMWARE_POLARIS11;
 170                 break;
 171         case CHIP_POLARIS12:
 172                 fw_name = FIRMWARE_POLARIS12;
 173                 break;
 174         case CHIP_VEGA10:
 175                 fw_name = FIRMWARE_VEGA10;
 176                 break;
 177         case CHIP_VEGA12:
 178                 fw_name = FIRMWARE_VEGA12;
 179                 break;
 180         case CHIP_VEGAM:
 181                 fw_name = FIRMWARE_VEGAM;
 182                 break;
 183         case CHIP_VEGA20:
 184                 fw_name = FIRMWARE_VEGA20;
 185                 break;
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
 191         if (r) {
 192                 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
 193                         fw_name);
 194                 return r;
 195         }
 196
 197         r = amdgpu_ucode_validate(adev->uvd.fw);
 198         if (r) {
 199                 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
 200                         fw_name);
 201                 release_firmware(adev->uvd.fw);
 202                 adev->uvd.fw = NULL;
 203                 return r;
 204         }
 205
 206         /* Set the default UVD handles that the firmware can handle */
 207         adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
 208
 209         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 210         family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
 211
 212         if (adev->asic_type < CHIP_VEGA20) {
 213                 unsigned version_major, version_minor;
 214
 215                 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
 216                 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 217                 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 218                         version_major, version_minor, family_id);
 219
 220                 /*
 221                  * Limit the number of UVD handles depending on microcode major
 222                  * and minor versions. The firmware version which has 40 UVD
 223                  * instances support is 1.80. So all subsequent versions should
 224                  * also have the same support.
 225                  */
 226                 if ((version_major > 0x01) ||
 227                     ((version_major == 0x01) && (version_minor >= 0x50)))
 228                         adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 229
 230                 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
 231                                         (family_id << 8));
 232
 233                 if ((adev->asic_type == CHIP_POLARIS10 ||
 234                      adev->asic_type == CHIP_POLARIS11) &&
 235                     (adev->uvd.fw_version < FW_1_66_16))
 236                         DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n",
 237                                   version_major, version_minor);
 238         } else {
 239                 unsigned int enc_major, enc_minor, dec_minor;
 240
 241                 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
 242                 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;
 243                 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;
 244                 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n",
 245                         enc_major, enc_minor, dec_minor, family_id);
 246
 247                 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
 248
 249                 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);
 250         }
 251
 252         bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE
 253                   +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
 254         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 255                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 256
 257         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 258                 if (adev->uvd.harvest_config & (1 << j))
 259                         continue;
 260                 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
 261                                             AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
 262                                             &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
 263                 if (r) {
 264                         dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
 265                         return r;
 266                 }
 267         }
 268
 269         ring = &adev->uvd.inst[0].ring;
 270         rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 271         r = drm_sched_entity_init(&adev->uvd.entity, &rq, 1, NULL);
 272         if (r) {
 273                 DRM_ERROR("Failed setting up UVD kernel entity.\n");
 274                 return r;
 275         }
 276         for (i = 0; i < adev->uvd.max_handles; ++i) {
 277                 atomic_set(&adev->uvd.handles[i], 0);
 278                 adev->uvd.filp[i] = NULL;
 279         }
 280
 281         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
 282         if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
 283                 adev->uvd.address_64_bit = true;
 284
 285         switch (adev->asic_type) {
 286         case CHIP_TONGA:
 287                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
 288                 break;
 289         case CHIP_CARRIZO:
 290                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
 291                 break;
 292         case CHIP_FIJI:
 293                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
 294                 break;
 295         case CHIP_STONEY:
 296                 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
 297                 break;
 298         default:
 299                 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
 300         }
 301
 302         return 0;
 303 }
 304
 305 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 306 {
 307         int i, j;
 308
 309         drm_sched_entity_destroy(&adev->uvd.entity);
 310
 311         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 312                 if (adev->uvd.harvest_config & (1 << j))
 313                         continue;
 314                 kfree(adev->uvd.inst[j].saved_bo);
 315
 316                 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
 317                                       &adev->uvd.inst[j].gpu_addr,
 318                                       (void **)&adev->uvd.inst[j].cpu_addr);
 319
 320                 amdgpu_ring_fini(&adev->uvd.inst[j].ring);
 321
 322                 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
 323                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 324         }
 325         release_firmware(adev->uvd.fw);
 326
 327         return 0;
 328 }
 329
 330 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 331 {
 332         unsigned size;
 333         void *ptr;
 334         int i, j;
 335
 336         cancel_delayed_work_sync(&adev->uvd.idle_work);
 337
 338         /* only valid for physical mode */
 339         if (adev->asic_type < CHIP_POLARIS10) {
 340                 for (i = 0; i < adev->uvd.max_handles; ++i)
 341                         if (atomic_read(&adev->uvd.handles[i]))
 342                                 break;
 343
 344                 if (i == adev->uvd.max_handles)
 345                         return 0;
 346         }
 347
 348         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 349                 if (adev->uvd.harvest_config & (1 << j))
 350                         continue;
 351                 if (adev->uvd.inst[j].vcpu_bo == NULL)
 352                         continue;
 353
 354                 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
 355                 ptr = adev->uvd.inst[j].cpu_addr;
 356
 357                 adev->uvd.inst[j].saved_bo = kmalloc(size, GFP_KERNEL);
 358                 if (!adev->uvd.inst[j].saved_bo)
 359                         return -ENOMEM;
 360
 361                 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
 362         }
 363         return 0;
 364 }
 365
 366 int amdgpu_uvd_resume(struct amdgpu_device *adev)
 367 {
 368         unsigned size;
 369         void *ptr;
 370         int i;
 371
 372         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 373                 if (adev->uvd.harvest_config & (1 << i))
 374                         continue;
 375                 if (adev->uvd.inst[i].vcpu_bo == NULL)
 376                         return -EINVAL;
 377
 378                 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
 379                 ptr = adev->uvd.inst[i].cpu_addr;
 380
 381                 if (adev->uvd.inst[i].saved_bo != NULL) {
 382                         memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
 383                         kfree(adev->uvd.inst[i].saved_bo);
 384                         adev->uvd.inst[i].saved_bo = NULL;
 385                 } else {
 386                         const struct common_firmware_header *hdr;
 387                         unsigned offset;
 388
 389                         hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 390                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 391                                 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
 392                                 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
 393                                             le32_to_cpu(hdr->ucode_size_bytes));
 394                                 size -= le32_to_cpu(hdr->ucode_size_bytes);
 395                                 ptr += le32_to_cpu(hdr->ucode_size_bytes);
 396                         }
 397                         memset_io(ptr, 0, size);
 398                         /* to restore uvd fence seq */
 399                         amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
 400                 }
 401         }
 402         return 0;
 403 }
 404
 405 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 406 {
 407         struct amdgpu_ring *ring = &adev->uvd.inst[0].ring;
 408         int i, r;
 409
 410         for (i = 0; i < adev->uvd.max_handles; ++i) {
 411                 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
 412
 413                 if (handle != 0 && adev->uvd.filp[i] == filp) {
 414                         struct dma_fence *fence;
 415
 416                         r = amdgpu_uvd_get_destroy_msg(ring, handle, false,
 417                                                        &fence);
 418                         if (r) {
 419                                 DRM_ERROR("Error destroying UVD %d!\n", r);
 420                                 continue;
 421                         }
 422
 423                         dma_fence_wait(fence, false);
 424                         dma_fence_put(fence);
 425
 426                         adev->uvd.filp[i] = NULL;
 427                         atomic_set(&adev->uvd.handles[i], 0);
 428                 }
 429         }
 430 }
 431
 432 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo)
 433 {
 434         int i;
 435         for (i = 0; i < abo->placement.num_placement; ++i) {
 436                 abo->placements[i].fpfn = 0 >> PAGE_SHIFT;
 437                 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 438         }
 439 }
 440
 441 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx)
 442 {
 443         uint32_t lo, hi;
 444         uint64_t addr;
 445
 446         lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
 447         hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
 448         addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
 449
 450         return addr;
 451 }
 452
 453 /**
 454  * amdgpu_uvd_cs_pass1 - first parsing round
 455  *
 456  * @ctx: UVD parser context
 457  *
 458  * Make sure UVD message and feedback buffers are in VRAM and
 459  * nobody is violating an 256MB boundary.
 460  */
 461 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
 462 {
 463         struct ttm_operation_ctx tctx = { false, false };
 464         struct amdgpu_bo_va_mapping *mapping;
 465         struct amdgpu_bo *bo;
 466         uint32_t cmd;
 467         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 468         int r = 0;
 469
 470         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
 471         if (r) {
 472                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 473                 return r;
 474         }
 475
 476         if (!ctx->parser->adev->uvd.address_64_bit) {
 477                 /* check if it's a message or feedback command */
 478                 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 479                 if (cmd == 0x0 || cmd == 0x3) {
 480                         /* yes, force it into VRAM */
 481                         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 482                         amdgpu_bo_placement_from_domain(bo, domain);
 483                 }
 484                 amdgpu_uvd_force_into_uvd_segment(bo);
 485
 486                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx);
 487         }
 488
 489         return r;
 490 }
 491
 492 /**
 493  * amdgpu_uvd_cs_msg_decode - handle UVD decode message
 494  *
 495  * @msg: pointer to message structure
 496  * @buf_sizes: returned buffer sizes
 497  *
 498  * Peek into the decode message and calculate the necessary buffer sizes.
 499  */
 500 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
 501         unsigned buf_sizes[])
 502 {
 503         unsigned stream_type = msg[4];
 504         unsigned width = msg[6];
 505         unsigned height = msg[7];
 506         unsigned dpb_size = msg[9];
 507         unsigned pitch = msg[28];
 508         unsigned level = msg[57];
 509
 510         unsigned width_in_mb = width / 16;
 511         unsigned height_in_mb = ALIGN(height / 16, 2);
 512         unsigned fs_in_mb = width_in_mb * height_in_mb;
 513
 514         unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
 515         unsigned min_ctx_size = ~0;
 516
 517         image_size = width * height;
 518         image_size += image_size / 2;
 519         image_size = ALIGN(image_size, 1024);
 520
 521         switch (stream_type) {
 522         case 0: /* H264 */
 523                 switch(level) {
 524                 case 30:
 525                         num_dpb_buffer = 8100 / fs_in_mb;
 526                         break;
 527                 case 31:
 528                         num_dpb_buffer = 18000 / fs_in_mb;
 529                         break;
 530                 case 32:
 531                         num_dpb_buffer = 20480 / fs_in_mb;
 532                         break;
 533                 case 41:
 534                         num_dpb_buffer = 32768 / fs_in_mb;
 535                         break;
 536                 case 42:
 537                         num_dpb_buffer = 34816 / fs_in_mb;
 538                         break;
 539                 case 50:
 540                         num_dpb_buffer = 110400 / fs_in_mb;
 541                         break;
 542                 case 51:
 543                         num_dpb_buffer = 184320 / fs_in_mb;
 544                         break;
 545                 default:
 546                         num_dpb_buffer = 184320 / fs_in_mb;
 547                         break;
 548                 }
 549                 num_dpb_buffer++;
 550                 if (num_dpb_buffer > 17)
 551                         num_dpb_buffer = 17;
 552
 553                 /* reference picture buffer */
 554                 min_dpb_size = image_size * num_dpb_buffer;
 555
 556                 /* macroblock context buffer */
 557                 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
 558
 559                 /* IT surface buffer */
 560                 min_dpb_size += width_in_mb * height_in_mb * 32;
 561                 break;
 562
 563         case 1: /* VC1 */
 564
 565                 /* reference picture buffer */
 566                 min_dpb_size = image_size * 3;
 567
 568                 /* CONTEXT_BUFFER */
 569                 min_dpb_size += width_in_mb * height_in_mb * 128;
 570
 571                 /* IT surface buffer */
 572                 min_dpb_size += width_in_mb * 64;
 573
 574                 /* DB surface buffer */
 575                 min_dpb_size += width_in_mb * 128;
 576
 577                 /* BP */
 578                 tmp = max(width_in_mb, height_in_mb);
 579                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 580                 break;
 581
 582         case 3: /* MPEG2 */
 583
 584                 /* reference picture buffer */
 585                 min_dpb_size = image_size * 3;
 586                 break;
 587
 588         case 4: /* MPEG4 */
 589
 590                 /* reference picture buffer */
 591                 min_dpb_size = image_size * 3;
 592
 593                 /* CM */
 594                 min_dpb_size += width_in_mb * height_in_mb * 64;
 595
 596                 /* IT surface buffer */
 597                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 598                 break;
 599
 600         case 7: /* H264 Perf */
 601                 switch(level) {
 602                 case 30:
 603                         num_dpb_buffer = 8100 / fs_in_mb;
 604                         break;
 605                 case 31:
 606                         num_dpb_buffer = 18000 / fs_in_mb;
 607                         break;
 608                 case 32:
 609                         num_dpb_buffer = 20480 / fs_in_mb;
 610                         break;
 611                 case 41:
 612                         num_dpb_buffer = 32768 / fs_in_mb;
 613                         break;
 614                 case 42:
 615                         num_dpb_buffer = 34816 / fs_in_mb;
 616                         break;
 617                 case 50:
 618                         num_dpb_buffer = 110400 / fs_in_mb;
 619                         break;
 620                 case 51:
 621                         num_dpb_buffer = 184320 / fs_in_mb;
 622                         break;
 623                 default:
 624                         num_dpb_buffer = 184320 / fs_in_mb;
 625                         break;
 626                 }
 627                 num_dpb_buffer++;
 628                 if (num_dpb_buffer > 17)
 629                         num_dpb_buffer = 17;
 630
 631                 /* reference picture buffer */
 632                 min_dpb_size = image_size * num_dpb_buffer;
 633
 634                 if (!adev->uvd.use_ctx_buf){
 635                         /* macroblock context buffer */
 636                         min_dpb_size +=
 637                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 638
 639                         /* IT surface buffer */
 640                         min_dpb_size += width_in_mb * height_in_mb * 32;
 641                 } else {
 642                         /* macroblock context buffer */
 643                         min_ctx_size =
 644                                 width_in_mb * height_in_mb * num_dpb_buffer * 192;
 645                 }
 646                 break;
 647
 648         case 8: /* MJPEG */
 649                 min_dpb_size = 0;
 650                 break;
 651
 652         case 16: /* H265 */
 653                 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
 654                 image_size = ALIGN(image_size, 256);
 655
 656                 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
 657                 min_dpb_size = image_size * num_dpb_buffer;
 658                 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
 659                                            * 16 * num_dpb_buffer + 52 * 1024;
 660                 break;
 661
 662         default:
 663                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 664                 return -EINVAL;
 665         }
 666
 667         if (width > pitch) {
 668                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 669                 return -EINVAL;
 670         }
 671
 672         if (dpb_size < min_dpb_size) {
 673                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 674                           dpb_size, min_dpb_size);
 675                 return -EINVAL;
 676         }
 677
 678         buf_sizes[0x1] = dpb_size;
 679         buf_sizes[0x2] = image_size;
 680         buf_sizes[0x4] = min_ctx_size;
 681         return 0;
 682 }
 683
 684 /**
 685  * amdgpu_uvd_cs_msg - handle UVD message
 686  *
 687  * @ctx: UVD parser context
 688  * @bo: buffer object containing the message
 689  * @offset: offset into the buffer object
 690  *
 691  * Peek into the UVD message and extract the session id.
 692  * Make sure that we don't open up to many sessions.
 693  */
 694 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 695                              struct amdgpu_bo *bo, unsigned offset)
 696 {
 697         struct amdgpu_device *adev = ctx->parser->adev;
 698         int32_t *msg, msg_type, handle;
 699         void *ptr;
 700         long r;
 701         int i;
 702
 703         if (offset & 0x3F) {
 704                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 705                 return -EINVAL;
 706         }
 707
 708         r = amdgpu_bo_kmap(bo, &ptr);
 709         if (r) {
 710                 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r);
 711                 return r;
 712         }
 713
 714         msg = ptr + offset;
 715
 716         msg_type = msg[1];
 717         handle = msg[2];
 718
 719         if (handle == 0) {
 720                 DRM_ERROR("Invalid UVD handle!\n");
 721                 return -EINVAL;
 722         }
 723
 724         switch (msg_type) {
 725         case 0:
 726                 /* it's a create msg, calc image size (width * height) */
 727                 amdgpu_bo_kunmap(bo);
 728
 729                 /* try to alloc a new handle */
 730                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 731                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 732                                 DRM_ERROR(")Handle 0x%x already in use!\n",
 733                                           handle);
 734                                 return -EINVAL;
 735                         }
 736
 737                         if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
 738                                 adev->uvd.filp[i] = ctx->parser->filp;
 739                                 return 0;
 740                         }
 741                 }
 742
 743                 DRM_ERROR("No more free UVD handles!\n");
 744                 return -ENOSPC;
 745
 746         case 1:
 747                 /* it's a decode msg, calc buffer sizes */
 748                 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes);
 749                 amdgpu_bo_kunmap(bo);
 750                 if (r)
 751                         return r;
 752
 753                 /* validate the handle */
 754                 for (i = 0; i < adev->uvd.max_handles; ++i) {
 755                         if (atomic_read(&adev->uvd.handles[i]) == handle) {
 756                                 if (adev->uvd.filp[i] != ctx->parser->filp) {
 757                                         DRM_ERROR("UVD handle collision detected!\n");
 758                                         return -EINVAL;
 759                                 }
 760                                 return 0;
 761                         }
 762                 }
 763
 764                 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
 765                 return -ENOENT;
 766
 767         case 2:
 768                 /* it's a destroy msg, free the handle */
 769                 for (i = 0; i < adev->uvd.max_handles; ++i)
 770                         atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
 771                 amdgpu_bo_kunmap(bo);
 772                 return 0;
 773
 774         default:
 775                 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
 776                 return -EINVAL;
 777         }
 778         BUG();
 779         return -EINVAL;
 780 }
 781
 782 /**
 783  * amdgpu_uvd_cs_pass2 - second parsing round
 784  *
 785  * @ctx: UVD parser context
 786  *
 787  * Patch buffer addresses, make sure buffer sizes are correct.
 788  */
 789 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
 790 {
 791         struct amdgpu_bo_va_mapping *mapping;
 792         struct amdgpu_bo *bo;
 793         uint32_t cmd;
 794         uint64_t start, end;
 795         uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
 796         int r;
 797
 798         r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
 799         if (r) {
 800                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
 801                 return r;
 802         }
 803
 804         start = amdgpu_bo_gpu_offset(bo);
 805
 806         end = (mapping->last + 1 - mapping->start);
 807         end = end * AMDGPU_GPU_PAGE_SIZE + start;
 808
 809         addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE;
 810         start += addr;
 811
 812         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
 813                             lower_32_bits(start));
 814         amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
 815                             upper_32_bits(start));
 816
 817         cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
 818         if (cmd < 0x4) {
 819                 if ((end - start) < ctx->buf_sizes[cmd]) {
 820                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 821                                   (unsigned)(end - start),
 822                                   ctx->buf_sizes[cmd]);
 823                         return -EINVAL;
 824                 }
 825
 826         } else if (cmd == 0x206) {
 827                 if ((end - start) < ctx->buf_sizes[4]) {
 828                         DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
 829                                           (unsigned)(end - start),
 830                                           ctx->buf_sizes[4]);
 831                         return -EINVAL;
 832                 }
 833         } else if ((cmd != 0x100) && (cmd != 0x204)) {
 834                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 835                 return -EINVAL;
 836         }
 837
 838         if (!ctx->parser->adev->uvd.address_64_bit) {
 839                 if ((start >> 28) != ((end - 1) >> 28)) {
 840                         DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 841                                   start, end);
 842                         return -EINVAL;
 843                 }
 844
 845                 if ((cmd == 0 || cmd == 0x3) &&
 846                     (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
 847                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 848                                   start, end);
 849                         return -EINVAL;
 850                 }
 851         }
 852
 853         if (cmd == 0) {
 854                 ctx->has_msg_cmd = true;
 855                 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
 856                 if (r)
 857                         return r;
 858         } else if (!ctx->has_msg_cmd) {
 859                 DRM_ERROR("Message needed before other commands are send!\n");
 860                 return -EINVAL;
 861         }
 862
 863         return 0;
 864 }
 865
 866 /**
 867  * amdgpu_uvd_cs_reg - parse register writes
 868  *
 869  * @ctx: UVD parser context
 870  * @cb: callback function
 871  *
 872  * Parse the register writes, call cb on each complete command.
 873  */
 874 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
 875                              int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 876 {
 877         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 878         int i, r;
 879
 880         ctx->idx++;
 881         for (i = 0; i <= ctx->count; ++i) {
 882                 unsigned reg = ctx->reg + i;
 883
 884                 if (ctx->idx >= ib->length_dw) {
 885                         DRM_ERROR("Register command after end of CS!\n");
 886                         return -EINVAL;
 887                 }
 888
 889                 switch (reg) {
 890                 case mmUVD_GPCOM_VCPU_DATA0:
 891                         ctx->data0 = ctx->idx;
 892                         break;
 893                 case mmUVD_GPCOM_VCPU_DATA1:
 894                         ctx->data1 = ctx->idx;
 895                         break;
 896                 case mmUVD_GPCOM_VCPU_CMD:
 897                         r = cb(ctx);
 898                         if (r)
 899                                 return r;
 900                         break;
 901                 case mmUVD_ENGINE_CNTL:
 902                 case mmUVD_NO_OP:
 903                         break;
 904                 default:
 905                         DRM_ERROR("Invalid reg 0x%X!\n", reg);
 906                         return -EINVAL;
 907                 }
 908                 ctx->idx++;
 909         }
 910         return 0;
 911 }
 912
 913 /**
 914  * amdgpu_uvd_cs_packets - parse UVD packets
 915  *
 916  * @ctx: UVD parser context
 917  * @cb: callback function
 918  *
 919  * Parse the command stream packets.
 920  */
 921 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
 922                                  int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
 923 {
 924         struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
 925         int r;
 926
 927         for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
 928                 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
 929                 unsigned type = CP_PACKET_GET_TYPE(cmd);
 930                 switch (type) {
 931                 case PACKET_TYPE0:
 932                         ctx->reg = CP_PACKET0_GET_REG(cmd);
 933                         ctx->count = CP_PACKET_GET_COUNT(cmd);
 934                         r = amdgpu_uvd_cs_reg(ctx, cb);
 935                         if (r)
 936                                 return r;
 937                         break;
 938                 case PACKET_TYPE2:
 939                         ++ctx->idx;
 940                         break;
 941                 default:
 942                         DRM_ERROR("Unknown packet type %d !\n", type);
 943                         return -EINVAL;
 944                 }
 945         }
 946         return 0;
 947 }
 948
 949 /**
 950  * amdgpu_uvd_ring_parse_cs - UVD command submission parser
 951  *
 952  * @parser: Command submission parser context
 953  *
 954  * Parse the command stream, patch in addresses as necessary.
 955  */
 956 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
 957 {
 958         struct amdgpu_uvd_cs_ctx ctx = {};
 959         unsigned buf_sizes[] = {
 960                 [0x00000000]    =       2048,
 961                 [0x00000001]    =       0xFFFFFFFF,
 962                 [0x00000002]    =       0xFFFFFFFF,
 963                 [0x00000003]    =       2048,
 964                 [0x00000004]    =       0xFFFFFFFF,
 965         };
 966         struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
 967         int r;
 968
 969         parser->job->vm = NULL;
 970         ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 971
 972         if (ib->length_dw % 16) {
 973                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 974                           ib->length_dw);
 975                 return -EINVAL;
 976         }
 977
 978         ctx.parser = parser;
 979         ctx.buf_sizes = buf_sizes;
 980         ctx.ib_idx = ib_idx;
 981
 982         /* first round only required on chips without UVD 64 bit address support */
 983         if (!parser->adev->uvd.address_64_bit) {
 984                 /* first round, make sure the buffers are actually in the UVD segment */
 985                 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
 986                 if (r)
 987                         return r;
 988         }
 989
 990         /* second round, patch buffer addresses into the command stream */
 991         r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
 992         if (r)
 993                 return r;
 994
 995         if (!ctx.has_msg_cmd) {
 996                 DRM_ERROR("UVD-IBs need a msg command!\n");
 997                 return -EINVAL;
 998         }
 999
1000         return 0;
1001 }
1002
1003 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
1004                                bool direct, struct dma_fence **fence)
1005 {
1006         struct amdgpu_device *adev = ring->adev;
1007         struct dma_fence *f = NULL;
1008         struct amdgpu_job *job;
1009         struct amdgpu_ib *ib;
1010         uint32_t data[4];
1011         uint64_t addr;
1012         long r;
1013         int i;
1014         unsigned offset_idx = 0;
1015         unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
1016
1017         amdgpu_bo_kunmap(bo);
1018         amdgpu_bo_unpin(bo);
1019
1020         if (!ring->adev->uvd.address_64_bit) {
1021                 struct ttm_operation_ctx ctx = { true, false };
1022
1023                 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
1024                 amdgpu_uvd_force_into_uvd_segment(bo);
1025                 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1026                 if (r)
1027                         goto err;
1028         }
1029
1030         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
1031         if (r)
1032                 goto err;
1033
1034         if (adev->asic_type >= CHIP_VEGA10) {
1035                 offset_idx = 1 + ring->me;
1036                 offset[1] = adev->reg_offset[UVD_HWIP][0][1];
1037                 offset[2] = adev->reg_offset[UVD_HWIP][1][1];
1038         }
1039
1040         data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1041         data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1042         data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1043         data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
1044
1045         ib = &job->ibs[0];
1046         addr = amdgpu_bo_gpu_offset(bo);
1047         ib->ptr[0] = data[0];
1048         ib->ptr[1] = addr;
1049         ib->ptr[2] = data[1];
1050         ib->ptr[3] = addr >> 32;
1051         ib->ptr[4] = data[2];
1052         ib->ptr[5] = 0;
1053         for (i = 6; i < 16; i += 2) {
1054                 ib->ptr[i] = data[3];
1055                 ib->ptr[i+1] = 0;
1056         }
1057         ib->length_dw = 16;
1058
1059         if (direct) {
1060                 r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
1061                                                         true, false,
1062                                                         msecs_to_jiffies(10));
1063                 if (r == 0)
1064                         r = -ETIMEDOUT;
1065                 if (r < 0)
1066                         goto err_free;
1067
1068                 r = amdgpu_job_submit_direct(job, ring, &f);
1069                 if (r)
1070                         goto err_free;
1071         } else {
1072                 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
1073                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
1074                 if (r)
1075                         goto err_free;
1076
1077                 r = amdgpu_job_submit(job, &adev->uvd.entity,
1078                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
1079                 if (r)
1080                         goto err_free;
1081         }
1082
1083         amdgpu_bo_fence(bo, f, false);
1084         amdgpu_bo_unreserve(bo);
1085         amdgpu_bo_unref(&bo);
1086
1087         if (fence)
1088                 *fence = dma_fence_get(f);
1089         dma_fence_put(f);
1090
1091         return 0;
1092
1093 err_free:
1094         amdgpu_job_free(job);
1095
1096 err:
1097         amdgpu_bo_unreserve(bo);
1098         amdgpu_bo_unref(&bo);
1099         return r;
1100 }
1101
1102 /* multiple fence commands without any stream commands in between can
1103    crash the vcpu so just try to emmit a dummy create/destroy msg to
1104    avoid this */
1105 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
1106                               struct dma_fence **fence)
1107 {
1108         struct amdgpu_device *adev = ring->adev;
1109         struct amdgpu_bo *bo = NULL;
1110         uint32_t *msg;
1111         int r, i;
1112
1113         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1114                                       AMDGPU_GEM_DOMAIN_VRAM,
1115                                       &bo, NULL, (void **)&msg);
1116         if (r)
1117                 return r;
1118
1119         /* stitch together an UVD create msg */
1120         msg[0] = cpu_to_le32(0x00000de4);
1121         msg[1] = cpu_to_le32(0x00000000);
1122         msg[2] = cpu_to_le32(handle);
1123         msg[3] = cpu_to_le32(0x00000000);
1124         msg[4] = cpu_to_le32(0x00000000);
1125         msg[5] = cpu_to_le32(0x00000000);
1126         msg[6] = cpu_to_le32(0x00000000);
1127         msg[7] = cpu_to_le32(0x00000780);
1128         msg[8] = cpu_to_le32(0x00000440);
1129         msg[9] = cpu_to_le32(0x00000000);
1130         msg[10] = cpu_to_le32(0x01b37000);
1131         for (i = 11; i < 1024; ++i)
1132                 msg[i] = cpu_to_le32(0x0);
1133
1134         return amdgpu_uvd_send_msg(ring, bo, true, fence);
1135 }
1136
1137 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
1138                                bool direct, struct dma_fence **fence)
1139 {
1140         struct amdgpu_device *adev = ring->adev;
1141         struct amdgpu_bo *bo = NULL;
1142         uint32_t *msg;
1143         int r, i;
1144
1145         r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
1146                                       AMDGPU_GEM_DOMAIN_VRAM,
1147                                       &bo, NULL, (void **)&msg);
1148         if (r)
1149                 return r;
1150
1151         /* stitch together an UVD destroy msg */
1152         msg[0] = cpu_to_le32(0x00000de4);
1153         msg[1] = cpu_to_le32(0x00000002);
1154         msg[2] = cpu_to_le32(handle);
1155         msg[3] = cpu_to_le32(0x00000000);
1156         for (i = 4; i < 1024; ++i)
1157                 msg[i] = cpu_to_le32(0x0);
1158
1159         return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1160 }
1161
1162 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1163 {
1164         struct amdgpu_device *adev =
1165                 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1166         unsigned fences = 0, i, j;
1167
1168         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1169                 if (adev->uvd.harvest_config & (1 << i))
1170                         continue;
1171                 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
1172                 for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
1173                         fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
1174                 }
1175         }
1176
1177         if (fences == 0) {
1178                 if (adev->pm.dpm_enabled) {
1179                         amdgpu_dpm_enable_uvd(adev, false);
1180                 } else {
1181                         amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1182                         /* shutdown the UVD block */
1183                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1184                                                                AMD_PG_STATE_GATE);
1185                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1186                                                                AMD_CG_STATE_GATE);
1187                 }
1188         } else {
1189                 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1190         }
1191 }
1192
1193 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
1194 {
1195         struct amdgpu_device *adev = ring->adev;
1196         bool set_clocks;
1197
1198         if (amdgpu_sriov_vf(adev))
1199                 return;
1200
1201         set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1202         if (set_clocks) {
1203                 if (adev->pm.dpm_enabled) {
1204                         amdgpu_dpm_enable_uvd(adev, true);
1205                 } else {
1206                         amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1207                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1208                                                                AMD_CG_STATE_UNGATE);
1209                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1210                                                                AMD_PG_STATE_UNGATE);
1211                 }
1212         }
1213 }
1214
1215 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
1216 {
1217         if (!amdgpu_sriov_vf(ring->adev))
1218                 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
1219 }
1220
1221 /**
1222  * amdgpu_uvd_ring_test_ib - test ib execution
1223  *
1224  * @ring: amdgpu_ring pointer
1225  *
1226  * Test if we can successfully execute an IB
1227  */
1228 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1229 {
1230         struct dma_fence *fence;
1231         long r;
1232         uint32_t ip_instance = ring->me;
1233
1234         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
1235         if (r) {
1236                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ip_instance, r);
1237                 goto error;
1238         }
1239
1240         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
1241         if (r) {
1242                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ip_instance, r);
1243                 goto error;
1244         }
1245
1246         r = dma_fence_wait_timeout(fence, false, timeout);
1247         if (r == 0) {
1248                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ip_instance);
1249                 r = -ETIMEDOUT;
1250         } else if (r < 0) {
1251                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ip_instance, r);
1252         } else {
1253                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ip_instance, ring->idx);
1254                 r = 0;
1255         }
1256
1257         dma_fence_put(fence);
1258
1259 error:
1260         return r;
1261 }
1262
1263 /**
1264  * amdgpu_uvd_used_handles - returns used UVD handles
1265  *
1266  * @adev: amdgpu_device pointer
1267  *
1268  * Returns the number of UVD handles in use
1269  */
1270 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
1271 {
1272         unsigned i;
1273         uint32_t used_handles = 0;
1274
1275         for (i = 0; i < adev->uvd.max_handles; ++i) {
1276                 /*
1277                  * Handles can be freed in any order, and not
1278                  * necessarily linear. So we need to count
1279                  * all non-zero handles.
1280                  */
1281                 if (atomic_read(&adev->uvd.handles[i]))
1282                         used_handles++;
1283         }
1284
1285         return used_handles;
1286 }