drivers/gpu/drm/lima/lima_mmu.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /* Copyright 2017-2019 Qiang Yu <[email protected]> */
   3
   4 #include <linux/interrupt.h>
   5 #include <linux/iopoll.h>
   6 #include <linux/device.h>
   7
   8 #include "lima_device.h"
   9 #include "lima_mmu.h"
  10 #include "lima_vm.h"
  11 #include "lima_regs.h"
  12
  13 #define mmu_write(reg, data) writel(data, ip->iomem + reg)
  14 #define mmu_read(reg) readl(ip->iomem + reg)
  15
  16 #define lima_mmu_send_command(cmd, addr, val, cond)          \
  17 ({                                                           \
  18         int __ret;                                           \
  19                                                              \
  20         mmu_write(LIMA_MMU_COMMAND, cmd);                    \
  21         __ret = readl_poll_timeout(ip->iomem + (addr), val,  \
  22                                   cond, 0, 100);             \
  23         if (__ret)                                           \
  24                 dev_err(dev->dev,                            \
  25                         "mmu command %x timeout\n", cmd);    \
  26         __ret;                                               \
  27 })
  28
  29 static irqreturn_t lima_mmu_irq_handler(int irq, void *data)
  30 {
  31         struct lima_ip *ip = data;
  32         struct lima_device *dev = ip->dev;
  33         u32 status = mmu_read(LIMA_MMU_INT_STATUS);
  34         struct lima_sched_pipe *pipe;
  35
  36         /* for shared irq case */
  37         if (!status)
  38                 return IRQ_NONE;
  39
  40         if (status & LIMA_MMU_INT_PAGE_FAULT) {
  41                 u32 fault = mmu_read(LIMA_MMU_PAGE_FAULT_ADDR);
  42
  43                 dev_err(dev->dev, "mmu page fault at 0x%x from bus id %d of type %s on %s\n",
  44                         fault, LIMA_MMU_STATUS_BUS_ID(status),
  45                         status & LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE ? "write" : "read",
  46                         lima_ip_name(ip));
  47         }
  48
  49         if (status & LIMA_MMU_INT_READ_BUS_ERROR)
  50                 dev_err(dev->dev, "mmu %s irq bus error\n", lima_ip_name(ip));
  51
  52         /* mask all interrupts before resume */
  53         mmu_write(LIMA_MMU_INT_MASK, 0);
  54         mmu_write(LIMA_MMU_INT_CLEAR, status);
  55
  56         pipe = dev->pipe + (ip->id == lima_ip_gpmmu ? lima_pipe_gp : lima_pipe_pp);
  57         lima_sched_pipe_mmu_error(pipe);
  58
  59         return IRQ_HANDLED;
  60 }
  61
  62 int lima_mmu_init(struct lima_ip *ip)
  63 {
  64         struct lima_device *dev = ip->dev;
  65         int err;
  66         u32 v;
  67
  68         if (ip->id == lima_ip_ppmmu_bcast)
  69                 return 0;
  70
  71         mmu_write(LIMA_MMU_DTE_ADDR, 0xCAFEBABE);
  72         if (mmu_read(LIMA_MMU_DTE_ADDR) != 0xCAFEB000) {
  73                 dev_err(dev->dev, "mmu %s dte write test fail\n", lima_ip_name(ip));
  74                 return -EIO;
  75         }
  76
  77         mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_HARD_RESET);
  78         err = lima_mmu_send_command(LIMA_MMU_COMMAND_HARD_RESET,
  79                                     LIMA_MMU_DTE_ADDR, v, v == 0);
  80         if (err)
  81                 return err;
  82
  83         err = devm_request_irq(dev->dev, ip->irq, lima_mmu_irq_handler,
  84                                IRQF_SHARED, lima_ip_name(ip), ip);
  85         if (err) {
  86                 dev_err(dev->dev, "mmu %s fail to request irq\n", lima_ip_name(ip));
  87                 return err;
  88         }
  89
  90         mmu_write(LIMA_MMU_INT_MASK, LIMA_MMU_INT_PAGE_FAULT | LIMA_MMU_INT_READ_BUS_ERROR);
  91         mmu_write(LIMA_MMU_DTE_ADDR, dev->empty_vm->pd.dma);
  92         return lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_PAGING,
  93                                      LIMA_MMU_STATUS, v,
  94                                      v & LIMA_MMU_STATUS_PAGING_ENABLED);
  95 }
  96
  97 void lima_mmu_fini(struct lima_ip *ip)
  98 {
  99
 100 }
 101
 102 void lima_mmu_flush_tlb(struct lima_ip *ip)
 103 {
 104         mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_ZAP_CACHE);
 105 }
 106
 107 void lima_mmu_switch_vm(struct lima_ip *ip, struct lima_vm *vm)
 108 {
 109         struct lima_device *dev = ip->dev;
 110         u32 v;
 111
 112         lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_STALL,
 113                               LIMA_MMU_STATUS, v,
 114                               v & LIMA_MMU_STATUS_STALL_ACTIVE);
 115
 116         if (vm)
 117                 mmu_write(LIMA_MMU_DTE_ADDR, vm->pd.dma);
 118
 119         /* flush the TLB */
 120         mmu_write(LIMA_MMU_COMMAND, LIMA_MMU_COMMAND_ZAP_CACHE);
 121
 122         lima_mmu_send_command(LIMA_MMU_COMMAND_DISABLE_STALL,
 123                               LIMA_MMU_STATUS, v,
 124                               !(v & LIMA_MMU_STATUS_STALL_ACTIVE));
 125 }
 126
 127 void lima_mmu_page_fault_resume(struct lima_ip *ip)
 128 {
 129         struct lima_device *dev = ip->dev;
 130         u32 status = mmu_read(LIMA_MMU_STATUS);
 131         u32 v;
 132
 133         if (status & LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE) {
 134                 dev_info(dev->dev, "mmu resume\n");
 135
 136                 mmu_write(LIMA_MMU_INT_MASK, 0);
 137                 mmu_write(LIMA_MMU_DTE_ADDR, 0xCAFEBABE);
 138                 lima_mmu_send_command(LIMA_MMU_COMMAND_HARD_RESET,
 139                                       LIMA_MMU_DTE_ADDR, v, v == 0);
 140                 mmu_write(LIMA_MMU_INT_MASK, LIMA_MMU_INT_PAGE_FAULT | LIMA_MMU_INT_READ_BUS_ERROR);
 141                 mmu_write(LIMA_MMU_DTE_ADDR, dev->empty_vm->pd.dma);
 142                 lima_mmu_send_command(LIMA_MMU_COMMAND_ENABLE_PAGING,
 143                                       LIMA_MMU_STATUS, v,
 144                                       v & LIMA_MMU_STATUS_PAGING_ENABLED);
 145         }
 146 }