drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/iommu.h>
  13 #include <linux/of_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/reset.h>
  16
  17 #include <soc/tegra/pmc.h>
  18
  19 #include "dc.h"
  20 #include "drm.h"
  21 #include "gem.h"
  22
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_plane_helper.h>
  26
  27 struct tegra_plane {
  28         struct drm_plane base;
  29         unsigned int index;
  30 };
  31
  32 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  33 {
  34         return container_of(plane, struct tegra_plane, base);
  35 }
  36
  37 struct tegra_dc_state {
  38         struct drm_crtc_state base;
  39
  40         struct clk *clk;
  41         unsigned long pclk;
  42         unsigned int div;
  43
  44         u32 planes;
  45 };
  46
  47 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
  48 {
  49         if (state)
  50                 return container_of(state, struct tegra_dc_state, base);
  51
  52         return NULL;
  53 }
  54
  55 struct tegra_plane_state {
  56         struct drm_plane_state base;
  57
  58         struct tegra_bo_tiling tiling;
  59         u32 format;
  60         u32 swap;
  61 };
  62
  63 static inline struct tegra_plane_state *
  64 to_tegra_plane_state(struct drm_plane_state *state)
  65 {
  66         if (state)
  67                 return container_of(state, struct tegra_plane_state, base);
  68
  69         return NULL;
  70 }
  71
  72 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
  73 {
  74         stats->frames = 0;
  75         stats->vblank = 0;
  76         stats->underflow = 0;
  77         stats->overflow = 0;
  78 }
  79
  80 /*
  81  * Reads the active copy of a register. This takes the dc->lock spinlock to
  82  * prevent races with the VBLANK processing which also needs access to the
  83  * active copy of some registers.
  84  */
  85 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
  86 {
  87         unsigned long flags;
  88         u32 value;
  89
  90         spin_lock_irqsave(&dc->lock, flags);
  91
  92         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
  93         value = tegra_dc_readl(dc, offset);
  94         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
  95
  96         spin_unlock_irqrestore(&dc->lock, flags);
  97         return value;
  98 }
  99
 100 /*
 101  * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
 102  * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
 103  * Latching happens mmediately if the display controller is in STOP mode or
 104  * on the next frame boundary otherwise.
 105  *
 106  * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
 107  * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
 108  * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
 109  * into the ACTIVE copy, either immediately if the display controller is in
 110  * STOP mode, or at the next frame boundary otherwise.
 111  */
 112 void tegra_dc_commit(struct tegra_dc *dc)
 113 {
 114         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 115         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 116 }
 117
 118 static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
 119 {
 120         /* assume no swapping of fetched data */
 121         if (swap)
 122                 *swap = BYTE_SWAP_NOSWAP;
 123
 124         switch (fourcc) {
 125         case DRM_FORMAT_XBGR8888:
 126                 *format = WIN_COLOR_DEPTH_R8G8B8A8;
 127                 break;
 128
 129         case DRM_FORMAT_XRGB8888:
 130                 *format = WIN_COLOR_DEPTH_B8G8R8A8;
 131                 break;
 132
 133         case DRM_FORMAT_RGB565:
 134                 *format = WIN_COLOR_DEPTH_B5G6R5;
 135                 break;
 136
 137         case DRM_FORMAT_UYVY:
 138                 *format = WIN_COLOR_DEPTH_YCbCr422;
 139                 break;
 140
 141         case DRM_FORMAT_YUYV:
 142                 if (swap)
 143                         *swap = BYTE_SWAP_SWAP2;
 144
 145                 *format = WIN_COLOR_DEPTH_YCbCr422;
 146                 break;
 147
 148         case DRM_FORMAT_YUV420:
 149                 *format = WIN_COLOR_DEPTH_YCbCr420P;
 150                 break;
 151
 152         case DRM_FORMAT_YUV422:
 153                 *format = WIN_COLOR_DEPTH_YCbCr422P;
 154                 break;
 155
 156         default:
 157                 return -EINVAL;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
 164 {
 165         switch (format) {
 166         case WIN_COLOR_DEPTH_YCbCr422:
 167         case WIN_COLOR_DEPTH_YUV422:
 168                 if (planar)
 169                         *planar = false;
 170
 171                 return true;
 172
 173         case WIN_COLOR_DEPTH_YCbCr420P:
 174         case WIN_COLOR_DEPTH_YUV420P:
 175         case WIN_COLOR_DEPTH_YCbCr422P:
 176         case WIN_COLOR_DEPTH_YUV422P:
 177         case WIN_COLOR_DEPTH_YCbCr422R:
 178         case WIN_COLOR_DEPTH_YUV422R:
 179         case WIN_COLOR_DEPTH_YCbCr422RA:
 180         case WIN_COLOR_DEPTH_YUV422RA:
 181                 if (planar)
 182                         *planar = true;
 183
 184                 return true;
 185         }
 186
 187         if (planar)
 188                 *planar = false;
 189
 190         return false;
 191 }
 192
 193 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 194                                   unsigned int bpp)
 195 {
 196         fixed20_12 outf = dfixed_init(out);
 197         fixed20_12 inf = dfixed_init(in);
 198         u32 dda_inc;
 199         int max;
 200
 201         if (v)
 202                 max = 15;
 203         else {
 204                 switch (bpp) {
 205                 case 2:
 206                         max = 8;
 207                         break;
 208
 209                 default:
 210                         WARN_ON_ONCE(1);
 211                         /* fallthrough */
 212                 case 4:
 213                         max = 4;
 214                         break;
 215                 }
 216         }
 217
 218         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 219         inf.full -= dfixed_const(1);
 220
 221         dda_inc = dfixed_div(inf, outf);
 222         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 223
 224         return dda_inc;
 225 }
 226
 227 static inline u32 compute_initial_dda(unsigned int in)
 228 {
 229         fixed20_12 inf = dfixed_init(in);
 230         return dfixed_frac(inf);
 231 }
 232
 233 static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 234                                   const struct tegra_dc_window *window)
 235 {
 236         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 237         unsigned long value, flags;
 238         bool yuv, planar;
 239
 240         /*
 241          * For YUV planar modes, the number of bytes per pixel takes into
 242          * account only the luma component and therefore is 1.
 243          */
 244         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 245         if (!yuv)
 246                 bpp = window->bits_per_pixel / 8;
 247         else
 248                 bpp = planar ? 1 : 2;
 249
 250         spin_lock_irqsave(&dc->lock, flags);
 251
 252         value = WINDOW_A_SELECT << index;
 253         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 254
 255         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 256         tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
 257
 258         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 259         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 260
 261         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 262         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 263
 264         h_offset = window->src.x * bpp;
 265         v_offset = window->src.y;
 266         h_size = window->src.w * bpp;
 267         v_size = window->src.h;
 268
 269         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 270         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 271
 272         /*
 273          * For DDA computations the number of bytes per pixel for YUV planar
 274          * modes needs to take into account all Y, U and V components.
 275          */
 276         if (yuv && planar)
 277                 bpp = 2;
 278
 279         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 280         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 281
 282         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 283         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 284
 285         h_dda = compute_initial_dda(window->src.x);
 286         v_dda = compute_initial_dda(window->src.y);
 287
 288         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 289         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 290
 291         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 292         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 293
 294         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 295
 296         if (yuv && planar) {
 297                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 298                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 299                 value = window->stride[1] << 16 | window->stride[0];
 300                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 301         } else {
 302                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 303         }
 304
 305         if (window->bottom_up)
 306                 v_offset += window->src.h - 1;
 307
 308         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 309         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 310
 311         if (dc->soc->supports_block_linear) {
 312                 unsigned long height = window->tiling.value;
 313
 314                 switch (window->tiling.mode) {
 315                 case TEGRA_BO_TILING_MODE_PITCH:
 316                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 317                         break;
 318
 319                 case TEGRA_BO_TILING_MODE_TILED:
 320                         value = DC_WINBUF_SURFACE_KIND_TILED;
 321                         break;
 322
 323                 case TEGRA_BO_TILING_MODE_BLOCK:
 324                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 325                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 326                         break;
 327                 }
 328
 329                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
 330         } else {
 331                 switch (window->tiling.mode) {
 332                 case TEGRA_BO_TILING_MODE_PITCH:
 333                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 334                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 335                         break;
 336
 337                 case TEGRA_BO_TILING_MODE_TILED:
 338                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 339                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 340                         break;
 341
 342                 case TEGRA_BO_TILING_MODE_BLOCK:
 343                         /*
 344                          * No need to handle this here because ->atomic_check
 345                          * will already have filtered it out.
 346                          */
 347                         break;
 348                 }
 349
 350                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
 351         }
 352
 353         value = WIN_ENABLE;
 354
 355         if (yuv) {
 356                 /* setup default colorspace conversion coefficients */
 357                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 358                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 359                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 360                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 361                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 362                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 363                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 364                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 365
 366                 value |= CSC_ENABLE;
 367         } else if (window->bits_per_pixel < 24) {
 368                 value |= COLOR_EXPAND;
 369         }
 370
 371         if (window->bottom_up)
 372                 value |= V_DIRECTION;
 373
 374         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 375
 376         /*
 377          * Disable blending and assume Window A is the bottom-most window,
 378          * Window C is the top-most window and Window B is in the middle.
 379          */
 380         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 381         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 382
 383         switch (index) {
 384         case 0:
 385                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 386                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 387                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 388                 break;
 389
 390         case 1:
 391                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 392                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 393                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 394                 break;
 395
 396         case 2:
 397                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 398                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 399                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 400                 break;
 401         }
 402
 403         spin_unlock_irqrestore(&dc->lock, flags);
 404 }
 405
 406 static void tegra_plane_destroy(struct drm_plane *plane)
 407 {
 408         struct tegra_plane *p = to_tegra_plane(plane);
 409
 410         drm_plane_cleanup(plane);
 411         kfree(p);
 412 }
 413
 414 static const u32 tegra_primary_plane_formats[] = {
 415         DRM_FORMAT_XBGR8888,
 416         DRM_FORMAT_XRGB8888,
 417         DRM_FORMAT_RGB565,
 418 };
 419
 420 static void tegra_primary_plane_destroy(struct drm_plane *plane)
 421 {
 422         tegra_plane_destroy(plane);
 423 }
 424
 425 static void tegra_plane_reset(struct drm_plane *plane)
 426 {
 427         struct tegra_plane_state *state;
 428
 429         if (plane->state)
 430                 __drm_atomic_helper_plane_destroy_state(plane->state);
 431
 432         kfree(plane->state);
 433         plane->state = NULL;
 434
 435         state = kzalloc(sizeof(*state), GFP_KERNEL);
 436         if (state) {
 437                 plane->state = &state->base;
 438                 plane->state->plane = plane;
 439         }
 440 }
 441
 442 static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
 443 {
 444         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 445         struct tegra_plane_state *copy;
 446
 447         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
 448         if (!copy)
 449                 return NULL;
 450
 451         __drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
 452         copy->tiling = state->tiling;
 453         copy->format = state->format;
 454         copy->swap = state->swap;
 455
 456         return &copy->base;
 457 }
 458
 459 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
 460                                              struct drm_plane_state *state)
 461 {
 462         __drm_atomic_helper_plane_destroy_state(state);
 463         kfree(state);
 464 }
 465
 466 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
 467         .update_plane = drm_atomic_helper_update_plane,
 468         .disable_plane = drm_atomic_helper_disable_plane,
 469         .destroy = tegra_primary_plane_destroy,
 470         .reset = tegra_plane_reset,
 471         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 472         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 473 };
 474
 475 static int tegra_plane_state_add(struct tegra_plane *plane,
 476                                  struct drm_plane_state *state)
 477 {
 478         struct drm_crtc_state *crtc_state;
 479         struct tegra_dc_state *tegra;
 480         struct drm_rect clip;
 481         int err;
 482
 483         /* Propagate errors from allocation or locking failures. */
 484         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 485         if (IS_ERR(crtc_state))
 486                 return PTR_ERR(crtc_state);
 487
 488         clip.x1 = 0;
 489         clip.y1 = 0;
 490         clip.x2 = crtc_state->mode.hdisplay;
 491         clip.y2 = crtc_state->mode.vdisplay;
 492
 493         /* Check plane state for visibility and calculate clipping bounds */
 494         err = drm_plane_helper_check_state(state, &clip, 0, INT_MAX,
 495                                            true, true);
 496         if (err < 0)
 497                 return err;
 498
 499         tegra = to_dc_state(crtc_state);
 500
 501         tegra->planes |= WIN_A_ACT_REQ << plane->index;
 502
 503         return 0;
 504 }
 505
 506 static int tegra_plane_atomic_check(struct drm_plane *plane,
 507                                     struct drm_plane_state *state)
 508 {
 509         struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
 510         struct tegra_bo_tiling *tiling = &plane_state->tiling;
 511         struct tegra_plane *tegra = to_tegra_plane(plane);
 512         struct tegra_dc *dc = to_tegra_dc(state->crtc);
 513         int err;
 514
 515         /* no need for further checks if the plane is being disabled */
 516         if (!state->crtc)
 517                 return 0;
 518
 519         err = tegra_dc_format(state->fb->format->format, &plane_state->format,
 520                               &plane_state->swap);
 521         if (err < 0)
 522                 return err;
 523
 524         err = tegra_fb_get_tiling(state->fb, tiling);
 525         if (err < 0)
 526                 return err;
 527
 528         if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
 529             !dc->soc->supports_block_linear) {
 530                 DRM_ERROR("hardware doesn't support block linear mode\n");
 531                 return -EINVAL;
 532         }
 533
 534         /*
 535          * Tegra doesn't support different strides for U and V planes so we
 536          * error out if the user tries to display a framebuffer with such a
 537          * configuration.
 538          */
 539         if (state->fb->format->num_planes > 2) {
 540                 if (state->fb->pitches[2] != state->fb->pitches[1]) {
 541                         DRM_ERROR("unsupported UV-plane configuration\n");
 542                         return -EINVAL;
 543                 }
 544         }
 545
 546         err = tegra_plane_state_add(tegra, state);
 547         if (err < 0)
 548                 return err;
 549
 550         return 0;
 551 }
 552
 553 static void tegra_plane_atomic_disable(struct drm_plane *plane,
 554                                        struct drm_plane_state *old_state)
 555 {
 556         struct tegra_dc *dc = to_tegra_dc(old_state->crtc);
 557         struct tegra_plane *p = to_tegra_plane(plane);
 558         unsigned long flags;
 559         u32 value;
 560
 561         /* rien ne va plus */
 562         if (!old_state || !old_state->crtc)
 563                 return;
 564
 565         spin_lock_irqsave(&dc->lock, flags);
 566
 567         value = WINDOW_A_SELECT << p->index;
 568         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 569
 570         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 571         value &= ~WIN_ENABLE;
 572         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 573
 574         spin_unlock_irqrestore(&dc->lock, flags);
 575 }
 576
 577 static void tegra_plane_atomic_update(struct drm_plane *plane,
 578                                       struct drm_plane_state *old_state)
 579 {
 580         struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
 581         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 582         struct drm_framebuffer *fb = plane->state->fb;
 583         struct tegra_plane *p = to_tegra_plane(plane);
 584         struct tegra_dc_window window;
 585         unsigned int i;
 586
 587         /* rien ne va plus */
 588         if (!plane->state->crtc || !plane->state->fb)
 589                 return;
 590
 591         if (!plane->state->visible)
 592                 return tegra_plane_atomic_disable(plane, old_state);
 593
 594         memset(&window, 0, sizeof(window));
 595         window.src.x = plane->state->src.x1 >> 16;
 596         window.src.y = plane->state->src.y1 >> 16;
 597         window.src.w = drm_rect_width(&plane->state->src) >> 16;
 598         window.src.h = drm_rect_height(&plane->state->src) >> 16;
 599         window.dst.x = plane->state->dst.x1;
 600         window.dst.y = plane->state->dst.y1;
 601         window.dst.w = drm_rect_width(&plane->state->dst);
 602         window.dst.h = drm_rect_height(&plane->state->dst);
 603         window.bits_per_pixel = fb->format->cpp[0] * 8;
 604         window.bottom_up = tegra_fb_is_bottom_up(fb);
 605
 606         /* copy from state */
 607         window.tiling = state->tiling;
 608         window.format = state->format;
 609         window.swap = state->swap;
 610
 611         for (i = 0; i < fb->format->num_planes; i++) {
 612                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 613
 614                 window.base[i] = bo->paddr + fb->offsets[i];
 615
 616                 /*
 617                  * Tegra uses a shared stride for UV planes. Framebuffers are
 618                  * already checked for this in the tegra_plane_atomic_check()
 619                  * function, so it's safe to ignore the V-plane pitch here.
 620                  */
 621                 if (i < 2)
 622                         window.stride[i] = fb->pitches[i];
 623         }
 624
 625         tegra_dc_setup_window(dc, p->index, &window);
 626 }
 627
 628 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
 629         .atomic_check = tegra_plane_atomic_check,
 630         .atomic_disable = tegra_plane_atomic_disable,
 631         .atomic_update = tegra_plane_atomic_update,
 632 };
 633
 634 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
 635                                                        struct tegra_dc *dc)
 636 {
 637         /*
 638          * Ideally this would use drm_crtc_mask(), but that would require the
 639          * CRTC to already be in the mode_config's list of CRTCs. However, it
 640          * will only be added to that list in the drm_crtc_init_with_planes()
 641          * (in tegra_dc_init()), which in turn requires registration of these
 642          * planes. So we have ourselves a nice little chicken and egg problem
 643          * here.
 644          *
 645          * We work around this by manually creating the mask from the number
 646          * of CRTCs that have been registered, and should therefore always be
 647          * the same as drm_crtc_index() after registration.
 648          */
 649         unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
 650         struct tegra_plane *plane;
 651         unsigned int num_formats;
 652         const u32 *formats;
 653         int err;
 654
 655         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 656         if (!plane)
 657                 return ERR_PTR(-ENOMEM);
 658
 659         num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
 660         formats = tegra_primary_plane_formats;
 661
 662         err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
 663                                        &tegra_primary_plane_funcs, formats,
 664                                        num_formats, NULL,
 665                                        DRM_PLANE_TYPE_PRIMARY, NULL);
 666         if (err < 0) {
 667                 kfree(plane);
 668                 return ERR_PTR(err);
 669         }
 670
 671         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
 672
 673         return &plane->base;
 674 }
 675
 676 static const u32 tegra_cursor_plane_formats[] = {
 677         DRM_FORMAT_RGBA8888,
 678 };
 679
 680 static int tegra_cursor_atomic_check(struct drm_plane *plane,
 681                                      struct drm_plane_state *state)
 682 {
 683         struct tegra_plane *tegra = to_tegra_plane(plane);
 684         int err;
 685
 686         /* no need for further checks if the plane is being disabled */
 687         if (!state->crtc)
 688                 return 0;
 689
 690         /* scaling not supported for cursor */
 691         if ((state->src_w >> 16 != state->crtc_w) ||
 692             (state->src_h >> 16 != state->crtc_h))
 693                 return -EINVAL;
 694
 695         /* only square cursors supported */
 696         if (state->src_w != state->src_h)
 697                 return -EINVAL;
 698
 699         if (state->crtc_w != 32 && state->crtc_w != 64 &&
 700             state->crtc_w != 128 && state->crtc_w != 256)
 701                 return -EINVAL;
 702
 703         err = tegra_plane_state_add(tegra, state);
 704         if (err < 0)
 705                 return err;
 706
 707         return 0;
 708 }
 709
 710 static void tegra_cursor_atomic_update(struct drm_plane *plane,
 711                                        struct drm_plane_state *old_state)
 712 {
 713         struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
 714         struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
 715         struct drm_plane_state *state = plane->state;
 716         u32 value = CURSOR_CLIP_DISPLAY;
 717
 718         /* rien ne va plus */
 719         if (!plane->state->crtc || !plane->state->fb)
 720                 return;
 721
 722         switch (state->crtc_w) {
 723         case 32:
 724                 value |= CURSOR_SIZE_32x32;
 725                 break;
 726
 727         case 64:
 728                 value |= CURSOR_SIZE_64x64;
 729                 break;
 730
 731         case 128:
 732                 value |= CURSOR_SIZE_128x128;
 733                 break;
 734
 735         case 256:
 736                 value |= CURSOR_SIZE_256x256;
 737                 break;
 738
 739         default:
 740                 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
 741                      state->crtc_h);
 742                 return;
 743         }
 744
 745         value |= (bo->paddr >> 10) & 0x3fffff;
 746         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
 747
 748 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 749         value = (bo->paddr >> 32) & 0x3;
 750         tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
 751 #endif
 752
 753         /* enable cursor and set blend mode */
 754         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 755         value |= CURSOR_ENABLE;
 756         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 757
 758         value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 759         value &= ~CURSOR_DST_BLEND_MASK;
 760         value &= ~CURSOR_SRC_BLEND_MASK;
 761         value |= CURSOR_MODE_NORMAL;
 762         value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 763         value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 764         value |= CURSOR_ALPHA;
 765         tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 766
 767         /* position the cursor */
 768         value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
 769         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 770 }
 771
 772 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
 773                                         struct drm_plane_state *old_state)
 774 {
 775         struct tegra_dc *dc;
 776         u32 value;
 777
 778         /* rien ne va plus */
 779         if (!old_state || !old_state->crtc)
 780                 return;
 781
 782         dc = to_tegra_dc(old_state->crtc);
 783
 784         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 785         value &= ~CURSOR_ENABLE;
 786         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 787 }
 788
 789 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
 790         .update_plane = drm_atomic_helper_update_plane,
 791         .disable_plane = drm_atomic_helper_disable_plane,
 792         .destroy = tegra_plane_destroy,
 793         .reset = tegra_plane_reset,
 794         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 795         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 796 };
 797
 798 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
 799         .atomic_check = tegra_cursor_atomic_check,
 800         .atomic_update = tegra_cursor_atomic_update,
 801         .atomic_disable = tegra_cursor_atomic_disable,
 802 };
 803
 804 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
 805                                                       struct tegra_dc *dc)
 806 {
 807         struct tegra_plane *plane;
 808         unsigned int num_formats;
 809         const u32 *formats;
 810         int err;
 811
 812         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 813         if (!plane)
 814                 return ERR_PTR(-ENOMEM);
 815
 816         /*
 817          * This index is kind of fake. The cursor isn't a regular plane, but
 818          * its update and activation request bits in DC_CMD_STATE_CONTROL do
 819          * use the same programming. Setting this fake index here allows the
 820          * code in tegra_add_plane_state() to do the right thing without the
 821          * need to special-casing the cursor plane.
 822          */
 823         plane->index = 6;
 824
 825         num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
 826         formats = tegra_cursor_plane_formats;
 827
 828         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 829                                        &tegra_cursor_plane_funcs, formats,
 830                                        num_formats, NULL,
 831                                        DRM_PLANE_TYPE_CURSOR, NULL);
 832         if (err < 0) {
 833                 kfree(plane);
 834                 return ERR_PTR(err);
 835         }
 836
 837         drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
 838
 839         return &plane->base;
 840 }
 841
 842 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
 843 {
 844         tegra_plane_destroy(plane);
 845 }
 846
 847 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
 848         .update_plane = drm_atomic_helper_update_plane,
 849         .disable_plane = drm_atomic_helper_disable_plane,
 850         .destroy = tegra_overlay_plane_destroy,
 851         .reset = tegra_plane_reset,
 852         .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
 853         .atomic_destroy_state = tegra_plane_atomic_destroy_state,
 854 };
 855
 856 static const uint32_t tegra_overlay_plane_formats[] = {
 857         DRM_FORMAT_XBGR8888,
 858         DRM_FORMAT_XRGB8888,
 859         DRM_FORMAT_RGB565,
 860         DRM_FORMAT_UYVY,
 861         DRM_FORMAT_YUYV,
 862         DRM_FORMAT_YUV420,
 863         DRM_FORMAT_YUV422,
 864 };
 865
 866 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
 867                                                        struct tegra_dc *dc,
 868                                                        unsigned int index)
 869 {
 870         struct tegra_plane *plane;
 871         unsigned int num_formats;
 872         const u32 *formats;
 873         int err;
 874
 875         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 876         if (!plane)
 877                 return ERR_PTR(-ENOMEM);
 878
 879         plane->index = index;
 880
 881         num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
 882         formats = tegra_overlay_plane_formats;
 883
 884         err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
 885                                        &tegra_overlay_plane_funcs, formats,
 886                                        num_formats, NULL,
 887                                        DRM_PLANE_TYPE_OVERLAY, NULL);
 888         if (err < 0) {
 889                 kfree(plane);
 890                 return ERR_PTR(err);
 891         }
 892
 893         drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
 894
 895         return &plane->base;
 896 }
 897
 898 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 899 {
 900         struct drm_plane *plane;
 901         unsigned int i;
 902
 903         for (i = 0; i < 2; i++) {
 904                 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
 905                 if (IS_ERR(plane))
 906                         return PTR_ERR(plane);
 907         }
 908
 909         return 0;
 910 }
 911
 912 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
 913 {
 914         struct tegra_dc *dc = to_tegra_dc(crtc);
 915
 916         if (dc->syncpt)
 917                 return host1x_syncpt_read(dc->syncpt);
 918
 919         /* fallback to software emulated VBLANK counter */
 920         return drm_crtc_vblank_count(&dc->base);
 921 }
 922
 923 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
 924 {
 925         struct tegra_dc *dc = to_tegra_dc(crtc);
 926         unsigned long value, flags;
 927
 928         spin_lock_irqsave(&dc->lock, flags);
 929
 930         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 931         value |= VBLANK_INT;
 932         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 933
 934         spin_unlock_irqrestore(&dc->lock, flags);
 935
 936         return 0;
 937 }
 938
 939 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
 940 {
 941         struct tegra_dc *dc = to_tegra_dc(crtc);
 942         unsigned long value, flags;
 943
 944         spin_lock_irqsave(&dc->lock, flags);
 945
 946         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 947         value &= ~VBLANK_INT;
 948         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 949
 950         spin_unlock_irqrestore(&dc->lock, flags);
 951 }
 952
 953 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
 954 {
 955         struct drm_device *drm = dc->base.dev;
 956         struct drm_crtc *crtc = &dc->base;
 957         unsigned long flags, base;
 958         struct tegra_bo *bo;
 959
 960         spin_lock_irqsave(&drm->event_lock, flags);
 961
 962         if (!dc->event) {
 963                 spin_unlock_irqrestore(&drm->event_lock, flags);
 964                 return;
 965         }
 966
 967         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 968
 969         spin_lock(&dc->lock);
 970
 971         /* check if new start address has been latched */
 972         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 973         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 974         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
 975         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 976
 977         spin_unlock(&dc->lock);
 978
 979         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
 980                 drm_crtc_send_vblank_event(crtc, dc->event);
 981                 drm_crtc_vblank_put(crtc);
 982                 dc->event = NULL;
 983         }
 984
 985         spin_unlock_irqrestore(&drm->event_lock, flags);
 986 }
 987
 988 static void tegra_dc_destroy(struct drm_crtc *crtc)
 989 {
 990         drm_crtc_cleanup(crtc);
 991 }
 992
 993 static void tegra_crtc_reset(struct drm_crtc *crtc)
 994 {
 995         struct tegra_dc_state *state;
 996
 997         if (crtc->state)
 998                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 999
1000         kfree(crtc->state);
1001         crtc->state = NULL;
1002
1003         state = kzalloc(sizeof(*state), GFP_KERNEL);
1004         if (state) {
1005                 crtc->state = &state->base;
1006                 crtc->state->crtc = crtc;
1007         }
1008
1009         drm_crtc_vblank_reset(crtc);
1010 }
1011
1012 static struct drm_crtc_state *
1013 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1014 {
1015         struct tegra_dc_state *state = to_dc_state(crtc->state);
1016         struct tegra_dc_state *copy;
1017
1018         copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1019         if (!copy)
1020                 return NULL;
1021
1022         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
1023         copy->clk = state->clk;
1024         copy->pclk = state->pclk;
1025         copy->div = state->div;
1026         copy->planes = state->planes;
1027
1028         return &copy->base;
1029 }
1030
1031 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1032                                             struct drm_crtc_state *state)
1033 {
1034         __drm_atomic_helper_crtc_destroy_state(state);
1035         kfree(state);
1036 }
1037
1038 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1039         .page_flip = drm_atomic_helper_page_flip,
1040         .set_config = drm_atomic_helper_set_config,
1041         .destroy = tegra_dc_destroy,
1042         .reset = tegra_crtc_reset,
1043         .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1044         .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1045         .get_vblank_counter = tegra_dc_get_vblank_counter,
1046         .enable_vblank = tegra_dc_enable_vblank,
1047         .disable_vblank = tegra_dc_disable_vblank,
1048 };
1049
1050 static int tegra_dc_set_timings(struct tegra_dc *dc,
1051                                 struct drm_display_mode *mode)
1052 {
1053         unsigned int h_ref_to_sync = 1;
1054         unsigned int v_ref_to_sync = 1;
1055         unsigned long value;
1056
1057         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1058
1059         value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1061
1062         value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063                 ((mode->hsync_end - mode->hsync_start) <<  0);
1064         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1065
1066         value = ((mode->vtotal - mode->vsync_end) << 16) |
1067                 ((mode->htotal - mode->hsync_end) <<  0);
1068         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1069
1070         value = ((mode->vsync_start - mode->vdisplay) << 16) |
1071                 ((mode->hsync_start - mode->hdisplay) <<  0);
1072         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1073
1074         value = (mode->vdisplay << 16) | mode->hdisplay;
1075         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1076
1077         return 0;
1078 }
1079
1080 /**
1081  * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1082  *     state
1083  * @dc: display controller
1084  * @crtc_state: CRTC atomic state
1085  * @clk: parent clock for display controller
1086  * @pclk: pixel clock
1087  * @div: shift clock divider
1088  *
1089  * Returns:
1090  * 0 on success or a negative error-code on failure.
1091  */
1092 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1093                                struct drm_crtc_state *crtc_state,
1094                                struct clk *clk, unsigned long pclk,
1095                                unsigned int div)
1096 {
1097         struct tegra_dc_state *state = to_dc_state(crtc_state);
1098
1099         if (!clk_has_parent(dc->clk, clk))
1100                 return -EINVAL;
1101
1102         state->clk = clk;
1103         state->pclk = pclk;
1104         state->div = div;
1105
1106         return 0;
1107 }
1108
1109 static void tegra_dc_commit_state(struct tegra_dc *dc,
1110                                   struct tegra_dc_state *state)
1111 {
1112         u32 value;
1113         int err;
1114
1115         err = clk_set_parent(dc->clk, state->clk);
1116         if (err < 0)
1117                 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1118
1119         /*
1120          * Outputs may not want to change the parent clock rate. This is only
1121          * relevant to Tegra20 where only a single display PLL is available.
1122          * Since that PLL would typically be used for HDMI, an internal LVDS
1123          * panel would need to be driven by some other clock such as PLL_P
1124          * which is shared with other peripherals. Changing the clock rate
1125          * should therefore be avoided.
1126          */
1127         if (state->pclk > 0) {
1128                 err = clk_set_rate(state->clk, state->pclk);
1129                 if (err < 0)
1130                         dev_err(dc->dev,
1131                                 "failed to set clock rate to %lu Hz\n",
1132                                 state->pclk);
1133         }
1134
1135         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1136                       state->div);
1137         DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1138
1139         value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1140         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1141
1142         err = clk_set_rate(dc->clk, state->pclk);
1143         if (err < 0)
1144                 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1145                         dc->clk, state->pclk, err);
1146 }
1147
1148 static void tegra_dc_stop(struct tegra_dc *dc)
1149 {
1150         u32 value;
1151
1152         /* stop the display controller */
1153         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1154         value &= ~DISP_CTRL_MODE_MASK;
1155         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1156
1157         tegra_dc_commit(dc);
1158 }
1159
1160 static bool tegra_dc_idle(struct tegra_dc *dc)
1161 {
1162         u32 value;
1163
1164         value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1165
1166         return (value & DISP_CTRL_MODE_MASK) == 0;
1167 }
1168
1169 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1170 {
1171         timeout = jiffies + msecs_to_jiffies(timeout);
1172
1173         while (time_before(jiffies, timeout)) {
1174                 if (tegra_dc_idle(dc))
1175                         return 0;
1176
1177                 usleep_range(1000, 2000);
1178         }
1179
1180         dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1181         return -ETIMEDOUT;
1182 }
1183
1184 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1185                                       struct drm_crtc_state *old_state)
1186 {
1187         struct tegra_dc *dc = to_tegra_dc(crtc);
1188         u32 value;
1189
1190         if (!tegra_dc_idle(dc)) {
1191                 tegra_dc_stop(dc);
1192
1193                 /*
1194                  * Ignore the return value, there isn't anything useful to do
1195                  * in case this fails.
1196                  */
1197                 tegra_dc_wait_idle(dc, 100);
1198         }
1199
1200         /*
1201          * This should really be part of the RGB encoder driver, but clearing
1202          * these bits has the side-effect of stopping the display controller.
1203          * When that happens no VBLANK interrupts will be raised. At the same
1204          * time the encoder is disabled before the display controller, so the
1205          * above code is always going to timeout waiting for the controller
1206          * to go idle.
1207          *
1208          * Given the close coupling between the RGB encoder and the display
1209          * controller doing it here is still kind of okay. None of the other
1210          * encoder drivers require these bits to be cleared.
1211          *
1212          * XXX: Perhaps given that the display controller is switched off at
1213          * this point anyway maybe clearing these bits isn't even useful for
1214          * the RGB encoder?
1215          */
1216         if (dc->rgb) {
1217                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1218                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1219                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1220                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1221         }
1222
1223         tegra_dc_stats_reset(&dc->stats);
1224         drm_crtc_vblank_off(crtc);
1225
1226         pm_runtime_put_sync(dc->dev);
1227 }
1228
1229 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1230                                      struct drm_crtc_state *old_state)
1231 {
1232         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1233         struct tegra_dc_state *state = to_dc_state(crtc->state);
1234         struct tegra_dc *dc = to_tegra_dc(crtc);
1235         u32 value;
1236
1237         pm_runtime_get_sync(dc->dev);
1238
1239         /* initialize display controller */
1240         if (dc->syncpt) {
1241                 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1242
1243                 value = SYNCPT_CNTRL_NO_STALL;
1244                 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1245
1246                 value = SYNCPT_VSYNC_ENABLE | syncpt;
1247                 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1248         }
1249
1250         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1251                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1252         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1253
1254         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1255                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1256         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1257
1258         /* initialize timer */
1259         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1260                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1261         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1262
1263         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1264                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1265         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1266
1267         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1268                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1269         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1270
1271         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1272                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1273         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1274
1275         if (dc->soc->supports_border_color)
1276                 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1277
1278         /* apply PLL and pixel clock changes */
1279         tegra_dc_commit_state(dc, state);
1280
1281         /* program display mode */
1282         tegra_dc_set_timings(dc, mode);
1283
1284         /* interlacing isn't supported yet, so disable it */
1285         if (dc->soc->supports_interlacing) {
1286                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1287                 value &= ~INTERLACE_ENABLE;
1288                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1289         }
1290
1291         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1292         value &= ~DISP_CTRL_MODE_MASK;
1293         value |= DISP_CTRL_MODE_C_DISPLAY;
1294         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1295
1296         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1297         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1298                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1299         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1300
1301         tegra_dc_commit(dc);
1302
1303         drm_crtc_vblank_on(crtc);
1304 }
1305
1306 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1307                                    struct drm_crtc_state *state)
1308 {
1309         return 0;
1310 }
1311
1312 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1313                                     struct drm_crtc_state *old_crtc_state)
1314 {
1315         struct tegra_dc *dc = to_tegra_dc(crtc);
1316
1317         if (crtc->state->event) {
1318                 crtc->state->event->pipe = drm_crtc_index(crtc);
1319
1320                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1321
1322                 dc->event = crtc->state->event;
1323                 crtc->state->event = NULL;
1324         }
1325 }
1326
1327 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1328                                     struct drm_crtc_state *old_crtc_state)
1329 {
1330         struct tegra_dc_state *state = to_dc_state(crtc->state);
1331         struct tegra_dc *dc = to_tegra_dc(crtc);
1332
1333         tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1334         tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1335 }
1336
1337 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1338         .atomic_check = tegra_crtc_atomic_check,
1339         .atomic_begin = tegra_crtc_atomic_begin,
1340         .atomic_flush = tegra_crtc_atomic_flush,
1341         .atomic_enable = tegra_crtc_atomic_enable,
1342         .atomic_disable = tegra_crtc_atomic_disable,
1343 };
1344
1345 static irqreturn_t tegra_dc_irq(int irq, void *data)
1346 {
1347         struct tegra_dc *dc = data;
1348         unsigned long status;
1349
1350         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1351         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1352
1353         if (status & FRAME_END_INT) {
1354                 /*
1355                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1356                 */
1357                 dc->stats.frames++;
1358         }
1359
1360         if (status & VBLANK_INT) {
1361                 /*
1362                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1363                 */
1364                 drm_crtc_handle_vblank(&dc->base);
1365                 tegra_dc_finish_page_flip(dc);
1366                 dc->stats.vblank++;
1367         }
1368
1369         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1370                 /*
1371                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1372                 */
1373                 dc->stats.underflow++;
1374         }
1375
1376         if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1377                 /*
1378                 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1379                 */
1380                 dc->stats.overflow++;
1381         }
1382
1383         return IRQ_HANDLED;
1384 }
1385
1386 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1387 {
1388         struct drm_info_node *node = s->private;
1389         struct tegra_dc *dc = node->info_ent->data;
1390         int err = 0;
1391
1392         drm_modeset_lock(&dc->base.mutex, NULL);
1393
1394         if (!dc->base.state->active) {
1395                 err = -EBUSY;
1396                 goto unlock;
1397         }
1398
1399 #define DUMP_REG(name)                                          \
1400         seq_printf(s, "%-40s %#05x %08x\n", #name, name,        \
1401                    tegra_dc_readl(dc, name))
1402
1403         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1404         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1405         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1406         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1407         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1408         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1409         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1410         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1411         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1412         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1413         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1414         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1415         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1416         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1417         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1418         DUMP_REG(DC_CMD_SIGNAL_RAISE);
1419         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1420         DUMP_REG(DC_CMD_INT_STATUS);
1421         DUMP_REG(DC_CMD_INT_MASK);
1422         DUMP_REG(DC_CMD_INT_ENABLE);
1423         DUMP_REG(DC_CMD_INT_TYPE);
1424         DUMP_REG(DC_CMD_INT_POLARITY);
1425         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1426         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1427         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1428         DUMP_REG(DC_CMD_STATE_ACCESS);
1429         DUMP_REG(DC_CMD_STATE_CONTROL);
1430         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1431         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1432         DUMP_REG(DC_COM_CRC_CONTROL);
1433         DUMP_REG(DC_COM_CRC_CHECKSUM);
1434         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1435         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1436         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1437         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1438         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1439         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1440         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1441         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1442         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1443         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1444         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1445         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1446         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1447         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1448         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1449         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1450         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1451         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1452         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1453         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1454         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1455         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1456         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1457         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1458         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1459         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1460         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1461         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1462         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1463         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1464         DUMP_REG(DC_COM_SPI_CONTROL);
1465         DUMP_REG(DC_COM_SPI_START_BYTE);
1466         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1467         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1468         DUMP_REG(DC_COM_HSPI_CS_DC);
1469         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1470         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1471         DUMP_REG(DC_COM_GPIO_CTRL);
1472         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1473         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1474         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1475         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1476         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1477         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1478         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1479         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1480         DUMP_REG(DC_DISP_REF_TO_SYNC);
1481         DUMP_REG(DC_DISP_SYNC_WIDTH);
1482         DUMP_REG(DC_DISP_BACK_PORCH);
1483         DUMP_REG(DC_DISP_ACTIVE);
1484         DUMP_REG(DC_DISP_FRONT_PORCH);
1485         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1486         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1487         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1488         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1489         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1490         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1491         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1492         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1493         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1494         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1495         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1496         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1497         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1498         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1499         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1500         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1501         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1502         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1503         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1504         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1505         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1506         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1507         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1508         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1509         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1510         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1511         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1512         DUMP_REG(DC_DISP_M0_CONTROL);
1513         DUMP_REG(DC_DISP_M1_CONTROL);
1514         DUMP_REG(DC_DISP_DI_CONTROL);
1515         DUMP_REG(DC_DISP_PP_CONTROL);
1516         DUMP_REG(DC_DISP_PP_SELECT_A);
1517         DUMP_REG(DC_DISP_PP_SELECT_B);
1518         DUMP_REG(DC_DISP_PP_SELECT_C);
1519         DUMP_REG(DC_DISP_PP_SELECT_D);
1520         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1521         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1522         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1523         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1524         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1525         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1526         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1527         DUMP_REG(DC_DISP_BORDER_COLOR);
1528         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1529         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1530         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1531         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1532         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1533         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1534         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1535         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1536         DUMP_REG(DC_DISP_CURSOR_POSITION);
1537         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1538         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1539         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1540         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1541         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1542         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1543         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1544         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1545         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1546         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1547         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1548         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1549         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1550         DUMP_REG(DC_DISP_SD_CONTROL);
1551         DUMP_REG(DC_DISP_SD_CSC_COEFF);
1552         DUMP_REG(DC_DISP_SD_LUT(0));
1553         DUMP_REG(DC_DISP_SD_LUT(1));
1554         DUMP_REG(DC_DISP_SD_LUT(2));
1555         DUMP_REG(DC_DISP_SD_LUT(3));
1556         DUMP_REG(DC_DISP_SD_LUT(4));
1557         DUMP_REG(DC_DISP_SD_LUT(5));
1558         DUMP_REG(DC_DISP_SD_LUT(6));
1559         DUMP_REG(DC_DISP_SD_LUT(7));
1560         DUMP_REG(DC_DISP_SD_LUT(8));
1561         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1562         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1563         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1564         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1565         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1566         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1567         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1568         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1569         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1570         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1571         DUMP_REG(DC_DISP_SD_BL_TF(0));
1572         DUMP_REG(DC_DISP_SD_BL_TF(1));
1573         DUMP_REG(DC_DISP_SD_BL_TF(2));
1574         DUMP_REG(DC_DISP_SD_BL_TF(3));
1575         DUMP_REG(DC_DISP_SD_BL_CONTROL);
1576         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1577         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1578         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1579         DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1580         DUMP_REG(DC_WIN_WIN_OPTIONS);
1581         DUMP_REG(DC_WIN_BYTE_SWAP);
1582         DUMP_REG(DC_WIN_BUFFER_CONTROL);
1583         DUMP_REG(DC_WIN_COLOR_DEPTH);
1584         DUMP_REG(DC_WIN_POSITION);
1585         DUMP_REG(DC_WIN_SIZE);
1586         DUMP_REG(DC_WIN_PRESCALED_SIZE);
1587         DUMP_REG(DC_WIN_H_INITIAL_DDA);
1588         DUMP_REG(DC_WIN_V_INITIAL_DDA);
1589         DUMP_REG(DC_WIN_DDA_INC);
1590         DUMP_REG(DC_WIN_LINE_STRIDE);
1591         DUMP_REG(DC_WIN_BUF_STRIDE);
1592         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1593         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1594         DUMP_REG(DC_WIN_DV_CONTROL);
1595         DUMP_REG(DC_WIN_BLEND_NOKEY);
1596         DUMP_REG(DC_WIN_BLEND_1WIN);
1597         DUMP_REG(DC_WIN_BLEND_2WIN_X);
1598         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1599         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1600         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1601         DUMP_REG(DC_WINBUF_START_ADDR);
1602         DUMP_REG(DC_WINBUF_START_ADDR_NS);
1603         DUMP_REG(DC_WINBUF_START_ADDR_U);
1604         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1605         DUMP_REG(DC_WINBUF_START_ADDR_V);
1606         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1607         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1608         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1609         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1610         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1611         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1612         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1613         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1614         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1615
1616 #undef DUMP_REG
1617
1618 unlock:
1619         drm_modeset_unlock(&dc->base.mutex);
1620         return err;
1621 }
1622
1623 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1624 {
1625         struct drm_info_node *node = s->private;
1626         struct tegra_dc *dc = node->info_ent->data;
1627         int err = 0;
1628         u32 value;
1629
1630         drm_modeset_lock(&dc->base.mutex, NULL);
1631
1632         if (!dc->base.state->active) {
1633                 err = -EBUSY;
1634                 goto unlock;
1635         }
1636
1637         value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1638         tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1639         tegra_dc_commit(dc);
1640
1641         drm_crtc_wait_one_vblank(&dc->base);
1642         drm_crtc_wait_one_vblank(&dc->base);
1643
1644         value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1645         seq_printf(s, "%08x\n", value);
1646
1647         tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1648
1649 unlock:
1650         drm_modeset_unlock(&dc->base.mutex);
1651         return err;
1652 }
1653
1654 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1655 {
1656         struct drm_info_node *node = s->private;
1657         struct tegra_dc *dc = node->info_ent->data;
1658
1659         seq_printf(s, "frames: %lu\n", dc->stats.frames);
1660         seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1661         seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1662         seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1663
1664         return 0;
1665 }
1666
1667 static struct drm_info_list debugfs_files[] = {
1668         { "regs", tegra_dc_show_regs, 0, NULL },
1669         { "crc", tegra_dc_show_crc, 0, NULL },
1670         { "stats", tegra_dc_show_stats, 0, NULL },
1671 };
1672
1673 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1674 {
1675         unsigned int i;
1676         char *name;
1677         int err;
1678
1679         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1680         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1681         kfree(name);
1682
1683         if (!dc->debugfs)
1684                 return -ENOMEM;
1685
1686         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1687                                     GFP_KERNEL);
1688         if (!dc->debugfs_files) {
1689                 err = -ENOMEM;
1690                 goto remove;
1691         }
1692
1693         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1694                 dc->debugfs_files[i].data = dc;
1695
1696         err = drm_debugfs_create_files(dc->debugfs_files,
1697                                        ARRAY_SIZE(debugfs_files),
1698                                        dc->debugfs, minor);
1699         if (err < 0)
1700                 goto free;
1701
1702         dc->minor = minor;
1703
1704         return 0;
1705
1706 free:
1707         kfree(dc->debugfs_files);
1708         dc->debugfs_files = NULL;
1709 remove:
1710         debugfs_remove(dc->debugfs);
1711         dc->debugfs = NULL;
1712
1713         return err;
1714 }
1715
1716 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1717 {
1718         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1719                                  dc->minor);
1720         dc->minor = NULL;
1721
1722         kfree(dc->debugfs_files);
1723         dc->debugfs_files = NULL;
1724
1725         debugfs_remove(dc->debugfs);
1726         dc->debugfs = NULL;
1727
1728         return 0;
1729 }
1730
1731 static int tegra_dc_init(struct host1x_client *client)
1732 {
1733         struct drm_device *drm = dev_get_drvdata(client->parent);
1734         unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1735         struct tegra_dc *dc = host1x_client_to_dc(client);
1736         struct tegra_drm *tegra = drm->dev_private;
1737         struct drm_plane *primary = NULL;
1738         struct drm_plane *cursor = NULL;
1739         int err;
1740
1741         dc->syncpt = host1x_syncpt_request(client, flags);
1742         if (!dc->syncpt)
1743                 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1744
1745         if (tegra->domain) {
1746                 err = iommu_attach_device(tegra->domain, dc->dev);
1747                 if (err < 0) {
1748                         dev_err(dc->dev, "failed to attach to domain: %d\n",
1749                                 err);
1750                         return err;
1751                 }
1752
1753                 dc->domain = tegra->domain;
1754         }
1755
1756         primary = tegra_dc_primary_plane_create(drm, dc);
1757         if (IS_ERR(primary)) {
1758                 err = PTR_ERR(primary);
1759                 goto cleanup;
1760         }
1761
1762         if (dc->soc->supports_cursor) {
1763                 cursor = tegra_dc_cursor_plane_create(drm, dc);
1764                 if (IS_ERR(cursor)) {
1765                         err = PTR_ERR(cursor);
1766                         goto cleanup;
1767                 }
1768         }
1769
1770         err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1771                                         &tegra_crtc_funcs, NULL);
1772         if (err < 0)
1773                 goto cleanup;
1774
1775         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1776
1777         /*
1778          * Keep track of the minimum pitch alignment across all display
1779          * controllers.
1780          */
1781         if (dc->soc->pitch_align > tegra->pitch_align)
1782                 tegra->pitch_align = dc->soc->pitch_align;
1783
1784         err = tegra_dc_rgb_init(drm, dc);
1785         if (err < 0 && err != -ENODEV) {
1786                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1787                 goto cleanup;
1788         }
1789
1790         err = tegra_dc_add_planes(drm, dc);
1791         if (err < 0)
1792                 goto cleanup;
1793
1794         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1795                 err = tegra_dc_debugfs_init(dc, drm->primary);
1796                 if (err < 0)
1797                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1798         }
1799
1800         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1801                                dev_name(dc->dev), dc);
1802         if (err < 0) {
1803                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1804                         err);
1805                 goto cleanup;
1806         }
1807
1808         return 0;
1809
1810 cleanup:
1811         if (cursor)
1812                 drm_plane_cleanup(cursor);
1813
1814         if (primary)
1815                 drm_plane_cleanup(primary);
1816
1817         if (tegra->domain) {
1818                 iommu_detach_device(tegra->domain, dc->dev);
1819                 dc->domain = NULL;
1820         }
1821
1822         return err;
1823 }
1824
1825 static int tegra_dc_exit(struct host1x_client *client)
1826 {
1827         struct tegra_dc *dc = host1x_client_to_dc(client);
1828         int err;
1829
1830         devm_free_irq(dc->dev, dc->irq, dc);
1831
1832         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1833                 err = tegra_dc_debugfs_exit(dc);
1834                 if (err < 0)
1835                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1836         }
1837
1838         err = tegra_dc_rgb_exit(dc);
1839         if (err) {
1840                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1841                 return err;
1842         }
1843
1844         if (dc->domain) {
1845                 iommu_detach_device(dc->domain, dc->dev);
1846                 dc->domain = NULL;
1847         }
1848
1849         host1x_syncpt_free(dc->syncpt);
1850
1851         return 0;
1852 }
1853
1854 static const struct host1x_client_ops dc_client_ops = {
1855         .init = tegra_dc_init,
1856         .exit = tegra_dc_exit,
1857 };
1858
1859 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1860         .supports_border_color = true,
1861         .supports_interlacing = false,
1862         .supports_cursor = false,
1863         .supports_block_linear = false,
1864         .pitch_align = 8,
1865         .has_powergate = false,
1866         .broken_reset = true,
1867 };
1868
1869 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1870         .supports_border_color = true,
1871         .supports_interlacing = false,
1872         .supports_cursor = false,
1873         .supports_block_linear = false,
1874         .pitch_align = 8,
1875         .has_powergate = false,
1876         .broken_reset = false,
1877 };
1878
1879 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1880         .supports_border_color = true,
1881         .supports_interlacing = false,
1882         .supports_cursor = false,
1883         .supports_block_linear = false,
1884         .pitch_align = 64,
1885         .has_powergate = true,
1886         .broken_reset = false,
1887 };
1888
1889 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1890         .supports_border_color = false,
1891         .supports_interlacing = true,
1892         .supports_cursor = true,
1893         .supports_block_linear = true,
1894         .pitch_align = 64,
1895         .has_powergate = true,
1896         .broken_reset = false,
1897 };
1898
1899 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1900         .supports_border_color = false,
1901         .supports_interlacing = true,
1902         .supports_cursor = true,
1903         .supports_block_linear = true,
1904         .pitch_align = 64,
1905         .has_powergate = true,
1906         .broken_reset = false,
1907 };
1908
1909 static const struct of_device_id tegra_dc_of_match[] = {
1910         {
1911                 .compatible = "nvidia,tegra210-dc",
1912                 .data = &tegra210_dc_soc_info,
1913         }, {
1914                 .compatible = "nvidia,tegra124-dc",
1915                 .data = &tegra124_dc_soc_info,
1916         }, {
1917                 .compatible = "nvidia,tegra114-dc",
1918                 .data = &tegra114_dc_soc_info,
1919         }, {
1920                 .compatible = "nvidia,tegra30-dc",
1921                 .data = &tegra30_dc_soc_info,
1922         }, {
1923                 .compatible = "nvidia,tegra20-dc",
1924                 .data = &tegra20_dc_soc_info,
1925         }, {
1926                 /* sentinel */
1927         }
1928 };
1929 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1930
1931 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1932 {
1933         struct device_node *np;
1934         u32 value = 0;
1935         int err;
1936
1937         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1938         if (err < 0) {
1939                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1940
1941                 /*
1942                  * If the nvidia,head property isn't present, try to find the
1943                  * correct head number by looking up the position of this
1944                  * display controller's node within the device tree. Assuming
1945                  * that the nodes are ordered properly in the DTS file and
1946                  * that the translation into a flattened device tree blob
1947                  * preserves that ordering this will actually yield the right
1948                  * head number.
1949                  *
1950                  * If those assumptions don't hold, this will still work for
1951                  * cases where only a single display controller is used.
1952                  */
1953                 for_each_matching_node(np, tegra_dc_of_match) {
1954                         if (np == dc->dev->of_node) {
1955                                 of_node_put(np);
1956                                 break;
1957                         }
1958
1959                         value++;
1960                 }
1961         }
1962
1963         dc->pipe = value;
1964
1965         return 0;
1966 }
1967
1968 static int tegra_dc_probe(struct platform_device *pdev)
1969 {
1970         struct resource *regs;
1971         struct tegra_dc *dc;
1972         int err;
1973
1974         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1975         if (!dc)
1976                 return -ENOMEM;
1977
1978         dc->soc = of_device_get_match_data(&pdev->dev);
1979
1980         spin_lock_init(&dc->lock);
1981         INIT_LIST_HEAD(&dc->list);
1982         dc->dev = &pdev->dev;
1983
1984         err = tegra_dc_parse_dt(dc);
1985         if (err < 0)
1986                 return err;
1987
1988         dc->clk = devm_clk_get(&pdev->dev, NULL);
1989         if (IS_ERR(dc->clk)) {
1990                 dev_err(&pdev->dev, "failed to get clock\n");
1991                 return PTR_ERR(dc->clk);
1992         }
1993
1994         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1995         if (IS_ERR(dc->rst)) {
1996                 dev_err(&pdev->dev, "failed to get reset\n");
1997                 return PTR_ERR(dc->rst);
1998         }
1999
2000         /* assert reset and disable clock */
2001         if (!dc->soc->broken_reset) {
2002                 err = clk_prepare_enable(dc->clk);
2003                 if (err < 0)
2004                         return err;
2005
2006                 usleep_range(2000, 4000);
2007
2008                 err = reset_control_assert(dc->rst);
2009                 if (err < 0)
2010                         return err;
2011
2012                 usleep_range(2000, 4000);
2013
2014                 clk_disable_unprepare(dc->clk);
2015         }
2016
2017         if (dc->soc->has_powergate) {
2018                 if (dc->pipe == 0)
2019                         dc->powergate = TEGRA_POWERGATE_DIS;
2020                 else
2021                         dc->powergate = TEGRA_POWERGATE_DISB;
2022
2023                 tegra_powergate_power_off(dc->powergate);
2024         }
2025
2026         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2027         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2028         if (IS_ERR(dc->regs))
2029                 return PTR_ERR(dc->regs);
2030
2031         dc->irq = platform_get_irq(pdev, 0);
2032         if (dc->irq < 0) {
2033                 dev_err(&pdev->dev, "failed to get IRQ\n");
2034                 return -ENXIO;
2035         }
2036
2037         err = tegra_dc_rgb_probe(dc);
2038         if (err < 0 && err != -ENODEV) {
2039                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2040                 return err;
2041         }
2042
2043         platform_set_drvdata(pdev, dc);
2044         pm_runtime_enable(&pdev->dev);
2045
2046         INIT_LIST_HEAD(&dc->client.list);
2047         dc->client.ops = &dc_client_ops;
2048         dc->client.dev = &pdev->dev;
2049
2050         err = host1x_client_register(&dc->client);
2051         if (err < 0) {
2052                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2053                         err);
2054                 return err;
2055         }
2056
2057         return 0;
2058 }
2059
2060 static int tegra_dc_remove(struct platform_device *pdev)
2061 {
2062         struct tegra_dc *dc = platform_get_drvdata(pdev);
2063         int err;
2064
2065         err = host1x_client_unregister(&dc->client);
2066         if (err < 0) {
2067                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2068                         err);
2069                 return err;
2070         }
2071
2072         err = tegra_dc_rgb_remove(dc);
2073         if (err < 0) {
2074                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2075                 return err;
2076         }
2077
2078         pm_runtime_disable(&pdev->dev);
2079
2080         return 0;
2081 }
2082
2083 #ifdef CONFIG_PM
2084 static int tegra_dc_suspend(struct device *dev)
2085 {
2086         struct tegra_dc *dc = dev_get_drvdata(dev);
2087         int err;
2088
2089         if (!dc->soc->broken_reset) {
2090                 err = reset_control_assert(dc->rst);
2091                 if (err < 0) {
2092                         dev_err(dev, "failed to assert reset: %d\n", err);
2093                         return err;
2094                 }
2095         }
2096
2097         if (dc->soc->has_powergate)
2098                 tegra_powergate_power_off(dc->powergate);
2099
2100         clk_disable_unprepare(dc->clk);
2101
2102         return 0;
2103 }
2104
2105 static int tegra_dc_resume(struct device *dev)
2106 {
2107         struct tegra_dc *dc = dev_get_drvdata(dev);
2108         int err;
2109
2110         if (dc->soc->has_powergate) {
2111                 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2112                                                         dc->rst);
2113                 if (err < 0) {
2114                         dev_err(dev, "failed to power partition: %d\n", err);
2115                         return err;
2116                 }
2117         } else {
2118                 err = clk_prepare_enable(dc->clk);
2119                 if (err < 0) {
2120                         dev_err(dev, "failed to enable clock: %d\n", err);
2121                         return err;
2122                 }
2123
2124                 if (!dc->soc->broken_reset) {
2125                         err = reset_control_deassert(dc->rst);
2126                         if (err < 0) {
2127                                 dev_err(dev,
2128                                         "failed to deassert reset: %d\n", err);
2129                                 return err;
2130                         }
2131                 }
2132         }
2133
2134         return 0;
2135 }
2136 #endif
2137
2138 static const struct dev_pm_ops tegra_dc_pm_ops = {
2139         SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2140 };
2141
2142 struct platform_driver tegra_dc_driver = {
2143         .driver = {
2144                 .name = "tegra-dc",
2145                 .of_match_table = tegra_dc_of_match,
2146                 .pm = &tegra_dc_pm_ops,
2147         },
2148         .probe = tegra_dc_probe,
2149         .remove = tegra_dc_remove,
2150 };