drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <[email protected]>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  *
  13  * Some ideas are from old omap-sha1-md5.c driver.
  14  */
  15
  16 #define pr_fmt(fmt) "%s: " fmt, __func__
  17
  18 #include <linux/err.h>
  19 #include <linux/device.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/clk.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/crypto.h>
  33 #include <linux/cryptohash.h>
  34 #include <crypto/scatterwalk.h>
  35 #include <crypto/algapi.h>
  36 #include <crypto/sha.h>
  37 #include <crypto/hash.h>
  38 #include <crypto/internal/hash.h>
  39
  40 #include <linux/omap-dma.h>
  41
  42 #ifdef CONFIG_ARCH_OMAP1
  43 #include <mach/irqs.h>
  44 #endif
  45
  46 #define SHA_REG_DIGEST(x)               (0x00 + ((x) * 0x04))
  47 #define SHA_REG_DIN(x)                  (0x1C + ((x) * 0x04))
  48
  49 #define SHA1_MD5_BLOCK_SIZE             SHA1_BLOCK_SIZE
  50 #define MD5_DIGEST_SIZE                 16
  51
  52 #define SHA_REG_DIGCNT                  0x14
  53
  54 #define SHA_REG_CTRL                    0x18
  55 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  56 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  57 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  58 #define SHA_REG_CTRL_ALGO               (1 << 2)
  59 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  60 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  61
  62 #define SHA_REG_REV                     0x5C
  63 #define SHA_REG_REV_MAJOR               0xF0
  64 #define SHA_REG_REV_MINOR               0x0F
  65
  66 #define SHA_REG_MASK                    0x60
  67 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  68 #define SHA_REG_MASK_IT_EN              (1 << 2)
  69 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  70 #define SHA_REG_AUTOIDLE                (1 << 0)
  71
  72 #define SHA_REG_SYSSTATUS               0x64
  73 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  74
  75 #define DEFAULT_TIMEOUT_INTERVAL        HZ
  76
  77 /* mostly device flags */
  78 #define FLAGS_BUSY              0
  79 #define FLAGS_FINAL             1
  80 #define FLAGS_DMA_ACTIVE        2
  81 #define FLAGS_OUTPUT_READY      3
  82 #define FLAGS_INIT              4
  83 #define FLAGS_CPU               5
  84 #define FLAGS_DMA_READY         6
  85 /* context flags */
  86 #define FLAGS_FINUP             16
  87 #define FLAGS_SG                17
  88 #define FLAGS_SHA1              18
  89 #define FLAGS_HMAC              19
  90 #define FLAGS_ERROR             20
  91
  92 #define OP_UPDATE       1
  93 #define OP_FINAL        2
  94
  95 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
  96 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
  97
  98 #define BUFLEN          PAGE_SIZE
  99
 100 struct omap_sham_dev;
 101
 102 struct omap_sham_reqctx {
 103         struct omap_sham_dev    *dd;
 104         unsigned long           flags;
 105         unsigned long           op;
 106
 107         u8                      digest[SHA1_DIGEST_SIZE] OMAP_ALIGNED;
 108         size_t                  digcnt;
 109         size_t                  bufcnt;
 110         size_t                  buflen;
 111         dma_addr_t              dma_addr;
 112
 113         /* walk state */
 114         struct scatterlist      *sg;
 115         unsigned int            offset; /* offset in current sg */
 116         unsigned int            total;  /* total request */
 117
 118         u8                      buffer[0] OMAP_ALIGNED;
 119 };
 120
 121 struct omap_sham_hmac_ctx {
 122         struct crypto_shash     *shash;
 123         u8                      ipad[SHA1_MD5_BLOCK_SIZE];
 124         u8                      opad[SHA1_MD5_BLOCK_SIZE];
 125 };
 126
 127 struct omap_sham_ctx {
 128         struct omap_sham_dev    *dd;
 129
 130         unsigned long           flags;
 131
 132         /* fallback stuff */
 133         struct crypto_shash     *fallback;
 134
 135         struct omap_sham_hmac_ctx base[0];
 136 };
 137
 138 #define OMAP_SHAM_QUEUE_LENGTH  1
 139
 140 struct omap_sham_dev {
 141         struct list_head        list;
 142         unsigned long           phys_base;
 143         struct device           *dev;
 144         void __iomem            *io_base;
 145         int                     irq;
 146         struct clk              *iclk;
 147         spinlock_t              lock;
 148         int                     err;
 149         int                     dma;
 150         int                     dma_lch;
 151         struct tasklet_struct   done_task;
 152
 153         unsigned long           flags;
 154         struct crypto_queue     queue;
 155         struct ahash_request    *req;
 156 };
 157
 158 struct omap_sham_drv {
 159         struct list_head        dev_list;
 160         spinlock_t              lock;
 161         unsigned long           flags;
 162 };
 163
 164 static struct omap_sham_drv sham = {
 165         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 166         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 167 };
 168
 169 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 170 {
 171         return __raw_readl(dd->io_base + offset);
 172 }
 173
 174 static inline void omap_sham_write(struct omap_sham_dev *dd,
 175                                         u32 offset, u32 value)
 176 {
 177         __raw_writel(value, dd->io_base + offset);
 178 }
 179
 180 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 181                                         u32 value, u32 mask)
 182 {
 183         u32 val;
 184
 185         val = omap_sham_read(dd, address);
 186         val &= ~mask;
 187         val |= value;
 188         omap_sham_write(dd, address, val);
 189 }
 190
 191 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 192 {
 193         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 194
 195         while (!(omap_sham_read(dd, offset) & bit)) {
 196                 if (time_is_before_jiffies(timeout))
 197                         return -ETIMEDOUT;
 198         }
 199
 200         return 0;
 201 }
 202
 203 static void omap_sham_copy_hash(struct ahash_request *req, int out)
 204 {
 205         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 206         u32 *hash = (u32 *)ctx->digest;
 207         int i;
 208
 209         /* MD5 is almost unused. So copy sha1 size to reduce code */
 210         for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) {
 211                 if (out)
 212                         hash[i] = omap_sham_read(ctx->dd,
 213                                                 SHA_REG_DIGEST(i));
 214                 else
 215                         omap_sham_write(ctx->dd,
 216                                         SHA_REG_DIGEST(i), hash[i]);
 217         }
 218 }
 219
 220 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 221 {
 222         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 223         u32 *in = (u32 *)ctx->digest;
 224         u32 *hash = (u32 *)req->result;
 225         int i;
 226
 227         if (!hash)
 228                 return;
 229
 230         if (likely(ctx->flags & BIT(FLAGS_SHA1))) {
 231                 /* SHA1 results are in big endian */
 232                 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
 233                         hash[i] = be32_to_cpu(in[i]);
 234         } else {
 235                 /* MD5 results are in little endian */
 236                 for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
 237                         hash[i] = le32_to_cpu(in[i]);
 238         }
 239 }
 240
 241 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 242 {
 243         clk_enable(dd->iclk);
 244
 245         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 246                 omap_sham_write_mask(dd, SHA_REG_MASK,
 247                         SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
 248
 249                 if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
 250                                         SHA_REG_SYSSTATUS_RESETDONE))
 251                         return -ETIMEDOUT;
 252
 253                 set_bit(FLAGS_INIT, &dd->flags);
 254                 dd->err = 0;
 255         }
 256
 257         return 0;
 258 }
 259
 260 static void omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
 261                                  int final, int dma)
 262 {
 263         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 264         u32 val = length << 5, mask;
 265
 266         if (likely(ctx->digcnt))
 267                 omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
 268
 269         omap_sham_write_mask(dd, SHA_REG_MASK,
 270                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 271                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 272         /*
 273          * Setting ALGO_CONST only for the first iteration
 274          * and CLOSE_HASH only for the last one.
 275          */
 276         if (ctx->flags & BIT(FLAGS_SHA1))
 277                 val |= SHA_REG_CTRL_ALGO;
 278         if (!ctx->digcnt)
 279                 val |= SHA_REG_CTRL_ALGO_CONST;
 280         if (final)
 281                 val |= SHA_REG_CTRL_CLOSE_HASH;
 282
 283         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 284                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 285
 286         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 287 }
 288
 289 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
 290                               size_t length, int final)
 291 {
 292         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 293         int count, len32;
 294         const u32 *buffer = (const u32 *)buf;
 295
 296         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 297                                                 ctx->digcnt, length, final);
 298
 299         omap_sham_write_ctrl(dd, length, final, 0);
 300
 301         /* should be non-zero before next lines to disable clocks later */
 302         ctx->digcnt += length;
 303
 304         if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
 305                 return -ETIMEDOUT;
 306
 307         if (final)
 308                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 309
 310         set_bit(FLAGS_CPU, &dd->flags);
 311
 312         len32 = DIV_ROUND_UP(length, sizeof(u32));
 313
 314         for (count = 0; count < len32; count++)
 315                 omap_sham_write(dd, SHA_REG_DIN(count), buffer[count]);
 316
 317         return -EINPROGRESS;
 318 }
 319
 320 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
 321                               size_t length, int final)
 322 {
 323         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 324         int len32;
 325
 326         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 327                                                 ctx->digcnt, length, final);
 328
 329         len32 = DIV_ROUND_UP(length, sizeof(u32));
 330
 331         omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
 332                         1, OMAP_DMA_SYNC_PACKET, dd->dma,
 333                                 OMAP_DMA_DST_SYNC_PREFETCH);
 334
 335         omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
 336                                 dma_addr, 0, 0);
 337
 338         omap_sham_write_ctrl(dd, length, final, 1);
 339
 340         ctx->digcnt += length;
 341
 342         if (final)
 343                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 344
 345         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 346
 347         omap_start_dma(dd->dma_lch);
 348
 349         return -EINPROGRESS;
 350 }
 351
 352 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
 353                                 const u8 *data, size_t length)
 354 {
 355         size_t count = min(length, ctx->buflen - ctx->bufcnt);
 356
 357         count = min(count, ctx->total);
 358         if (count <= 0)
 359                 return 0;
 360         memcpy(ctx->buffer + ctx->bufcnt, data, count);
 361         ctx->bufcnt += count;
 362
 363         return count;
 364 }
 365
 366 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
 367 {
 368         size_t count;
 369
 370         while (ctx->sg) {
 371                 count = omap_sham_append_buffer(ctx,
 372                                 sg_virt(ctx->sg) + ctx->offset,
 373                                 ctx->sg->length - ctx->offset);
 374                 if (!count)
 375                         break;
 376                 ctx->offset += count;
 377                 ctx->total -= count;
 378                 if (ctx->offset == ctx->sg->length) {
 379                         ctx->sg = sg_next(ctx->sg);
 380                         if (ctx->sg)
 381                                 ctx->offset = 0;
 382                         else
 383                                 ctx->total = 0;
 384                 }
 385         }
 386
 387         return 0;
 388 }
 389
 390 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
 391                                         struct omap_sham_reqctx *ctx,
 392                                         size_t length, int final)
 393 {
 394         ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
 395                                        DMA_TO_DEVICE);
 396         if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
 397                 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
 398                 return -EINVAL;
 399         }
 400
 401         ctx->flags &= ~BIT(FLAGS_SG);
 402
 403         /* next call does not fail... so no unmap in the case of error */
 404         return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
 405 }
 406
 407 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 408 {
 409         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 410         unsigned int final;
 411         size_t count;
 412
 413         omap_sham_append_sg(ctx);
 414
 415         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 416
 417         dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
 418                                          ctx->bufcnt, ctx->digcnt, final);
 419
 420         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 421                 count = ctx->bufcnt;
 422                 ctx->bufcnt = 0;
 423                 return omap_sham_xmit_dma_map(dd, ctx, count, final);
 424         }
 425
 426         return 0;
 427 }
 428
 429 /* Start address alignment */
 430 #define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
 431 /* SHA1 block size alignment */
 432 #define SG_SA(sg)       (IS_ALIGNED(sg->length, SHA1_MD5_BLOCK_SIZE))
 433
 434 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
 435 {
 436         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 437         unsigned int length, final, tail;
 438         struct scatterlist *sg;
 439
 440         if (!ctx->total)
 441                 return 0;
 442
 443         if (ctx->bufcnt || ctx->offset)
 444                 return omap_sham_update_dma_slow(dd);
 445
 446         dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
 447                         ctx->digcnt, ctx->bufcnt, ctx->total);
 448
 449         sg = ctx->sg;
 450
 451         if (!SG_AA(sg))
 452                 return omap_sham_update_dma_slow(dd);
 453
 454         if (!sg_is_last(sg) && !SG_SA(sg))
 455                 /* size is not SHA1_BLOCK_SIZE aligned */
 456                 return omap_sham_update_dma_slow(dd);
 457
 458         length = min(ctx->total, sg->length);
 459
 460         if (sg_is_last(sg)) {
 461                 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
 462                         /* not last sg must be SHA1_MD5_BLOCK_SIZE aligned */
 463                         tail = length & (SHA1_MD5_BLOCK_SIZE - 1);
 464                         /* without finup() we need one block to close hash */
 465                         if (!tail)
 466                                 tail = SHA1_MD5_BLOCK_SIZE;
 467                         length -= tail;
 468                 }
 469         }
 470
 471         if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
 472                 dev_err(dd->dev, "dma_map_sg  error\n");
 473                 return -EINVAL;
 474         }
 475
 476         ctx->flags |= BIT(FLAGS_SG);
 477
 478         ctx->total -= length;
 479         ctx->offset = length; /* offset where to start slow */
 480
 481         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 482
 483         /* next call does not fail... so no unmap in the case of error */
 484         return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
 485 }
 486
 487 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
 488 {
 489         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 490         int bufcnt;
 491
 492         omap_sham_append_sg(ctx);
 493         bufcnt = ctx->bufcnt;
 494         ctx->bufcnt = 0;
 495
 496         return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
 497 }
 498
 499 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 500 {
 501         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 502
 503         omap_stop_dma(dd->dma_lch);
 504         if (ctx->flags & BIT(FLAGS_SG)) {
 505                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 506                 if (ctx->sg->length == ctx->offset) {
 507                         ctx->sg = sg_next(ctx->sg);
 508                         if (ctx->sg)
 509                                 ctx->offset = 0;
 510                 }
 511         } else {
 512                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 513                                  DMA_TO_DEVICE);
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int omap_sham_init(struct ahash_request *req)
 520 {
 521         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 522         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 523         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 524         struct omap_sham_dev *dd = NULL, *tmp;
 525
 526         spin_lock_bh(&sham.lock);
 527         if (!tctx->dd) {
 528                 list_for_each_entry(tmp, &sham.dev_list, list) {
 529                         dd = tmp;
 530                         break;
 531                 }
 532                 tctx->dd = dd;
 533         } else {
 534                 dd = tctx->dd;
 535         }
 536         spin_unlock_bh(&sham.lock);
 537
 538         ctx->dd = dd;
 539
 540         ctx->flags = 0;
 541
 542         dev_dbg(dd->dev, "init: digest size: %d\n",
 543                 crypto_ahash_digestsize(tfm));
 544
 545         if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
 546                 ctx->flags |= BIT(FLAGS_SHA1);
 547
 548         ctx->bufcnt = 0;
 549         ctx->digcnt = 0;
 550         ctx->buflen = BUFLEN;
 551
 552         if (tctx->flags & BIT(FLAGS_HMAC)) {
 553                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 554
 555                 memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE);
 556                 ctx->bufcnt = SHA1_MD5_BLOCK_SIZE;
 557                 ctx->flags |= BIT(FLAGS_HMAC);
 558         }
 559
 560         return 0;
 561
 562 }
 563
 564 static int omap_sham_update_req(struct omap_sham_dev *dd)
 565 {
 566         struct ahash_request *req = dd->req;
 567         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 568         int err;
 569
 570         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 571                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 572
 573         if (ctx->flags & BIT(FLAGS_CPU))
 574                 err = omap_sham_update_cpu(dd);
 575         else
 576                 err = omap_sham_update_dma_start(dd);
 577
 578         /* wait for dma completion before can take more data */
 579         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
 580
 581         return err;
 582 }
 583
 584 static int omap_sham_final_req(struct omap_sham_dev *dd)
 585 {
 586         struct ahash_request *req = dd->req;
 587         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 588         int err = 0, use_dma = 1;
 589
 590         if (ctx->bufcnt <= 64)
 591                 /* faster to handle last block with cpu */
 592                 use_dma = 0;
 593
 594         if (use_dma)
 595                 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
 596         else
 597                 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
 598
 599         ctx->bufcnt = 0;
 600
 601         dev_dbg(dd->dev, "final_req: err: %d\n", err);
 602
 603         return err;
 604 }
 605
 606 static int omap_sham_finish_hmac(struct ahash_request *req)
 607 {
 608         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 609         struct omap_sham_hmac_ctx *bctx = tctx->base;
 610         int bs = crypto_shash_blocksize(bctx->shash);
 611         int ds = crypto_shash_digestsize(bctx->shash);
 612         struct {
 613                 struct shash_desc shash;
 614                 char ctx[crypto_shash_descsize(bctx->shash)];
 615         } desc;
 616
 617         desc.shash.tfm = bctx->shash;
 618         desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
 619
 620         return crypto_shash_init(&desc.shash) ?:
 621                crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
 622                crypto_shash_finup(&desc.shash, req->result, ds, req->result);
 623 }
 624
 625 static int omap_sham_finish(struct ahash_request *req)
 626 {
 627         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 628         struct omap_sham_dev *dd = ctx->dd;
 629         int err = 0;
 630
 631         if (ctx->digcnt) {
 632                 omap_sham_copy_ready_hash(req);
 633                 if (ctx->flags & BIT(FLAGS_HMAC))
 634                         err = omap_sham_finish_hmac(req);
 635         }
 636
 637         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
 638
 639         return err;
 640 }
 641
 642 static void omap_sham_finish_req(struct ahash_request *req, int err)
 643 {
 644         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 645         struct omap_sham_dev *dd = ctx->dd;
 646
 647         if (!err) {
 648                 omap_sham_copy_hash(req, 1);
 649                 if (test_bit(FLAGS_FINAL, &dd->flags))
 650                         err = omap_sham_finish(req);
 651         } else {
 652                 ctx->flags |= BIT(FLAGS_ERROR);
 653         }
 654
 655         /* atomic operation is not needed here */
 656         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
 657                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
 658         clk_disable(dd->iclk);
 659
 660         if (req->base.complete)
 661                 req->base.complete(&req->base, err);
 662
 663         /* handle new request */
 664         tasklet_schedule(&dd->done_task);
 665 }
 666
 667 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
 668                                   struct ahash_request *req)
 669 {
 670         struct crypto_async_request *async_req, *backlog;
 671         struct omap_sham_reqctx *ctx;
 672         unsigned long flags;
 673         int err = 0, ret = 0;
 674
 675         spin_lock_irqsave(&dd->lock, flags);
 676         if (req)
 677                 ret = ahash_enqueue_request(&dd->queue, req);
 678         if (test_bit(FLAGS_BUSY, &dd->flags)) {
 679                 spin_unlock_irqrestore(&dd->lock, flags);
 680                 return ret;
 681         }
 682         backlog = crypto_get_backlog(&dd->queue);
 683         async_req = crypto_dequeue_request(&dd->queue);
 684         if (async_req)
 685                 set_bit(FLAGS_BUSY, &dd->flags);
 686         spin_unlock_irqrestore(&dd->lock, flags);
 687
 688         if (!async_req)
 689                 return ret;
 690
 691         if (backlog)
 692                 backlog->complete(backlog, -EINPROGRESS);
 693
 694         req = ahash_request_cast(async_req);
 695         dd->req = req;
 696         ctx = ahash_request_ctx(req);
 697
 698         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
 699                                                 ctx->op, req->nbytes);
 700
 701         err = omap_sham_hw_init(dd);
 702         if (err)
 703                 goto err1;
 704
 705         omap_set_dma_dest_params(dd->dma_lch, 0,
 706                         OMAP_DMA_AMODE_CONSTANT,
 707                         dd->phys_base + SHA_REG_DIN(0), 0, 16);
 708
 709         omap_set_dma_dest_burst_mode(dd->dma_lch,
 710                         OMAP_DMA_DATA_BURST_16);
 711
 712         omap_set_dma_src_burst_mode(dd->dma_lch,
 713                         OMAP_DMA_DATA_BURST_4);
 714
 715         if (ctx->digcnt)
 716                 /* request has changed - restore hash */
 717                 omap_sham_copy_hash(req, 0);
 718
 719         if (ctx->op == OP_UPDATE) {
 720                 err = omap_sham_update_req(dd);
 721                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
 722                         /* no final() after finup() */
 723                         err = omap_sham_final_req(dd);
 724         } else if (ctx->op == OP_FINAL) {
 725                 err = omap_sham_final_req(dd);
 726         }
 727 err1:
 728         if (err != -EINPROGRESS)
 729                 /* done_task will not finish it, so do it here */
 730                 omap_sham_finish_req(req, err);
 731
 732         dev_dbg(dd->dev, "exit, err: %d\n", err);
 733
 734         return ret;
 735 }
 736
 737 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
 738 {
 739         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 740         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 741         struct omap_sham_dev *dd = tctx->dd;
 742
 743         ctx->op = op;
 744
 745         return omap_sham_handle_queue(dd, req);
 746 }
 747
 748 static int omap_sham_update(struct ahash_request *req)
 749 {
 750         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 751
 752         if (!req->nbytes)
 753                 return 0;
 754
 755         ctx->total = req->nbytes;
 756         ctx->sg = req->src;
 757         ctx->offset = 0;
 758
 759         if (ctx->flags & BIT(FLAGS_FINUP)) {
 760                 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
 761                         /*
 762                         * OMAP HW accel works only with buffers >= 9
 763                         * will switch to bypass in final()
 764                         * final has the same request and data
 765                         */
 766                         omap_sham_append_sg(ctx);
 767                         return 0;
 768                 } else if (ctx->bufcnt + ctx->total <= SHA1_MD5_BLOCK_SIZE) {
 769                         /*
 770                         * faster to use CPU for short transfers
 771                         */
 772                         ctx->flags |= BIT(FLAGS_CPU);
 773                 }
 774         } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
 775                 omap_sham_append_sg(ctx);
 776                 return 0;
 777         }
 778
 779         return omap_sham_enqueue(req, OP_UPDATE);
 780 }
 781
 782 static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags,
 783                                   const u8 *data, unsigned int len, u8 *out)
 784 {
 785         struct {
 786                 struct shash_desc shash;
 787                 char ctx[crypto_shash_descsize(shash)];
 788         } desc;
 789
 790         desc.shash.tfm = shash;
 791         desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 792
 793         return crypto_shash_digest(&desc.shash, data, len, out);
 794 }
 795
 796 static int omap_sham_final_shash(struct ahash_request *req)
 797 {
 798         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 799         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 800
 801         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
 802                                       ctx->buffer, ctx->bufcnt, req->result);
 803 }
 804
 805 static int omap_sham_final(struct ahash_request *req)
 806 {
 807         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 808
 809         ctx->flags |= BIT(FLAGS_FINUP);
 810
 811         if (ctx->flags & BIT(FLAGS_ERROR))
 812                 return 0; /* uncompleted hash is not needed */
 813
 814         /* OMAP HW accel works only with buffers >= 9 */
 815         /* HMAC is always >= 9 because ipad == block size */
 816         if ((ctx->digcnt + ctx->bufcnt) < 9)
 817                 return omap_sham_final_shash(req);
 818         else if (ctx->bufcnt)
 819                 return omap_sham_enqueue(req, OP_FINAL);
 820
 821         /* copy ready hash (+ finalize hmac) */
 822         return omap_sham_finish(req);
 823 }
 824
 825 static int omap_sham_finup(struct ahash_request *req)
 826 {
 827         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 828         int err1, err2;
 829
 830         ctx->flags |= BIT(FLAGS_FINUP);
 831
 832         err1 = omap_sham_update(req);
 833         if (err1 == -EINPROGRESS || err1 == -EBUSY)
 834                 return err1;
 835         /*
 836          * final() has to be always called to cleanup resources
 837          * even if udpate() failed, except EINPROGRESS
 838          */
 839         err2 = omap_sham_final(req);
 840
 841         return err1 ?: err2;
 842 }
 843
 844 static int omap_sham_digest(struct ahash_request *req)
 845 {
 846         return omap_sham_init(req) ?: omap_sham_finup(req);
 847 }
 848
 849 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
 850                       unsigned int keylen)
 851 {
 852         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 853         struct omap_sham_hmac_ctx *bctx = tctx->base;
 854         int bs = crypto_shash_blocksize(bctx->shash);
 855         int ds = crypto_shash_digestsize(bctx->shash);
 856         int err, i;
 857         err = crypto_shash_setkey(tctx->fallback, key, keylen);
 858         if (err)
 859                 return err;
 860
 861         if (keylen > bs) {
 862                 err = omap_sham_shash_digest(bctx->shash,
 863                                 crypto_shash_get_flags(bctx->shash),
 864                                 key, keylen, bctx->ipad);
 865                 if (err)
 866                         return err;
 867                 keylen = ds;
 868         } else {
 869                 memcpy(bctx->ipad, key, keylen);
 870         }
 871
 872         memset(bctx->ipad + keylen, 0, bs - keylen);
 873         memcpy(bctx->opad, bctx->ipad, bs);
 874
 875         for (i = 0; i < bs; i++) {
 876                 bctx->ipad[i] ^= 0x36;
 877                 bctx->opad[i] ^= 0x5c;
 878         }
 879
 880         return err;
 881 }
 882
 883 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
 884 {
 885         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
 886         const char *alg_name = crypto_tfm_alg_name(tfm);
 887
 888         /* Allocate a fallback and abort if it failed. */
 889         tctx->fallback = crypto_alloc_shash(alg_name, 0,
 890                                             CRYPTO_ALG_NEED_FALLBACK);
 891         if (IS_ERR(tctx->fallback)) {
 892                 pr_err("omap-sham: fallback driver '%s' "
 893                                 "could not be loaded.\n", alg_name);
 894                 return PTR_ERR(tctx->fallback);
 895         }
 896
 897         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 898                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
 899
 900         if (alg_base) {
 901                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 902                 tctx->flags |= BIT(FLAGS_HMAC);
 903                 bctx->shash = crypto_alloc_shash(alg_base, 0,
 904                                                 CRYPTO_ALG_NEED_FALLBACK);
 905                 if (IS_ERR(bctx->shash)) {
 906                         pr_err("omap-sham: base driver '%s' "
 907                                         "could not be loaded.\n", alg_base);
 908                         crypto_free_shash(tctx->fallback);
 909                         return PTR_ERR(bctx->shash);
 910                 }
 911
 912         }
 913
 914         return 0;
 915 }
 916
 917 static int omap_sham_cra_init(struct crypto_tfm *tfm)
 918 {
 919         return omap_sham_cra_init_alg(tfm, NULL);
 920 }
 921
 922 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
 923 {
 924         return omap_sham_cra_init_alg(tfm, "sha1");
 925 }
 926
 927 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
 928 {
 929         return omap_sham_cra_init_alg(tfm, "md5");
 930 }
 931
 932 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
 933 {
 934         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
 935
 936         crypto_free_shash(tctx->fallback);
 937         tctx->fallback = NULL;
 938
 939         if (tctx->flags & BIT(FLAGS_HMAC)) {
 940                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 941                 crypto_free_shash(bctx->shash);
 942         }
 943 }
 944
 945 static struct ahash_alg algs[] = {
 946 {
 947         .init           = omap_sham_init,
 948         .update         = omap_sham_update,
 949         .final          = omap_sham_final,
 950         .finup          = omap_sham_finup,
 951         .digest         = omap_sham_digest,
 952         .halg.digestsize        = SHA1_DIGEST_SIZE,
 953         .halg.base      = {
 954                 .cra_name               = "sha1",
 955                 .cra_driver_name        = "omap-sha1",
 956                 .cra_priority           = 100,
 957                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 958                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
 959                                                 CRYPTO_ALG_ASYNC |
 960                                                 CRYPTO_ALG_NEED_FALLBACK,
 961                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 962                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
 963                 .cra_alignmask          = 0,
 964                 .cra_module             = THIS_MODULE,
 965                 .cra_init               = omap_sham_cra_init,
 966                 .cra_exit               = omap_sham_cra_exit,
 967         }
 968 },
 969 {
 970         .init           = omap_sham_init,
 971         .update         = omap_sham_update,
 972         .final          = omap_sham_final,
 973         .finup          = omap_sham_finup,
 974         .digest         = omap_sham_digest,
 975         .halg.digestsize        = MD5_DIGEST_SIZE,
 976         .halg.base      = {
 977                 .cra_name               = "md5",
 978                 .cra_driver_name        = "omap-md5",
 979                 .cra_priority           = 100,
 980                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 981                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
 982                                                 CRYPTO_ALG_ASYNC |
 983                                                 CRYPTO_ALG_NEED_FALLBACK,
 984                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 985                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
 986                 .cra_alignmask          = OMAP_ALIGN_MASK,
 987                 .cra_module             = THIS_MODULE,
 988                 .cra_init               = omap_sham_cra_init,
 989                 .cra_exit               = omap_sham_cra_exit,
 990         }
 991 },
 992 {
 993         .init           = omap_sham_init,
 994         .update         = omap_sham_update,
 995         .final          = omap_sham_final,
 996         .finup          = omap_sham_finup,
 997         .digest         = omap_sham_digest,
 998         .setkey         = omap_sham_setkey,
 999         .halg.digestsize        = SHA1_DIGEST_SIZE,
1000         .halg.base      = {
1001                 .cra_name               = "hmac(sha1)",
1002                 .cra_driver_name        = "omap-hmac-sha1",
1003                 .cra_priority           = 100,
1004                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1005                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1006                                                 CRYPTO_ALG_ASYNC |
1007                                                 CRYPTO_ALG_NEED_FALLBACK,
1008                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1009                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1010                                         sizeof(struct omap_sham_hmac_ctx),
1011                 .cra_alignmask          = OMAP_ALIGN_MASK,
1012                 .cra_module             = THIS_MODULE,
1013                 .cra_init               = omap_sham_cra_sha1_init,
1014                 .cra_exit               = omap_sham_cra_exit,
1015         }
1016 },
1017 {
1018         .init           = omap_sham_init,
1019         .update         = omap_sham_update,
1020         .final          = omap_sham_final,
1021         .finup          = omap_sham_finup,
1022         .digest         = omap_sham_digest,
1023         .setkey         = omap_sham_setkey,
1024         .halg.digestsize        = MD5_DIGEST_SIZE,
1025         .halg.base      = {
1026                 .cra_name               = "hmac(md5)",
1027                 .cra_driver_name        = "omap-hmac-md5",
1028                 .cra_priority           = 100,
1029                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1030                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1031                                                 CRYPTO_ALG_ASYNC |
1032                                                 CRYPTO_ALG_NEED_FALLBACK,
1033                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1034                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1035                                         sizeof(struct omap_sham_hmac_ctx),
1036                 .cra_alignmask          = OMAP_ALIGN_MASK,
1037                 .cra_module             = THIS_MODULE,
1038                 .cra_init               = omap_sham_cra_md5_init,
1039                 .cra_exit               = omap_sham_cra_exit,
1040         }
1041 }
1042 };
1043
1044 static void omap_sham_done_task(unsigned long data)
1045 {
1046         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1047         int err = 0;
1048
1049         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1050                 omap_sham_handle_queue(dd, NULL);
1051                 return;
1052         }
1053
1054         if (test_bit(FLAGS_CPU, &dd->flags)) {
1055                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1056                         goto finish;
1057         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1058                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1059                         omap_sham_update_dma_stop(dd);
1060                         if (dd->err) {
1061                                 err = dd->err;
1062                                 goto finish;
1063                         }
1064                 }
1065                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1066                         /* hash or semi-hash ready */
1067                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1068                         err = omap_sham_update_dma_start(dd);
1069                         if (err != -EINPROGRESS)
1070                                 goto finish;
1071                 }
1072         }
1073
1074         return;
1075
1076 finish:
1077         dev_dbg(dd->dev, "update done: err: %d\n", err);
1078         /* finish curent request */
1079         omap_sham_finish_req(dd->req, err);
1080 }
1081
1082 static irqreturn_t omap_sham_irq(int irq, void *dev_id)
1083 {
1084         struct omap_sham_dev *dd = dev_id;
1085
1086         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1087                 /* final -> allow device to go to power-saving mode */
1088                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1089
1090         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1091                                  SHA_REG_CTRL_OUTPUT_READY);
1092         omap_sham_read(dd, SHA_REG_CTRL);
1093
1094         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1095                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1096                 return IRQ_HANDLED;
1097         }
1098
1099         set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1100         tasklet_schedule(&dd->done_task);
1101
1102         return IRQ_HANDLED;
1103 }
1104
1105 static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
1106 {
1107         struct omap_sham_dev *dd = data;
1108
1109         if (ch_status != OMAP_DMA_BLOCK_IRQ) {
1110                 pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
1111                 dd->err = -EIO;
1112                 clear_bit(FLAGS_INIT, &dd->flags);/* request to re-initialize */
1113         }
1114
1115         set_bit(FLAGS_DMA_READY, &dd->flags);
1116         tasklet_schedule(&dd->done_task);
1117 }
1118
1119 static int omap_sham_dma_init(struct omap_sham_dev *dd)
1120 {
1121         int err;
1122
1123         dd->dma_lch = -1;
1124
1125         err = omap_request_dma(dd->dma, dev_name(dd->dev),
1126                         omap_sham_dma_callback, dd, &dd->dma_lch);
1127         if (err) {
1128                 dev_err(dd->dev, "Unable to request DMA channel\n");
1129                 return err;
1130         }
1131
1132         return 0;
1133 }
1134
1135 static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
1136 {
1137         if (dd->dma_lch >= 0) {
1138                 omap_free_dma(dd->dma_lch);
1139                 dd->dma_lch = -1;
1140         }
1141 }
1142
1143 static int omap_sham_probe(struct platform_device *pdev)
1144 {
1145         struct omap_sham_dev *dd;
1146         struct device *dev = &pdev->dev;
1147         struct resource *res;
1148         int err, i, j;
1149
1150         dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
1151         if (dd == NULL) {
1152                 dev_err(dev, "unable to alloc data struct.\n");
1153                 err = -ENOMEM;
1154                 goto data_err;
1155         }
1156         dd->dev = dev;
1157         platform_set_drvdata(pdev, dd);
1158
1159         INIT_LIST_HEAD(&dd->list);
1160         spin_lock_init(&dd->lock);
1161         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1162         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1163
1164         dd->irq = -1;
1165
1166         /* Get the base address */
1167         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1168         if (!res) {
1169                 dev_err(dev, "no MEM resource info\n");
1170                 err = -ENODEV;
1171                 goto res_err;
1172         }
1173         dd->phys_base = res->start;
1174
1175         /* Get the DMA */
1176         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1177         if (!res) {
1178                 dev_err(dev, "no DMA resource info\n");
1179                 err = -ENODEV;
1180                 goto res_err;
1181         }
1182         dd->dma = res->start;
1183
1184         /* Get the IRQ */
1185         dd->irq = platform_get_irq(pdev,  0);
1186         if (dd->irq < 0) {
1187                 dev_err(dev, "no IRQ resource info\n");
1188                 err = dd->irq;
1189                 goto res_err;
1190         }
1191
1192         err = request_irq(dd->irq, omap_sham_irq,
1193                         IRQF_TRIGGER_LOW, dev_name(dev), dd);
1194         if (err) {
1195                 dev_err(dev, "unable to request irq.\n");
1196                 goto res_err;
1197         }
1198
1199         err = omap_sham_dma_init(dd);
1200         if (err)
1201                 goto dma_err;
1202
1203         /* Initializing the clock */
1204         dd->iclk = clk_get(dev, "ick");
1205         if (IS_ERR(dd->iclk)) {
1206                 dev_err(dev, "clock intialization failed.\n");
1207                 err = PTR_ERR(dd->iclk);
1208                 goto clk_err;
1209         }
1210
1211         dd->io_base = ioremap(dd->phys_base, SZ_4K);
1212         if (!dd->io_base) {
1213                 dev_err(dev, "can't ioremap\n");
1214                 err = -ENOMEM;
1215                 goto io_err;
1216         }
1217
1218         clk_enable(dd->iclk);
1219         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1220                 (omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MAJOR) >> 4,
1221                 omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MINOR);
1222         clk_disable(dd->iclk);
1223
1224         spin_lock(&sham.lock);
1225         list_add_tail(&dd->list, &sham.dev_list);
1226         spin_unlock(&sham.lock);
1227
1228         for (i = 0; i < ARRAY_SIZE(algs); i++) {
1229                 err = crypto_register_ahash(&algs[i]);
1230                 if (err)
1231                         goto err_algs;
1232         }
1233
1234         return 0;
1235
1236 err_algs:
1237         for (j = 0; j < i; j++)
1238                 crypto_unregister_ahash(&algs[j]);
1239         iounmap(dd->io_base);
1240 io_err:
1241         clk_put(dd->iclk);
1242 clk_err:
1243         omap_sham_dma_cleanup(dd);
1244 dma_err:
1245         if (dd->irq >= 0)
1246                 free_irq(dd->irq, dd);
1247 res_err:
1248         kfree(dd);
1249         dd = NULL;
1250 data_err:
1251         dev_err(dev, "initialization failed.\n");
1252
1253         return err;
1254 }
1255
1256 static int omap_sham_remove(struct platform_device *pdev)
1257 {
1258         static struct omap_sham_dev *dd;
1259         int i;
1260
1261         dd = platform_get_drvdata(pdev);
1262         if (!dd)
1263                 return -ENODEV;
1264         spin_lock(&sham.lock);
1265         list_del(&dd->list);
1266         spin_unlock(&sham.lock);
1267         for (i = 0; i < ARRAY_SIZE(algs); i++)
1268                 crypto_unregister_ahash(&algs[i]);
1269         tasklet_kill(&dd->done_task);
1270         iounmap(dd->io_base);
1271         clk_put(dd->iclk);
1272         omap_sham_dma_cleanup(dd);
1273         if (dd->irq >= 0)
1274                 free_irq(dd->irq, dd);
1275         kfree(dd);
1276         dd = NULL;
1277
1278         return 0;
1279 }
1280
1281 static struct platform_driver omap_sham_driver = {
1282         .probe  = omap_sham_probe,
1283         .remove = omap_sham_remove,
1284         .driver = {
1285                 .name   = "omap-sham",
1286                 .owner  = THIS_MODULE,
1287         },
1288 };
1289
1290 static int __init omap_sham_mod_init(void)
1291 {
1292         pr_info("loading %s driver\n", "omap-sham");
1293
1294         return platform_driver_register(&omap_sham_driver);
1295 }
1296
1297 static void __exit omap_sham_mod_exit(void)
1298 {
1299         platform_driver_unregister(&omap_sham_driver);
1300 }
1301
1302 module_init(omap_sham_mod_init);
1303 module_exit(omap_sham_mod_exit);
1304
1305 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
1306 MODULE_LICENSE("GPL v2");
1307 MODULE_AUTHOR("Dmitry Kasatkin");