drivers/gpu/drm/solomon/ssd130x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * DRM driver for Solomon SSD13xx OLED displays
   4  *
   5  * Copyright 2022 Red Hat Inc.
   6  * Author: Javier Martinez Canillas <[email protected]>
   7  *
   8  * Based on drivers/video/fbdev/ssd1307fb.c
   9  * Copyright 2012 Free Electrons
  10  */
  11
  12 #include <linux/backlight.h>
  13 #include <linux/bitfield.h>
  14 #include <linux/bits.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio/consumer.h>
  17 #include <linux/property.h>
  18 #include <linux/pwm.h>
  19 #include <linux/regulator/consumer.h>
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_crtc_helper.h>
  24 #include <drm/drm_damage_helper.h>
  25 #include <drm/drm_edid.h>
  26 #include <drm/drm_fbdev_generic.h>
  27 #include <drm/drm_format_helper.h>
  28 #include <drm/drm_framebuffer.h>
  29 #include <drm/drm_gem_atomic_helper.h>
  30 #include <drm/drm_gem_framebuffer_helper.h>
  31 #include <drm/drm_gem_shmem_helper.h>
  32 #include <drm/drm_managed.h>
  33 #include <drm/drm_modes.h>
  34 #include <drm/drm_rect.h>
  35 #include <drm/drm_probe_helper.h>
  36
  37 #include "ssd130x.h"
  38
  39 #define DRIVER_NAME     "ssd130x"
  40 #define DRIVER_DESC     "DRM driver for Solomon SSD13xx OLED displays"
  41 #define DRIVER_DATE     "20220131"
  42 #define DRIVER_MAJOR    1
  43 #define DRIVER_MINOR    0
  44
  45 #define SSD130X_PAGE_HEIGHT 8
  46
  47 #define SSD132X_SEGMENT_WIDTH 2
  48
  49 /* ssd13xx commands */
  50 #define SSD13XX_CONTRAST                        0x81
  51 #define SSD13XX_SET_SEG_REMAP                   0xa0
  52 #define SSD13XX_SET_MULTIPLEX_RATIO             0xa8
  53 #define SSD13XX_DISPLAY_OFF                     0xae
  54 #define SSD13XX_DISPLAY_ON                      0xaf
  55
  56 #define SSD13XX_SET_SEG_REMAP_MASK              GENMASK(0, 0)
  57 #define SSD13XX_SET_SEG_REMAP_SET(val)          FIELD_PREP(SSD13XX_SET_SEG_REMAP_MASK, (val))
  58
  59 /* ssd130x commands */
  60 #define SSD130X_PAGE_COL_START_LOW              0x00
  61 #define SSD130X_PAGE_COL_START_HIGH             0x10
  62 #define SSD130X_SET_ADDRESS_MODE                0x20
  63 #define SSD130X_SET_COL_RANGE                   0x21
  64 #define SSD130X_SET_PAGE_RANGE                  0x22
  65 #define SSD130X_SET_LOOKUP_TABLE                0x91
  66 #define SSD130X_CHARGE_PUMP                     0x8d
  67 #define SSD130X_START_PAGE_ADDRESS              0xb0
  68 #define SSD130X_SET_COM_SCAN_DIR                0xc0
  69 #define SSD130X_SET_DISPLAY_OFFSET              0xd3
  70 #define SSD130X_SET_CLOCK_FREQ                  0xd5
  71 #define SSD130X_SET_AREA_COLOR_MODE             0xd8
  72 #define SSD130X_SET_PRECHARGE_PERIOD            0xd9
  73 #define SSD130X_SET_COM_PINS_CONFIG             0xda
  74 #define SSD130X_SET_VCOMH                       0xdb
  75
  76 /* ssd130x commands accessors */
  77 #define SSD130X_PAGE_COL_START_MASK             GENMASK(3, 0)
  78 #define SSD130X_PAGE_COL_START_HIGH_SET(val)    FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val) >> 4)
  79 #define SSD130X_PAGE_COL_START_LOW_SET(val)     FIELD_PREP(SSD130X_PAGE_COL_START_MASK, (val))
  80 #define SSD130X_START_PAGE_ADDRESS_MASK         GENMASK(2, 0)
  81 #define SSD130X_START_PAGE_ADDRESS_SET(val)     FIELD_PREP(SSD130X_START_PAGE_ADDRESS_MASK, (val))
  82 #define SSD130X_SET_COM_SCAN_DIR_MASK           GENMASK(3, 3)
  83 #define SSD130X_SET_COM_SCAN_DIR_SET(val)       FIELD_PREP(SSD130X_SET_COM_SCAN_DIR_MASK, (val))
  84 #define SSD130X_SET_CLOCK_DIV_MASK              GENMASK(3, 0)
  85 #define SSD130X_SET_CLOCK_DIV_SET(val)          FIELD_PREP(SSD130X_SET_CLOCK_DIV_MASK, (val))
  86 #define SSD130X_SET_CLOCK_FREQ_MASK             GENMASK(7, 4)
  87 #define SSD130X_SET_CLOCK_FREQ_SET(val)         FIELD_PREP(SSD130X_SET_CLOCK_FREQ_MASK, (val))
  88 #define SSD130X_SET_PRECHARGE_PERIOD1_MASK      GENMASK(3, 0)
  89 #define SSD130X_SET_PRECHARGE_PERIOD1_SET(val)  FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD1_MASK, (val))
  90 #define SSD130X_SET_PRECHARGE_PERIOD2_MASK      GENMASK(7, 4)
  91 #define SSD130X_SET_PRECHARGE_PERIOD2_SET(val)  FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD2_MASK, (val))
  92 #define SSD130X_SET_COM_PINS_CONFIG1_MASK       GENMASK(4, 4)
  93 #define SSD130X_SET_COM_PINS_CONFIG1_SET(val)   FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (val))
  94 #define SSD130X_SET_COM_PINS_CONFIG2_MASK       GENMASK(5, 5)
  95 #define SSD130X_SET_COM_PINS_CONFIG2_SET(val)   FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG2_MASK, (val))
  96
  97 #define SSD130X_SET_ADDRESS_MODE_HORIZONTAL     0x00
  98 #define SSD130X_SET_ADDRESS_MODE_VERTICAL       0x01
  99 #define SSD130X_SET_ADDRESS_MODE_PAGE           0x02
 100
 101 #define SSD130X_SET_AREA_COLOR_MODE_ENABLE      0x1e
 102 #define SSD130X_SET_AREA_COLOR_MODE_LOW_POWER   0x05
 103
 104 /* ssd132x commands */
 105 #define SSD132X_SET_COL_RANGE                   0x15
 106 #define SSD132X_SET_DEACTIVATE_SCROLL           0x2e
 107 #define SSD132X_SET_ROW_RANGE                   0x75
 108 #define SSD132X_SET_DISPLAY_START               0xa1
 109 #define SSD132X_SET_DISPLAY_OFFSET              0xa2
 110 #define SSD132X_SET_DISPLAY_NORMAL              0xa4
 111 #define SSD132X_SET_FUNCTION_SELECT_A           0xab
 112 #define SSD132X_SET_PHASE_LENGTH                0xb1
 113 #define SSD132X_SET_CLOCK_FREQ                  0xb3
 114 #define SSD132X_SET_GPIO                        0xb5
 115 #define SSD132X_SET_PRECHARGE_PERIOD            0xb6
 116 #define SSD132X_SET_GRAY_SCALE_TABLE            0xb8
 117 #define SSD132X_SELECT_DEFAULT_TABLE            0xb9
 118 #define SSD132X_SET_PRECHARGE_VOLTAGE           0xbc
 119 #define SSD130X_SET_VCOMH_VOLTAGE               0xbe
 120 #define SSD132X_SET_FUNCTION_SELECT_B           0xd5
 121
 122 #define MAX_CONTRAST 255
 123
 124 const struct ssd130x_deviceinfo ssd130x_variants[] = {
 125         [SH1106_ID] = {
 126                 .default_vcomh = 0x40,
 127                 .default_dclk_div = 1,
 128                 .default_dclk_frq = 5,
 129                 .default_width = 132,
 130                 .default_height = 64,
 131                 .page_mode_only = 1,
 132                 .family_id = SSD130X_FAMILY,
 133         },
 134         [SSD1305_ID] = {
 135                 .default_vcomh = 0x34,
 136                 .default_dclk_div = 1,
 137                 .default_dclk_frq = 7,
 138                 .default_width = 132,
 139                 .default_height = 64,
 140                 .family_id = SSD130X_FAMILY,
 141         },
 142         [SSD1306_ID] = {
 143                 .default_vcomh = 0x20,
 144                 .default_dclk_div = 1,
 145                 .default_dclk_frq = 8,
 146                 .need_chargepump = 1,
 147                 .default_width = 128,
 148                 .default_height = 64,
 149                 .family_id = SSD130X_FAMILY,
 150         },
 151         [SSD1307_ID] = {
 152                 .default_vcomh = 0x20,
 153                 .default_dclk_div = 2,
 154                 .default_dclk_frq = 12,
 155                 .need_pwm = 1,
 156                 .default_width = 128,
 157                 .default_height = 39,
 158                 .family_id = SSD130X_FAMILY,
 159         },
 160         [SSD1309_ID] = {
 161                 .default_vcomh = 0x34,
 162                 .default_dclk_div = 1,
 163                 .default_dclk_frq = 10,
 164                 .default_width = 128,
 165                 .default_height = 64,
 166                 .family_id = SSD130X_FAMILY,
 167         },
 168         /* ssd132x family */
 169         [SSD1322_ID] = {
 170                 .default_width = 480,
 171                 .default_height = 128,
 172                 .family_id = SSD132X_FAMILY,
 173         },
 174         [SSD1325_ID] = {
 175                 .default_width = 128,
 176                 .default_height = 80,
 177                 .family_id = SSD132X_FAMILY,
 178         },
 179         [SSD1327_ID] = {
 180                 .default_width = 128,
 181                 .default_height = 128,
 182                 .family_id = SSD132X_FAMILY,
 183         }
 184 };
 185 EXPORT_SYMBOL_NS_GPL(ssd130x_variants, DRM_SSD130X);
 186
 187 struct ssd130x_crtc_state {
 188         struct drm_crtc_state base;
 189         /* Buffer to store pixels in HW format and written to the panel */
 190         u8 *data_array;
 191 };
 192
 193 struct ssd130x_plane_state {
 194         struct drm_shadow_plane_state base;
 195         /* Intermediate buffer to convert pixels from XRGB8888 to HW format */
 196         u8 *buffer;
 197 };
 198
 199 static inline struct ssd130x_crtc_state *to_ssd130x_crtc_state(struct drm_crtc_state *state)
 200 {
 201         return container_of(state, struct ssd130x_crtc_state, base);
 202 }
 203
 204 static inline struct ssd130x_plane_state *to_ssd130x_plane_state(struct drm_plane_state *state)
 205 {
 206         return container_of(state, struct ssd130x_plane_state, base.base);
 207 }
 208
 209 static inline struct ssd130x_device *drm_to_ssd130x(struct drm_device *drm)
 210 {
 211         return container_of(drm, struct ssd130x_device, drm);
 212 }
 213
 214 /*
 215  * Helper to write data (SSD13XX_DATA) to the device.
 216  */
 217 static int ssd130x_write_data(struct ssd130x_device *ssd130x, u8 *values, int count)
 218 {
 219         return regmap_bulk_write(ssd130x->regmap, SSD13XX_DATA, values, count);
 220 }
 221
 222 /*
 223  * Helper to write command (SSD13XX_COMMAND). The fist variadic argument
 224  * is the command to write and the following are the command options.
 225  *
 226  * Note that the ssd13xx protocol requires each command and option to be
 227  * written as a SSD13XX_COMMAND device register value. That is why a call
 228  * to regmap_write(..., SSD13XX_COMMAND, ...) is done for each argument.
 229  */
 230 static int ssd130x_write_cmd(struct ssd130x_device *ssd130x, int count,
 231                              /* u8 cmd, u8 option, ... */...)
 232 {
 233         va_list ap;
 234         u8 value;
 235         int ret;
 236
 237         va_start(ap, count);
 238
 239         do {
 240                 value = va_arg(ap, int);
 241                 ret = regmap_write(ssd130x->regmap, SSD13XX_COMMAND, value);
 242                 if (ret)
 243                         goto out_end;
 244         } while (--count);
 245
 246 out_end:
 247         va_end(ap);
 248
 249         return ret;
 250 }
 251
 252 /* Set address range for horizontal/vertical addressing modes */
 253 static int ssd130x_set_col_range(struct ssd130x_device *ssd130x,
 254                                  u8 col_start, u8 cols)
 255 {
 256         u8 col_end = col_start + cols - 1;
 257         int ret;
 258
 259         if (col_start == ssd130x->col_start && col_end == ssd130x->col_end)
 260                 return 0;
 261
 262         ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_COL_RANGE, col_start, col_end);
 263         if (ret < 0)
 264                 return ret;
 265
 266         ssd130x->col_start = col_start;
 267         ssd130x->col_end = col_end;
 268         return 0;
 269 }
 270
 271 static int ssd130x_set_page_range(struct ssd130x_device *ssd130x,
 272                                   u8 page_start, u8 pages)
 273 {
 274         u8 page_end = page_start + pages - 1;
 275         int ret;
 276
 277         if (page_start == ssd130x->page_start && page_end == ssd130x->page_end)
 278                 return 0;
 279
 280         ret = ssd130x_write_cmd(ssd130x, 3, SSD130X_SET_PAGE_RANGE, page_start, page_end);
 281         if (ret < 0)
 282                 return ret;
 283
 284         ssd130x->page_start = page_start;
 285         ssd130x->page_end = page_end;
 286         return 0;
 287 }
 288
 289 /* Set page and column start address for page addressing mode */
 290 static int ssd130x_set_page_pos(struct ssd130x_device *ssd130x,
 291                                 u8 page_start, u8 col_start)
 292 {
 293         int ret;
 294         u32 page, col_low, col_high;
 295
 296         page = SSD130X_START_PAGE_ADDRESS |
 297                SSD130X_START_PAGE_ADDRESS_SET(page_start);
 298         col_low = SSD130X_PAGE_COL_START_LOW |
 299                   SSD130X_PAGE_COL_START_LOW_SET(col_start);
 300         col_high = SSD130X_PAGE_COL_START_HIGH |
 301                    SSD130X_PAGE_COL_START_HIGH_SET(col_start);
 302         ret = ssd130x_write_cmd(ssd130x, 3, page, col_low, col_high);
 303         if (ret < 0)
 304                 return ret;
 305
 306         return 0;
 307 }
 308
 309 static int ssd130x_pwm_enable(struct ssd130x_device *ssd130x)
 310 {
 311         struct device *dev = ssd130x->dev;
 312         struct pwm_state pwmstate;
 313
 314         ssd130x->pwm = pwm_get(dev, NULL);
 315         if (IS_ERR(ssd130x->pwm)) {
 316                 dev_err(dev, "Could not get PWM from firmware description!\n");
 317                 return PTR_ERR(ssd130x->pwm);
 318         }
 319
 320         pwm_init_state(ssd130x->pwm, &pwmstate);
 321         pwm_set_relative_duty_cycle(&pwmstate, 50, 100);
 322         pwm_apply_state(ssd130x->pwm, &pwmstate);
 323
 324         /* Enable the PWM */
 325         pwm_enable(ssd130x->pwm);
 326
 327         dev_dbg(dev, "Using PWM %s with a %lluns period.\n",
 328                 ssd130x->pwm->label, pwm_get_period(ssd130x->pwm));
 329
 330         return 0;
 331 }
 332
 333 static void ssd130x_reset(struct ssd130x_device *ssd130x)
 334 {
 335         if (!ssd130x->reset)
 336                 return;
 337
 338         /* Reset the screen */
 339         gpiod_set_value_cansleep(ssd130x->reset, 1);
 340         udelay(4);
 341         gpiod_set_value_cansleep(ssd130x->reset, 0);
 342         udelay(4);
 343 }
 344
 345 static int ssd130x_power_on(struct ssd130x_device *ssd130x)
 346 {
 347         struct device *dev = ssd130x->dev;
 348         int ret;
 349
 350         ssd130x_reset(ssd130x);
 351
 352         ret = regulator_enable(ssd130x->vcc_reg);
 353         if (ret) {
 354                 dev_err(dev, "Failed to enable VCC: %d\n", ret);
 355                 return ret;
 356         }
 357
 358         if (ssd130x->device_info->need_pwm) {
 359                 ret = ssd130x_pwm_enable(ssd130x);
 360                 if (ret) {
 361                         dev_err(dev, "Failed to enable PWM: %d\n", ret);
 362                         regulator_disable(ssd130x->vcc_reg);
 363                         return ret;
 364                 }
 365         }
 366
 367         return 0;
 368 }
 369
 370 static void ssd130x_power_off(struct ssd130x_device *ssd130x)
 371 {
 372         pwm_disable(ssd130x->pwm);
 373         pwm_put(ssd130x->pwm);
 374
 375         regulator_disable(ssd130x->vcc_reg);
 376 }
 377
 378 static int ssd130x_init(struct ssd130x_device *ssd130x)
 379 {
 380         u32 precharge, dclk, com_invdir, compins, chargepump, seg_remap;
 381         bool scan_mode;
 382         int ret;
 383
 384         /* Set initial contrast */
 385         ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_CONTRAST, ssd130x->contrast);
 386         if (ret < 0)
 387                 return ret;
 388
 389         /* Set segment re-map */
 390         seg_remap = (SSD13XX_SET_SEG_REMAP |
 391                      SSD13XX_SET_SEG_REMAP_SET(ssd130x->seg_remap));
 392         ret = ssd130x_write_cmd(ssd130x, 1, seg_remap);
 393         if (ret < 0)
 394                 return ret;
 395
 396         /* Set COM direction */
 397         com_invdir = (SSD130X_SET_COM_SCAN_DIR |
 398                       SSD130X_SET_COM_SCAN_DIR_SET(ssd130x->com_invdir));
 399         ret = ssd130x_write_cmd(ssd130x,  1, com_invdir);
 400         if (ret < 0)
 401                 return ret;
 402
 403         /* Set multiplex ratio value */
 404         ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1);
 405         if (ret < 0)
 406                 return ret;
 407
 408         /* set display offset value */
 409         ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_DISPLAY_OFFSET, ssd130x->com_offset);
 410         if (ret < 0)
 411                 return ret;
 412
 413         /* Set clock frequency */
 414         dclk = (SSD130X_SET_CLOCK_DIV_SET(ssd130x->dclk_div - 1) |
 415                 SSD130X_SET_CLOCK_FREQ_SET(ssd130x->dclk_frq));
 416         ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_CLOCK_FREQ, dclk);
 417         if (ret < 0)
 418                 return ret;
 419
 420         /* Set Area Color Mode ON/OFF & Low Power Display Mode */
 421         if (ssd130x->area_color_enable || ssd130x->low_power) {
 422                 u32 mode = 0;
 423
 424                 if (ssd130x->area_color_enable)
 425                         mode |= SSD130X_SET_AREA_COLOR_MODE_ENABLE;
 426
 427                 if (ssd130x->low_power)
 428                         mode |= SSD130X_SET_AREA_COLOR_MODE_LOW_POWER;
 429
 430                 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_AREA_COLOR_MODE, mode);
 431                 if (ret < 0)
 432                         return ret;
 433         }
 434
 435         /* Set precharge period in number of ticks from the internal clock */
 436         precharge = (SSD130X_SET_PRECHARGE_PERIOD1_SET(ssd130x->prechargep1) |
 437                      SSD130X_SET_PRECHARGE_PERIOD2_SET(ssd130x->prechargep2));
 438         ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_PRECHARGE_PERIOD, precharge);
 439         if (ret < 0)
 440                 return ret;
 441
 442         /* Set COM pins configuration */
 443         compins = BIT(1);
 444         /*
 445          * The COM scan mode field values are the inverse of the boolean DT
 446          * property "solomon,com-seq". The value 0b means scan from COM0 to
 447          * COM[N - 1] while 1b means scan from COM[N - 1] to COM0.
 448          */
 449         scan_mode = !ssd130x->com_seq;
 450         compins |= (SSD130X_SET_COM_PINS_CONFIG1_SET(scan_mode) |
 451                     SSD130X_SET_COM_PINS_CONFIG2_SET(ssd130x->com_lrremap));
 452         ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_COM_PINS_CONFIG, compins);
 453         if (ret < 0)
 454                 return ret;
 455
 456         /* Set VCOMH */
 457         ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_VCOMH, ssd130x->vcomh);
 458         if (ret < 0)
 459                 return ret;
 460
 461         /* Turn on the DC-DC Charge Pump */
 462         chargepump = BIT(4);
 463
 464         if (ssd130x->device_info->need_chargepump)
 465                 chargepump |= BIT(2);
 466
 467         ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_CHARGE_PUMP, chargepump);
 468         if (ret < 0)
 469                 return ret;
 470
 471         /* Set lookup table */
 472         if (ssd130x->lookup_table_set) {
 473                 int i;
 474
 475                 ret = ssd130x_write_cmd(ssd130x, 1, SSD130X_SET_LOOKUP_TABLE);
 476                 if (ret < 0)
 477                         return ret;
 478
 479                 for (i = 0; i < ARRAY_SIZE(ssd130x->lookup_table); i++) {
 480                         u8 val = ssd130x->lookup_table[i];
 481
 482                         if (val < 31 || val > 63)
 483                                 dev_warn(ssd130x->dev,
 484                                          "lookup table index %d value out of range 31 <= %d <= 63\n",
 485                                          i, val);
 486                         ret = ssd130x_write_cmd(ssd130x, 1, val);
 487                         if (ret < 0)
 488                                 return ret;
 489                 }
 490         }
 491
 492         /* Switch to page addressing mode */
 493         if (ssd130x->page_address_mode)
 494                 return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE,
 495                                          SSD130X_SET_ADDRESS_MODE_PAGE);
 496
 497         /* Switch to horizontal addressing mode */
 498         return ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_ADDRESS_MODE,
 499                                  SSD130X_SET_ADDRESS_MODE_HORIZONTAL);
 500 }
 501
 502 static int ssd132x_init(struct ssd130x_device *ssd130x)
 503 {
 504         int ret;
 505
 506         /* Set initial contrast */
 507         ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_CONTRAST, 0x80);
 508         if (ret < 0)
 509                 return ret;
 510
 511         /* Set column start and end */
 512         ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_COL_RANGE, 0x00,
 513                                 ssd130x->width / SSD132X_SEGMENT_WIDTH - 1);
 514         if (ret < 0)
 515                 return ret;
 516
 517         /* Set row start and end */
 518         ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_ROW_RANGE, 0x00, ssd130x->height - 1);
 519         if (ret < 0)
 520                 return ret;
 521         /*
 522          * Horizontal Address Increment
 523          * Re-map for Column Address, Nibble and COM
 524          * COM Split Odd Even
 525          */
 526         ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_SEG_REMAP, 0x53);
 527         if (ret < 0)
 528                 return ret;
 529
 530         /* Set display start and offset */
 531         ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_DISPLAY_START, 0x00);
 532         if (ret < 0)
 533                 return ret;
 534
 535         ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_DISPLAY_OFFSET, 0x00);
 536         if (ret < 0)
 537                 return ret;
 538
 539         /* Set display mode normal */
 540         ret = ssd130x_write_cmd(ssd130x, 1, SSD132X_SET_DISPLAY_NORMAL);
 541         if (ret < 0)
 542                 return ret;
 543
 544         /* Set multiplex ratio value */
 545         ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1);
 546         if (ret < 0)
 547                 return ret;
 548
 549         /* Set phase length */
 550         ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PHASE_LENGTH, 0x55);
 551         if (ret < 0)
 552                 return ret;
 553
 554         /* Select default linear gray scale table */
 555         ret = ssd130x_write_cmd(ssd130x, 1, SSD132X_SELECT_DEFAULT_TABLE);
 556         if (ret < 0)
 557                 return ret;
 558
 559         /* Set clock frequency */
 560         ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_CLOCK_FREQ, 0x01);
 561         if (ret < 0)
 562                 return ret;
 563
 564         /* Enable internal VDD regulator */
 565         ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_FUNCTION_SELECT_A, 0x1);
 566         if (ret < 0)
 567                 return ret;
 568
 569         /* Set pre-charge period */
 570         ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_PERIOD, 0x01);
 571         if (ret < 0)
 572                 return ret;
 573
 574         /* Set pre-charge voltage */
 575         ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_VOLTAGE, 0x08);
 576         if (ret < 0)
 577                 return ret;
 578
 579         /* Set VCOMH voltage */
 580         ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_VCOMH_VOLTAGE, 0x07);
 581         if (ret < 0)
 582                 return ret;
 583
 584         /* Enable second pre-charge and internal VSL */
 585         ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_FUNCTION_SELECT_B, 0x62);
 586         if (ret < 0)
 587                 return ret;
 588
 589         return 0;
 590 }
 591
 592 static int ssd130x_update_rect(struct ssd130x_device *ssd130x,
 593                                struct drm_rect *rect, u8 *buf,
 594                                u8 *data_array)
 595 {
 596         unsigned int x = rect->x1;
 597         unsigned int y = rect->y1;
 598         unsigned int width = drm_rect_width(rect);
 599         unsigned int height = drm_rect_height(rect);
 600         unsigned int line_length = DIV_ROUND_UP(width, 8);
 601         unsigned int page_height = SSD130X_PAGE_HEIGHT;
 602         unsigned int pages = DIV_ROUND_UP(height, page_height);
 603         struct drm_device *drm = &ssd130x->drm;
 604         u32 array_idx = 0;
 605         int ret, i, j, k;
 606
 607         drm_WARN_ONCE(drm, y % page_height != 0, "y must be aligned to screen page\n");
 608
 609         /*
 610          * The screen is divided in pages, each having a height of 8
 611          * pixels, and the width of the screen. When sending a byte of
 612          * data to the controller, it gives the 8 bits for the current
 613          * column. I.e, the first byte are the 8 bits of the first
 614          * column, then the 8 bits for the second column, etc.
 615          *
 616          *
 617          * Representation of the screen, assuming it is 5 bits
 618          * wide. Each letter-number combination is a bit that controls
 619          * one pixel.
 620          *
 621          * A0 A1 A2 A3 A4
 622          * B0 B1 B2 B3 B4
 623          * C0 C1 C2 C3 C4
 624          * D0 D1 D2 D3 D4
 625          * E0 E1 E2 E3 E4
 626          * F0 F1 F2 F3 F4
 627          * G0 G1 G2 G3 G4
 628          * H0 H1 H2 H3 H4
 629          *
 630          * If you want to update this screen, you need to send 5 bytes:
 631          *  (1) A0 B0 C0 D0 E0 F0 G0 H0
 632          *  (2) A1 B1 C1 D1 E1 F1 G1 H1
 633          *  (3) A2 B2 C2 D2 E2 F2 G2 H2
 634          *  (4) A3 B3 C3 D3 E3 F3 G3 H3
 635          *  (5) A4 B4 C4 D4 E4 F4 G4 H4
 636          */
 637
 638         if (!ssd130x->page_address_mode) {
 639                 u8 page_start;
 640
 641                 /* Set address range for horizontal addressing mode */
 642                 ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset + x, width);
 643                 if (ret < 0)
 644                         return ret;
 645
 646                 page_start = ssd130x->page_offset + y / page_height;
 647                 ret = ssd130x_set_page_range(ssd130x, page_start, pages);
 648                 if (ret < 0)
 649                         return ret;
 650         }
 651
 652         for (i = 0; i < pages; i++) {
 653                 int m = page_height;
 654
 655                 /* Last page may be partial */
 656                 if (page_height * (y / page_height + i + 1) > ssd130x->height)
 657                         m = ssd130x->height % page_height;
 658
 659                 for (j = 0; j < width; j++) {
 660                         u8 data = 0;
 661
 662                         for (k = 0; k < m; k++) {
 663                                 u32 idx = (page_height * i + k) * line_length + j / 8;
 664                                 u8 byte = buf[idx];
 665                                 u8 bit = (byte >> (j % 8)) & 1;
 666
 667                                 data |= bit << k;
 668                         }
 669                         data_array[array_idx++] = data;
 670                 }
 671
 672                 /*
 673                  * In page addressing mode, the start address needs to be reset,
 674                  * and each page then needs to be written out separately.
 675                  */
 676                 if (ssd130x->page_address_mode) {
 677                         ret = ssd130x_set_page_pos(ssd130x,
 678                                                    ssd130x->page_offset + i,
 679                                                    ssd130x->col_offset + x);
 680                         if (ret < 0)
 681                                 return ret;
 682
 683                         ret = ssd130x_write_data(ssd130x, data_array, width);
 684                         if (ret < 0)
 685                                 return ret;
 686
 687                         array_idx = 0;
 688                 }
 689         }
 690
 691         /* Write out update in one go if we aren't using page addressing mode */
 692         if (!ssd130x->page_address_mode)
 693                 ret = ssd130x_write_data(ssd130x, data_array, width * pages);
 694
 695         return ret;
 696 }
 697
 698 static int ssd132x_update_rect(struct ssd130x_device *ssd130x,
 699                                struct drm_rect *rect, u8 *buf,
 700                                u8 *data_array)
 701 {
 702         unsigned int x = rect->x1;
 703         unsigned int y = rect->y1;
 704         unsigned int segment_width = SSD132X_SEGMENT_WIDTH;
 705         unsigned int width = drm_rect_width(rect);
 706         unsigned int height = drm_rect_height(rect);
 707         unsigned int columns = DIV_ROUND_UP(width, segment_width);
 708         unsigned int rows = height;
 709         struct drm_device *drm = &ssd130x->drm;
 710         u32 array_idx = 0;
 711         unsigned int i, j;
 712         int ret;
 713
 714         drm_WARN_ONCE(drm, x % segment_width != 0, "x must be aligned to screen segment\n");
 715
 716         /*
 717          * The screen is divided in Segment and Common outputs, where
 718          * COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are
 719          * the columns.
 720          *
 721          * Each Segment has a 4-bit pixel and each Common output has a
 722          * row of pixels. When using the (default) horizontal address
 723          * increment mode, each byte of data sent to the controller has
 724          * two Segments (e.g: SEG0 and SEG1) that are stored in the lower
 725          * and higher nibbles of a single byte representing one column.
 726          * That is, the first byte are SEG0 (D0[3:0]) and SEG1 (D0[7:4]),
 727          * the second byte are SEG2 (D1[3:0]) and SEG3 (D1[7:4]) and so on.
 728          */
 729
 730         /* Set column start and end */
 731         ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_COL_RANGE, x / segment_width, columns - 1);
 732         if (ret < 0)
 733                 return ret;
 734
 735         /* Set row start and end */
 736         ret = ssd130x_write_cmd(ssd130x, 3, SSD132X_SET_ROW_RANGE, y, rows - 1);
 737         if (ret < 0)
 738                 return ret;
 739
 740         for (i = 0; i < height; i++) {
 741                 /* Process pair of pixels and combine them into a single byte */
 742                 for (j = 0; j < width; j += segment_width) {
 743                         u8 n1 = buf[i * width + j];
 744                         u8 n2 = buf[i * width + j + 1];
 745
 746                         data_array[array_idx++] = (n2 << 4) | n1;
 747                 }
 748         }
 749
 750         /* Write out update in one go since horizontal addressing mode is used */
 751         ret = ssd130x_write_data(ssd130x, data_array, columns * rows);
 752
 753         return ret;
 754 }
 755
 756 static void ssd130x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
 757 {
 758         unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT);
 759         unsigned int width = ssd130x->width;
 760         int ret, i;
 761
 762         if (!ssd130x->page_address_mode) {
 763                 memset(data_array, 0, width * pages);
 764
 765                 /* Set address range for horizontal addressing mode */
 766                 ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset, width);
 767                 if (ret < 0)
 768                         return;
 769
 770                 ret = ssd130x_set_page_range(ssd130x, ssd130x->page_offset, pages);
 771                 if (ret < 0)
 772                         return;
 773
 774                 /* Write out update in one go if we aren't using page addressing mode */
 775                 ssd130x_write_data(ssd130x, data_array, width * pages);
 776         } else {
 777                 /*
 778                  * In page addressing mode, the start address needs to be reset,
 779                  * and each page then needs to be written out separately.
 780                  */
 781                 memset(data_array, 0, width);
 782
 783                 for (i = 0; i < pages; i++) {
 784                         ret = ssd130x_set_page_pos(ssd130x,
 785                                                    ssd130x->page_offset + i,
 786                                                    ssd130x->col_offset);
 787                         if (ret < 0)
 788                                 return;
 789
 790                         ret = ssd130x_write_data(ssd130x, data_array, width);
 791                         if (ret < 0)
 792                                 return;
 793                 }
 794         }
 795 }
 796
 797 static void ssd132x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
 798 {
 799         unsigned int columns = DIV_ROUND_UP(ssd130x->height, SSD132X_SEGMENT_WIDTH);
 800         unsigned int height = ssd130x->height;
 801
 802         memset(data_array, 0, columns * height);
 803
 804         /* Write out update in one go since horizontal addressing mode is used */
 805         ssd130x_write_data(ssd130x, data_array, columns * height);
 806 }
 807
 808 static int ssd130x_fb_blit_rect(struct drm_framebuffer *fb,
 809                                 const struct iosys_map *vmap,
 810                                 struct drm_rect *rect,
 811                                 u8 *buf, u8 *data_array)
 812 {
 813         struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);
 814         struct iosys_map dst;
 815         unsigned int dst_pitch;
 816         int ret = 0;
 817
 818         /* Align y to display page boundaries */
 819         rect->y1 = round_down(rect->y1, SSD130X_PAGE_HEIGHT);
 820         rect->y2 = min_t(unsigned int, round_up(rect->y2, SSD130X_PAGE_HEIGHT), ssd130x->height);
 821
 822         dst_pitch = DIV_ROUND_UP(drm_rect_width(rect), 8);
 823
 824         ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
 825         if (ret)
 826                 return ret;
 827
 828         iosys_map_set_vaddr(&dst, buf);
 829         drm_fb_xrgb8888_to_mono(&dst, &dst_pitch, vmap, fb, rect);
 830
 831         drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
 832
 833         ssd130x_update_rect(ssd130x, rect, buf, data_array);
 834
 835         return ret;
 836 }
 837
 838 static int ssd132x_fb_blit_rect(struct drm_framebuffer *fb,
 839                                 const struct iosys_map *vmap,
 840                                 struct drm_rect *rect, u8 *buf,
 841                                 u8 *data_array)
 842 {
 843         struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);
 844         unsigned int dst_pitch = drm_rect_width(rect);
 845         struct iosys_map dst;
 846         int ret = 0;
 847
 848         /* Align x to display segment boundaries */
 849         rect->x1 = round_down(rect->x1, SSD132X_SEGMENT_WIDTH);
 850         rect->x2 = min_t(unsigned int, round_up(rect->x2, SSD132X_SEGMENT_WIDTH),
 851                          ssd130x->width);
 852
 853         ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
 854         if (ret)
 855                 return ret;
 856
 857         iosys_map_set_vaddr(&dst, buf);
 858         drm_fb_xrgb8888_to_gray8(&dst, &dst_pitch, vmap, fb, rect);
 859
 860         drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
 861
 862         ssd132x_update_rect(ssd130x, rect, buf, data_array);
 863
 864         return ret;
 865 }
 866
 867 static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane,
 868                                               struct drm_atomic_state *state)
 869 {
 870         struct drm_device *drm = plane->dev;
 871         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
 872         struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
 873         struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);
 874         struct drm_crtc *crtc = plane_state->crtc;
 875         struct drm_crtc_state *crtc_state = NULL;
 876         const struct drm_format_info *fi;
 877         unsigned int pitch;
 878         int ret;
 879
 880         if (crtc)
 881                 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
 882
 883         ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
 884                                                   DRM_PLANE_NO_SCALING,
 885                                                   DRM_PLANE_NO_SCALING,
 886                                                   false, false);
 887         if (ret)
 888                 return ret;
 889         else if (!plane_state->visible)
 890                 return 0;
 891
 892         fi = drm_format_info(DRM_FORMAT_R1);
 893         if (!fi)
 894                 return -EINVAL;
 895
 896         pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width);
 897
 898         ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL);
 899         if (!ssd130x_state->buffer)
 900                 return -ENOMEM;
 901
 902         return 0;
 903 }
 904
 905 static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane,
 906                                               struct drm_atomic_state *state)
 907 {
 908         struct drm_device *drm = plane->dev;
 909         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
 910         struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
 911         struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(plane_state);
 912         struct drm_crtc *crtc = plane_state->crtc;
 913         struct drm_crtc_state *crtc_state = NULL;
 914         const struct drm_format_info *fi;
 915         unsigned int pitch;
 916         int ret;
 917
 918         if (crtc)
 919                 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
 920
 921         ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
 922                                                   DRM_PLANE_NO_SCALING,
 923                                                   DRM_PLANE_NO_SCALING,
 924                                                   false, false);
 925         if (ret)
 926                 return ret;
 927         else if (!plane_state->visible)
 928                 return 0;
 929
 930         fi = drm_format_info(DRM_FORMAT_R8);
 931         if (!fi)
 932                 return -EINVAL;
 933
 934         pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width);
 935
 936         ssd130x_state->buffer = kcalloc(pitch, ssd130x->height, GFP_KERNEL);
 937         if (!ssd130x_state->buffer)
 938                 return -ENOMEM;
 939
 940         return 0;
 941 }
 942
 943 static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane,
 944                                                 struct drm_atomic_state *state)
 945 {
 946         struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
 947         struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
 948         struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
 949         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
 950         struct ssd130x_crtc_state *ssd130x_crtc_state =  to_ssd130x_crtc_state(crtc_state);
 951         struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);
 952         struct drm_framebuffer *fb = plane_state->fb;
 953         struct drm_atomic_helper_damage_iter iter;
 954         struct drm_device *drm = plane->dev;
 955         struct drm_rect dst_clip;
 956         struct drm_rect damage;
 957         int idx;
 958
 959         if (!drm_dev_enter(drm, &idx))
 960                 return;
 961
 962         drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
 963         drm_atomic_for_each_plane_damage(&iter, &damage) {
 964                 dst_clip = plane_state->dst;
 965
 966                 if (!drm_rect_intersect(&dst_clip, &damage))
 967                         continue;
 968
 969                 ssd130x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip,
 970                                      ssd130x_plane_state->buffer,
 971                                      ssd130x_crtc_state->data_array);
 972         }
 973
 974         drm_dev_exit(idx);
 975 }
 976
 977 static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane,
 978                                                 struct drm_atomic_state *state)
 979 {
 980         struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
 981         struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
 982         struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
 983         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
 984         struct ssd130x_crtc_state *ssd130x_crtc_state =  to_ssd130x_crtc_state(crtc_state);
 985         struct ssd130x_plane_state *ssd130x_plane_state = to_ssd130x_plane_state(plane_state);
 986         struct drm_framebuffer *fb = plane_state->fb;
 987         struct drm_atomic_helper_damage_iter iter;
 988         struct drm_device *drm = plane->dev;
 989         struct drm_rect dst_clip;
 990         struct drm_rect damage;
 991         int idx;
 992
 993         if (!drm_dev_enter(drm, &idx))
 994                 return;
 995
 996         drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
 997         drm_atomic_for_each_plane_damage(&iter, &damage) {
 998                 dst_clip = plane_state->dst;
 999
1000                 if (!drm_rect_intersect(&dst_clip, &damage))
1001                         continue;
1002
1003                 ssd132x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip,
1004                                      ssd130x_plane_state->buffer,
1005                                      ssd130x_crtc_state->data_array);
1006         }
1007
1008         drm_dev_exit(idx);
1009 }
1010
1011 static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane,
1012                                                  struct drm_atomic_state *state)
1013 {
1014         struct drm_device *drm = plane->dev;
1015         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1016         struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1017         struct drm_crtc_state *crtc_state;
1018         struct ssd130x_crtc_state *ssd130x_crtc_state;
1019         int idx;
1020
1021         if (!plane_state->crtc)
1022                 return;
1023
1024         crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
1025         ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);
1026
1027         if (!drm_dev_enter(drm, &idx))
1028                 return;
1029
1030         ssd130x_clear_screen(ssd130x, ssd130x_crtc_state->data_array);
1031
1032         drm_dev_exit(idx);
1033 }
1034
1035 static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane,
1036                                                  struct drm_atomic_state *state)
1037 {
1038         struct drm_device *drm = plane->dev;
1039         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1040         struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
1041         struct drm_crtc_state *crtc_state;
1042         struct ssd130x_crtc_state *ssd130x_crtc_state;
1043         int idx;
1044
1045         if (!plane_state->crtc)
1046                 return;
1047
1048         crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
1049         ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);
1050
1051         if (!drm_dev_enter(drm, &idx))
1052                 return;
1053
1054         ssd132x_clear_screen(ssd130x, ssd130x_crtc_state->data_array);
1055
1056         drm_dev_exit(idx);
1057 }
1058
1059 /* Called during init to allocate the plane's atomic state. */
1060 static void ssd130x_primary_plane_reset(struct drm_plane *plane)
1061 {
1062         struct ssd130x_plane_state *ssd130x_state;
1063
1064         WARN_ON(plane->state);
1065
1066         ssd130x_state = kzalloc(sizeof(*ssd130x_state), GFP_KERNEL);
1067         if (!ssd130x_state)
1068                 return;
1069
1070         __drm_gem_reset_shadow_plane(plane, &ssd130x_state->base);
1071 }
1072
1073 static struct drm_plane_state *ssd130x_primary_plane_duplicate_state(struct drm_plane *plane)
1074 {
1075         struct drm_shadow_plane_state *new_shadow_plane_state;
1076         struct ssd130x_plane_state *old_ssd130x_state;
1077         struct ssd130x_plane_state *ssd130x_state;
1078
1079         if (WARN_ON(!plane->state))
1080                 return NULL;
1081
1082         old_ssd130x_state = to_ssd130x_plane_state(plane->state);
1083         ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL);
1084         if (!ssd130x_state)
1085                 return NULL;
1086
1087         /* The buffer is not duplicated and is allocated in .atomic_check */
1088         ssd130x_state->buffer = NULL;
1089
1090         new_shadow_plane_state = &ssd130x_state->base;
1091
1092         __drm_gem_duplicate_shadow_plane_state(plane, new_shadow_plane_state);
1093
1094         return &new_shadow_plane_state->base;
1095 }
1096
1097 static void ssd130x_primary_plane_destroy_state(struct drm_plane *plane,
1098                                                 struct drm_plane_state *state)
1099 {
1100         struct ssd130x_plane_state *ssd130x_state = to_ssd130x_plane_state(state);
1101
1102         kfree(ssd130x_state->buffer);
1103
1104         __drm_gem_destroy_shadow_plane_state(&ssd130x_state->base);
1105
1106         kfree(ssd130x_state);
1107 }
1108
1109 static const struct drm_plane_helper_funcs ssd130x_primary_plane_helper_funcs[] = {
1110         [SSD130X_FAMILY] = {
1111                 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
1112                 .atomic_check = ssd130x_primary_plane_atomic_check,
1113                 .atomic_update = ssd130x_primary_plane_atomic_update,
1114                 .atomic_disable = ssd130x_primary_plane_atomic_disable,
1115         },
1116         [SSD132X_FAMILY] = {
1117                 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
1118                 .atomic_check = ssd132x_primary_plane_atomic_check,
1119                 .atomic_update = ssd132x_primary_plane_atomic_update,
1120                 .atomic_disable = ssd132x_primary_plane_atomic_disable,
1121         }
1122 };
1123
1124 static const struct drm_plane_funcs ssd130x_primary_plane_funcs = {
1125         .update_plane = drm_atomic_helper_update_plane,
1126         .disable_plane = drm_atomic_helper_disable_plane,
1127         .reset = ssd130x_primary_plane_reset,
1128         .atomic_duplicate_state = ssd130x_primary_plane_duplicate_state,
1129         .atomic_destroy_state = ssd130x_primary_plane_destroy_state,
1130         .destroy = drm_plane_cleanup,
1131 };
1132
1133 static enum drm_mode_status ssd130x_crtc_mode_valid(struct drm_crtc *crtc,
1134                                                     const struct drm_display_mode *mode)
1135 {
1136         struct ssd130x_device *ssd130x = drm_to_ssd130x(crtc->dev);
1137
1138         if (mode->hdisplay != ssd130x->mode.hdisplay &&
1139             mode->vdisplay != ssd130x->mode.vdisplay)
1140                 return MODE_ONE_SIZE;
1141         else if (mode->hdisplay != ssd130x->mode.hdisplay)
1142                 return MODE_ONE_WIDTH;
1143         else if (mode->vdisplay != ssd130x->mode.vdisplay)
1144                 return MODE_ONE_HEIGHT;
1145
1146         return MODE_OK;
1147 }
1148
1149 static int ssd130x_crtc_atomic_check(struct drm_crtc *crtc,
1150                                      struct drm_atomic_state *state)
1151 {
1152         struct drm_device *drm = crtc->dev;
1153         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1154         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1155         struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);
1156         unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT);
1157         int ret;
1158
1159         ret = drm_crtc_helper_atomic_check(crtc, state);
1160         if (ret)
1161                 return ret;
1162
1163         ssd130x_state->data_array = kmalloc(ssd130x->width * pages, GFP_KERNEL);
1164         if (!ssd130x_state->data_array)
1165                 return -ENOMEM;
1166
1167         return 0;
1168 }
1169
1170 static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc,
1171                                      struct drm_atomic_state *state)
1172 {
1173         struct drm_device *drm = crtc->dev;
1174         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1175         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1176         struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);
1177         unsigned int columns = DIV_ROUND_UP(ssd130x->width, SSD132X_SEGMENT_WIDTH);
1178         int ret;
1179
1180         ret = drm_crtc_helper_atomic_check(crtc, state);
1181         if (ret)
1182                 return ret;
1183
1184         ssd130x_state->data_array = kmalloc(columns * ssd130x->height, GFP_KERNEL);
1185         if (!ssd130x_state->data_array)
1186                 return -ENOMEM;
1187
1188         return 0;
1189 }
1190
1191 /* Called during init to allocate the CRTC's atomic state. */
1192 static void ssd130x_crtc_reset(struct drm_crtc *crtc)
1193 {
1194         struct ssd130x_crtc_state *ssd130x_state;
1195
1196         WARN_ON(crtc->state);
1197
1198         ssd130x_state = kzalloc(sizeof(*ssd130x_state), GFP_KERNEL);
1199         if (!ssd130x_state)
1200                 return;
1201
1202         __drm_atomic_helper_crtc_reset(crtc, &ssd130x_state->base);
1203 }
1204
1205 static struct drm_crtc_state *ssd130x_crtc_duplicate_state(struct drm_crtc *crtc)
1206 {
1207         struct ssd130x_crtc_state *old_ssd130x_state;
1208         struct ssd130x_crtc_state *ssd130x_state;
1209
1210         if (WARN_ON(!crtc->state))
1211                 return NULL;
1212
1213         old_ssd130x_state = to_ssd130x_crtc_state(crtc->state);
1214         ssd130x_state = kmemdup(old_ssd130x_state, sizeof(*ssd130x_state), GFP_KERNEL);
1215         if (!ssd130x_state)
1216                 return NULL;
1217
1218         /* The buffer is not duplicated and is allocated in .atomic_check */
1219         ssd130x_state->data_array = NULL;
1220
1221         __drm_atomic_helper_crtc_duplicate_state(crtc, &ssd130x_state->base);
1222
1223         return &ssd130x_state->base;
1224 }
1225
1226 static void ssd130x_crtc_destroy_state(struct drm_crtc *crtc,
1227                                        struct drm_crtc_state *state)
1228 {
1229         struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(state);
1230
1231         kfree(ssd130x_state->data_array);
1232
1233         __drm_atomic_helper_crtc_destroy_state(state);
1234
1235         kfree(ssd130x_state);
1236 }
1237
1238 /*
1239  * The CRTC is always enabled. Screen updates are performed by
1240  * the primary plane's atomic_update function. Disabling clears
1241  * the screen in the primary plane's atomic_disable function.
1242  */
1243 static const struct drm_crtc_helper_funcs ssd130x_crtc_helper_funcs[] = {
1244         [SSD130X_FAMILY] = {
1245                 .mode_valid = ssd130x_crtc_mode_valid,
1246                 .atomic_check = ssd130x_crtc_atomic_check,
1247         },
1248         [SSD132X_FAMILY] = {
1249                 .mode_valid = ssd130x_crtc_mode_valid,
1250                 .atomic_check = ssd132x_crtc_atomic_check,
1251         },
1252 };
1253
1254 static const struct drm_crtc_funcs ssd130x_crtc_funcs = {
1255         .reset = ssd130x_crtc_reset,
1256         .destroy = drm_crtc_cleanup,
1257         .set_config = drm_atomic_helper_set_config,
1258         .page_flip = drm_atomic_helper_page_flip,
1259         .atomic_duplicate_state = ssd130x_crtc_duplicate_state,
1260         .atomic_destroy_state = ssd130x_crtc_destroy_state,
1261 };
1262
1263 static void ssd130x_encoder_atomic_enable(struct drm_encoder *encoder,
1264                                           struct drm_atomic_state *state)
1265 {
1266         struct drm_device *drm = encoder->dev;
1267         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1268         int ret;
1269
1270         ret = ssd130x_power_on(ssd130x);
1271         if (ret)
1272                 return;
1273
1274         ret = ssd130x_init(ssd130x);
1275         if (ret)
1276                 goto power_off;
1277
1278         ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON);
1279
1280         backlight_enable(ssd130x->bl_dev);
1281
1282         return;
1283
1284 power_off:
1285         ssd130x_power_off(ssd130x);
1286         return;
1287 }
1288
1289 static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder,
1290                                           struct drm_atomic_state *state)
1291 {
1292         struct drm_device *drm = encoder->dev;
1293         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1294         int ret;
1295
1296         ret = ssd130x_power_on(ssd130x);
1297         if (ret)
1298                 return;
1299
1300         ret = ssd132x_init(ssd130x);
1301         if (ret)
1302                 goto power_off;
1303
1304         ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON);
1305
1306         backlight_enable(ssd130x->bl_dev);
1307
1308         return;
1309
1310 power_off:
1311         ssd130x_power_off(ssd130x);
1312 }
1313
1314 static void ssd130x_encoder_atomic_disable(struct drm_encoder *encoder,
1315                                            struct drm_atomic_state *state)
1316 {
1317         struct drm_device *drm = encoder->dev;
1318         struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
1319
1320         backlight_disable(ssd130x->bl_dev);
1321
1322         ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_OFF);
1323
1324         ssd130x_power_off(ssd130x);
1325 }
1326
1327 static const struct drm_encoder_helper_funcs ssd130x_encoder_helper_funcs[] = {
1328         [SSD130X_FAMILY] = {
1329                 .atomic_enable = ssd130x_encoder_atomic_enable,
1330                 .atomic_disable = ssd130x_encoder_atomic_disable,
1331         },
1332         [SSD132X_FAMILY] = {
1333                 .atomic_enable = ssd132x_encoder_atomic_enable,
1334                 .atomic_disable = ssd130x_encoder_atomic_disable,
1335         }
1336 };
1337
1338 static const struct drm_encoder_funcs ssd130x_encoder_funcs = {
1339         .destroy = drm_encoder_cleanup,
1340 };
1341
1342 static int ssd130x_connector_get_modes(struct drm_connector *connector)
1343 {
1344         struct ssd130x_device *ssd130x = drm_to_ssd130x(connector->dev);
1345         struct drm_display_mode *mode;
1346         struct device *dev = ssd130x->dev;
1347
1348         mode = drm_mode_duplicate(connector->dev, &ssd130x->mode);
1349         if (!mode) {
1350                 dev_err(dev, "Failed to duplicated mode\n");
1351                 return 0;
1352         }
1353
1354         drm_mode_probed_add(connector, mode);
1355         drm_set_preferred_mode(connector, mode->hdisplay, mode->vdisplay);
1356
1357         /* There is only a single mode */
1358         return 1;
1359 }
1360
1361 static const struct drm_connector_helper_funcs ssd130x_connector_helper_funcs = {
1362         .get_modes = ssd130x_connector_get_modes,
1363 };
1364
1365 static const struct drm_connector_funcs ssd130x_connector_funcs = {
1366         .reset = drm_atomic_helper_connector_reset,
1367         .fill_modes = drm_helper_probe_single_connector_modes,
1368         .destroy = drm_connector_cleanup,
1369         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1370         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1371 };
1372
1373 static const struct drm_mode_config_funcs ssd130x_mode_config_funcs = {
1374         .fb_create = drm_gem_fb_create_with_dirty,
1375         .atomic_check = drm_atomic_helper_check,
1376         .atomic_commit = drm_atomic_helper_commit,
1377 };
1378
1379 static const uint32_t ssd130x_formats[] = {
1380         DRM_FORMAT_XRGB8888,
1381 };
1382
1383 DEFINE_DRM_GEM_FOPS(ssd130x_fops);
1384
1385 static const struct drm_driver ssd130x_drm_driver = {
1386         DRM_GEM_SHMEM_DRIVER_OPS,
1387         .name                   = DRIVER_NAME,
1388         .desc                   = DRIVER_DESC,
1389         .date                   = DRIVER_DATE,
1390         .major                  = DRIVER_MAJOR,
1391         .minor                  = DRIVER_MINOR,
1392         .driver_features        = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET,
1393         .fops                   = &ssd130x_fops,
1394 };
1395
1396 static int ssd130x_update_bl(struct backlight_device *bdev)
1397 {
1398         struct ssd130x_device *ssd130x = bl_get_data(bdev);
1399         int brightness = backlight_get_brightness(bdev);
1400         int ret;
1401
1402         ssd130x->contrast = brightness;
1403
1404         ret = ssd130x_write_cmd(ssd130x, 1, SSD13XX_CONTRAST);
1405         if (ret < 0)
1406                 return ret;
1407
1408         ret = ssd130x_write_cmd(ssd130x, 1, ssd130x->contrast);
1409         if (ret < 0)
1410                 return ret;
1411
1412         return 0;
1413 }
1414
1415 static const struct backlight_ops ssd130xfb_bl_ops = {
1416         .update_status  = ssd130x_update_bl,
1417 };
1418
1419 static void ssd130x_parse_properties(struct ssd130x_device *ssd130x)
1420 {
1421         struct device *dev = ssd130x->dev;
1422
1423         if (device_property_read_u32(dev, "solomon,width", &ssd130x->width))
1424                 ssd130x->width = ssd130x->device_info->default_width;
1425
1426         if (device_property_read_u32(dev, "solomon,height", &ssd130x->height))
1427                 ssd130x->height = ssd130x->device_info->default_height;
1428
1429         if (device_property_read_u32(dev, "solomon,page-offset", &ssd130x->page_offset))
1430                 ssd130x->page_offset = 1;
1431
1432         if (device_property_read_u32(dev, "solomon,col-offset", &ssd130x->col_offset))
1433                 ssd130x->col_offset = 0;
1434
1435         if (device_property_read_u32(dev, "solomon,com-offset", &ssd130x->com_offset))
1436                 ssd130x->com_offset = 0;
1437
1438         if (device_property_read_u32(dev, "solomon,prechargep1", &ssd130x->prechargep1))
1439                 ssd130x->prechargep1 = 2;
1440
1441         if (device_property_read_u32(dev, "solomon,prechargep2", &ssd130x->prechargep2))
1442                 ssd130x->prechargep2 = 2;
1443
1444         if (!device_property_read_u8_array(dev, "solomon,lookup-table",
1445                                            ssd130x->lookup_table,
1446                                            ARRAY_SIZE(ssd130x->lookup_table)))
1447                 ssd130x->lookup_table_set = 1;
1448
1449         ssd130x->seg_remap = !device_property_read_bool(dev, "solomon,segment-no-remap");
1450         ssd130x->com_seq = device_property_read_bool(dev, "solomon,com-seq");
1451         ssd130x->com_lrremap = device_property_read_bool(dev, "solomon,com-lrremap");
1452         ssd130x->com_invdir = device_property_read_bool(dev, "solomon,com-invdir");
1453         ssd130x->area_color_enable =
1454                 device_property_read_bool(dev, "solomon,area-color-enable");
1455         ssd130x->low_power = device_property_read_bool(dev, "solomon,low-power");
1456
1457         ssd130x->contrast = 127;
1458         ssd130x->vcomh = ssd130x->device_info->default_vcomh;
1459
1460         /* Setup display timing */
1461         if (device_property_read_u32(dev, "solomon,dclk-div", &ssd130x->dclk_div))
1462                 ssd130x->dclk_div = ssd130x->device_info->default_dclk_div;
1463         if (device_property_read_u32(dev, "solomon,dclk-frq", &ssd130x->dclk_frq))
1464                 ssd130x->dclk_frq = ssd130x->device_info->default_dclk_frq;
1465 }
1466
1467 static int ssd130x_init_modeset(struct ssd130x_device *ssd130x)
1468 {
1469         enum ssd130x_family_ids family_id = ssd130x->device_info->family_id;
1470         struct drm_display_mode *mode = &ssd130x->mode;
1471         struct device *dev = ssd130x->dev;
1472         struct drm_device *drm = &ssd130x->drm;
1473         unsigned long max_width, max_height;
1474         struct drm_plane *primary_plane;
1475         struct drm_crtc *crtc;
1476         struct drm_encoder *encoder;
1477         struct drm_connector *connector;
1478         int ret;
1479
1480         /*
1481          * Modesetting
1482          */
1483
1484         ret = drmm_mode_config_init(drm);
1485         if (ret) {
1486                 dev_err(dev, "DRM mode config init failed: %d\n", ret);
1487                 return ret;
1488         }
1489
1490         mode->type = DRM_MODE_TYPE_DRIVER;
1491         mode->clock = 1;
1492         mode->hdisplay = mode->htotal = ssd130x->width;
1493         mode->hsync_start = mode->hsync_end = ssd130x->width;
1494         mode->vdisplay = mode->vtotal = ssd130x->height;
1495         mode->vsync_start = mode->vsync_end = ssd130x->height;
1496         mode->width_mm = 27;
1497         mode->height_mm = 27;
1498
1499         max_width = max_t(unsigned long, mode->hdisplay, DRM_SHADOW_PLANE_MAX_WIDTH);
1500         max_height = max_t(unsigned long, mode->vdisplay, DRM_SHADOW_PLANE_MAX_HEIGHT);
1501
1502         drm->mode_config.min_width = mode->hdisplay;
1503         drm->mode_config.max_width = max_width;
1504         drm->mode_config.min_height = mode->vdisplay;
1505         drm->mode_config.max_height = max_height;
1506         drm->mode_config.preferred_depth = 24;
1507         drm->mode_config.funcs = &ssd130x_mode_config_funcs;
1508
1509         /* Primary plane */
1510
1511         primary_plane = &ssd130x->primary_plane;
1512         ret = drm_universal_plane_init(drm, primary_plane, 0, &ssd130x_primary_plane_funcs,
1513                                        ssd130x_formats, ARRAY_SIZE(ssd130x_formats),
1514                                        NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1515         if (ret) {
1516                 dev_err(dev, "DRM primary plane init failed: %d\n", ret);
1517                 return ret;
1518         }
1519
1520         drm_plane_helper_add(primary_plane, &ssd130x_primary_plane_helper_funcs[family_id]);
1521
1522         drm_plane_enable_fb_damage_clips(primary_plane);
1523
1524         /* CRTC */
1525
1526         crtc = &ssd130x->crtc;
1527         ret = drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1528                                         &ssd130x_crtc_funcs, NULL);
1529         if (ret) {
1530                 dev_err(dev, "DRM crtc init failed: %d\n", ret);
1531                 return ret;
1532         }
1533
1534         drm_crtc_helper_add(crtc, &ssd130x_crtc_helper_funcs[family_id]);
1535
1536         /* Encoder */
1537
1538         encoder = &ssd130x->encoder;
1539         ret = drm_encoder_init(drm, encoder, &ssd130x_encoder_funcs,
1540                                DRM_MODE_ENCODER_NONE, NULL);
1541         if (ret) {
1542                 dev_err(dev, "DRM encoder init failed: %d\n", ret);
1543                 return ret;
1544         }
1545
1546         drm_encoder_helper_add(encoder, &ssd130x_encoder_helper_funcs[family_id]);
1547
1548         encoder->possible_crtcs = drm_crtc_mask(crtc);
1549
1550         /* Connector */
1551
1552         connector = &ssd130x->connector;
1553         ret = drm_connector_init(drm, connector, &ssd130x_connector_funcs,
1554                                  DRM_MODE_CONNECTOR_Unknown);
1555         if (ret) {
1556                 dev_err(dev, "DRM connector init failed: %d\n", ret);
1557                 return ret;
1558         }
1559
1560         drm_connector_helper_add(connector, &ssd130x_connector_helper_funcs);
1561
1562         ret = drm_connector_attach_encoder(connector, encoder);
1563         if (ret) {
1564                 dev_err(dev, "DRM attach connector to encoder failed: %d\n", ret);
1565                 return ret;
1566         }
1567
1568         drm_mode_config_reset(drm);
1569
1570         return 0;
1571 }
1572
1573 static int ssd130x_get_resources(struct ssd130x_device *ssd130x)
1574 {
1575         struct device *dev = ssd130x->dev;
1576
1577         ssd130x->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1578         if (IS_ERR(ssd130x->reset))
1579                 return dev_err_probe(dev, PTR_ERR(ssd130x->reset),
1580                                      "Failed to get reset gpio\n");
1581
1582         ssd130x->vcc_reg = devm_regulator_get(dev, "vcc");
1583         if (IS_ERR(ssd130x->vcc_reg))
1584                 return dev_err_probe(dev, PTR_ERR(ssd130x->vcc_reg),
1585                                      "Failed to get VCC regulator\n");
1586
1587         return 0;
1588 }
1589
1590 struct ssd130x_device *ssd130x_probe(struct device *dev, struct regmap *regmap)
1591 {
1592         struct ssd130x_device *ssd130x;
1593         struct backlight_device *bl;
1594         struct drm_device *drm;
1595         int ret;
1596
1597         ssd130x = devm_drm_dev_alloc(dev, &ssd130x_drm_driver,
1598                                      struct ssd130x_device, drm);
1599         if (IS_ERR(ssd130x))
1600                 return ERR_PTR(dev_err_probe(dev, PTR_ERR(ssd130x),
1601                                              "Failed to allocate DRM device\n"));
1602
1603         drm = &ssd130x->drm;
1604
1605         ssd130x->dev = dev;
1606         ssd130x->regmap = regmap;
1607         ssd130x->device_info = device_get_match_data(dev);
1608
1609         if (ssd130x->device_info->page_mode_only)
1610                 ssd130x->page_address_mode = 1;
1611
1612         ssd130x_parse_properties(ssd130x);
1613
1614         ret = ssd130x_get_resources(ssd130x);
1615         if (ret)
1616                 return ERR_PTR(ret);
1617
1618         bl = devm_backlight_device_register(dev, dev_name(dev), dev, ssd130x,
1619                                             &ssd130xfb_bl_ops, NULL);
1620         if (IS_ERR(bl))
1621                 return ERR_PTR(dev_err_probe(dev, PTR_ERR(bl),
1622                                              "Unable to register backlight device\n"));
1623
1624         bl->props.brightness = ssd130x->contrast;
1625         bl->props.max_brightness = MAX_CONTRAST;
1626         ssd130x->bl_dev = bl;
1627
1628         ret = ssd130x_init_modeset(ssd130x);
1629         if (ret)
1630                 return ERR_PTR(ret);
1631
1632         ret = drm_dev_register(drm, 0);
1633         if (ret)
1634                 return ERR_PTR(dev_err_probe(dev, ret, "DRM device register failed\n"));
1635
1636         drm_fbdev_generic_setup(drm, 32);
1637
1638         return ssd130x;
1639 }
1640 EXPORT_SYMBOL_GPL(ssd130x_probe);
1641
1642 void ssd130x_remove(struct ssd130x_device *ssd130x)
1643 {
1644         drm_dev_unplug(&ssd130x->drm);
1645         drm_atomic_helper_shutdown(&ssd130x->drm);
1646 }
1647 EXPORT_SYMBOL_GPL(ssd130x_remove);
1648
1649 void ssd130x_shutdown(struct ssd130x_device *ssd130x)
1650 {
1651         drm_atomic_helper_shutdown(&ssd130x->drm);
1652 }
1653 EXPORT_SYMBOL_GPL(ssd130x_shutdown);
1654
1655 MODULE_DESCRIPTION(DRIVER_DESC);
1656 MODULE_AUTHOR("Javier Martinez Canillas <[email protected]>");
1657 MODULE_LICENSE("GPL v2");